Semiconductor package assembly and method of forming the same

Abstract

A semiconductor package assembly is provided that includes a base substrate, a lower electronic element mounted on the base substrate, a lower cap mounted on the base substrate, wherein the lower cap has a top plate thermally coupled to the lower electronic element to dissipate heat generated by the lower electronic element and at least one opening through the top plate and partially exposing the base substrate, at least one interconnect structure vertically aligned with the at least one opening and mounted on the base substrate through the at least one opening, a middle layer mounted on the at least one interconnect structure and electrically coupled to the base substrate via the at least one interconnect structure, one or more upper electronic elements mounted on the middle layer and electrically coupled to the base substrate via the middle layer and the at least one interconnect structure, and an upper cap mounted on the lower cap and the one or more upper electronic elements.

Description

Technical Field

[0001] This application generally relates to semiconductor technology, and more specifically, to a semiconductor packaging assembly and a method for forming a semiconductor packaging assembly. Background Technology

[0002] The semiconductor industry has always faced complex integration challenges as consumers demand smaller, faster, and higher-performing electronics, with an increasing number of functions being packaged into a single device. To meet these demands, more and more electronic components are being integrated into a single package, resulting in larger semiconductor packages. However, larger semiconductor packages can have various drawbacks, such as package warpage and unsatisfactory thermal performance.

[0003] Therefore, a semiconductor package component with a compact structure is needed. Summary of the Invention

[0004] The objective of this application is to provide a semiconductor packaging component with a compact structure.

[0005] According to one aspect of this application, a semiconductor packaging assembly is provided. The semiconductor packaging assembly includes: a substrate; a lower electronic component mounted on the substrate; a lower cover mounted on the substrate and enclosing the lower electronic component, wherein the lower cover has a top plate and at least one opening, the top plate being thermally coupled to the lower electronic component to dissipate heat generated by the lower electronic component, the at least one opening passing through the top plate and partially exposing the substrate; at least one interconnect structure vertically aligned with and mounted on the substrate through the at least one opening; an interposer layer mounted on and electrically coupled to the substrate via the at least one interconnect structure; one or more upper electronic components mounted on the interposer layer and electrically coupled to the substrate via the interposer layer and the at least one interconnect structure; and an upper cover mounted on the lower cover and the one or more upper electronic components, the upper cover enclosing the one or more upper electronic components and the interposer layer.

[0006] According to another aspect of this application, a method for forming a semiconductor package assembly is disclosed. The method includes: providing a substrate; mounting lower electronic components on the substrate; mounting at least one interconnect structure on the substrate; mounting a lower cover having a top plate and at least one opening through the top plate on the substrate to enclose the lower electronic components and the at least one interconnect structure, and thermally coupling the top plate of the lower cover to the lower electronic components, wherein the at least one opening partially exposes the substrate and is vertically aligned with the at least one interconnect structure; mounting an interposer on the at least one interconnect structure to electrically couple the interposer to the substrate via the at least one interconnect structure; mounting one or more upper electronic components on the interposer to electrically couple the one or more upper electronic components to the substrate via the interposer and the at least one interconnect structure; and mounting an upper cover on the lower cover and the one or more upper electronic components to enclose the one or more upper electronic components and the interposer.

[0007] According to another aspect of this application, a method for forming a semiconductor package assembly is disclosed. The method includes: providing a substrate; mounting lower electronic components on the substrate; mounting at least one interconnect structure on the substrate; mounting a lower cover having a top plate and at least one opening through the top plate on the substrate to enclose the lower electronic components and the at least one interconnect structure, and thermally coupling the top plate of the lower cover to the lower electronic components, wherein the at least one opening partially exposes the substrate and is vertically aligned with the at least one interconnect structure; mounting an interposer having one or more upper electronic components on it on the at least one interconnect structure to electrically couple the one or more upper electronic components on the interposer to the substrate via the interposer and the at least one interconnect structure; and mounting an upper cover on the lower cover and the one or more upper electronic components to enclose the one or more upper electronic components and the interposer.

[0008] It should be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only, and do not limit the invention. Furthermore, the accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention. Attached Figure Description

[0009] The drawings referenced herein form part of this specification. Unless otherwise expressly indicated in the detailed description, the features shown in the drawings illustrate only some embodiments of this application, and not all embodiments of this application, and the reader of this specification should not imply the contrary.

[0010] Figure 1A A semiconductor packaging assembly according to an embodiment of this application is shown.

[0011] Figure 1B exhibit Figure 1A The image shows a top view of the lower cover of a semiconductor packaging assembly.

[0012] Figure 2 A semiconductor packaging assembly according to another embodiment of this application is shown.

[0013] Figures 3A to 3G A method for forming a semiconductor package assembly according to embodiments of this application is illustrated.

[0014] Figure 4 A method for forming an interconnect structure according to an embodiment of this application is shown.

[0015] Figure 5 A method for forming an intermediary layer according to an embodiment of this application is shown.

[0016] Use the same reference numerals to refer to the same or similar parts in a continuous diagram. Detailed Implementation

[0017] The following detailed description of exemplary embodiments of this application takes into account the accompanying drawings, which form a part of the description. The drawings illustrate specific exemplary embodiments in which this application may be practiced. The detailed description, including the drawings, describes these embodiments in sufficient detail to enable those skilled in the art to practice this application. Those skilled in the art may further utilize other embodiments of this application and make logical, mechanical, and other changes without departing from the spirit or scope of this application. Therefore, the reader of the following detailed description should not interpret the description in a limiting sense, and the scope of the embodiments of this application is defined only by the appended claims.

[0018] In this application, unless otherwise expressly stated, the use of the singular includes the plural form. In this application, unless otherwise stated, the use of “or” means “and / or”. Furthermore, the use of the term “comprising” is not restrictive. Additionally, unless otherwise expressly stated, terms such as “element” or “assembly” cover both elements and assemblies comprising one unit and elements and assemblies comprising more than one sub-unit. Furthermore, the section headings used herein are for organizational purposes only and should not be construed as limiting the subject matter described.

[0019] As used herein, for ease of description, spatial relative terms such as “below,” “under,” “above,” “upper,” “upper,” “lower,” “left,” “right,” “vertical,” “horizontal,” and “side” may be used to describe the relationship between an element or feature and another element (or feature) or feature (or feature), as shown in the diagrams. In addition to the orientations depicted in the diagrams, the spatial relative terms are intended to cover different orientations of the device in use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein shall be interpreted accordingly. It should be understood that when an element is referred to as “connected to” or “coupled to” another element, the element may be directly connected to or coupled to the other element, or there may be intermediate elements present.

[0020] This invention relates to semiconductor package assemblies with compact structures to address various drawbacks of larger semiconductor packages. In some embodiments, the semiconductor package assembly may have an embedded heat sink cover that dissipates heat to the external environment of the semiconductor package assembly, thus improving its thermal performance. Furthermore, the embedded heat sink cover can also provide support for other components within the semiconductor package assembly, which can be stacked on the embedded heat sink. Consequently, the semiconductor package assembly can be structurally compact and has a low risk of package warpage. Therefore, the reliability of the semiconductor package assembly can be improved.

[0021] Figure 1A A semiconductor packaging assembly 100 according to an embodiment of this application is shown.

[0022] like Figure 1A As shown, the semiconductor packaging assembly 100 includes a substrate 102 in which various components and other structures are mounted and formed. The substrate 102 includes... Figure 1A The orientation shown is an upward-facing front side and a back side opposite the front side. In some embodiments, the substrate 102 may be made of silicon or other semiconductor materials, or may include a printed circuit board (PCB), carrier substrate, ceramic substrate, laminated interposer, strip interposer, lead frame, or other suitable substrate. In some examples, the substrate 102 may include a redistribution layer or structure having one or more dielectric layers and one or more conductive layers between and through the dielectric layers. Therefore, various elements and other structures on one or both sides of the substrate 102 can be electrically coupled to each other to form an integrated electronic system. Figure 1AIn the embodiment shown, most electronic components are mounted on the front side of the substrate 102, with only solder bumps 126 and some passive discrete electronic components 128 (e.g., resistors) mounted on the back side of the substrate 102. Thus, the electronic components mounted on the front side of the substrate 102 can be electrically coupled to the solder bumps 126 via the substrate 102, and are further electrically coupled to external systems such as power systems or controllers when the semiconductor package assembly 100 is connected.

[0023] The lower electronic component 104 is mounted on the front side of the substrate 102, for example, via solder bumps or other similar conductive structures. In some embodiments, the lower electronic component 104 may be a semiconductor chip or a semiconductor package. Figure 1A In the embodiments shown, the lower electronic component 104 has a relatively large size and can occupy a large portion of the front surface of the substrate 102. For example, the lower electronic component 104 may be a signal processing chip or a controller chip, which can generate a significant amount of heat during operation and therefore requires heat dissipation to the external environment to prevent heat buildup. In some alternative embodiments, more than one lower electronic component 104 may be mounted on the front side of the substrate 102, and some or all of these multiple lower electronic components may require specific heat dissipation paths or components.

[0024] The lower cover 106 is further mounted on the front side of the substrate 102. The lower cover 106 may have a larger dimension (in length, width, and height) than the lower electronic component 104, such that it can enclose the lower electronic component 104 for protection and other purposes. In other words, the lower cover 106 and the substrate 102 together define a lower chamber therein where the lower electronic component 104 is housed. Figure 1AAs shown, the lower cover 106 has a top plate 108, the area of ​​which is substantially equal to the area of ​​the substrate 102. Furthermore, sidewalls 110 of the lower cover 106 are connected to and extend downward from the top plate 108. The sidewalls 110 are attached to the substrate 102 via an adhesive material, such that the top plate 108 is securely supported on and fixed to the substrate 102. It will be understood that in some other embodiments, the lower cover 106 may be attached or connected to the substrate 102 in other suitable ways (e.g., using fasteners). When the lower electronic component 104 is mounted on the substrate 102, the sidewalls 110 of the lower cover 106 may have a height slightly greater than the height of the lower electronic component 104. In this configuration, a gap may exist between the top plate 108 and the top surface of the lower electronic component 104 to avoid friction between the top plate 108 and the top surface of the lower electronic component 104 during the mounting of the lower cover 106 onto the substrate 102. As previously mentioned, the lower electronic component 104 may generate significant heat during operation, and the lower cover 106 may be made of a metal such as copper or alumina, or any other suitable material with good thermal conductivity. Thus, the lower electronic component 104 may be thermally coupled to the lower cover 106, for example, at the top plate 108, to dissipate the heat generated by the lower electronic component 104 to the external environment. For example, a thermal interface material layer 112 may be formed in the gap between the top plate 108 and the lower electronic component 104 to achieve the desired thermal coupling. It is understood that in some embodiments, two or more lower electronic components 104 are mounted on a substrate 102, each of which may be thermally coupled to a lower cover 106 via, for example, a thermal interface material layer 112, or a portion of these lower electronic components 104 that may generate significant heat may be thermally coupled to the lower cover 106.

[0025] The lower cover 106 further has at least one opening 114 through the top plate 108. Figure 1B exhibit Figure 1A The image shows a top view of the lower cover 106 of the semiconductor packaging assembly 100. Figure 1A and 1B As shown, two openings 114 are formed in the lower cover 106, which are generally opposite each other relative to the center of the top plate 108. However, it is understood that other numbers of openings may be formed as needed. The openings 114 do not completely disrupt the connection from the central portion of the top plate 108 to the sidewalls 110 of the lower cover 106, and thus the heat generated by the lower electronic components 104 can still be effectively transferred across the openings 114 from the central portion to the edge of the top plate 108 and then to the sidewalls 110, where the heat can be dissipated to the external environment.

[0026] Furthermore, the opening 114 of the lower cover 106 is vertically offset from the lower electronic component 104, and thus partially exposes the substrate 102, particularly exposing conductive pads formed on the substrate 102 that are not covered by the lower electronic component 104. Therefore, at least one interconnect structure 116 can be vertically aligned with at least one opening 114 and mounted on the substrate 102 through at least one opening 114. Figure 1A and 1B In the embodiment shown, two openings 114 are formed in the lower cover 106, and each of the interconnect structures 116 is mounted within one of the openings 114. The interconnect structure 116 may include an electronic bar (e-bar) block with solder bumps mounted or formed on both sides. The e-bar block is an integrated interconnect structure that may be pre-formed and have various internal conductive pillars, such as copper pillars extending through an insulating material, for example, a molding material. Depending on the number of conductive pillars, a corresponding number of solder bumps may be formed between the e-bar block and the substrate 102 to achieve electrical connection between the e-bar block and the substrate 102. Furthermore, a corresponding number of solder bumps may be similarly formed between the e-bar block and another element or structure above the e-bar block, which will be described in more detail below. The height of each interconnect structure 116 (including the height of the solder bumps on the front side of the interconnect structure 116) may be equal to or slightly greater than the height of the lower cover 106, allowing another component or structure to be indirectly mounted on the substrate 102 via the interconnect structure 116 to avoid interfering with the lower cover 106. In some alternative embodiments, the interconnect structure 116 may be a set of larger solder balls, the height of which is slightly greater than the height of the lower cover 106. For example, each of the larger solder balls may include a copper core with a tin coating, which provides not only electrical conductivity but also the desired thermal conductivity. Figure 1B In the embodiment shown, each of the openings 114 is formed in a rectangular shape, and therefore more than one solder ball can be mounted or attached to the interconnect structure 116 in a column manner. In some other embodiments, two or more columns of solder balls may be mounted or attached to the interconnect structure 116 as needed.

[0027] The lower cover 106 provides a direct heat dissipation path from the lower electronic components 104 to the external environment without restricting electrical connections to the substrate 102. Therefore, additional components can be stacked on the substrate 102 and above the lower cover 116. Specifically, an interposer 118 is further mounted on and electrically coupled to the substrate 102 via at least one interconnect structure 116. For example, the interposer 118 may have a back-side conductive pad (not shown) aligned and connected to solder bumps on the front side of the interconnect structure 116. Furthermore, the interconnect structure 116 may support and secure the interposer 118 to the substrate 102. As mentioned above, since the interconnect structure 116 (including solder balls on its respective front side) is generally higher than the lower cover 106, the interposer 118 can be supported on the substrate 102 without interfering with the lower cover 106.

[0028] One or more upper electronic components 120 (e.g., semiconductor chips or semiconductor packages or other suitable electronic components) may be mounted on the interposer 118. Due to the presence of the interconnect structure 116 and the interposer 118, the upper electronic components 120 can be electrically coupled to the substrate 102 and operate as a single integrated electronic system together with the lower electronic components 104. Furthermore, the upper cover 122 may be further mounted on the lower cover 106, for example, via an adhesive material. The upper cover 122 encloses the upper electronic components 120 and the interposer 118, and thus protects them from external environmental influences and prevents damage. In other words, the upper cover 122 and the lower cover 106 together define an upper chamber for housing the upper electronic components 120, which is generally separate from the lower chamber defined by the lower cover 106 and the substrate 102. For example, the upper cover 122 may be made of alumina, copper, or other similar metals or alloys. Preferably, the coverage area of ​​the upper cover 122 may be the same as that of the lower cover 106. Since the upper cover 122 is supported on the lower cover 106, or specifically on the top plate 108 of the lower cover 106, it does not obstruct the heat dissipation path from the sidewall 110 of the lower cover 106 to the external environment. In some embodiments, the lower cover 106 may be made of alumina, copper, or other similar metals or alloys, which can function as an electromagnetic interference shielding layer, and thus reduce or avoid electromagnetic interference between electronic components in the two chambers.

[0029] In some embodiments, the upper electronics 120 may include a package in which a memory chip is integrated, while the lower electronics 104 may be a logic chip that generates significant heat during operation and requires an effective heat dissipation path. A portion of the lower cover 106 is located inside the entire semiconductor package assembly 100, while another portion is exposed to the external environment, providing the lower electronics 104 with the desired direct heat dissipation path. Furthermore, when the upper electronics 120 and the upper cover 122 are stacked over the lower cover 106, the entire semiconductor package assembly 100 can be structurally compact, which reduces the risk of package warpage. Additionally, it is understood that in some alternative embodiments, the lower electronics 104 and the upper electronics 120 may be semiconductor devices with any other suitable type of functionality. For example, in some embodiments where more memory resources are required, the lower electronics 104 may be a memory chip or package, while the upper electronics 120 may be a semiconductor package with logic circuitry or functionality.

[0030] exist Figure 1A In the embodiment shown, two smaller semiconductor packages are mounted on the interposer 118, and the two semiconductor packages may have substantially the same height. In addition to being supported on the lower cover 106, the upper cover 122 may also be mounted on the two upper electronic components 120, for example, via an adhesive material 124 between the upper cover 122 and the upper electronic components 120. In this way, the upper cover 122 provides additional anchoring for the upper electronic components 120, and thus improves the structural reliability of the entire semiconductor package assembly 100. In some embodiments, the adhesive material 124 between the upper electronic components 124 and the upper cover 122 may also be thermally conductive, providing a direct heat dissipation path for the upper electronic components 124.

[0031] Figure 2 A semiconductor packaging assembly 200 according to an embodiment of this application is shown. For example... Figure 2 What is shown is different Figure 1A The semiconductor package assembly 100 shown has a lower electronic component 104 mounted below the central region of a lower cover 106 and at least one interconnect structure 116 distributed around the lower electronic component 104 and closer to the sidewalls 110 of the lower cover 106. The semiconductor package assembly 200 has a lower electronic component 204 vertically offset from the central region of the lower cover 206. Correspondingly, an interconnect structure 216 of the semiconductor package assembly 200 is also vertically offset from the central region of the lower cover 206, and the interconnect structure 216 is used for electrically and mechanically connecting the interposer 218 to the substrate 202. In other words, in Figure 2In the embodiment shown, two or more interconnect structures are formed as a single piece, which facilitates their attachment to the substrate 202. Accordingly, an opening 214 is formed in the top plate 208 through the lower cover 206 to allow the interconnect structure 216 to pass through the lower cover 206. Since the opening 214 may occupy only a portion of the area of ​​the top plate 208, a heat dissipation path can still be established from the lower electronic components 204 through the lower cover 204 to the external environment. It will be understood that the location and number of openings in the top plate of the lower cover can be modified depending on the layout of the components mounted on the substrate.

[0032] Figures 3A to 3G A method for forming a semiconductor package assembly according to embodiments of this application is illustrated. For example, the method can be used to form... Figure 1A The semiconductor packaging component 100 shown in the figure, or Figure 2 The semiconductor packaging component 200 shown in the figure has some modifications.

[0033] like Figure 3A As shown, a substrate 302 is provided. In some embodiments, the substrate 302 may be made of silicon or other semiconductor materials, or may include a printed circuit board (PCB), carrier substrate, ceramic substrate, laminated interposer, strip interposer, lead frame, or other suitable substrate. A lower electronic component 304 (e.g., a semiconductor chip) is mounted on the substrate 302, for example, via solder bumps. An underfill material may be filled between the lower electronic component 304 and the substrate 302 to improve the attachment of the lower electronic component 304 to the substrate 302. In one embodiment, the lower electronic component 304 is mounted at the central region of the substrate 302, but in some alternative embodiments, the lower electronic component 304 may be offset from the central region.

[0034] Next, as Figure 3B As shown, two interconnect structures 316 are mounted on a substrate 302, positioned on opposite sides of the lower electronic component 304 and close to the edge of the substrate 302. In an embodiment, each of the two interconnect structures 316 includes an e-bar block with a set of solder bumps on its back side, the solder bumps allowing the interconnect structure 316 to be mounted on the substrate 302. The two interconnect structures 316 may be in the form of an elongated plate having a back-side surface sufficient for mounting one or more columns of solder bumps. It will be understood that other numbers of interconnect structures 316 may be mounted on the substrate 302.

[0035] In one embodiment, the e-bar block and the underlying solder bump of each interconnect structure 316 can be pre-formed as a single piece, and then the interconnect structures 316 can be mounted together at predetermined locations on the substrate 302. A reflow process can be performed to reflow the solder bumps and secure the interconnect structure 316 to the substrate 302. Because the interconnect structure 316 can serve as an anchor for components to be subsequently mounted, it can have the required height to avoid any potential interference. Furthermore, in some other embodiments, the interconnect structure 316 can be mounted on the substrate 302 before, rather than after, the mounting of the lower electronic component 304.

[0036] Next, as Figure 3C As shown, the lower cover 306 is mounted on the substrate 302, for example, via an adhesive material disposed on the back side of the lower cover 306. For example, the adhesive material may be disposed between the sidewall 310 of the lower cover 306 and the substrate 302. After the lower cover 306 is mounted, the lower electronic components 304 and the interconnect structure 316 can be enclosed by the lower cover 306. Specifically, the lower cover 306 has a top plate 308 on its front side and at least one opening 314 through the top plate 308. Figure 3C In the embodiment shown, two interconnect structures 316 are mounted on a substrate 302, forming two openings 314 through a top plate 308, each of which is aligned with one of the interconnect structures 316. Because the lower electronic component 304 is vertically offset from the openings 314, the openings 314 may partially expose the substrate 302, or in particular, expose the interconnect structures 316 mounted on the substrate 302.

[0037] In some embodiments, a thermal interface material layer 312 may be formed between the lower electronic component 304 and the top plate 308 of the lower cover 306, such that the lower cover 306 and the lower electronic component 304 are thermally coupled to each other to provide a heat dissipation path from the lower electronic component 304 through the lower cover 306 to the external environment. For example, the thermal interface material layer 312 may be distributed or otherwise formed on the top surface of the lower electronic component 304 before the lower cover 306 is mounted onto the substrate 302. In this case, both the thermal interface material layer 312 beneath the top plate 308 and the adhesive material beneath the sidewalls 310 enhance the attachment of the lower cover 306 to the substrate 302, thereby improving the reliability of the semiconductor package assembly.

[0038] Next, as Figure 3DAs shown, an interposer 318 is mounted on at least one interconnect structure 316 to electrically couple the interposer 318 to the substrate 302 via the at least one interconnect structure 316. In this embodiment, the interposer 318 may have solder bumps pre-formed on its back side, which may be aligned with corresponding conductive pads or other conductive patterns on the front side of the e-bar block of the interconnect structure 316 when the interposer 318 is mounted on the at least one interconnect structure 316. Since the solder bumps below the interposer 318 have a certain height and are raised above the interposer 318 relative to the substrate 302, the top surface of the e-bar block of the interconnect structure 316 may be slightly recessed relative to the lower cover 306. However, the total height of each of the interconnect structures 316, including the e-bar block and the solder bumps on both sides thereof, should be equal to or greater than the height of the lower cover 306 to avoid interference between the interconnect structure 316 and the lower cover 306.

[0039] Next, as Figure 3E As shown, one or more upper electronic components 320 can be mounted on an interposer 318 to electrically couple one or more upper electronic components 320 to a substrate 302 via the interposer 318 and at least one interconnect structure 316. In some embodiments, the upper electronic components 320 may be semiconductor packages that can be mounted on the interposer 318 via solder bumps or other similar bonding members. In some preferred embodiments, the upper electronic components 320 may have the same height or similar height.

[0040] Next, as Figure 3F As shown, an upper cover 322 is mounted on a lower cover 306 and one or more upper electronic components 320 to enclose one or more upper electronic components 320 and an interposer layer 318. For example, an adhesive material may be distributed between the top plate 308 of the lower cover 306 and the upper cover 322 to connect the top plate 308 and the upper cover 322 to each other. Preferably, an adhesive material may also be distributed on the top surface of the upper electronic component 320, which may fill a corresponding gap between the upper electronic component 320 and the upper cover 322 and enhance the attachment of the upper cover 322 to other parts of the semiconductor package assembly. In some optional embodiments, after the upper cover 322 is mounted on the lower cover 306 and one or more upper electronic components 320, molding material may be filled within the upper cover 322. For example, one or more openings (not shown) may be formed through the upper cover 322 to allow for the filling of the molding material. The opening can then be blocked by the molding material, and therefore may not adversely affect the hermeticity of the entire semiconductor package assembly.

[0041] Next, as Figure 3GAs shown, the entire semiconductor package assembly can be flipped, and solder bumps 326 and additional electronic components 328 (e.g., certain passive discrete electronic components) can then be mounted on the back side of the substrate 302. The solder bumps 326 and additional electronic components 328 can be electrically coupled to electronic components (e.g., lower electronic component 316 and upper electronic component 320) on the front side of the substrate 302. Thus, a semiconductor package assembly can be formed.

[0042] Figure 4 This application illustrates a method for forming an interconnect structure according to embodiments thereof. The interconnect structure may be... Figure 3C The interconnect structure 316 shown in the figure. For example... Figure 4 As shown, interconnect structures can be obtained by single-cutting a substrate strip 432 having multiple identical or similar interconnect units 416. Specifically, all interconnect units 416 of the substrate strip 432 can be processed in batches, for example, by mounting corresponding sets of back-side solder bumps. Subsequently, the substrate strip 432 can be individually cut into multiple units, where each interconnect unit is one of the multiple units. Batch processing not only improves efficiency but also reduces manufacturing complexity, which is particularly advantageous when individual interconnect structures have relatively small dimensions (e.g., less than one centimeter). It is understood that interconnect structures may not be mounted with their corresponding front-side solder bumps; they may be mounted with an interposer, as described in detail below.

[0043] Figure 5 This application illustrates a method for forming an intermediary layer according to embodiments of the present application. The intermediary layer may be... Figure 3D The intermediate layer 318 is shown in the image. Figure 5 As shown, the interposer can be individually cut from an interposer strip 534 having multiple identical or similar interposer units 518. Specifically, all interposer units 518 of the interposer strip 534 can be processed in batches, for example, by mounting corresponding sets of solder bumps on its back side. Subsequently, the interposer strip 534 can be individually cut into multiple units, where each interposer unit is one of the multiple units.

[0044] In some alternative embodiments, before the interposer strip is individually cut into multiple units, in addition to pre-installing multiple sets of solder bumps on the interposer strip, corresponding multiple sets of upper electronic components can also be pre-installed on the back side of the interposer strip. In this case, after individual cutting, the interposer strip, along with the solder bumps on its back side and the upper electronic components on its front side, can be mounted together as follows: Figure 3C On the interconnect structure shown, that is, Figure 3D and 3E The installation steps shown can be performed in a single step, which improves the efficiency of the overall packaging process.

[0045] The discussion herein includes numerous illustrative diagrams showing the various parts of a semiconductor package assembly and methods for forming the semiconductor package assembly. For clarity, these diagrams do not show all aspects of each example component. Any of the example components and / or methods provided herein may share any or all characteristics with any or all other components and / or methods provided herein.

[0046] Various embodiments have been described herein with reference to the accompanying drawings. However, it will be apparent that various modifications and alterations can be made thereto, and additional embodiments can be implemented, without departing from the broader scope of the invention as set forth in the appended claims. Furthermore, other embodiments will be apparent to those skilled in the art upon consideration of the description and practice of one or more embodiments of the invention disclosed herein. Therefore, the examples in this application and herein are intended to be considered exemplary only, wherein the true scope and spirit of the invention are indicated by the list of exemplary claims below.

Claims

1. A semiconductor packaging component, characterized in that, include: Substrate; Lower electronic components are mounted on the substrate. A lower cover, which is mounted on the substrate and encloses the lower electronic component, wherein the lower cover has a top plate and at least one opening, the top plate being thermally coupled to the lower electronic component to dissipate heat generated by the lower electronic component, and the at least one opening passing through the top plate and partially exposing the substrate; At least one interconnect structure is vertically aligned with the at least one opening and mounted on the substrate through the at least one opening; An interposer layer is mounted on the at least one interconnect structure and electrically coupled to the substrate via the at least one interconnect structure; One or more upper electronic components are mounted on the interposer and electrically coupled to the substrate via the interposer and the at least one interconnect structure; as well as An upper cover is mounted on the lower cover and the one or more upper electronic components, and the upper cover encloses the one or more upper electronic components and the interlayer.

2. The semiconductor packaging assembly according to claim 1, characterized in that, Each of the at least one interconnect structure includes an electronic strip with solder bumps mounted on both sides.

3. The semiconductor packaging assembly according to claim 1, characterized in that, Each of the at least one interconnect structure includes solder balls with copper cores.

4. The semiconductor packaging assembly according to claim 1, characterized in that, The lower electronic components are located below the central area of ​​the lower cover, and the at least one interconnect structure is distributed around the lower electronic components and closer to the sidewall of the lower cover.

5. The semiconductor packaging assembly according to claim 1, characterized in that, The lower electronic components are vertically offset from the central region of the lower cover, and the at least one interconnect structure is also vertically offset from the central region of the lower cover.

6. The semiconductor packaging assembly according to claim 1, characterized in that, The top plate of the lower cover is attached to the lower electronic components via a thermal interface layer.

7. The semiconductor packaging assembly according to claim 1, characterized in that, The lower electronic component is a semiconductor chip.

8. The semiconductor packaging assembly according to claim 1, characterized in that, The lower electronic component, the lower cover, the one or more upper electronic components, and the upper cover are all mounted on the front side of the substrate, and the semiconductor package further includes solder bumps mounted on the back side of the substrate.

9. The semiconductor packaging assembly according to claim 8, characterized in that, The semiconductor package further includes at least one back-side electronic component mounted on the back side of the substrate.

10. A method for forming a semiconductor package assembly, characterized in that, include: Provide a substrate; The lower electronic components are mounted on the substrate; At least one interconnect structure is mounted on the substrate; A lower cover having a top plate and at least one opening through the top plate is mounted on the substrate to enclose the lower electronic component and the at least one interconnect structure, and the top plate of the lower cover is thermally coupled to the lower electronic component, wherein the at least one opening partially exposes the substrate and is vertically aligned with the at least one interconnect structure; An interposer is mounted on the at least one interconnect structure to electrically couple the interposer to the substrate via the at least one interconnect structure; One or more upper electronic components are mounted on the interposer to electrically couple the one or more upper electronic components to the substrate via the interposer and the at least one interconnect structure; as well as The upper cover is mounted on the lower cover and the one or more upper electronic components to enclose the one or more upper electronic components and the interlayer.

11. The method according to claim 10, characterized in that, Each of the at least one interconnect structure includes an electron strip, and the step of mounting the at least one interconnect structure on the substrate further includes: Solder bumps are mounted on the back side of the electronic strip of each interconnect structure in the at least one interconnect structure; The electronic strip is attached to the substrate via corresponding solder bumps; and Reflow solder bumps.

12. The method according to claim 10, characterized in that, The step of mounting the intermediary layer on the at least one interconnect structure further includes: Solder bumps are mounted on the back side of the interposer layer; and The interposer layer is attached to the at least one interconnect structure via the solder bumps.

13. The method according to claim 10, characterized in that, Before mounting a lower cover having a top plate and at least one opening through the top plate onto the substrate, the method further includes: A thermal interface layer is formed on the lower electronic component.

14. The method according to claim 10, characterized in that, The lower electronic component is a semiconductor chip.

15. The method according to claim 10, characterized in that, The lower electronic component, the lower cover, the one or more upper electronic components, and the upper cover are all mounted on the front side of the substrate, and the method further includes: Solder bumps are mounted on the back side of the substrate.

16. A method for forming a semiconductor package assembly, characterized in that, include: Provide a substrate; The lower electronic components are mounted on the substrate; At least one interconnect structure is mounted on the substrate; A lower cover having a top plate and at least one opening through the top plate is mounted on the substrate to enclose the lower electronic component and the at least one interconnect structure, and the top plate of the lower cover is thermally coupled to the lower electronic component, wherein the at least one opening partially exposes the substrate and is vertically aligned with the at least one interconnect structure; An interposer having one or more upper electronic components is mounted on the at least one interconnect structure to electrically couple one or more upper electronic components on the interposer to the substrate via the interposer and the at least one interconnect structure; as well as The upper cover is mounted on the lower cover and the one or more upper electronic components to enclose the one or more upper electronic components and the interlayer.

17. The method according to claim 16, characterized in that, The step of mounting an intermediary layer having one or more upper electronic components on the at least one interconnect structure further includes: Solder bumps are mounted on the back side of the interposer layer; Mount the one or more upper electronic components on the front side of the interposer layer; and The interposer layer is attached to the at least one interconnect structure via the solder bumps.

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