Semiconductor device and method of manufacturing semiconductor device

Abstract

The present application relates to a semiconductor device and a method of manufacturing a semiconductor device. A semiconductor device includes a semiconductor chip and a chip protector surrounding the semiconductor chip, wherein the chip protector includes a plurality of columns arranged along a first direction and extending in a second direction intersecting the first direction, a first protrusion extending from the plurality of columns along the first direction, and a second protrusion extending from the plurality of columns along the first direction and spaced apart from the first protrusion along the second direction.

Description

Technical Field

[0001] This disclosure relates to semiconductor devices and methods of manufacturing semiconductor devices, including but not limited to semiconductor devices including chip guards. Background Technology

[0002] Multiple chip regions are formed on a semiconductor substrate using semiconductor integration processes. These chip regions are separated by scribe lines that serve as boundaries. Multiple semiconductor chips are then manufactured by separating the chip regions using a dicing process.

[0003] Chip protectors are formed around a chip region to protect the integrated circuits within that region. For example, the chip protectors are arranged to surround the chip region. The chip protectors can prevent defect-inducing factors that occur outside the chip region and then transfer or spread within it. Summary of the Invention

[0004] According to one embodiment, a semiconductor device may include a semiconductor chip and a chip protector surrounding the semiconductor chip, wherein the chip protector includes: a plurality of pillars arranged along a first direction and extending in a second direction intersecting the first direction; a first protrusion extending from the plurality of pillars along the first direction; and a second protrusion extending from the plurality of pillars along the first direction and spaced apart from the first protrusion along the second direction.

[0005] According to one embodiment, a method of manufacturing a semiconductor device may include the steps of: forming a stack of sacrificial layers, which are alternately stacked with interlayer insulating layers, in a chip region and a protective region surrounding the chip region; forming openings in the protective region that extend through and are spaced apart from the stack of layers; etching the sacrificial layers exposed through the openings to form recesses adjacent to the openings; and forming chip protectors within the openings and the recesses. Attached Figure Description

[0006] Figure 1 This is a diagram illustrating the structure of a semiconductor device according to one embodiment of the present disclosure;

[0007] Figures 2A to 2E This is a diagram illustrating the structure of a chip protection device according to one embodiment of the present disclosure;

[0008] Figures 3A to 3D This is a cross-sectional view of a chip protector formed using a chip protector manufacturing method according to one embodiment of the present disclosure;

[0009] Figure 4A and Figure 4BThis is a diagram illustrating a chip protection element connected to the underwire according to one embodiment of the present disclosure;

[0010] Figure 5 This is a diagram illustrating a chip protection device with a dual structure according to one embodiment of the present disclosure;

[0011] Figure 6 This is a diagram illustrating a memory card system according to one embodiment of the present disclosure; and

[0012] Figure 7 This is a diagram illustrating a solid-state drive (SSD) system including a memory device according to one embodiment of the present disclosure. Detailed Implementation

[0013] This disclosure describes a semiconductor device and a method of manufacturing the semiconductor device, which can use a chip protector to reduce the stress applied to the semiconductor device.

[0014] Embodiments of this disclosure will be described in detail with reference to the accompanying drawings. Specific structural or functional descriptions of the embodiments are provided as examples to illustrate the concepts disclosed in this application. Examples or embodiments based on these concepts can be implemented in various forms, and the scope of this disclosure is not limited to the examples or embodiments described in this specification.

[0015] When one element is labeled “connected” or “linked” to another element, these elements may be directly connected or linked, or connected through at least one intermediate element between the elements. When two elements are labeled “directly connected” or “directly linked”, one element is directly connected or directly linked to the other element, and there is no intermediate element between the two elements.

[0016] The use of terms such as “vertical,” “horizontal,” “top,” “bottom,” “overlapping,” “upper,” “side,” “upper part,” “lower part,” “height,” and other terms that suggest relative spatial relationships or orientations are for the purpose of description or reference to the accompanying drawings only, and not to limit in any other way.

[0017] Cross-shading throughout the figures indicates corresponding or similar areas between figures, rather than indicating the material associated with those areas. The figures are not necessarily drawn to scale and include a varying number of structures between the sectional views and the corresponding plan views, and full versions of some structures between the sectional views and the corresponding plan views are not shown.

[0018] Figure 1 This is a diagram illustrating the structure of a semiconductor device according to one embodiment of the present disclosure.

[0019] Semiconductor devices include structures STRs. For example, a structure STR includes at least one of a substrate such as a silicon wafer, a SiGe wafer, or an SOI wafer, and a stack of layers formed on the substrate.

[0020] Reference Figure 1 The structure STR has a chip region CHA, a protection region GDA, and a scribing region SLA. For example, the structure STR includes a chip region CHA, a protection region GDA surrounding the corresponding chip region CHA, and a scribing region SLA surrounding the protection region GDA.

[0021] A chip region CHA is a region where a semiconductor chip is formed. Chip regions CHA are arranged along the X and Y directions. Semiconductor chips are formed by performing semiconductor integration processes on the chip regions CHA. The semiconductor chips formed within multiple chip regions CHA within a structure STR can be substantially identical. After the semiconductor integration process on the substrate is completed, the structure STR is separated according to the chip regions CHA, thus separating the chip regions CHA into individual semiconductor chips.

[0022] Each of the protective regions GDAs is adjacent to a corresponding chip region CHA. Each of the protective regions GDAs is positioned along the periphery of the corresponding chip region CHA. Each of the protective regions GDAs may surround the corresponding chip region. For example, the protective regions GDAs may be formed within a predetermined distance of the boundary of the chip region CHA. When the chip region CHA has a rectangular shape in a plane, the protective regions GDAs may have a rectangular frame shape in a plane, the rectangular frame shape having an opening or central region to surround the periphery of the chip region CHA. The outer surface of the chip region CHA may contact the inner surface of the protective regions GDAs.

[0023] A chip protector is formed within the protected area (GDA). The chip protector prevents moisture or oxygen from penetrating from the outside of the chip area (CHA) into its interior. The chip protector also reduces inter-die interference during packaging processes performed after the chip area (CHA) has been separated into individual semiconductor chips. (See reference...) Figures 2A to 2E and Figures 3A to 3D Describes the manufacturing form and method of the chip protection component formed within the protected area GDA.

[0024] The scribing trace area (SLA) is located outside the chip region (CHA) and the guard region (GDA). For example, the scribing trace area (SLA) may be located between the chip regions (CHA). After the semiconductor integration process is completed, the scribing trace area (SLA) can be removed during the dicing process to separate the semiconductor chip. The chip regions (CHA) are separated from each other by cutting the structure STR along the scribing trace area (SLA). The separated semiconductor chip consists of a chip region (CHA) and a guard region (GDA) surrounding the chip region (CHA). Blade sawing, laser cutting, or stealth scribing can be used as processes for cutting the structure STR. Electrical test patterns, process monitoring patterns, and alignment keys can be set in the scribing trace area (SLA).

[0025] exist Figure 1 For simplicity, six chip regions CHA are shown in this illustration, but the present disclosure is not limited to this example. For instance, the structure STR may include seven or more chip regions CHA, and the number of chip regions can vary. Although for simplicity, the chip regions CHA, guard regions GDA, and scribing regions SLA are shown separately, the chip regions CHA, guard regions GDA, and scribing regions SLA may not be physically separated but may be continuously connected to each other. For example, the positions of the chip regions CHA, guard regions GDA, and scribing regions SLA on the substrate can be arbitrarily determined.

[0026] Figures 2A to 2E This is a diagram illustrating the structure of a chip protection device GD according to one embodiment of the present disclosure. Figure 2A This is a plan view showing the layout of the chip protector GD located within the protection area GDA. Figure 2B yes Figure 2A A cross-sectional view taken through lines A-A' and B-B'. Figure 2C Is with Figure 2B The plan view corresponding to the cross-section of the first height LV1. Figure 2D Is with Figure 2B The plan view corresponding to the cross-section of the second height LV2. Figure 2E This is a perspective view showing the shape of the chip protector GD.

[0027] Reference Figure 2A The guard region GDA is located between the chip region CHA and the scribing region SLA. The guard region GDA can be located outside the chip region CHA. The guard region GDA is configured to surround the chip region CHA. For example, the chip region CHA can have a rectangular shape in a plane, and the guard region GDA can extend along the boundary of the chip region CHA.

[0028] A chip protector GD is formed within a protector region GDA. The chip protector GD may be located on the periphery of the chip region CHA. The chip protector GD may contact the chip region CHA. The chip protector GD may surround the chip region CHA. For example, outside the chip region CHA, the chip protector GD extends in the Y and X directions to surround the chip region CHA.

[0029] The chip protector GD includes a vertical pillar VP and a horizontal protrusion HP. The vertical pillar VP is arranged along the X and Y directions. The horizontal protrusion HP surrounds the vertical pillar VP.

[0030] Reference Figure 2B The stacked component STK is located within the protection region GDA. The stacked component STK extends from the chip region CHA to the protection region GDA. The stacked component STK includes a sacrificial layer SF alternating with the interlayer insulating layer IL in the Z direction. The interlayer insulating layer IL may include an oxide layer such as a silicon oxide layer. The sacrificial layer SF may include a material that is selectively etchable or removable in subsequent processes. The sacrificial layer SF may include a material with a different etch selectivity relative to the interlayer insulating layer IL. For example, the sacrificial layer SF may include a nitride layer. The chip protection component GD may extend through the stacked component STK in the Z direction.

[0031] Each vertical pillar VP can extend along the Z-direction. Each vertical pillar VP can penetrate the stacked element STK. The vertical pillar VP can extend through the sacrificial layer SF and the interlayer insulation layer IL. In one embodiment, the width of each of the vertical pillars VP gradually tapers towards the bottom of the vertical pillar. In one embodiment, the width of each of the vertical pillars VP does not change in the Z-direction.

[0032] like Figures 2A to 2D As shown, the vertical pillars VP are arranged along the X direction. For example, the vertical pillars VP may include a first vertical pillar VP1, a second vertical pillar VP2, and an nth vertical pillar VPn arranged along the X direction. The vertical pillars VP1 and VP2 are spaced apart in the X direction. The chip protection component GD includes vertical pillars VP arranged along the Y direction, similar to the vertical pillars VP arranged along the X direction.

[0033] A horizontal protrusion HP contacts or extends from a vertical post VP. For example, a first horizontal protrusion HP1 contacts each of the first vertical post VP1, the second vertical post VP2, ..., the nth vertical post VPn. The first horizontal protrusion HP1 contacts a portion of the side surface of the first vertical post VP1, a portion of the side surface of the second vertical post VP2, ..., the nth vertical post VPn. The first horizontal protrusion HP1 extends from the side surface of the first vertical post VP1, the side surface of the second vertical post VP2, ..., the nth vertical post VPn. The first horizontal protrusion HP1 surrounds at least a portion of the first vertical post VP1, at least a portion of the second vertical post VP2, ..., the nth vertical post VPn. The first horizontal protrusion HP1 connects the first vertical post VP1, the second vertical post VP2, ..., the nth vertical post VPn to each other in the X direction.

[0034] The second horizontal protrusion HP2 contacts or extends from each of the first vertical post VP1, the second vertical post VP2, ..., the nth vertical post VPn. The second horizontal protrusion HP2 contacts a portion of the side surface of the first vertical post VP1, a portion of the side surface of the second vertical post VP2, ..., the nth vertical post VPn. The second horizontal protrusion HP2 extends from the side surface of the first vertical post VP1, the second vertical post VP2, ..., the nth vertical post VPn. The second horizontal protrusion HP2 surrounds at least a portion of the first vertical post VP1, at least a portion of the second vertical post VP2, ..., the nth vertical post VPn. The second horizontal protrusion HP2 connects the first vertical post VP1, the second vertical post VP2, ..., the nth vertical post VPn to each other in the X direction.

[0035] Horizontal protrusions HP can connect vertical posts VP that are spaced apart along the X direction. For example, horizontal protrusions HP1 to HP5 are provided between the first vertical post VP1 and the second vertical post VP2 that are spaced apart along the X direction. The horizontal protrusions HP that connect with the vertical posts VP can have a trapezoidal shape in the Z direction.

[0036] The horizontal protrusion HP extends between the side of the laminate STK and the vertical post VP. For example, the horizontal protrusion HP extends along the Y direction from the side of each of the first vertical post VP1, the second vertical post VP2, ..., the nth vertical post VPn.

[0037] The horizontal protrusions HP are spaced apart in the Z direction. For example, the horizontal protrusions HP include a first horizontal protrusion HP1 to a fifth horizontal protrusion HP5 arranged in the Z direction. The second horizontal protrusion HP2 is spaced apart from the first horizontal protrusion HP1 in the Z direction.

[0038] In one embodiment, each of the horizontal protrusions HP is located at a height corresponding to one of the sacrificial layers SF. The height of the horizontal protrusion HP is substantially the same as the height of the sacrificial layer SF. For example, the first horizontal protrusion HP1 to the fifth horizontal protrusion HP5 overlap with the sacrificial layer SF in the Y and X directions. The horizontal protrusions HP are located at the height of the sacrificial layer SF, but not at the height of the interlayer insulation layer IL. For example, no horizontal protrusion HP is formed at the first height LV1 where the interlayer insulation layer IL is located, but a third horizontal protrusion HP3 is formed at the second height LV2 where the sacrificial layer SF is located.

[0039] The outer surface of the horizontal protrusion HP contacts the sacrificial layer SF. For example, the side of the horizontal protrusion HP in the Y direction contacts the sacrificial layer SF. The top and bottom surfaces of the horizontal protrusion HP contact the interlayer insulation layer IL. For example, the top and bottom surfaces of the first horizontal protrusion HP1 may contact the interlayer insulation layer IL. The interlayer insulation layer IL is located between the horizontal protrusions HP. For example, the interlayer insulation layer IL is located between the first horizontal protrusion HP1 and the second horizontal protrusion HP2. The interlayer insulation layer IL protrudes between the vertical posts VP and is parallel to the sacrificial layer SF.

[0040] Figure 2C The layout of the protective region GDA located at the first height LV1 where the interlayer insulation layer IL is located is shown, and Figure 2D The layout of the protection zone GDA located at the second altitude LV2, where the sacrificial layer SF is situated, is shown.

[0041] Reference Figure 2C The vertical pillars VP are spaced apart in the X direction. At a first height LV1, an interlayer insulation layer IL is disposed between the vertical pillars VP. At the first height LV1, the vertical pillars VP are separated by the interlayer insulation layer IL and can be formed in a straight line.

[0042] The sides of the vertical columns VP can be curved. For example, each of the vertical columns VP can have a circular or elliptical planar shape.

[0043] Reference Figure 2D At the second height LV2, a horizontal protrusion HP (in this example, a third horizontal protrusion HP3) extends in the X direction. At the second height LV2, the horizontal protrusion HP is formed between the vertical posts VP. At least a portion of the horizontal protrusion HP is located between the vertical posts VP. The horizontal protrusion HP contacts or extends from each of the vertical posts VP. At the second height LV2, the vertical posts VP are connected to each other via the horizontal protrusion HP. The horizontal protrusion HP connects the vertical posts VP to each other. For example, the horizontal protrusion HP electrically connects the vertical posts VP to each other.

[0044] In one embodiment, the horizontal protrusion HP has a curved surface. The outer surface of the horizontal protrusion HP includes a curved surface. The horizontal protrusion HP includes an extension projecting perpendicular to the side of the vertical column VP. The outer surface of the horizontal protrusion HP may include a curved surface adjacent to the sacrificial layer SF. For example, the horizontal protrusion HP extends in both the X and Y directions, and the horizontal protrusion HP has curved surfaces on each side of the vertical column VP in the Y direction.

[0045] The horizontal protrusion HP has an outer width that varies between a first width W1 and a second width W2 in the Y direction. The second width W2 is greater than the first width W1. In this example, the outer width of the horizontal protrusion HP refers to the distance between the outermost surfaces of the horizontal protrusion HP in the Y direction or in a direction perpendicular to the direction in which the horizontal protrusion HP extends, in a plan view. For example, in Figure 2D In the middle, the horizontal protrusion HP extends in the X direction, and the outer width of the horizontal protrusion HP extends in the Y direction.

[0046] The outer width of the horizontal protrusion HP includes a first width W1, a second width W2, and a continuous range of values ​​between the first width W1 and the second width W2. For example, in Figure 2D In the above, the outer width of the horizontal protrusion HP has a minimum value of a first width W1 and a maximum value of a second width W2. Besides the first width W1 and the second width W2, the horizontal protrusion HP can have a width of any value between the first width W1 and the second width W2. The outer width of the horizontal protrusion HP can include the first width W1 and the second width W2.

[0047] Reference Figure 2E The chip protection component GD includes first vertical pillars VP1 to third vertical pillars VP3 and horizontal protrusions HP1 to HP5. Vertical pillars VP1 to VP3 refer to... Figure 2C and Figure 2D Any set of three vertical columns VP arranged continuously along the X direction. Horizontal protrusions HP1 to HP5 correspond to... Figure 2B The horizontal protrusions HP1 to HP5.

[0048] In one embodiment, each vertical column VP has a cylindrical shape extending in the Z direction. The vertical columns VP may be formed with equal width or diameter in the Y direction. The vertical columns VP are continuously spaced apart in the X direction. For example, a second vertical column VP2 is spaced apart from a first vertical column VP1 in the X direction, and a third vertical column VP3 is spaced apart from a second vertical column VP2 in the X direction.

[0049] Each of the horizontal protrusions HP extends in the X direction. Each of the horizontal protrusions HP contacts or integrates with a vertical post VP. For example, the first horizontal protrusion HP1 includes a disc or ring RS11 that contacts or extends from the side of the first vertical post VP1. The first horizontal protrusion HP1 includes a ring RS12 that contacts or extends from the side of the second vertical post VP2. The first horizontal protrusion HP1 includes a ring RS13 that contacts or extends from the side of the third vertical post VP3. Rings RS11 to RS13 surround portions of the respective sides of vertical posts VP1 to VP3. Rings RS11 to RS13 may each have a circular, elliptical, or square ring shape. Rings RS11 to RS13 may each have a cylindrical shape. The first horizontal protrusion HP1 includes rings RS11 to RS13 that are interconnected or intersecting with each other. The first horizontal protrusion HP1 has the form of cylinders or rings arranged in the X direction and extending from each other. The outer and inner surfaces of the first horizontal protrusion HP1 may include curved surfaces.

[0050] Horizontal protrusions HP1 to HP5 are spaced apart and stacked in the Z direction. The first horizontal protrusions HP1 to the fifth horizontal protrusion HP5 can have similar structures, or they can be formed with the same shape but different lengths. For example, the fifth horizontal protrusion HP5 includes a ring RS51 that contacts the side of the first vertical post VP1. The fifth horizontal protrusion HP5 includes a ring RS52 that contacts the side of the second vertical post VP2. The fifth horizontal protrusion HP5 includes a ring RS53 that contacts the side of the third vertical post VP3. Rings RS51 to RS53 surround portions of the sides of the vertical posts VP1 to VP3. Rings RS51 to RS53 can each have a circular, elliptical, or square ring shape. Rings RS51 to RS53 can each have a cylindrical shape. The fifth horizontal protrusion HP5 includes rings RS51 to RS53 that are interconnected or intersecting with each other. The fifth horizontal protrusion HP5 has the form of cylinders or rings arranged in the X direction and extending from each other. The outer and inner surfaces of the fifth horizontal protrusion HP5 can include curved surfaces.

[0051] The chip protection device (GD) may include a conductive layer. For example, the chip protection device (GD) may include at least one of tungsten (W), cobalt (Co), nickel (Ni), molybdenum (Mo), silicon (Si), or polycrystalline silicon (poly-Si).

[0052] The vertical posts VP are connected to each other via horizontal protrusions HP. The horizontal protrusions HP connect the vertical posts VP that are spaced apart in the X direction. In one embodiment, the vertical posts VP are electrically connected to each other via the horizontal protrusions HP.

[0053] The horizontal protrusions HP are connected to each other via vertical posts VP. The vertical posts VP connect the horizontal protrusions HP that are spaced apart along the Z direction. In one embodiment, the horizontal protrusions HP are electrically connected to each other via vertical posts VP.

[0054] To simplify the explanation, such as Figures 2A to 2E The vertical pillars VP and horizontal protrusions HP shown correspond to a portion of the chip protector GD, and the number of vertical pillars VP and horizontal protrusions HP is not limited to... Figures 2A to 2E The quantity shown.

[0055] Figures 3A to 3D This is a cross-sectional view of a chip protector formed using a chip protector manufacturing method according to one embodiment of the present disclosure. Figures 3A to 3D It is along Figure 2A Cross-sectional views of lines A-A' and B-B'.

[0056] Reference Figure 3A This forms a stacked assembly STK comprising a sacrificial layer SF alternately laminated with an interlayer insulating layer IL in a protective region GDA. For example, the interlayer insulating layer IL may comprise an oxide layer such as silicon oxide. The sacrificial layer SF may comprise a material that is selectively removable in subsequent processes. The sacrificial layer SF may comprise a material with a different etch selectivity ratio relative to the interlayer insulating layer IL. For example, the sacrificial layer SF may comprise a nitride. Although... Figure 3A The stacked component STK formed in the protection region GDA is shown, but a stacked component STK including alternating sacrificial layers SF and interlayer insulating layers IL is also formed in the chip region CHA.

[0057] Reference Figure 3B An opening OP is formed by etching through the stacked STK. The stacked STK in the protective region GDA can be etched to form the opening OP. Each of the opening OPs extends in the Z direction. The opening OPs extend through the sacrificial layer SF and the interlayer insulating layer IL. The opening OPs are spaced apart in the X direction.

[0058] Reference Figure 3C The sacrificial layer SF is etched through the opening OP. The sacrificial layer SF is etched from the side exposed by the opening OP. The sacrificial layer SF is selectively etched between the sacrificial layer SF exposed by the opening OP and the interlayer insulating layer IL. When the sacrificial layer SF is etched, the interlayer insulating layer IL may not be etched. For example, HF or buffered oxide etchant (BOE) can be used to selectively etch the sacrificial layer SF.

[0059] At least a portion of the sacrificial layer SF is removed to form a recess RC. The recess RC extends from the opening OP toward the remaining sacrificial layer SF. The openings OP are connected to each other through the recess RC. For example, the amount of sacrificial layer SF to be etched is determined such that a segment of each of the sacrificial layers SF located between the openings OP is removed.

[0060] Reference Figure 3D A chip protector GD is formed within an opening OP and a recess RC. The chip protector GD fills the opening OP and the recess RC. A vertical post VP of the chip protector GD is located inside the opening OP, and a horizontal protrusion HP of the chip protector GD is located inside the recess RC. The chip protector GD may include a conductive layer. The vertical post VP of the chip protector GD may be formed separately from the horizontal protrusion HP, or the vertical post VP of the chip protector GD may be formed integrally or continuously with the horizontal protrusion HP. The opening OP and the recess RC may be filled with a conductive material to form the chip protector GD.

[0061] Chip protection devices (GD) prevent or reduce the entry of harmful substances such as H2O or O2 from the outside of the chip region CHA into its interior. GD also reduces interference between semiconductor chips during the packaging process performed when the chip region CHA is separated into semiconductor chips.

[0062] In one embodiment, the chip protector GD includes a horizontal protrusion HP configured to correspond to a selected height of the vertical pillar VP. Compared to an example where the sacrificial layer SF and interlayer insulating layer IL are etched through the opening OP, the volume of the chip protector GD can be reduced when the sacrificial layer SF is selectively etched according to one embodiment. The stress on the structure STR caused by the conductive material filling the chip protector GD can be reduced.

[0063] Figure 4A and Figure 4B This is a diagram illustrating a chip protection element connected to the underwire according to one embodiment of the present disclosure.

[0064] Reference Figure 4A and Figure 4B A first lower insulating layer LIL1 to a third lower insulating layer LIL3 are disposed at the lower end of the stacked assembly STK. The lower insulating layers LIL1 to LIL3 are formed sequentially in the Z direction. Lower insulating layers LIL1 and LIL3 may comprise a material similar to that of the interlayer insulating layer IL. The second lower insulating layer LIL2 may comprise a material similar to that of the sacrificial layer SF. In one embodiment, a vertical pillar VP included in the chip protector GD extends through the third lower insulating layer LIL3 and the second lower insulating layer LIL2.

[0065] Reference Figure 4AMultiple lower wirings LL1 to LLn are disposed within a first lower insulating layer LIL1. The multiple lower wirings LL1 to LLn are spaced apart in the X direction. The multiple lower wirings LL1 to LLn extend through the first lower insulating layer LIL1. Each of the multiple lower wirings LL1 to LLn may comprise a conductive material.

[0066] Vertical posts VP1 to VPn are in contact with lower wirings LL1 to LLn, respectively. Vertical posts VP1 to VPn are connected to lower wirings LL1 to LLn, respectively. Lower wirings LL1 to LLn are interconnected via chip protection device GD.

[0067] Reference Figure 4B A lower wiring LL is disposed inside the first lower insulating layer LIL1. The lower wiring LL extends in the X direction. The lower wiring LL extends through the first lower insulating layer LIL1. The lower wiring LL may include a conductive material.

[0068] Vertical posts VP1 to VPn are in contact with the lower wiring LL. Vertical posts VP1 to VPn are collectively connected to the lower wiring LL.

[0069] Figure 5 This is a diagram illustrating a chip protector with a dual structure according to one embodiment of the present disclosure.

[0070] Reference Figure 5 In one embodiment, two or more chip protectors are located within a protection region GDA. For example, a first chip protector 1GD and a second chip protector 2GD are arranged in parallel within the protection region GDA. The first chip protector 1GD is located between the chip region CHA and the second chip protector 2GD. Chip protectors 1GD and 2GD may each surround the chip region CHA. The second chip protector 2GD surrounds the first chip protector 1GD and the chip region CHA.

[0071] The first chip protector 1GD and the second chip protector 2GD can have substantially the same shape. For example, the first chip protector 1GD includes a vertical post 1VP and a horizontal protrusion 1HP that contacts or extends from the vertical post 1VP, and the second chip protector 2GD includes a vertical post 2VP and a horizontal protrusion 2HP that contacts or extends from the vertical post 2VP. The vertical post 1VP of the first chip protector 1GD and the vertical post 2VP of the second chip protector 2GD correspond to, for example, Figures 2A to 2E The vertical column VP described herein. The horizontal protrusion 1HP of the first chip protector 1GD and the horizontal protrusion 2HP of the second chip protector 2GD correspond to, as shown in the figure. Figures 2A to 2E The horizontal protrusion HP described in the text.

[0072] Figure 6This is a block diagram illustrating a memory card system 3000 according to one embodiment of the present disclosure.

[0073] Reference Figure 6 The memory card system 3000 includes a controller 3100, a memory device 3200, and a connector 3300.

[0074] Controller 3100 is coupled to memory device 3200. Controller 3100 accesses memory device 3200. For example, controller 3100 controls programming operations, reading operations, erasing operations, and background operations of memory device 3200. Controller 3100 provides an interface between memory device 3200 and the host. Controller 3100 can drive firmware used to control memory device 3200. For example, controller 3100 may include components such as random access memory (RAM), processing unit, host interface, memory interface, and ECC circuitry.

[0075] Controller 3100 communicates with external devices via connector 3300. Controller 3100 communicates with external devices, such as a host, based on a specific communication protocol. For example, controller 3100 uses at least one of the following communication protocols to communicate with external devices: Universal Serial Bus (USB), Multimedia Card (MMC), Embedded MMC (eMMC), Peripheral Component Interconnect (PCI), High-Speed ​​PCI (PCIE), Advanced Technology Attachment (ATA), Serial ATA (SATA), Parallel ATA (PATA), Small Computer System Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronics (IDE), FireWire, Universal Flash Memory (UFS), WiFi, Bluetooth, and High-Speed ​​Non-Volatile Memory (NVMe) protocols. For example, connector 3300 can be configured according to at least one of these communication protocols.

[0076] The memory device 3200 includes a plurality of memory cells, and corresponds to Figure 1 One of the chip regions CHA.

[0077] The controller 3100 and the memory device 3200 can be integrated into a single semiconductor device to form a memory card. For example, the controller 3100 and the memory device 3200 can be integrated into a single semiconductor device to form memory cards such as PCMCIA cards, compact flash memory (CF) cards, smart media cards (SM or SMC), memory sticks, multimedia cards (MMC, RS-MMC, MMCmicro or eMMC), SD cards (SD, mini SD, micro SD or SDHC), universal flash memory (UFS), etc.

[0078] Figure 7This is a block diagram illustrating a solid-state drive (SSD) system 4000 including a memory device according to one embodiment of the present disclosure.

[0079] Reference Figure 7 The SSD system 4000 includes a host 4100 and an SSD 4200. The SSD 4200 exchanges signals with the host 4100 through a signal connector 4001 and receives power through a power connector 4002. The SSD 4200 includes a controller 4210, multiple memory devices 4221 to 422n, an auxiliary power supply 4230, and a cache memory 4240.

[0080] Controller 4210 controls a plurality of memory devices 4221 to 422n in response to signals received from host 4100. For example, the signals are based on the interface between host 4100 and SSD 4200. For example, the signals can be constructed according to at least one of the following interfaces: Universal Serial Bus (USB), Multimedia Card (MMC), Embedded MMC (eMMC), Peripheral Component Interconnect (PCI), High-Speed ​​PCI (PCIE), Advanced Technology Attachment (ATA), Serial ATA (SATA), Parallel ATA (PATA), Small Computer System Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronics (IDE), FireWire, Universal Flash Memory (UFS), WiFi, Bluetooth, and High-Speed ​​Non-Volatile Memory (NVMe) interface.

[0081] The plurality of memory devices 4221 to 422n include a plurality of memory cells configured to store data. Each of the plurality of memory devices 4221 to 422n corresponds to Figure 1 One of the chip regions CHA. Multiple memory devices 4221 to 422n communicate with controller 4210 through channels CH1 to CHn.

[0082] Auxiliary power supply 4230 is connected to host 4100 via power connector 4002. Auxiliary power supply 4230 is powered and charged by host 4100. When host 4100 does not provide a steady or continuous power supply, auxiliary power supply 4230 provides power to SSD 4200. For example, auxiliary power supply 4230 may be located inside or outside SSD 4200. For example, auxiliary power supply 4230 may be located within the motherboard and provide auxiliary power to SSD 4200.

[0083] Buffer memory 4240 serves as a buffer for SSD 4200. For example, buffer memory 4240 stores data received from host 4100 or from multiple memory devices 4221 to 422n, or stores metadata (such as mapping tables) of memory devices 4221 to 422n. Buffer memory 4240 includes volatile memory such as DRAM, SDRAM, DDR SDRAM, and LPDDR SDRAM, or non-volatile memory such as FRAM, ReRAM, STT-MRAM, and PRAM.

[0084] According to one embodiment of this disclosure, by improving the process of forming a chip protector, the stress applied to a semiconductor device can be reduced by using a chip protector.

[0085] The concepts have been disclosed in conjunction with examples and embodiments. Those skilled in the art will understand that various modifications, additions, combinations, and substitutions are possible without departing from the scope and technical concepts of this disclosure. The embodiments disclosed in this specification should be considered from an illustrative rather than restrictive perspective. Therefore, the scope of this disclosure is not limited to these descriptions. All variations within the meaning and equivalent scope of the claims are included within the scope of this disclosure.

[0086] Cross-reference to related applications

[0087] This application claims priority to Korean Patent Application No. 10-2025-0054595, filed with the Korean Intellectual Property Office on April 25, 2025, the entire disclosure of which is incorporated herein by reference.

Claims

1. A semiconductor device, the semiconductor device comprising: Semiconductor chips; as well as A first chip protector surrounds the semiconductor chip; The first chip protection component includes: A plurality of columns, the plurality of columns being arranged along a first direction and extending in a second direction intersecting the first direction; A first protrusion extending from the plurality of posts along the first direction; and A second protrusion extends from the plurality of posts along the first direction and is spaced apart from the first protrusion along the second direction.

2. The semiconductor device according to claim 1, wherein, The first chip protector surrounds the semiconductor chip.

3. The semiconductor device according to claim 1, wherein, The first protrusion connects the plurality of posts in the first direction; and The second protrusion connects the plurality of posts in the first direction.

4. The semiconductor device according to claim 1, wherein, A portion of the first protrusion is located between the plurality of posts; and A portion of the second protrusion is located between the plurality of posts.

5. The semiconductor device according to claim 1, wherein, The first protrusion surrounds a portion of each of the plurality of pillars; and The second protrusion surrounds a portion of each of the plurality of pillars.

6. The semiconductor device according to claim 1, wherein, The second protrusion overlaps with the first protrusion in the second direction.

7. The semiconductor device according to claim 1, wherein, The plurality of columns includes: The first pillar; and The second column is spaced apart from the first column in the first direction.

8. The semiconductor device according to claim 7, wherein, The first protrusion includes: A first ring, extending from the side of the first post; and The second ring extends from the side of the second post.

9. The semiconductor device according to claim 8, wherein, The second protrusion includes: A third ring extends from the side of the first post and overlaps with the first ring; and The fourth ring extends from the side of the second post and overlaps with the second ring.

10. The semiconductor device of claim 1, further comprising a stacked member extending from the chip region to the protection region. in, The semiconductor chip is located in the chip region, and The chip protection component is located in the protected area.

11. The semiconductor device according to claim 10, wherein, The laminate includes a sacrificial layer that is alternately laminated with an interlayer insulation layer along the second direction within the protected area.

12. The semiconductor device according to claim 11, wherein, The plurality of pillars extend through the laminate in the second direction.

13. The semiconductor device according to claim 11, wherein, The first protrusion is located at a first height of the first sacrificial layer in the sacrificial layer, and the second protrusion is located at a second height of the second sacrificial layer in the sacrificial layer.

14. The semiconductor device according to claim 11, wherein, The outer surface of the first protrusion contacts the first sacrificial layer in the sacrificial layer; and Wherein, the first surface of the first protrusion contacts the first interlayer insulation layer in the interlayer insulation layer, and the second surface of the first protrusion contacts the second interlayer insulation layer in the interlayer insulation layer.

15. The semiconductor device according to claim 11, wherein, One of the interlayer insulating layers is located between the first protrusion and the second protrusion.

16. The semiconductor device according to claim 1, wherein, Each outer surface of the plurality of pillars, each outer surface of the first protrusion, and each outer surface of the second protrusion includes a curved surface.

17. The semiconductor device according to claim 1, wherein, In a third direction, the outer width of the first protrusion varies between a first width and a second width greater than the first width; and The third direction intersects with the first direction and the second direction.

18. The semiconductor device according to claim 17, wherein, The outer width of the first protrusion varies between the first width and the second width.

19. The semiconductor device according to claim 1, wherein, The first chip protection component includes a conductive material.

20. The semiconductor device of claim 1, further comprising a second chip protector surrounding the semiconductor chip and the first chip protector.

21. A method for manufacturing a semiconductor device, the method comprising the following steps: A stack comprising sacrificial layers alternately stacked with interlayer insulating layers is formed in the chip region and the protective region surrounding the chip region; An opening is formed in the protected area that extends through the laminate and is spaced apart from each other; The sacrificial layer exposed through the opening is etched to form a recess adjacent to the opening; as well as A chip protection element is formed within the opening and the recess.

22. The method according to claim 21, wherein, The openings are spaced apart from each other in a first direction and extend in a second direction intersecting the first direction.

23. The method according to claim 21, wherein, During the formation of the recess, a portion of each of the sacrificial layers is selectively etched from the side surface of the laminate exposed through the opening.

24. The method according to claim 21, wherein, During the formation of the recess, the sacrificial layer located between the openings is removed, so that the openings are connected to each other.

25. The method according to claim 21, wherein, The step of forming the chip protection element includes filling the opening and the recess with a conductive layer.

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