Semiconductor device structure and method of forming the same

Abstract

Semiconductor device structures and methods of forming the same are described. The structures include an insulating material disposed adjacent to a base portion, a source / drain region disposed above the base portion, a contact etch stop layer (CESL) disposed above the source / drain region, and a first interlayer dielectric (ILD) layer disposed above the insulating material and the CESL. The structures also include an etch stop layer disposed above a top surface of the CESL and a top surface of the first ILD layer, a second ILD layer disposed above the etch stop layer, and a conductive feature disposed below the source / drain region. The conductive feature includes a portion that is located below the gate electrode layer.

Description

Technical Field

[0001] Embodiments of this disclosure relate to semiconductor device structures and methods of forming the same. Background Technology

[0002] The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advancements in IC materials and design have resulted in multiple generations of ICs, each featuring smaller and more complex circuitry than the previous generation. In the evolution of ICs, functional density (i.e., the number of interconnect devices per chip area) typically increases, while geometry (i.e., the smallest component (or line) that can be created using manufacturing processes) decreases. This scaling down process generally provides benefits through increased production efficiency and reduced associated costs. However, this scaling down also increases the complexity of handling and manufacturing ICs.

[0003] Therefore, improvements are needed in IC processing and manufacturing. Summary of the Invention

[0004] Embodiments of this disclosure provide a method for forming a semiconductor device structure, comprising: forming an insulating material over a substrate; forming a source / drain region over the substrate, wherein the source / drain region comprises a first semiconductor material and a second semiconductor material, wherein the first semiconductor material and the second semiconductor material are doped with a dopant, wherein the concentration of the dopant in the first semiconductor material is different from the concentration of the dopant in the second semiconductor material, and in a cross-sectional view, the thickness of the source / drain region is different from the width of the source / drain region; depositing a contact etch stop layer over the source / drain region and the insulating material; depositing an interlayer dielectric layer over the contact etch stop layer and the insulating material, wherein the dielectric constant of the contact etch stop layer is greater than the dielectric constant of the insulating material or the interlayer dielectric layer; flipping the substrate; forming a first opening to expose an intermediate component, wherein the central axis of the first opening and the central axis of the intermediate component are spaced apart by a distance; selectively removing the intermediate component to form a second opening; and forming a conductive component in the first opening and the second opening.

[0005] Another embodiment of this disclosure provides a method for forming a semiconductor device structure, comprising: forming a source / drain region over a substrate portion, wherein the source / drain region comprises a first semiconductor material and a second semiconductor material, wherein the first semiconductor material and the second semiconductor material are doped with a dopant, the concentration of the dopant in the first semiconductor material is different from the concentration of the dopant in the second semiconductor material, and in a cross-sectional view, the thickness of the source / drain region is different from the width of the source / drain region; depositing a contact etch stop layer over the source / drain region; depositing a first interlayer dielectric (ILD) layer over the contact etch stop layer; and depositing a first interlayer dielectric (ILD) layer over the first interlayer dielectric layer. An etch stop layer is deposited over the top surface and the top surface of the contact etch stop layer; a second interlayer dielectric layer is deposited over the etch stop layer, wherein the thickness of the first interlayer dielectric layer is greater than the thickness of the second interlayer dielectric layer; the substrate is flipped; a first opening is formed to expose a first interfacing member, a first portion of the substrate portion is disposed on a first side of the first interfacing member, and a second portion of the substrate portion is disposed on a second side of the first interfacing member opposite to the first side, wherein the width of the first portion of the substrate portion is different from the width of the second portion of the substrate portion; the first interfacing member is removed to form a second opening; and conductive members are formed in the first opening and the second opening.

[0006] Another embodiment of this disclosure provides a semiconductor device structure, including: an insulating material disposed adjacent to a substrate portion; a source / drain region disposed above the substrate portion; a contact etch stop layer (CESL) disposed above the source / drain region; a first interlayer dielectric (ILD) layer disposed above the insulating material and the contact etch stop layer, wherein the dielectric constant of the contact etch stop layer is greater than the dielectric constant of the insulating material or the first interlayer dielectric layer; an etch stop layer disposed above the top surface of the contact etch stop layer and the top surface of the first interlayer dielectric layer; a second interlayer dielectric layer disposed above the etch stop layer, wherein the thickness of the first interlayer dielectric layer is greater than the thickness of the second interlayer dielectric layer; and a conductive component disposed below the source / drain region, wherein the conductive component includes a portion located below a gate electrode layer. Attached Figure Description

[0007] When read in conjunction with the accompanying drawings, aspects of this disclosure are best understood from the following detailed description. It should be noted that, in accordance with standard industry practice, the various components are not drawn to scale. In fact, for clarity of discussion, the dimensions of the individual components may be arbitrarily increased or decreased.

[0008] Figure 1 , Figure 2 , Figure 3 , Figure 4 and Figure 5 These are perspective views of various stages of manufacturing a semiconductor device structure according to some embodiments.

[0009] Figure 6 , Figure 7 , Figure 8 , Figure 9 , Figure 10 , Figure 11 , Figure 12 , Figure 13 and Figure 14 It is according to some embodiments along Figure 5 A cross-sectional side view of each stage of manufacturing a semiconductor device structure, taken from line AA.

[0010] Figure 15 It is according to some embodiments along Figure 5 The BB line is a cross-sectional side view of one of the various stages of manufacturing a semiconductor device structure.

[0011] Figure 16 It is according to some embodiments along Figure 5 A cross-sectional side view of one of the various stages of manufacturing a semiconductor device structure, taken by line AA.

[0012] Figure 17 , Figure 17-1 , Figure 18 , Figure 19 , Figure 20 , Figure 21 , Figure 22 and Figure 23 This is a cross-sectional side view of various stages of manufacturing a semiconductor device structure according to some embodiments.

[0013] Figure 24 , Figure 25 , Figure 26 , Figure 27 , Figure 28 and Figure 29 This is a cross-sectional side view of various stages of manufacturing a semiconductor device structure according to an alternative embodiment.

[0014] Figure 26-1 Based on some embodiments Figure 26 A top view of the opening formed on the semiconductor device structure shown. Detailed Implementation

[0015] The following disclosure provides numerous different embodiments or examples for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below to simplify this disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first component on or over a second component may include embodiments where the first and second components are formed in direct contact, and may also include embodiments where an additional component may be formed between the first and second components, such that the first and second components may not be in direct contact. Furthermore, reference numerals and / or letters may be repeated in various examples. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0016] Additionally, for ease of description, spatial relative terms such as “below,” “under,” “lower,” “above,” “above,” “on,” “top,” and “upper” may be used herein to describe the relationship between one element or component and another, as shown in the figures. Besides the orientations shown in the figures, spatial relative terms are intended to include different orientations of the device in use or operation. The device may be positioned in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein may be interpreted accordingly.

[0017] Terms indicating relative degree (such as “about”, “basically”, etc.) should be interpreted as terms that a person skilled in the art would understand in accordance with current technical specifications.

[0018] The term "surround" can be used in this document to describe a structure that completely or partially encloses another element or structure, such as in three-dimensional space. For example, a first structure may "surround" a second structure on four lateral sides (e.g., left, right, front, and back) but not on two vertical sides (e.g., top and bottom). In other examples, a first structure may partially enclose a second structure, for example, by enclosing three side surfaces (e.g., top, front, and back) while leaving other side surfaces (e.g., left, right, and bottom) exposed.

[0019] While embodiments of this disclosure are discussed with respect to nanostructured channel FETs, such as gate-all-around (GAA) FETs, such as horizontal gate-all-around (HGAA) FETs or vertical gate-all-around (VGAA) FETs, embodiments of some aspects of this disclosure can be used with other processes and / or other devices, such as planar FETs, FinFETs, and other suitable devices. It will be readily understood by those skilled in the art that other modifications are contemplated within the scope of this disclosure. When adapting to a gate-all-around (GAA) transistor structure, the GAA transistor structure can be patterned by any suitable method. For example, the structure can be patterned using one or more photolithography processes, including dual-patterning or multi-patterning processes. Typically, dual-patterning or multi-patterning processes combine photolithography and self-alignment processes, allowing the creation of patterns with, for example, smaller pitches than that achievable using a single direct photolithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a photolithography process. Spacers are formed alongside the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers can then be used to pattern the GAA structure.

[0020] Figures 1 to 23 A sequential process for manufacturing a semiconductor device structure 100 according to an embodiment of the present disclosure is shown. It should be understood that... Figures 1 to 23 Additional operations are provided before, during, and after the process shown, and some of the operations described below may be replaced or eliminated in other embodiments of the method. The order of operations / processes is not limiting and may be interchangeable.

[0021] Figures 1 to 5 These are perspective views illustrating various stages of manufacturing a semiconductor device structure according to some embodiments. For example... Figure 1 As shown, the semiconductor device structure 100 includes a stack 104 of semiconductor layers formed over the front side of a substrate 101. The substrate 101 may be a semiconductor substrate. The substrate 101 may include crystalline semiconductor materials such as, but not limited to, silicon (Si), germanium (Ge), silicon-germanium (SiGe), gallium arsenide (GaAs), indium antimonide (InSb), gallium phosphide (GaP), gallium antimonide (GaSb), indium aluminum arsenide (InAlAs), indium gallium arsenide (InGaAs), gallium antimony phosphide (GaSbP), gallium antimony arsenide (GaAsSb), and indium phosphide (InP). In some embodiments, the substrate 101 is a silicon-on-insulator (SOI) substrate having an insulating layer (not shown) disposed between two silicon layers for reinforcement. In one aspect, the insulating layer is an oxygen-containing layer.

[0022] The substrate 101 may include various regions that are already doped with impurities (e.g., dopants with p-type or n-type conductivity). Depending on the circuit design, the dopants may be, for example, phosphorus for p-type field-effect transistors (PFETs) and boron for n-type field-effect transistors (NFETs).

[0023] The semiconductor layer stack 104 includes alternating semiconductor layers made of different materials to facilitate the formation of nanostructured channels in multi-gate devices, such as nanostructured channel FETs. In some embodiments, the semiconductor layer stack 104 includes a first semiconductor layer 106 and a second semiconductor layer 108. In some embodiments, the semiconductor layer stack 104 includes alternating first semiconductor layer 106 and second semiconductor layer 108. The first semiconductor layer 106 and the second semiconductor layer 108 are made of semiconductor materials with different etch selectivity and / or oxidation rates. For example, the first semiconductor layer 106 may be made of Si, and the second semiconductor layer 108 may be made of SiGe. In some examples, the first semiconductor layer 106 may be made of SiGe, and the second semiconductor layer 108 may be made of Si. Optionally, in some embodiments, either of the semiconductor layers 106, 108 may be or include other materials such as Ge, SiC, GeAs, GaP, InP, InAs, InSb, GaAsP, AlInAs, AlGaAs, InGaAs, GaInP, GaInAsP, or any combination thereof.

[0024] The first semiconductor layer 106 and the second semiconductor layer 108 are formed by any suitable deposition process, such as epitaxy. For example, the epitaxial growth of the layers of the stack of semiconductor layers 104 can be performed by molecular beam epitaxy (MBE), metal-organic chemical vapor deposition (MOCVD), and / or other suitable epitaxial growth processes.

[0025] In a later manufacturing stage, the first semiconductor layer 106 or a portion thereof may form a nanostructured channel of the semiconductor device structure 100. The term nanostructure is used herein to refer to any portion of material having a nanoscale or even microscale size and having an elongated shape, regardless of the cross-sectional shape of that portion. Thus, the term refers to elongated material portions with circular and substantially circular cross-sections, as well as beam-shaped or strip-shaped material portions including, for example, cylindrical or substantially rectangular cross-sections. The nanostructured channel of the semiconductor device structure 100 may be surrounded by a gate electrode. The semiconductor device structure 100 may include a nanostructured transistor. A nanostructured transistor may be referred to as a nanosheet transistor, a nanowire transistor, a gate all-around (GAA) transistor, a multi-bridge channel (MBC) transistor, or any transistor having a gate electrode surrounding the channel. The use of the first semiconductor layer 106 to define one or more channels of the semiconductor device structure 100 is further discussed below.

[0026] Each first semiconductor layer 106 may have a thickness ranging from about 3 nm to about 30 nm. The thickness of each second semiconductor layer 108 may be equal to, less than, or greater than the thickness of the first semiconductor layer 106. In some embodiments, the thickness of each second semiconductor layer 108 is in the range of about 2 nm to about 50 nm. Figure 1 As shown, three first semiconductor layers 106 and three second semiconductor layers 108 are arranged alternately for illustrative purposes and are not intended to limit the specific references in the claims. It will be understood that any number of first semiconductor layers 106 and second semiconductor layers 108 can be formed in the semiconductor layer stack 104, and the number of layers depends on a predetermined number of channels in the semiconductor device structure 100. In some embodiments, the semiconductor layer stack 104 includes two first semiconductor layers 106. In some embodiments, the semiconductor layer stack 104 includes three first semiconductor layers 106. In some embodiments, the semiconductor layer stack 104 includes four first semiconductor layers 106.

[0027] like Figure 2 As shown, fin structures 112 are formed from a stack of semiconductor layers 104. Each fin structure 112 has an upper portion including semiconductor layers 106, 108 and a base portion 116 formed from a substrate 101. The fin structures 112 can be formed by patterning a hard mask layer (not shown) formed on the stack of semiconductor layers 104 using multiple patterning operations including photolithography and etching processes. The etching process can include dry etching, wet etching, reactive ion etching (RIE), and / or other suitable processes. The photolithography process can include forming a photoresist layer (not shown) over the hard mask layer, exposing the photoresist layer to a pattern, performing a post-exposure baking process, and developing the photoresist layer to form a masking element including the photoresist layer. In some embodiments, an electron beam (e-beam) lithography process can be used to perform patterning of the photoresist layer to form the masking element. The etching process forms trenches 114 in unprotected areas, the trenches 114 passing through the hard mask layer, through the stack of semiconductor layers 104, and into the substrate 101, thereby leaving a plurality of extended fin structures 112. The groove 114 extends along the X direction.

[0028] like Figure 3As shown, after forming the fin structure 112, an insulating material 118 is formed on the substrate 101. The insulating material 118 fills the trenches 114 between adjacent fin structures 112 until the fin structures 112 are embedded in the insulating material 118. A planarization operation, such as a chemical mechanical polishing (CMP) method and / or an etch-back method, is then performed to expose the top of the fin structure 112. The insulating material 118 may be made of silicon oxide, silicon nitride, silicon oxynitride (SiON), SiOCN, SiCN, fluorine-doped silicate glass (FSG), a low-k dielectric material, or any suitable dielectric material. The insulating material 118 may be formed by any suitable method, such as low-pressure chemical vapor deposition (LPCVD), plasma-enhanced CVD (PECVD), or flowable CVD (FCVD). In some embodiments, the insulating material 118 has a dielectric constant of about 3 to about 5.

[0029] like Figure 4 As shown, insulating material 118 is recessed to form isolation region 120. The recess in insulating material 118 exposes portions of fin structures 112, such as the stack of semiconductor layers 104. The recess in insulating material 118 exposes trenches 114 between adjacent fin structures 112. Isolation region 120 can be formed using suitable processes, such as dry etching, wet etching, or combinations thereof. The top surface of insulating material 118 may be flush with or below the surface of the second semiconductor layer 108 that contacts the base portion 116 formed by substrate 101. In some embodiments, isolation region 120 is a shallow trench isolation (STI) region.

[0030] like Figure 5 As shown, one or more sacrificial gate structures 130 (only one is shown) are formed over the semiconductor device structure 100. The sacrificial gate structure 130 is formed over a portion of the fin structure 112. Each sacrificial gate structure 130 may include a sacrificial gate dielectric layer 132, a sacrificial gate electrode layer 134, and a mask layer 136. The sacrificial gate dielectric layer 132, the sacrificial gate electrode layer 134, and the mask layer 136 can be formed by sequentially depositing a blanket layer of the sacrificial gate dielectric layer 132, the sacrificial gate electrode layer 134, and the mask layer 136, and then patterning these layers into the sacrificial gate structure 130. Although one sacrificial gate structure 130 is shown, in some embodiments, two or more sacrificial gate structures may be arranged along the X direction.

[0031] The sacrificial gate dielectric layer 132 may include one or more dielectric materials, such as silicon oxide-based materials. The sacrificial gate electrode layer 134 may include silicon, such as polycrystalline silicon or amorphous silicon. The mask layer 136 may include more than one layer, such as an oxide layer and a nitride layer. The portion of the fin structure 112 covered by the sacrificial gate electrode layer 134 of the sacrificial gate structure 130 serves as a channel region for the semiconductor device structure 100.

[0032] Figures 6 to 14 It is according to some embodiments along Figure 5 The image shows a cross-sectional side view of each stage of manufacturing the semiconductor device structure 100, taken from line AA. Figure 6 As shown, a first gate spacer 138 is deposited on an exposed surface of the semiconductor device structure 100. For example, the first gate spacer 138 is deposited on the fin structure 112, the isolation region 120, and the sacrificial gate structure 130. The first gate spacer 138 may be made of a dielectric material such as silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, SiCN, silicon oxycarbide, SiCON, and / or combinations thereof. The first gate spacer 138 may be formed by any suitable process. In some embodiments, the first gate spacer 138 is a conformal layer formed by a conformal process such as atomic layer deposition (ALD).

[0033] like Figure 7 As shown, the second gate spacer 139 is deposited on the first gate spacer 138. The second gate spacer 139 may include any suitable dielectric material, such as SiO2. x The second gate spacer 139 may be made of SiON, SiN, SiCON, or SiCO. The second gate spacer 139 may have a thickness ranging from about 0.5 nm to about 5 nm. The second gate spacer 139 may be formed by any suitable process. In some embodiments, the second gate spacer 139 is deposited by CVD, PECVD, or electron cyclotron resonance CVD (ECR-CVD).

[0034] like Figure 8 As shown, the horizontal portions of the first gate spacer 138 and the second gate spacer 139 are removed. In some embodiments, the horizontal portions of the first gate spacer 138 and the second gate spacer 139 are removed by an anisotropic etching process. The anisotropic etching process can be a selective etching process that substantially does not affect the mask layer 136, the stack of semiconductor layers 104, and the isolation region 120.

[0035] like Figure 9 As shown, the portion of the fin structure 112 not covered by the sacrificial gate structure 130 and the first gate spacer 138 and the second gate spacer 139 is recessed to a level above, below, or on the top surface of the isolation region 120. This recessing of the fin structure 112 can be accomplished by an etching process. The etching process can be dry etching (such as RIE, NBE, etc.) or wet etching (such as using tetramethylammonium hydroxide (TMAH), ammonium hydroxide (NH4OH), or any suitable etchant). Figure 9 As shown, the substrate portion 116 is exposed on the opposite side of the sacrificial gate structure 130.

[0036] like Figure 10 As shown, edge portions of each second semiconductor layer 108 of the semiconductor layer stack 104 are removed horizontally along the X direction. Removing the edge portions of the second semiconductor layer 108 forms cavities. In some embodiments, portions of the second semiconductor layer 108 are removed by a selective wet etching process. When the second semiconductor layer 108 is made of SiGe and the first semiconductor layer 106 is made of silicon, the second semiconductor layer 108 can be selectively etched using a wet etchant, such as, but not limited to, ammonium hydroxide (NH4OH), tetramethylammonium hydroxide (TMAH), ethylenediamine catechol (EDP), or potassium hydroxide (KOH) solution.

[0037] After removing the edge portions of each second semiconductor layer 108, a dielectric layer is deposited in the cavity to form dielectric spacers 144. The dielectric spacers 144 can be made of a low-k dielectric material, such as SiON, SiCN, SiOC, SiOCN, or SiN. The dielectric spacers 144 can be formed by first forming a conformal dielectric layer using a conformal deposition process (such as ALD), followed by anisotropic etching to remove portions of the conformal dielectric layer other than the dielectric spacers 144. During the anisotropic etching process, the dielectric spacers 144 are protected by the first semiconductor layer 106. The remaining second semiconductor layer 108 covers the spacers 144 along the X-direction.

[0038] In some embodiments, instead of laterally recessing the second semiconductor layer 108, the entire second semiconductor layer 108 is removed to create an opening between vertically adjacent first semiconductor layers 106. A dielectric layer (not shown) is formed in the opening between the vertically adjacent first semiconductor layers 106, and the dielectric layer is laterally recessed to form a cavity. Dielectric spacers 144 are then formed in the cavity, and the dielectric layer covers the spacers 144 along the X direction. In some embodiments, the dielectric layer is an oxide formed by an ALD, CVD, or FCVD process. In some embodiments, the oxide is carbon-containing silicon oxide. In some embodiments, the dielectric layer and the isolation region 120 comprise the same material.

[0039] like Figure 11As shown, a first interposer 150 is formed on an exposed substrate portion 116. The first interposer 150 may be formed adjacent to the substrate portion 116 located below the bottommost second semiconductor layer 108. In some embodiments, the first interposer 150 comprises a material different from that of the substrate portion 116. In some embodiments, the first interposer 150 comprises undoped SiGe, and the substrate portion 116 comprises silicon. The term undoped may include unintentionally doped material. For example, the first interposer 150 may contain dopants diffused from other regions, such as the substrate portion 116. The first interposer 150 may first be formed on a semiconductor surface (such as on the exposed substrate portion 116) and on the semiconductor layer 106 by epitaxy. In some embodiments, the first interposer 150 is crystalline SiGe. A subsequent etching process is performed to remove portions of the first interposer 150 formed on the first semiconductor layer 106. In some embodiments, the first interposer 150 has a thickness ranging from about 20 nm to about 80 nm along the Z direction.

[0040] like Figure 12 As shown, a second interposer 152 is formed on a first interposer 150. The second interposer 152 can be formed by first forming a layer on an exposed surface of the semiconductor device structure 100, followed by one or more etching processes to remove portions of that layer other than the second interposer 152. A sacrificial layer (not shown) (such as a bottom antireflective coating (BARC) layer) can be used to help remove portions of that layer formed on the sidewalls of the second gate spacer 139, the first semiconductor layer 106, and the dielectric spacer 144. The second interposer 152 can include any suitable material. In some embodiments, the second interposer 152 includes a dielectric material such as SiN or SiOCN. The second interposer 152 can be formed by any suitable process. In some embodiments, the second interposer 152 is formed by ALD, CVD, or PECVD. In some embodiments, both the first interposer 150 and the second interposer 152 are present, as shown in the image. Figure 12 As shown. In some embodiments, the second intermediary component 152 is optional.

[0041] Next, as Figure 12As shown, a first semiconductor material 154 is formed from a first semiconductor layer 106. The first semiconductor material 154 may be made of one or more layers of Si, SiP, SiC, SiAs, SiSb, and SiCP for an n-channel FET, or of one or more layers of Si, SiGe, and Ge for a p-channel FET. For a p-channel FET, the first semiconductor material 154 may include a p-type dopant, such as boron (B). For an n-channel FET, the first semiconductor material 154 may include an n-type dopant, such as phosphorus (P) or arsenic (As). In some embodiments, the dopant concentration of the first semiconductor material 154 may range from about 1 x 10⁻⁶. 19 cm -3 To approximately 2 x 10 21 cm -3 Within this range, the first semiconductor material 154 can be formed using epitaxial growth methods such as CVD, ALD, or MBE. For example... Figure 12 As shown, in some embodiments, the first semiconductor material 154 is selectively formed on a semiconductor material (such as the first semiconductor layer 106) and not on a dielectric material (such as the second interposer 152 and the dielectric spacer 144). In some embodiments, the first semiconductor material 154 includes a facet that may correspond to a crystal plane of the material used for the first semiconductor layer 106.

[0042] Next, as Figure 12 As shown, a second semiconductor material 156 is formed from a first semiconductor material 154. The second semiconductor material 156 can be formed using epitaxial growth methods such as CVD, ALD, or MBE. The second semiconductor material 156 can be made of one or more layers of Si, SiP, SiC, and SiCP (for n-type FETs) or Si, SiGe, and Ge (for p-type FETs). For p-type FETs, the second semiconductor material 156 may include p-type dopants, such as boron (B). For n-type FETs, the second semiconductor material 156 may include n-type dopants, such as phosphorus (P) or arsenic (As). In some embodiments, the first semiconductor material 154 and the second semiconductor material 156 may include the same semiconductor material, but with different dopant concentrations. The dopant concentration of the second semiconductor material 156 can be substantially greater than the dopant concentration of the first semiconductor material 154. In some embodiments, the dopant concentration of the second semiconductor material 156 can be from about 5 x 10⁻⁶. 19 cm -3 To approximately 4 x 10 21 cm -3 Within the range, the second semiconductor material 156 can be epitaxially grown from the first semiconductor material 154.

[0043] The first semiconductor material 154 and the second semiconductor material 156 together can be a source / drain (S / D) region 146. In this disclosure, the source region and the drain region are used interchangeably, and their structures are substantially the same. Furthermore, depending on the context, the source / drain region can refer individually or collectively to the source or drain. In some embodiments, the p-type S / D region 146 and the n-type S / D region 146 can be formed separately using one or more mask layers. In some embodiments, the first semiconductor material 154 and the second semiconductor material 156 are crystalline semiconductor materials.

[0044] Next, as Figure 12 As shown, a contact etch stop layer (CESL) 162 is conformally formed on the exposed surface of the semiconductor device structure 100. CESL 162 covers the second gate spacer 139, the isolation region 120, and the second semiconductor material 156. CESL 162 may comprise an oxygen-containing or nitrogen-containing material, such as silicon nitride, silicon nitride carbon, silicon oxynitride, carbon nitride, silicon oxide, silicon oxide carbon, or combinations thereof, and may be formed by CVD, PECVD, ALD, or any suitable deposition technique. In some embodiments, CESL 162 is a single layer, such as... Figure 12 As shown. In some embodiments, CESL 162 comprises two or more layers. Next, an interlayer dielectric (ILD) layer 164 is formed on CESL 162. The material used for ILD layer 164 may include compounds comprising Si, O, C and / or H, such as silicon oxide, SiCOH, or SiOC. Organic materials, such as polymers, may also be used for ILD layer 164. ILD layer 164 may be deposited by a PECVD process or other suitable deposition techniques. In some embodiments, after the formation of ILD layer 164, the semiconductor device structure 100 may undergo a thermal process to anneal ILD layer 164. In some embodiments, the dielectric constant of CESL 162 is greater than the dielectric constant of insulating material 118 or ILD layer 164.

[0045] like Figure 12 As shown, after the formation of the ILD layer 164, a planarization operation, such as CMP, is performed on the semiconductor device structure 100 until the sacrificial gate electrode layer 134 is exposed.

[0046] Next, as Figure 13As shown, the sacrificial gate structure 130 and the second semiconductor layer 108 are removed. The removal of the sacrificial gate structure 130 and the semiconductor layer 108 forms an opening between the first gate spacer 138 and the first semiconductor layer 106. The ILD layer 164 protects the second semiconductor material 156 during the removal process. The sacrificial gate structure 130 can be removed using plasma dry etching and / or wet etching. The sacrificial gate electrode layer 134 can be removed first by any suitable process, such as dry etching, wet etching, or a combination thereof, followed by the removal of the sacrificial gate dielectric layer 132, which can also be performed by any suitable process, such as dry etching, wet etching, or a combination thereof. In some embodiments, a wet etchant such as a tetramethylammonium hydroxide (TMAH) solution can be used to selectively remove the sacrificial gate electrode layer 134, but not the first gate spacer 138, the ILD layer 164, and the CESL 162.

[0047] The second semiconductor layer 108 can be removed using a selective wet etching process. When the second semiconductor layer 108 is made of SiGe and the first semiconductor layer 106 is made of Si, the chemicals used in the selective wet etching process remove the SiGe while substantially not affecting the Si, the dielectric material of the first gate spacer 138, and the dielectric spacer 144. In one embodiment, the second semiconductor layer 108 can be removed using a wet etchant, such as, but not limited to, hydrofluoric acid (HF), nitric acid (HNO3), hydrochloric acid (HCl), or phosphoric acid (H3PO4).

[0048] like Figure 14As shown, after forming the nanostructured channel (i.e., the exposed portion of the first semiconductor layer 106), a gate dielectric layer 170 is formed to surround the exposed portion of the first semiconductor layer 106, and a gate electrode layer 172 is formed on the gate dielectric layer 170. The gate dielectric layer 170 and the gate electrode layer 172 may be collectively referred to as the gate structure 174. In some embodiments, an interface layer (IL) 168 is formed between the gate dielectric layer 170 and the exposed surface of the first semiconductor layer 106. The IL 168 may include an oxide, such as silicon oxide. In some embodiments, the gate dielectric layer 170 includes one or more layers of dielectric material, such as silicon oxide, silicon nitride, or a high-k dielectric material, other suitable dielectric materials, and / or combinations thereof. Examples of high-k dielectric materials include HfO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, zirconium oxide, alumina, titanium oxide, hafnium dioxide-alumina (HfO2-Al2O3) alloys, other suitable high-k dielectric materials, and / or combinations thereof. The gate dielectric layer 170 may be formed by CVD, ALD, or any suitable deposition technique. The gate electrode layer 172 may comprise one or more layers of conductive materials, such as polysilicon, hafnium, zirconium, platinum, palladium, ytterbium, silver, ruthenium, chromium, aluminum, copper, titanium, tantalum, tungsten, cobalt, molybdenum, tantalum nitride, nickel silicide, cobalt silicide, TiN, WN, TiAl, TiAlN, TaCN, TaC, TaSiN, metal alloys, or similar materials and / or any combination thereof. The gate electrode layer 172 may be formed by CVD, ALD, electroplating, or other suitable deposition techniques. The gate electrode layer 172 can also be deposited above the upper surface of the ILD layer 164. The gate dielectric layer 170 and the gate electrode layer 172 formed above the ILD layer 164 are then removed by means of, for example, CMP, until the top surface of the ILD layer 164 is exposed.

[0049] Figure 15 It is according to some embodiments along Figure 5 A cross-sectional side view of one of the various stages of manufacturing a semiconductor device structure 100, taken from line BB. Figure 15 It shows the relationship with Figure 14 The semiconductor device structure 100 shown is at the same manufacturing stage as the semiconductor device structure 100. In some embodiments, such as Figure 15 As shown in the cross-sectional view, the thickness of the S / D region 146 (the combination of the thicknesses of the first semiconductor material 154 and the second semiconductor material 156) is different from the width of the S / D region 46 (the combination of the widths of the first semiconductor material 154 and the second semiconductor material 156).

[0050] Figure 16 It is according to some embodiments along Figure 5 A cross-sectional side view of one of the various stages of manufacturing a semiconductor device structure 100, taken by line AA. (See also...) Figure 16 As shown, conductive contact 180 is formed in ILD layer 164 and CESL 162. Conductive contact 180 can be electrically coupled to S / D region 146 via silicide layer 182. Conductive contact 180 can include any suitable conductive material. In some embodiments, conductive contact 180 can include tungsten (W), platinum (Pt), tantalum (Ta), titanium (Ti), copper (Cu), cobalt (Co), ruthenium (Ru), rhodium (Rh), iridium (Ir), molybdenum (Mo), or other suitable metals. In some embodiments, the conductivity of conductive contact 180 is greater than the conductivity of S / D region 146 (i.e., semiconductor materials 154, 156). Silicate layer 182 can include any suitable material, such as titanium silicide, cobalt silicide, nickel silicide, tungsten silicide, copper silicide, or molybdenum silicide.

[0051] Next, as Figure 16 As shown, an etch stop layer 184 is deposited over the ILD layer 164, conductive contact 180, and gate structure 174, and another ILD layer 186 is deposited over the etch stop layer 184. In some embodiments, the etch stop layer 184 may comprise the same material as CESL 162 and may be formed using the same process as CESL 162. The ILD layer 186 may comprise the same material as ILD layer 164 and may be formed using the same process as ILD layer 164. In some embodiments, the thickness of ILD layer 164 is greater than the thickness of ILD layer 186. A conductive component 188 is formed in the ILD layer 186 and the etch stop layer 184. The conductive component 188 may comprise a conductive material, such as a metal. In some embodiments, the conductive component 188 comprises tungsten (W), platinum (Pt), tantalum (Ta), titanium (Ti), copper (Cu), cobalt (Co), ruthenium (Ru), rhodium (Rh), iridium (Ir), molybdenum (Mo), or other suitable metals. Figure 16 As shown, the conductive component 188 is electrically coupled to the conductive contact 180.

[0052] It should be understood that interconnect structures (not shown) may be formed over the ILD layer 186 and the conductive components 188. The interconnect structures may include conductive components, such as wires and conductive vias, embedded in a dielectric layer (such as an inter-metal dielectric (IMD) layer). After the interconnect structures are formed, the semiconductor device structure 100 is flipped for back-side processing.

[0053] Figure 17 , Figure 17-1 , Figure 18 , Figure 19 , Figure 20 , Figure 21 , Figure 22 and Figure 23This is a cross-sectional side view of various stages of manufacturing a semiconductor device structure 100 according to some embodiments. For clarity, details are omitted. Figure 16 The top portion of the semiconductor device structure 100 shown. (As shown) Figure 17 As shown, after flipping the semiconductor device structure 100, the substrate 101 is thinned. The substrate 101 can be thinned using a polishing process. In some embodiments, the substrate 101 is removed. After thinning or removing the substrate 101, the substrate portion 116 is exposed. In some embodiments, an insulating material 118 ( Figure 15 It was also exposed.

[0054] like Figure 17 As shown, after thinning the substrate 101, the substrate portion 116 has a top surface 202. In some embodiments, as Figure 17 As shown, a portion of the substrate portion 116 disposed above the first interposer 150 has a thickness T1, the first interposer 150 has a thickness T2, and the substrate portion 116 has a thickness T3. In some embodiments, the thickness T1 is in the range of about 0.5 nm to about 20 nm. In some embodiments, thinning of the substrate 101 exposes the first interposer 150. As a result, the thickness T1 is 0 nm. The thickness T2 can be in the range of about 20 nm to about 80 nm. In some embodiments, the thickness T3 is greater than about 40 nm, such as from about 45 nm to about 100 nm. In some embodiments, the thickness T2 is greater than the thickness T1, so that a subsequent selective etching process to remove the first interposer 150 has substantially no effect on the substrate portion 116. In some embodiments, the ratio of thickness T1 to thickness T2 is between about 0.1:1 and 0.95:1, such as between about 0.1:1 and 0.5:1. In some embodiments, the thickness T2 is about 50% to about 100% of the thickness T3. If the thickness T2 is less than 50% of the thickness T3, the subsequent selective etching process may remove the substrate portion 116 and damage the dielectric spacer 144.

[0055] like Figure 17 As shown, after thinning the substrate 101, a first mask layer 204 is formed on the top surface 202 of the substrate portion 116, and a second mask layer 206 is formed on the first mask layer 204. In some embodiments, the first mask layer 204 is a nitride layer, and the second mask layer 206 is an oxide layer.

[0056] In some embodiments, such as Figure 17-1 As shown, the thinning of substrate 101 exposes the first intermediate component 150. In such an embodiment, thicknesses T2 and T3 are substantially the same, and thickness T1 is 0 nm. In some embodiments, as Figure 17-1 As shown, the first mask layer 204 is deposited on the substrate portion 116 and the first intermediate component 150.

[0057] Next, in some embodiments, such as Figure 18 As shown, an opening 208 is formed in the first mask layer 204 and the second mask layer 206, and the opening 208 extends into the substrate portion 116 to expose the first intermediate member 150. Patterned photoresist (not shown) may be formed over the second mask layer 206, and the pattern of the photoresist may be transferred to the first mask layer 204 and the second mask layer 206. In some embodiments, the opening 208 may be formed by multiple etching processes. For example, a first etching process is performed to remove a portion of the second mask layer 206 to expose a portion of the first mask layer 204, a second etching process is performed to remove the exposed portion of the first mask layer 204 to expose a portion of the substrate portion 116, and a third etching process is performed to recess the exposed portion of the substrate portion 116. The first, second, and third etching processes may be selective etching processes. In some embodiments, the third etching process that recesses the exposed portion of the substrate portion 116 is an isotropic etching process. The third etching process may be a dry etching process or a wet etching process. In some embodiments, the third etching process is a dry etching process and does not have bias power. Figure 17-1 In the illustrated embodiment, the substrate portion 116 and the first interposer 150 are exposed after a second etching process that removes the exposed portion of the first mask layer 204. Therefore, a third etching process is not required to expose the first interposer 150.

[0058] In some embodiments, such as Figure 18 As shown, opening 208 has a top critical dimension (TCD) defined by the sidewalls of the second mask layer 206. In some embodiments, the sidewalls of the second mask layer 206 are not substantially straight, and the TCD may be the average of the critical dimensions of the portion of opening 208 defined by the second mask layer 206. Figure 18As shown, the first intermediary member 150 may have a maximum width W1. In some embodiments, the width of the first intermediary member 150 varies along the X direction, and the width W1 represents the maximum width of the first intermediary member 150 along the X direction. In some embodiments, the TCD is in the range of about 10 nm to about 50 nm, and the width W1 is in the range of about 10 nm to about 50 nm. The TCD may be greater than the width W1. In some embodiments, the ratio of TCD to width W1 is between about 1.1:1 and 5:1. In some embodiments, the opening 208 is aligned with the first intermediary member 150 along the Z direction. In other words, the central axis of the opening 208 is also the central axis of the first intermediary member 150. In some embodiments, the opening 208 is not aligned with the first intermediary member 150, such that the central axis of the opening 208 and the central axis of the first intermediary member 150 are spaced apart along the X direction. In some embodiments, the distance between the central axis of the opening 208 and the central axis of the first intermediary member 150 along the X direction is in the range of about 0 nm to about 20 nm, such as from about 1 nm to about 20 nm.

[0059] In some embodiments, such as Figure 18 As shown, the TCD of opening 208 is larger than the width W1 of the first intermediary member 150, and due to the coverage offset, opening 208 is not aligned with the first intermediary member 150. Figure 18 As shown, the portion 116a of the base portion 116 adjacent to the first intermediate member 150 and located below the opening 208 may have a width W2. In some embodiments, the width W2 is less than or equal to 40 nm, such as from about 0.1 nm to about 40 nm. In some embodiments, such as Figure 18 As shown, part 116a has a basically horizontal top surface 116at.

[0060] Next, as Figure 19As shown, the first intermediate component 150 is removed to form the opening 210. The first intermediate component 150 can be removed by a selective etching process. In some embodiments, the first intermediate component 150 comprises SiGe, and the selective etching process uses a fluorinated etchant, such as F2 and / or HF. For example, F2 gas flows into the processing chamber and selectively adsorbs onto the SiGe of the first intermediate component 150. The F2 then reacts with the SiGe of the first intermediate component 150 to form GeF3 and SiF3, which are then desorbed from the first intermediate component 140. In some embodiments, F2 gas and HF gas flow into the processing chamber and selectively adsorb onto the SiGe of the first intermediate component 150. The F2 and HF then react with the SiGe of the first intermediate component 150 to form GeH2F and SiHF2. GeH2F and SiHF2 react to form SiF2 and GeH3F, which are then desorbed from the first intermediate component 150. Other suitable selective etching processes can be performed to selectively remove the first intermediate component 150 without substantially affecting the substrate portion 116. Thus, in some embodiments, portion 116a of the substrate portion 116 is substantially unaffected and remains below the opening 208.

[0061] In some embodiments, such as Figure 19 As shown, opening 208 has a bottom, and opening 210 is formed in a first portion of the bottom, while a second portion of the bottom is the top surface 116at of portion 116a of base portion 116. In some embodiments, the critical size of opening 210 is smaller than the critical size of opening 208. Therefore, it may be difficult to use conductive component 220 ( Figure 22 The two openings 208 and 210 are filled. For example, the bottom of opening 208 may be clamped before opening 210 is filled. As a result, a void or air gap may form in opening 210, which increases resistance. In some embodiments, such as Figure 19 As shown, after the first intermediary member 150 is removed, a portion 116a of the base portion 116 includes a top surface 116at and a side surface 116as, and an angle A is formed between the top surface 116at and the side surface 116as. In some embodiments, angle A is an acute angle, such as an acute angle. For example, angle A can be in the range of about 30 degrees to about 90 degrees.

[0062] In some embodiments, such as Figure 19 As shown, the opening 210 has a top portion with a critical dimension CD1 and a bottom portion with a critical dimension CD2. In some embodiments, the critical dimension CD2 is substantially larger than the critical dimension CD1.

[0063] In some embodiments, such as Figure 20As shown, the bottom of opening 208 can be recessed to enlarge the critical size of opening 210, thereby improving the filling of openings 208 and 210. In other words, a portion 116a of the base portion 116 can be recessed to enlarge opening 210. In some embodiments, the portion 116a of the base portion 116 can be recessed by a selective etching process. In some embodiments, the selective etching process is a plasma etching process. The plasma etching process has a plasma power in the range of about 50 W to about 1000 W and a bias power in the range of about 50 W to about 1000 W. The processing pressure of the plasma etching process can be in the range of about 3 mT to about 100 mT. The etchant used in the plasma etching process can be different from the etchant used in the selective etching process for removing the first intermediate component 150. In some embodiments, the etchant used in the plasma etching process can be CH2F2 and / or CH3F. The flow rate of CH2F2 can be in the range of about 3 standard cubic centimeters per minute (sccm) to about 100 sccm. In some embodiments, other gases (such as carrier gas and / or passivation gas) may co-flow with the etchant. The carrier gas may include N2 or Ar and may have a flow rate ranging from about 50 sccm to about 1000 sccm. The passivation gas may include O2 and may have a flow rate ranging from about 3 sccm to about 100 sccm.

[0064] The plasma etching process that recesses portion 116a of the substrate portion 116 can be combined with Figure 18 The third etching process described herein, which recesses the exposed substrate portion 116, differs from that of the third etching process. The third etching process removes a portion of the substrate portion 116 to expose the first intermediate member 150. In some embodiments, the thickness T2 of the first intermediate member 150 is in the range of about 20 nm to about 80 nm, thus reducing the risk of damage to the dielectric spacer 144 due to over-etching in the third etching process. However, when a plasma etching process is performed to recess the portion 116a, the portion of the substrate portion 116 in contact with the dielectric spacer 144 is exposed at the bottom of the opening 210. Therefore, the plasma etching process is more anisotropic than the third etching process to avoid damage to the dielectric spacer 144. For example, in some embodiments, the third etching process is an isotropic etching process, and the plasma etching process is an anisotropic etching process. Furthermore, the plasma power and etchant flow rate of the plasma etching process can be lower than those of the third etching process to avoid over-etching.

[0065] In some embodiments, portion 116a of the base portion 116 located near the opening 210 is composed of Figure 20 The vertical line V and the horizontal line H are shown to define the boundaries. In some embodiments, such as Figure 20As shown, portions of the top surface 116at and side surfaces 116as are removed, and the remaining side surfaces 116as are substantially smooth without any sharp angles. In some embodiments, the remaining side surfaces 116as are curved and have a convex or concave profile.

[0066] In some embodiments, the plasma etching process is a selective etching process that substantially does not affect the second mask layer 206 and the second intermediate component 152.

[0067] Next, as Figure 20 As shown, another selective etching process is performed to remove at least a portion of the second intermediate component 152 to expose the S / D region 146. The selective etching process may substantially have no effect on the second mask layer 206 and the substrate portion 116.

[0068] like Figure 21 As shown, dielectric layer 212 is formed on the side surfaces of the second mask layer 206, the first mask layer 204, and the substrate portion 116. Dielectric layer 212 may include any suitable dielectric material. In some embodiments, dielectric layer 212 includes SiN. Dielectric layer 212 can be formed by first depositing dielectric layer 212 in the openings 208, 210 and over the second mask layer 206, and then performing an anisotropic etching process to remove portions of dielectric layer 212 formed on the horizontal surface. Dielectric layer 212 can be deposited by any suitable method, such as ALD or CVD.

[0069] Next, as Figure 22 As shown, conductive components 220 are formed to fill openings 208 and 210. Conductive components 220 may include tungsten (W), platinum (Pt), tantalum (Ta), titanium (Ti), copper (Cu), cobalt (Co), ruthenium (Ru), rhodium (Rh), iridium (Ir), molybdenum (Mo), or other suitable metals. In some embodiments, conductive components 220 include a liner, such as a TiN or TaN layer. In some embodiments, conductive components 220 are electrically coupled to the S / D region 146 via a silicide layer 222. The silicide layer 222 may include the same material as the silicide layer 182.

[0070] like Figure 23 As shown, a planarization process is performed to remove portions of the conductive component 220 formed above the second mask layer 206 and the second mask layer 206. The planarization process can be a CMP process. After the CMP process, the top surfaces of the first mask layer 204 and the conductive component 220 are substantially coplanar. In some embodiments, such as... Figure 23As shown, due to the overlay offset, the conductive component 220 includes a top portion 220a located directly above the gate structure 174. In some embodiments, the conductive component 220 is monolithic. Because the first interposer 150 and the substrate portion 116 comprise different materials, the selective etching process for removing the first interposer 150 substantially does not affect the substrate portion 116. As a result, the dielectric spacer 144 is not damaged. Furthermore, a portion 116a of the substrate portion 116 is recessed to improve gap filling of the conductive component 220 in the openings 208, 210.

[0071] Figure 24 , Figure 25 , Figure 26 , Figure 27 , Figure 28 and Figure 29 This is a cross-sectional side view of various stages of manufacturing the semiconductor device structure 100 according to an optional embodiment. In some embodiments, such as Figure 24 As shown, due to the coverage offset, the opening 208 partially overlaps with the first interposer 150. The portion of the first interposer 150 exposed in the opening 208 has a width W3. In some embodiments, the width W3 is in the range of about 5 nm to about 50 nm. If the width W3 is less than about 5 nm, a subsequent selective etching process to remove the first interposer 150 may not completely remove it due to the small opening at the bottom of the opening 208. As mentioned above, the maximum width of the first interposer 150 can be in the range of about 10 nm to about 50 nm. Next, as... Figure 25 As shown, a selective etching process is performed to remove the first intermediate component 150 and form the opening 210. Due to the larger coverage offset, portion 116a of the substrate portion 116 is larger than... Figure 19 Part 116a is shown. Next, execute... Figure 20 The plasma etching process described herein causes portion 116a to be recessed, thus removing sharp angles and forming smooth side surfaces 116as. As a result, the gap filling of conductive components 220 in openings 208, 210 is improved.

[0072] Figure 26 and Figure 27 Semiconductor device structures 100 at different manufacturing stages according to optional embodiments are shown, and Figure 26-1 It is formed according to some embodiments. Figure 26 A top view of the opening 208 on the semiconductor device structure 100 shown. (See diagram) Figure 26 As shown, opening 208 extends above the side surface of the first intermediary member 150 along the X direction. Consequently, portion 116a is located below opening 208, surrounding the first intermediary member 150. Figure 26-1As shown, portion 116a of the base portion 116 is located below the opening 208 and surrounds the first intermediate member 150 shown by the dashed line. Figure 26 and Figure 26-1 As shown, the width of the portion 116a on the opposite side of the first intermediary member 150 along the X direction may be different. In some embodiments, the portion 116a has a width W2 on one side of the first intermediary member 150 and a width W4 on the opposite side of the first intermediary structure 150. In some embodiments, the width W2 is greater than the width W4. Widths W2 and W4 may be greater than 0 nm. Next, as Figure 27 As shown, a selective etching process is performed to remove the first intermediate component 150 and form the opening 210. Next, a process is performed... Figure 20 The plasma etching process described herein causes the portions 116a on both sides of the opening 210 to be recessed, thus removing sharp angles and forming smooth side surfaces 116as. As a result, the gap filling of the conductive components 220 in the openings 208 and 210 is improved.

[0073] Figure 28 and Figure 29 Semiconductor device structures 100 at different manufacturing stages according to alternative embodiments are illustrated. In some embodiments, such as Figure 28 As shown, openings 208 and 210 are formed to expose the S / D region 146, and a dielectric layer 212 is formed in the openings 208 and 210. In some embodiments, the dielectric layer 212 includes discrete portions and has different thicknesses. The dielectric layer 212 may first be deposited on the exposed surface of the semiconductor device structure 100, and then an anisotropic etching process is performed to remove portions of the dielectric layer 212. In some embodiments, such as Figure 28 As shown, due to the shapes of openings 208 and 210, the anisotropic etching process may result in the dielectric layer 212 having portions 212a, 212b, 212c, and 212d. In some embodiments, portions 212a and 212b are located on one side of openings 208 and 210, and portions 212c and 212d are located on opposite sides of openings 208 and 210. In some embodiments, portions 212a and 212b have different thicknesses. For example, after the anisotropic etching process, portion 212a may be thinner than portion 212b because the portion of the base portion 116 defining opening 208 can protect portion 212b of the dielectric layer 212 located below it. On the other side of openings 208 and 210, portions 212c and 212d may be separated due to portion 116a of the base portion 116. In some embodiments, as Figure 28As shown, the thickness of portion 212c is less than the thickness of portion 212d. After the anisotropic etching process that removes the portion of dielectric layer 212, a plasma etching process can be performed to recess portion 116a of the substrate portion 116. Next, as... Figure 29 As shown, conductive components 220 are formed to fill openings 208 and 210. In some embodiments, the conductive component 220 includes a liner, such as a TiN or TaN layer, and the liner may have a non-uniform thickness along the Z direction. For clarity, Figure 29 The silicide layer 222 is omitted. In some embodiments, such as Figure 29 As shown, the conductive component 220 has a top width W5 and a bottom width W6 smaller than the top width W5. In some embodiments, the top width W5 can range from about 10 nm to about 50 nm, and the bottom width W6 can range from about 1 nm to about 50 nm. The distance D1 between the bottom portion of the conductive component 220 and the gate structure 174 can range from about 3 nm to about 30 nm. In some embodiments, the thickness of the dielectric spacer 144 along the X direction ranges from about 3 nm to about 10 nm. In some embodiments, the portion of the conductive component 220 located below the bottom surface of the substrate portion 116 has a height H1 along the Z direction, and the height H1 ranges from about 5 nm to about 30 nm.

[0074] Embodiments of this disclosure provide semiconductor device structures and methods of forming thereof. In some embodiments, the method includes forming a first interposer 150 comprising a material different from that of a substrate portion 116, and removing the first interposer 150 without substantially affecting the substrate portion 116. After selectively removing the first interposer 150, another etching process is performed to remove one or more sharp corners of a portion 116a of the substrate portion 116. Some embodiments may achieve advantages. For example, the substrate portion 116 is unaffected by the etching process that removes the first interposer 150, and the dielectric spacer 144 is not damaged. As a result, the risk of a short circuit between the gate structure 174 and the conductive member 220 is reduced. Furthermore, by removing one or more sharp corners of a portion 116a of the substrate portion 116, the gap filling of the conductive member 220 in the openings 208, 210 is improved.

[0075] An embodiment is a method. The method includes forming an insulating material over a substrate and forming source / drain regions over the substrate. The source / drain regions include a first semiconductor material and a second semiconductor material, both of which are doped with dopants. The concentration of the dopants in the first semiconductor material differs from the concentration of the dopants in the second semiconductor material, and in a cross-sectional view, the thickness of the source / drain regions differs from the width of the source / drain regions. The method also includes depositing a contact etch stop layer (CESL) over the source / drain regions and the insulating material, and depositing an interlayer dielectric (ILD) layer over the CESL and the insulating material. The dielectric constant of the CESL is greater than the dielectric constant of the insulating material or the ILD layer. The method further includes flipping the substrate and forming a first opening to expose an interposer. The central axis of the first opening and the central axis of the interposer are spaced apart by a distance. The method also includes selectively removing the interposer to form a second opening, and forming conductive components in the first and second openings.

[0076] In some embodiments, the distance is in the range of 1 nm to 20 nm. In some embodiments, a first portion of the substrate is exposed after selectively removing the intervening component. In some embodiments, the method further includes recessing the first portion of the substrate. In some embodiments, the first portion of the substrate is recessed by a first etching process. In some embodiments, the first opening is formed by removing a second portion of the substrate. In some embodiments, the second portion of the substrate is removed by a second etching process different from the first etching process. In some embodiments, the first etching process is an anisotropic etching process, and the second etching process is an isotropic etching process.

[0077] Another embodiment is a method. The method includes: forming a source / drain region over a substrate portion, the source / drain region comprising a first semiconductor material and a second semiconductor material, the first and second semiconductor materials being doped with dopants, the concentration of the dopants in the first semiconductor material being different from the concentration of the dopants in the second semiconductor material, and in a cross-sectional view, the thickness of the source / drain region being different from the width of the source / drain region. The method further includes depositing a contact etch stop layer over the source / drain region, depositing a first interlayer dielectric (ILD) layer over the contact etch stop layer, depositing an etch stop layer over the top surface of the first ILD layer and the top surface of the contact etch stop layer, and depositing a second ILD layer over the etch stop layer. The thickness of the first ILD layer is greater than the thickness of the second ILD layer. The method further includes flipping the substrate and forming a first opening to expose a first interposer. A first portion of the substrate portion is disposed on a first side of the first interposer, a second portion of the substrate portion is disposed on a second side of the first interposer opposite to the first side, and the width of the first portion of the substrate portion is different from the width of the second portion of the substrate portion. The method further includes removing the first interposer to form a second opening, and forming conductive components in the first and second openings.

[0078] In some embodiments, the method further includes forming a dielectric layer in the first and second openings, the conductive member being formed on the dielectric layer, and the dielectric layer including a first portion and a second portion on one side of the conductive member, and a third and a fourth portion on opposite sides of the conductive member. In some embodiments, the first and second portions of the dielectric layer are continuous, and the third and fourth portions of the remaining dielectric layer are discrete. In some embodiments, the first and second portions have different thicknesses, and the third and fourth portions have different thicknesses. In some embodiments, the dielectric layer is formed by depositing the dielectric layer and removing portions of the dielectric layer by an anisotropic etching process. In some embodiments, the method further includes removing a second interposer to expose the source / drain region. In some embodiments, the method further includes recessing the second portion of the substrate portion prior to forming the conductive member. In some embodiments, the removal of the second interposer and the recessing of the second portion of the substrate portion are performed using different etching processes.

[0079] Another embodiment is a semiconductor device structure. This structure includes: an insulating material disposed adjacent to a substrate portion; a source / drain region disposed above the substrate portion; a contact etch stop layer (CESL) disposed above the source / drain region; and a first interlayer dielectric (ILD) layer disposed above the insulating material and the CESL. The dielectric constant of the CESL is greater than the dielectric constant of the insulating material or the first ILD layer. The structure also includes: an etch stop layer disposed above the top surface of the CESL and the top surface of the first ILD layer; and a second ILD layer disposed above the etch stop layer. The thickness of the first ILD layer is greater than the thickness of the second ILD layer. The structure further includes: a conductive component disposed below the source / drain region, and the conductive component includes a portion located below the gate electrode layer.

[0080] In some embodiments, the semiconductor device structure further includes a dielectric layer disposed between the conductive component and the substrate portion. In some embodiments, the dielectric layer includes a continuous portion on one side of the conductive component and a discrete portion on the other side of the conductive component. In some embodiments, the continuous portion of the dielectric layer has a different thickness.

[0081] The foregoing outlines features of several embodiments to enable those skilled in the art to better understand aspects of this disclosure. Those skilled in the art should understand that they can readily use this disclosure as a basis to design or modify other processes and structures for implementing the same purposes and / or achieving the same advantages as the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and alterations can be made to them herein without departing from the spirit and scope of this disclosure.

Claims

1. A method for forming a semiconductor device structure, comprising: An insulating material is formed above the substrate; A source / drain region is formed above the substrate, wherein the source / drain region comprises a first semiconductor material and a second semiconductor material, wherein the first semiconductor material and the second semiconductor material are doped with dopants, wherein the concentration of the dopants in the first semiconductor material is different from the concentration of the dopants in the second semiconductor material, and in a cross-sectional view, the thickness of the source / drain region is different from the width of the source / drain region; A contact etch stop layer is deposited over the source / drain region and the insulating material; An interlayer dielectric layer is deposited over the contact etch stop layer and the insulating material, wherein the dielectric constant of the contact etch stop layer is greater than the dielectric constant of the insulating material or the interlayer dielectric layer; Flip the substrate; A first opening is formed to expose the intermediate component, wherein the central axis of the first opening and the central axis of the intermediate component are spaced apart by a distance; Selectively remove the intermediate component to form a second opening; and Conductive components are formed in the first opening and the second opening.

2. The method according to claim 1, wherein, The distance is in the range of 1 nm to 20 nm.

3. The method according to claim 1, wherein, After selectively removing the intermediate component, the first portion of the base portion is exposed.

4. The method of claim 3, further comprising recessing the first portion of the base portion.

5. The method according to claim 4, wherein, The first portion of the substrate is recessed by a first etching process.

6. The method according to claim 5, wherein, The first opening is formed by removing a second portion of the base portion.

7. The method according to claim 6, wherein, The second portion of the substrate is removed by a second etching process different from the first etching process.

8. The method according to claim 7, wherein, The first etching process is an anisotropic etching process, and the second etching process is an isotropic etching process.

9. A method for forming a semiconductor device structure, comprising: A source / drain region is formed above a substrate portion, wherein the source / drain region comprises a first semiconductor material and a second semiconductor material, wherein the first semiconductor material and the second semiconductor material are doped with dopants, the concentration of the dopants in the first semiconductor material is different from the concentration of the dopants in the second semiconductor material, and in a cross-sectional view, the thickness of the source / drain region is different from the width of the source / drain region; A contact etch stop layer is deposited above the source / drain region; A first interlayer dielectric (ILD) layer is deposited above the contact etch stop layer; An etch stop layer is deposited above the top surface of the first interlayer dielectric layer and the top surface of the contact etch stop layer; A second interlayer dielectric layer is deposited above the etch stop layer, wherein the thickness of the first interlayer dielectric layer is greater than the thickness of the second interlayer dielectric layer; Flip the substrate; A first opening is formed to expose a first intermediary member, a first portion of the base portion is disposed on a first side of the first intermediary member, and a second portion of the base portion is disposed on a second side of the first intermediary member opposite to the first side, wherein the width of the first portion of the base portion is different from the width of the second portion of the base portion; Remove the first intermediary component to form the second opening; and Conductive components are formed in the first opening and the second opening.

10. A semiconductor device structure, comprising: Insulating material, disposed adjacent to the base portion; The source / drain region is disposed above the substrate portion; A contact etch stop layer (CESL) is disposed above the source / drain region; A first interlayer dielectric (ILD) layer is disposed above the insulating material and the contact etch stop layer, wherein the dielectric constant of the contact etch stop layer is greater than the dielectric constant of the insulating material or the first interlayer dielectric layer. An etch stop layer is disposed above the top surface of the contact etch stop layer and the top surface of the first interlayer dielectric layer; A second interlayer dielectric layer is disposed above the etch stop layer, wherein the thickness of the first interlayer dielectric layer is greater than the thickness of the second interlayer dielectric layer; and A conductive component is disposed below the source / drain region, wherein the conductive component includes a portion located below the gate electrode layer.

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