Semiconductor device structure and method of forming the same

Abstract

Embodiments of the present disclosure provide a semiconductor device structure and a method of forming the same. The structure includes an insulating material disposed adjacent to a substrate portion, a source / drain region disposed above the substrate portion, a contact etch stop layer (CESL) disposed above the source / drain region, and an interlayer dielectric (ILD) layer disposed above the insulating material and the CESL. The structure also includes a conductive contact extending through the ILD layer, a conductive member extending through the insulating material, the CESL, and the ILD layer, and the conductive member is electrically coupled to the conductive contact. The structure also includes a nitrogen-rich region disposed along a side of the conductive member, and the nitrogen-rich region includes a different material.

Description

Technical Field

[0001] Embodiments of this disclosure relate to semiconductor device structures and methods of forming the same. Background Technology

[0002] The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advancements in IC materials and design have led to multiple generations of ICs, each featuring smaller and more complex circuitry than the previous generation. In the evolution of ICs, functional density (i.e., the number of interconnect devices per chip area) typically increases, while geometry (i.e., the smallest component (or line) that can be created using manufacturing processes) decreases. This scaling down process generally provides benefits by increasing production efficiency and reducing associated costs. However, this scaling down also increases the complexity of handling and manufacturing ICs.

[0003] Therefore, improvements are needed in IC processing and manufacturing. Summary of the Invention

[0004] Embodiments of this disclosure provide a method for forming a semiconductor device structure, comprising: forming an insulating material over a substrate; forming a source / drain region over the substrate; depositing a contact etch stop layer (CESL) over the source / drain region and the insulating material; depositing an interlayer dielectric (ILD) layer over the contact etch stop layer and the insulating material, wherein the dielectric constant of the contact etch stop layer is greater than the dielectric constant of the insulating material or the interlayer dielectric layer; forming a gate structure over a top surface of the insulating material, wherein forming the gate structure includes depositing a gate dielectric layer and depositing a gate electrode layer over the gate dielectric layer; forming conductive contacts over the source / drain region; forming an opening in the insulating material, the contact etch stop layer, and the interlayer dielectric layer, wherein the conductive contacts are exposed; introducing a nitrogen-containing gas into the opening; and depositing conductive components in the opening.

[0005] Another embodiment of this disclosure provides a method for forming a semiconductor device structure, comprising: forming a first fin structure and a second fin structure, wherein the first fin structure includes a first substrate portion and a first semiconductor layer disposed above the first substrate portion, and the second fin structure includes a second substrate portion and a second semiconductor layer disposed above the second substrate portion; forming an insulating material between the first substrate portion and the second substrate portion; forming a first source / drain region in contact with the sidewalls of the first semiconductor layer; forming a second source / drain region in contact with the sidewalls of the second semiconductor layer; and depositing a contact etch stop layer (CESL), wherein the contact etch stop layer extends continuously from above the first source / drain region. Extending over the second source / drain region; depositing an interlayer dielectric (ILD) layer over the contact etch stop layer, wherein the top surface of the insulating material is spaced apart from the interlayer dielectric layer by the contact etch stop layer; depositing a conductive contact through the interlayer dielectric layer, wherein the conductive contact is electrically coupled to the source / drain region and the conductivity of the conductive contact is greater than the conductivity of the source / drain region; forming an opening in the insulating material, the contact etch stop layer and the interlayer dielectric layer, wherein the conductive contact is exposed; forming a dielectric layer along the sidewalls of the insulating material, the contact etch stop layer and the interlayer dielectric layer in the opening; and depositing a conductive component in the opening.

[0006] Another embodiment of this disclosure provides a semiconductor device structure, including: an insulating material disposed adjacent to a substrate portion; a source / drain region disposed above the substrate portion; a contact etch stop layer (CESL) disposed above the source / drain region; an interlayer dielectric (ILD) layer disposed above the insulating material and the contact etch stop layer, wherein the dielectric constant of the contact etch stop layer is greater than the dielectric constant of the insulating material or the interlayer dielectric layer; a conductive contact extending through the interlayer dielectric layer, wherein the conductive contact is electrically coupled to the source / drain region, and the conductivity of the conductive contact is greater than the conductivity of the source / drain region; a conductive component extending through the insulating material, the contact etch stop layer, and the interlayer dielectric layer, wherein the conductive component is electrically coupled to the conductive contact; and a nitrogen-rich region disposed along the side of the conductive component, wherein the nitrogen-rich region comprises different materials. Attached Figure Description

[0007] When read in conjunction with the accompanying drawings, aspects of this disclosure are best understood from the following detailed description. It should be noted that, in accordance with standard industry practice, the various components are not drawn to scale. In fact, for clarity of discussion, the dimensions of the individual components may be arbitrarily increased or decreased.

[0008] Figure 1 , Figure 2 , Figure 3 , Figure 4 , Figure 5 and Figure 6 These are perspective views of various stages of manufacturing a semiconductor device structure according to some embodiments.

[0009] Figure 7A , Figure 8A , Figure 9A , Figure 10A , Figure 11A and Figure 12A It is according to some embodiments along Figure 6 The AA section is a cross-sectional side view of each stage of the manufacturing process of a semiconductor device structure.

[0010] Figure 7B , Figure 8B , Figure 9B , Figure 10B , Figure 11B and Figure 12B It is according to some embodiments along Figure 6 The BB line is a cross-sectional side view of each stage of the manufacturing process of a semiconductor device structure.

[0011] Figure 7C , Figure 8C , Figure 9C , Figure 10C , Figure 11C and Figure 12C It is according to some embodiments along Figure 6 The CC line is a cross-sectional side view of each stage of manufacturing a semiconductor device structure.

[0012] Figure 13 According to some embodiments Figure 12A , Figure 12B , Figure 12C A top view of the semiconductor device structure shown.

[0013] Figure 14 and Figure 15 It is according to some embodiments along Figure 13 The DD line is a cross-sectional side view of each stage of the manufacturing process of a semiconductor device structure.

[0014] Figure 16 , Figure 17 , Figure 18 and Figure 19 The following are shown at various manufacturing stages according to some embodiments. Figure 15 Part of the semiconductor device structure.

[0015] Figure 20 It is according to some embodiments along Figure 13A cross-sectional side view of one of the various stages of manufacturing a semiconductor device structure, taken by line DD.

[0016] Figure 21 and Figure 22 The following are shown at various manufacturing stages according to optional embodiments. Figure 15 Part of the semiconductor device structure.

[0017] Figure 23 and Figure 24 The following are shown at various manufacturing stages according to optional embodiments. Figure 15 Part of the semiconductor device structure.

[0018] Figure 25 , Figure 26 , Figure 27 and Figure 28 The following are shown at various manufacturing stages according to optional embodiments. Figure 15 Part of the semiconductor device structure.

[0019] Figure 29 , Figure 30 , Figure 31 , Figure 32 and Figure 33 The following are shown at various manufacturing stages according to optional embodiments. Figure 15 Part of the semiconductor device structure. Detailed Implementation

[0020] The following disclosure provides numerous different embodiments or examples for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below to simplify this disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first component on or over a second component may include embodiments where the first and second components are formed in direct contact, and may also include embodiments where an additional component may be formed between the first and second components, such that the first and second components may not be in direct contact. Furthermore, reference numerals and / or letters may be repeated in various examples. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0021] Additionally, for ease of description, spatial relative terms such as “below,” “under,” “lower,” “above,” “on,” “top,” “upper,” etc., may be used herein to describe the relationship between one element or component and another, as shown in the figures. Besides the orientations shown in the figures, spatial relative terms are intended to include different orientations of the device in use or operation. The device may be positioned in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein may be interpreted accordingly.

[0022] Terms indicating relative degree (such as “about”, “basically”, etc.) should be interpreted as terms that a person skilled in the art would understand in accordance with current technical specifications.

[0023] The term "surround" can be used in this document to describe a structure that completely or partially encloses another element or structure, such as in three-dimensional space. For example, a first structure may "surround" a second structure on four lateral sides (e.g., left, right, front, and back) but not on two vertical sides (e.g., top and bottom). In other examples, a first structure may partially enclose a second structure, for example, by enclosing three sides (e.g., top, front, and back) while leaving other sides (e.g., left, right, and bottom) exposed.

[0024] While embodiments of this disclosure are discussed in relation to nanostructured channel FETs, such as gate-all-around (GAA) FETs, e.g., horizontal gate-all-around (HGAA) FETs or vertical gate-all-around (VGAA) FETs, implementations of some aspects of this disclosure can be used with other processes and / or other devices, such as FinFETs and other suitable devices. It will be readily understood by those skilled in the art that other modifications are contemplated within the scope of this disclosure. When adapting a gate-all-around (GAA) transistor structure, the GAA transistor structure can be patterned by any suitable method. For example, the structure can be patterned using one or more photolithography processes, including dual-patterning or multi-patterning processes. Typically, dual-patterning or multi-patterning processes combine photolithography and self-alignment processes, allowing the creation of patterns with, for example, smaller pitches than that achievable using a single direct photolithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a photolithography process. Spacers are formed alongside the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers can then be used to pattern the GAA structure.

[0025] Figures 1 to 20 An exemplary process for manufacturing a semiconductor device structure 100 according to embodiments of the present disclosure is shown. It should be understood that... Figures 1 to 20Additional operations are provided before, during, and after the process shown, and for additional embodiments of the method, some of the operations described below may be replaced or eliminated. The order of operations / processes is not limited and can be interchanged.

[0026] Figures 1 to 6 These are perspective views of various stages in the fabrication of a semiconductor device structure 100 according to some embodiments. For example... Figure 1 As shown, the semiconductor device structure 100 includes a stack of semiconductor layers 104 formed over the front side of a substrate 101. The substrate 101 may be a semiconductor substrate. The substrate 101 may include crystalline semiconductor materials such as, but not limited to, silicon (Si), germanium (Ge), silicon-germanium (SiGe), gallium arsenide (GaAs), indium antimonide (InSb), gallium phosphide (GaP), gallium antimonide (GaSb), indium aluminum arsenide (InAlAs), indium gallium arsenide (InGaAs), gallium antimony phosphide (GaSbP), gallium antimony phosphide (GaAsSb), and indium phosphide (InP). In some embodiments, the substrate 101 is a silicon-on-insulator (SOI) substrate having an insulating layer (not shown) disposed between two silicon layers for reinforcement. In one aspect, the insulating layer is an oxygen-containing layer.

[0027] The substrate 101 may include various regions that are already doped with impurities (e.g., dopants with p-type or n-type conductivity). Depending on the circuit design, the dopants may be, for example, phosphorus for p-type field-effect transistors (PFETs) and boron for n-type field-effect transistors (NFETs).

[0028] The stack of semiconductor layers 104 includes alternating semiconductor layers made of different materials to facilitate the formation of nanostructured channels in multi-gate devices, such as nanostructured channel FETs. In some embodiments, the stack of semiconductor layers 104 includes a first semiconductor layer 106 and a second semiconductor layer 108. In some embodiments, the stack of semiconductor layers 104 includes alternating first semiconductor layers 106 and second semiconductor layers 108. The first semiconductor layer 106 and the second semiconductor layer 108 are made of semiconductor materials with different etch selectivity and / or oxidation rates. For example, the first semiconductor layer 106 may be made of Si, and the second semiconductor layer 108 may be made of SiGe. In some examples, the first semiconductor layer 106 may be made of SiGe, and the second semiconductor layer 108 may be made of Si. Optionally, in some embodiments, either of the semiconductor layers 106, 108 may be or include other materials such as Ge, SiC, GeAs, GaP, InP, InAs, InSb, GaAsP, AlInAs, AlGaAs, InGaAs, GaInP, GaInAsP, or any combination thereof.

[0029] The first semiconductor layer 106 and the second semiconductor layer 108 are formed by any suitable deposition process, such as epitaxy. For example, the epitaxial growth of the layers of the stack of semiconductor layers 104 can be performed by molecular beam epitaxy (MBE), metal-organic chemical vapor deposition (MOCVD), and / or other suitable epitaxial growth processes.

[0030] In a later manufacturing stage, the first semiconductor layer 106 or a portion thereof may form a nanostructured channel of the semiconductor device structure 100. The term nanostructure is used herein to refer to any portion of material having nanoscale or even microscale dimensions and having an elongated shape, regardless of the cross-sectional shape of that portion. Thus, the term refers to elongated material portions with circular and substantially circular cross-sections, as well as beam-shaped or strip-shaped material portions including, for example, cylindrical or substantially rectangular cross-sections. The nanostructured channel of the semiconductor device structure 100 may be surrounded by a gate electrode. The semiconductor device structure 100 may include a nanostructured transistor. A nanostructured transistor may be referred to as a nanosheet transistor, a nanowire transistor, a gate all-around (GAA) transistor, a multi-bridge channel (MBC) transistor, or any transistor having a gate electrode surrounding the channel. The use of the first semiconductor layer 106 to define one or more channels of the semiconductor device structure 100 is further discussed below.

[0031] Each first semiconductor layer 106 may have a thickness ranging from about 3 nm to about 30 nm, such as from about 3 nm to about 10 nm. The thickness of each second semiconductor layer 108 may be equal to, less than, or greater than the thickness of the first semiconductor layer 106. In some embodiments, each second semiconductor layer 108 has a thickness ranging from about 2 nm to about 50 nm. Figure 1 As shown, three first semiconductor layers 106 and three second semiconductor layers 108 are arranged alternately for illustrative purposes and are not intended to limit the specific references in the claims. It will be understood that any number of first semiconductor layers 106 and second semiconductor layers 108 may be formed in the stack of semiconductor layers 104, and the number of layers depends on the predetermined number of channels for the semiconductor device structure 100.

[0032] A mask structure (not shown) may be formed over the stack of semiconductor layer 104. The mask structure may include an oxygen-containing layer and a nitrogen-containing layer. The oxygen-containing layer may be a pad oxide layer, such as a SiO2 layer. The nitrogen-containing layer may be a pad nitride layer, such as Si3N4. The mask structure may be formed by any suitable deposition process, such as chemical vapor deposition (CVD).

[0033] exist Figure 2In this embodiment, fin structures 112 are formed from a stack of semiconductor layers 104. Each fin structure 112 has an upper portion including semiconductor layers 106, 108 and a substrate portion 116 formed from a substrate 101. The fin structures 112 can be formed by patterning a hard mask layer (not shown) formed on the stack of semiconductor layers 104 using multiple patterning operations including photolithography and etching processes. The etching process can include dry etching, wet etching, reactive ion etching (RIE), and / or other suitable processes. The photolithography process can include forming a photoresist layer (not shown) over the hard mask layer, exposing the photoresist layer to form a pattern, performing a post-exposure baking process, and developing the photoresist layer to form a masking element including the photoresist layer. In some embodiments, an electron beam (e-beam) lithography process can be used to perform patterning of the photoresist layer to form the masking element. The etching process forms trenches 114 in the unprotected area. The trenches 114 pass through the hard mask layer, through the stack of semiconductor layers 104, and into the substrate 101, leaving multiple extending fin structures 112. The trenches 114 extend along the X direction.

[0034] exist Figure 3 In the process, after forming the fin structure 112, an insulating material 118 is formed on the substrate 101. The insulating material 118 fills the trenches 114 between adjacent fin structures 112 until the fin structure 112 is embedded in the insulating material 118. Then, a planarization operation (such as a chemical mechanical polishing (CMP) method and / or an etch-back method) is performed to expose the top of the fin structure 112. The insulating material 118 can be made of silicon oxide, silicon nitride, silicon oxynitride (SiON), SiOCN, SiCN, fluorine-doped silicate glass (FSG), low-k dielectric material, or any suitable dielectric material. The insulating material 118 can be formed by any suitable method, such as low-pressure chemical vapor deposition (LPCVD), plasma-enhanced CVD (PECVD), or flowable CVD (FCVD).

[0035] exist Figure 4 In this process, insulating material 118 is recessed to form isolation region 120. The recess in insulating material 118 exposes portions of fin structures 112, such as stacks of semiconductor layers 104. The recess in insulating material 118 reveals trenches 114 between adjacent fin structures 112. Isolation region 120 can be formed using suitable processes, such as dry etching, wet etching, or combinations thereof. The top surface of insulating material 118 may be flush with or below the surface of the second semiconductor layer 108 in contact with the substrate portion 116 formed by substrate 101. In some embodiments, isolation region 120 is shallow trench isolation (STI).

[0036] exist Figure 5In this embodiment, one or more sacrificial gate structures 130 (only one shown) are formed over a semiconductor device structure 100. The sacrificial gate structure 130 is formed over a portion of the fin structure 112. Each sacrificial gate structure 130 may include a sacrificial gate dielectric layer 132, a sacrificial gate electrode layer 134, and a mask layer 136. The sacrificial gate dielectric layer 132, the sacrificial gate electrode layer 134, and the mask layer 136 can be formed by sequentially depositing a blanket layer of the sacrificial gate dielectric layer 132, the sacrificial gate electrode layer 134, and the mask layer 136, and then patterning these layers into the sacrificial gate structure 130. Spacers 138 are then formed on the sidewalls of the sacrificial gate structure 130. For example, the spacers 138 can be formed by conformally depositing one or more layers for the spacers 138 and anisotropically etching the one or more layers. In some embodiments, the spacers 138 are also formed on the sidewalls of the exposed portion of the fin structure 112. Although one sacrificial gate structure 130 is shown, in some embodiments, two or more sacrificial gate structures 130 may be arranged along the X direction.

[0037] The sacrificial gate dielectric layer 132 may comprise one or more layers of dielectric material, such as a silicon oxide-based material. In some embodiments, the sacrificial gate dielectric layer 132 is formed by a deposition process, such as CVD or ALD. In some embodiments, the sacrificial gate dielectric layer 132 is formed by oxidation of the stack of semiconductor layers 104. As a result, the sacrificial gate dielectric layer 132 is not formed over the insulating material 118. The sacrificial gate electrode layer 134 may comprise silicon, such as polycrystalline silicon or amorphous silicon. The mask layer 136 may comprise more than one layer, such as an oxide layer and a nitride layer. The spacer 138 may be made of a dielectric material, such as silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, SiCN, silicon oxycarbide, SiOCN, and / or combinations thereof.

[0038] A portion of the fin structure 112 covered by the sacrificial gate electrode layer 134 of the sacrificial gate structure 130 is used as a channel region for the semiconductor device structure 100.

[0039] exist Figure 6 In this process, portions of the fin structure 112 not covered by the sacrificial gate structure 130 and spacer 138 are recessed to a level above, at, or below the top surface of the isolation region 120. The recessing of the fin structure 112 can be accomplished by an etching process (isotropic or anisotropic etching), and the etching process can be selective relative to one or more crystal planes of the substrate 101. The etching process can be dry etching (such as RIE, NBE, etc.) or wet etching (such as using tetramethylammonium hydroxide (TMAH), ammonium hydroxide (NH4OH), or any suitable etchant).

[0040] Figure 7A , Figure 8A , Figure 9A , Figure 10A , Figure 11A and Figure 12A It is according to some embodiments along Figure 6 The AA section is a cross-sectional side view of each stage of the manufacturing process of a semiconductor device structure. Figure 7B , Figure 8B , Figure 9B , Figure 10B , Figure 11B and Figure 12B It is according to some embodiments along Figure 6 The BB line is a cross-sectional side view of each stage of the manufacturing process of a semiconductor device structure. Figure 7C , Figure 8C , Figure 9C , Figure 10C , Figure 11C and Figure 12C It is according to some embodiments along Figure 6 The CC line is a cross-sectional side view of each stage of manufacturing a semiconductor device structure.

[0041] Figure 7A , Figure 7B and Figure 7C They are along Figure 6 A cross-sectional side view of the semiconductor device structure 100, taken by lines AA, BB, and CC.

[0042] like Figure 8A , Figure 8B and Figure 8C As shown, the edge portions of each second semiconductor layer 108 of the stack of semiconductor layers 104 are removed horizontally along the X direction. Removing the edge portions of the second semiconductor layers 108 forms cavities. In some embodiments, portions of the second semiconductor layers 108 are removed by a selective wet etching process. When the second semiconductor layer 108 is made of SiGe and the first semiconductor layer 106 is made of silicon, the second semiconductor layer 108 can be selectively etched using a wet etchant such as, but not limited to, ammonium hydroxide (NH4OH), tetramethylammonium hydroxide (TMAH), ethylenediamine catechol (EDP), or potassium hydroxide (KOH) solution.

[0043] In some embodiments, instead of laterally recessing the second semiconductor layer 108, the entire second semiconductor layer 108 is removed to create an opening between vertically adjacent first semiconductor layers 106. A dielectric layer (not shown) is formed in the opening between the vertically adjacent first semiconductor layers 106, and the dielectric layer is laterally recessed to form a cavity.

[0044] After removing the edge portions (or dielectric layer edges) of each second semiconductor layer 108, a dielectric layer is deposited in the cavity to form dielectric spacers 144. The dielectric spacers 144 may be made of a low-k dielectric material, such as SiON, SiCN, SiOC, SiOCN, or SiN. The dielectric spacers 144 can be formed by first forming a conformal dielectric layer using a conformal deposition process (such as ALD), followed by anisotropic etching to remove portions of the conformal dielectric layer outside the dielectric spacers 144. During the anisotropic etching process, the dielectric spacers 144 are protected by a first semiconductor layer 106. The remaining second semiconductor layers 108 cover the spacers 144 along the X direction. In some embodiments, instead of the second semiconductor layers 108, dielectric layers cover the spacers 144 along the X direction.

[0045] like Figure 9A , Figure 9B and Figure 9C As shown, a source / drain (S / D) region 146 is formed by a substrate portion 116 and a first semiconductor layer 106. In some embodiments, the S / D region 146 may be grown vertically and horizontally to form a facet, which may correspond to a crystal plane of the material used for the substrate portion 116 and the first semiconductor layer 106. In this disclosure, the source region and the drain region are used interchangeably, and their structures are substantially the same. Furthermore, depending on the context, the source / drain region may refer individually or collectively to the source or drain. The S / D region 146 may be made of one or more layers of Si, SiP, SiC, and SiCP for an n-channel FET, or one or more layers of Si, SiGe, and Ge for a p-channel FET. For a p-channel FET, a p-type dopant (such as boron (B)) may also be included in the S / D region 146. The S / D region 146 may be formed by epitaxial growth methods using CVD, ALD, or MBE.

[0046] exist Figure 10A , Figure 10B and Figure 10CIn this process, a contact etch stop layer (CESL) 162 is conformally formed on the exposed surface of the semiconductor device structure 100. CESL 162 covers the sidewalls of the sacrificial gate structure 130, the insulating material 118, and the S / D region 146. CESL 162 may comprise oxygen-containing or nitrogen-containing materials, such as silicon nitride, silicon nitride carbon, silicon oxynitride, carbon nitride, silicon oxide, silicon oxide carbon, or combinations thereof, and may be formed by CVD, PECVD, ALD, or any suitable deposition technique. Next, an interlayer dielectric (ILD) layer 164 is formed on the CESL 162 above the semiconductor device structure 100. The material used for the ILD layer 164 may include compounds containing Si, O, C, and / or H, such as silicon oxide, SiCOH, or SiOC. Organic materials (such as polymers) may also be used for the ILD layer 164. The ILD layer 164 may be deposited by a PECVD process or other suitable deposition techniques. In some embodiments, after the formation of the ILD layer 164, the semiconductor device structure 100 may undergo a thermal process to cure the ILD layer 164. In some embodiments, the dielectric constant of CESL 162 is greater than the dielectric constant of the insulating material 118 or the ILD layer 164.

[0047] like Figure 10A and Figure 10B As shown, after the formation of the ILD layer 164, a planarization operation (such as CMP) is performed on the semiconductor device structure 100 until the sacrificial gate electrode layer 134 is exposed.

[0048] Next, as Figure 11A , Figure 11B and Figure 11C As shown, the sacrificial gate structure 130 and the second semiconductor layer 108 are replaced with a gate dielectric layer 170 and a gate electrode layer 172. The removal of the sacrificial gate structure 130 and the second semiconductor layer 108 forms an opening between the spacers 138 and the first semiconductor layer 106. The sacrificial gate structure 130 can be removed using plasma dry etching and / or wet etching. The sacrificial gate electrode layer 134 can be removed first by any suitable process, such as dry etching, wet etching, or a combination thereof, followed by the removal of the sacrificial gate dielectric layer 132, which can also be performed by any suitable process, such as dry etching, wet etching, or a combination thereof. In some embodiments, a wet etchant such as a tetramethylammonium hydroxide (TMAH) solution can be used to selectively remove the sacrificial gate electrode layer 134, but not the spacers 138, the ILD layer 164, and CESL 162.

[0049] A portion of the second semiconductor layer 108 can be removed using a selective wet etching process. In cases where the second semiconductor layer 108 is made of SiGe and the first semiconductor layer 106 is made of Si, the chemicals used in the selective wet etching process remove the SiGe while substantially not affecting the dielectric material of the Si, spacer 138, ILD layer 164, and dielectric spacer 144. In one embodiment, the second semiconductor layer 108 can be removed using a wet etchant (such as, but not limited to, hydrofluoric acid (HF), nitric acid (HNO3), hydrochloric acid (HCl), phosphoric acid (H3PO4)), a dry etchant (such as a fluorine-based gas (e.g., F2) or a chlorine-based gas (e.g., Cl2)), or any suitable isotropic etchant.

[0050] After forming the nanostructured channel (i.e., the exposed portion of the first semiconductor layer 106), a gate dielectric layer 170 is formed around the exposed portion of the first semiconductor layer 106, and a gate electrode layer 172 is formed on the gate dielectric layer 170. The gate dielectric layer 170 and the gate electrode layer 172 may be collectively referred to as the gate structure 174. In some embodiments, an interface layer (IL) (not shown) is formed between the gate dielectric layer 170 and the exposed surface of the first semiconductor layer 106. In some embodiments, the gate dielectric layer 170 comprises one or more layers of dielectric material, such as silicon oxide, silicon nitride, or high-k dielectric materials, other suitable dielectric materials, and / or combinations thereof. Examples of high-k dielectric materials include HfO2, HfSiO, HfSiON, HfTaO, HfTiO, HbZrO, zirconium oxide, alumina, titanium oxide, hafnium dioxide-alumina (HfO2-Al2O3) alloys, other suitable high-k dielectric materials, and / or combinations thereof. The gate dielectric layer 170 can be formed using CVD, ALD, or any suitable deposition technique. The gate electrode layer 172 may comprise one or more layers of conductive material, such as polysilicon, aluminum, copper, titanium, tantalum, tungsten, cobalt, molybdenum, tantalum nitride, nickel silicide, cobalt silicide, TiN, WN, TiAl, TiAlN, TaCN, TaC, TaSiN, metal alloys, other suitable materials, and / or any combination thereof. The gate electrode layer 172 can be formed using CVD, ALD, electroplating, or other suitable deposition techniques. The gate electrode layer 172 may also be deposited above the upper surface of the ILD layer 164. The gate dielectric layer 170 and the gate electrode layer 172 formed above the ILD layer 164 are then removed using, for example, CMP, until the top surface of the ILD layer 164 is exposed.

[0051] like Figure 12A , Figure 12B and Figure 12CAs shown, a conductive contact 178 is formed over the S / D region 146, and a silicide layer 179 is formed between the conductive contact 178 and the S / D region 146. The conductive contact 178 may be conductive and may comprise one or more materials having Ru, Mo, Co, Ni, W, Ti, Ta, Cu, Al, TiN, or TaN, and the conductive contact 178 may be formed by any suitable method, such as electrochemical plating (ECP) or PVD. The silicide layer 179 may comprise one or more materials having WSi, CoSi, NiSi, TiSi, MoSi, and TaSi. In some embodiments, such as... Figure 12C As shown, conductive contact 178 is electrically connected to two or more S / D regions 146. In some embodiments, the conductivity of conductive contact 178 is greater than the conductivity of S / D region 146.

[0052] Figure 13 According to some embodiments Figure 12A , Figure 12B , Figure 12C A top view of the semiconductor device structure 100 shown. In some embodiments, such as Figure 13 As shown, a plurality of conductive contacts 178 extend along the Y direction and traverse relative to the fin structure 112 (or the S / D region 146 and the first semiconductor layer 106). In some embodiments, such as Figure 12C and Figure 13 As shown, the conductive contact 178 can be continuous (connecting two or more S / D regions 146).

[0053] It should be understood that the semiconductor device structure 100 may undergo further processing to form conductive contacts electrically connected to the gate electrode layer 172. Interconnect structures (not shown) may be formed over the semiconductor device structure 100 to provide electrical paths to devices formed on the substrate 101. In some embodiments, conductive components (such as wires) are formed in the interconnect structure and electrically connect to the conductive contacts 178. After completing the interconnect structure, which includes multiple layers of conductive components (such as conductive vias and wires) embedded in the inter-metal dielectric (IMD) layer, the semiconductor device structure 100 is flipped for back-side processing.

[0054] Figure 14 and Figure 15 It is according to some embodiments along Figure 13 The image shows a cross-sectional side view of each stage of manufacturing the semiconductor device structure 100, taken from line DD. Figure 14 As shown, the semiconductor device structure 100 is flipped for back-side processing, and for clarity, the interconnect structure is not shown. Next, as... Figure 15As shown, substrate 101 is thinned, and insulating material 118 and substrate portion 116 are exposed. Thinning of substrate 101 can be achieved by any suitable process. In some embodiments, a planarization process (such as a CMP process) is performed to thin substrate 101.

[0055] Figure 16 , Figure 17 , Figure 18 and Figure 19 The following are shown at various manufacturing stages according to some embodiments. Figure 15 Part 200 of the semiconductor device structure. For example... Figure 16 As shown, an opening 202 is formed in the insulating material 118, CESL 162, and ILD layer 164, and a conductive contact 178 is exposed at the bottom of the opening 202. The opening 202 can be formed by one or more etching processes. It can be first formed on the back side of the semiconductor device structure 100 (such as in the insulating material 118 and substrate portion 116). Figure 15 A patterned photoresist layer (not shown) is formed on the opening 202, and the pattern of the patterned photoresist layer is transferred to the insulating material 118, CESL 162, and ILD layer 164. The patterned photoresist layer is removed after or during the formation of the opening 202. In some embodiments, one or more etching processes for forming the opening 202 remove the patterned photoresist layer. In some embodiments, an additional etching process may be performed after the formation of the opening 202 to remove the patterned photoresist layer. In some embodiments, the sidewalls of the opening 202 comprise different materials. For example, the sidewalls of the opening 202 may comprise an oxide of the insulating material 118 (such as silicon oxide), a nitride of CESL 162 (such as silicon nitride), and another oxide of the ILD layer 164 (such as silicon oxide). Therefore, based on the different materials of the sidewalls of the opening 202, conductive components 208 are formed in the opening 202. Figure 19 Subsequent processes can have different growth rates. For example, the conductive component 208 adjacent to the nitride of CESL162 can grow faster than the oxide of the insulating material 118 and the ILD layer 164. As a result, portions of the conductive component 208 adjacent to CESL162 may be pinched off, forming gaps in the conductive component 208. These gaps can have dimensions larger than about 4 nm. These gaps can lead to increased resistance and reduced yield.

[0056] Next, as Figure 17 As shown, a processing technique is performed on the sidewalls of the opening 202, and this processing can result in the uniform growth of the conductive components 208 in the opening 202. In some embodiments, such as Figure 17As shown, the processing technology is a nitriding process to incorporate nitrogenous substances (such as nitrogen atoms, nitrogen radicals, or nitrogen ions) into the exposed surfaces of the opening 202 and the top surface of the insulating material 118. The nitriding process can be any suitable nitriding process, such as thermal nitriding or plasma nitriding. In some embodiments, the nitriding process is an in-situ nitriding process, with a processing temperature ranging from about 200 degrees Celsius to about 450 degrees Celsius, a bias power ranging from about 0 W to about 100 W, and a processing pressure ranging from about 1.5 mTorr to about 1 Torr. One or more gases can be used in the nitriding process. In some embodiments, a gas mixture of N2 gas and H2 gas is used in the nitriding process, and the volume concentration of N2 gas in the gas mixture is about 3%.

[0057] The nitriding process forms a nitrogen-rich region 204 on the exposed surface of the back side of the semiconductor device structure 100. For example, the nitrogen-rich region 204 may be formed on the sidewalls of the opening 202, the bottom of the opening 202, and the top surface of the insulating material 118. The nitrogen-rich region 204 is not a continuous nitride layer. Instead, the nitrogen-rich region 204 comprises multiple regions of different layers having a higher nitrogen concentration compared to other regions of different layers. For example, the insulating material 118 may include the nitrogen-rich region 204 on exposed surfaces, such as the top and side surfaces exposed in the opening 202. The nitrogen-rich region 204 of the insulating material 118 may include a higher nitrogen concentration than the remaining insulating material 118. For example, the nitrogen-rich region 204 of the insulating material 118 comprises SiON, while the remaining insulating material 118 comprises silicon oxide. CESL 162 may include the nitrogen-rich region 204 on the exposed side surface in the opening 202, and the nitrogen concentration of the nitrogen-rich region 204 of CESL 162 is greater than the nitrogen concentration of the remaining CESL 162. For example, the nitrogen-rich region 204 of CESL162 includes SiN with a first nitrogen concentration, and the remainder of CESL162 includes SiN with a second nitrogen concentration less than the first nitrogen concentration. ILD layer 164 may include a nitrogen-rich region 204 located on the side surface exposed in opening 202, and the nitrogen concentration of the nitrogen-rich region 204 of ILD layer 164 is greater than that of the remainder of ILD layer 164. For example, the nitrogen-rich region 204 of ILD layer 164 includes SiON, while the remainder of ILD layer 164 includes silicon oxide. Conductive contact 178 may include a nitrogen-rich region 204 located on the top surface exposed in opening 202, and the nitrogen concentration of the nitrogen-rich region 204 of conductive contact 178 is greater than that of the remainder of conductive contact 178. For example, the nitrogen-rich region 204 of conductive contact 178 includes a metal nitride, such as WN, while the remainder of conductive contact 178 includes a metal, such as W. Because different layers may or may not contain nitrogen, the nitrogen concentration of the nitrogen-rich region may not be constant. For example, in some embodiments, since CESL162 is a nitride, the nitrogen concentration of the nitrogen-rich region 204 of the insulating material 118 is less than the nitrogen concentration of the nitrogen-rich region 204 of CESL162.

[0058] Next, as Figure 18 As shown, a seed layer 206 is deposited in the opening 202 and on the insulating material 118. In some embodiments, the seed layer 206 is deposited using a PVD process. Figure 18As shown, the PVD process produces a non-conformal seed layer 206. For example, portions of the seed layer 206 deposited on the top surface of the insulating material 118 and the top surface of the conductive contact 178 are thicker than portions of the seed layer 206 deposited on the sidewalls of the opening 202. The seed layer 206 may comprise conductive materials such as copper, aluminum, aluminum-copper alloys, titanium, titanium nitride, tantalum, tantalum nitride, titanium nitride silicon, zirconium, gold, silver, cobalt, nickel, tungsten, tungsten nitride, tungsten nitride silicon, platinum, chromium, molybdenum, hafnium, other suitable conductive materials, or combinations thereof. The seed layer 206 provides reaction sites for growing the conductive component 208 formed by CVD or ALD. In some embodiments, the seed layer 206 is not deposited by CVD or ALD because the precursors of the CVD or ALD process may not react with or adhere to the dielectric surfaces in the opening 202.

[0059] Next, as Figure 19 As shown, a conductive component 208 is deposited in the opening 202 and on the insulating material 118. The conductive component 208 may include conductive materials such as copper, aluminum, aluminum-copper alloys, titanium, titanium nitride, tantalum, tantalum nitride, titanium nitride silicon, zirconium, gold, silver, cobalt, nickel, tungsten, tungsten nitride, tungsten nitride silicon, platinum, chromium, molybdenum, hafnium, other suitable conductive materials, or combinations thereof. As described above, the conductive component 208 is deposited using a CVD process or an ALD process. Compared to the PVD process, the CVD or ALD process is better in terms of gap filling. In some embodiments, during the deposition of the conductive component 208, nitrogen from the nitrogen-rich region 204 diffuses through the seed layer 206 and forms nitrogen-containing reaction sites at the surface of the seed layer 206. The presence of nitrogen-containing reaction sites can increase the growth rate of the conductive component 208. For example, the growth rate of the conductive component 208 can increase by 20% with the increase of nitrogen-containing reaction sites. Furthermore, the sidewall of opening 202 includes a nitrogen-rich region 204, and nitrogen can diffuse along the wall of opening 202 through the seed layer 206. As a result, the growth rate of the conductive component 208 along the sidewall of opening 202 is uniform. In some embodiments, the diffusion path of nitrogen through the portion of seed layer 206 located on the top surface of insulating material 118 and the top surface of conductive contact 178 is longer than the diffusion path of nitrogen through the portion of seed layer 206 located on the sidewall of opening 202, because the thickness of the portion of seed layer 206 located on the top surface of insulating material 118 and the top surface of conductive contact 178 is greater than the thickness of the portion of seed layer 206 located on the sidewall of opening 202. As a result, the growth rate of conductive component 208 located above insulating material 118 is slower than the growth rate of conductive component 308 adjacent to the sidewall of opening 202. All of the above factors result in a reduced gap or seamless conductive component 208.

[0060] In some embodiments, the deposition temperature of the conductive component 208 is in the range of about 200 degrees Celsius to about 450 degrees Celsius. If the deposition temperature of the conductive component 208 is below about 200 degrees Celsius, nitrogen diffusion from the nitrogen-rich region 204 to the surface of the seed layer 206 may not occur. On the other hand, if the deposition temperature is above about 450 degrees Celsius, the conductive components formed in the interconnect structure may be damaged.

[0061] After depositing the conductive component 208, a planarization process (such as a CMP process) can be performed to remove portions of the conductive component 208 formed on the insulating material 118. In some embodiments, such as Figure 20 As shown, the surface of the conductive component 208 and the surface of the insulating material 118 are substantially coplanar. Figure 20 A semiconductor device structure 100 with the front side facing upwards is shown. For clarity, the front interconnect structure is omitted. In some embodiments, the nitrogen-rich region 204 located on the insulating material 118 is also removed by a CMP process. In some embodiments, the nitrogen-rich region 204 remains at the bottom of the insulating material 118.

[0062] Subsequent processes may include forming interconnect structures (not shown) on the back side of the semiconductor device structure 100. The interconnect structures may include conductive components (such as wires) electrically connected to the conductive component 208 to provide power to the conductive component 208.

[0063] Figure 21 and Figure 22 The following are shown at various manufacturing stages according to optional embodiments. Figure 15 The semiconductor device structure 100 is part 200. For example... Figure 21 As shown, a nitrogen-rich region 204 is formed through a nitriding process. Next, in some embodiments, such as... Figure 22 As shown, an anisotropic etching process is performed to remove portions of the nitrogen-rich regions 204 located on the insulating material 118 and the conductive contact 178, while portions of the nitrogen-rich regions 204 located on the sidewalls of the opening 202 are retained. In some embodiments, the nitrogen-rich regions 204 (including metal nitrides) located at the conductive contact 178 increase the resistance of the conductive contact 178. Therefore, by removing the nitrogen-rich regions 204 (or metal nitrides) located at the conductive contact 178, the resistance of the conductive contact is reduced. Furthermore, the top surface of the insulating material 118 without the nitrogen-rich regions 204 can also slow down the growth rate of the conductive component 208 to avoid pinching of the opening 202. As a result, the size of the gap in the conductive component 208 is reduced, or the conductive component 208 is seamless.

[0064] Anisotropic etching can be any suitable etching process. In some embodiments, the anisotropic etching process is a dry etching process that removes nitrogen-rich regions 204 (e.g., SiN) located on top of the insulating material 118 and nitrogen-rich regions 204 (e.g., metal nitride) located on top of the conductive contact 178. Subsequent processes, such as..., can be performed. Figure 18 , Figure 19 and Figure 20 The process described in the document.

[0065] Figure 23 and Figure 24 The following are shown at various manufacturing stages according to optional embodiments. Figure 15 A portion 200 of the semiconductor device structure 100. In some embodiments, such as Figure 23 As shown, CESL162 is not present in the structure, and nitrogen-rich regions 204 are formed in the opening 202 and on the insulating material 118 and conductive contact 178. In some embodiments, the sidewalls of the opening 202 comprise a single material, such as an oxide, for example, silicon oxide. As described above, having nitrogen-containing reaction sites on the surface of the seed layer 206 can increase the growth rate of the conductive component 208. Therefore, with nitrogen-rich regions 204, the growth rate of the conductive component 208 increases as nitrogen diffuses from the nitrogen-rich regions 204 through the seed layer 206. Next, as Figure 24 As shown, a seed layer 206 and a conductive component 208 are formed in the opening 202. In some embodiments, the conductive component 208 is seamless due to the presence of a nitrogen-rich region 204.

[0066] Figure 25 , Figure 26 , Figure 27 and Figure 28 The following are shown at various manufacturing stages according to optional embodiments. Figure 15 A portion 200 of the semiconductor device structure 100. In some embodiments, such as Figure 25 As shown, after forming opening 202, a dielectric layer 210 is formed in opening 202 and on insulating material 118. Dielectric layer 210 can be a nitrogen-containing layer, such as a SiN layer. Dielectric layer 210 can be deposited by any suitable process, such as ALD. Next, as... Figure 26 As shown, an etching process is performed to remove portions of the dielectric layer 210 formed on horizontal surfaces (such as the top surface of the insulating material 118 and the top surface of the conductive contact 178). The etching process can be an anisotropic etching process. Figure 27 As shown, a seed layer 206 is deposited in the opening 202 and on the insulating material 118. Next, as... Figure 28As shown, a conductive component 208 is deposited in the opening 202. During the deposition of the conductive component 208, nitrogen from the dielectric layer 210 diffuses through the seed layer 206 to form nitrogen-containing reaction sites, which increases the growth rate of the conductive component 208. In some embodiments, the conductive component 208 is seamless due to the presence of the dielectric layer 210.

[0067] Figure 29 , Figure 30 , Figure 31 , Figure 32 and Figure 33 The following are shown at various manufacturing stages according to optional embodiments. Figure 15 A portion 200 of the semiconductor device structure 100. In some embodiments, such as Figure 29 As shown, dielectric layer 210 is deposited in opening 202. Next, as... Figure 30 As shown, the horizontal portion of dielectric layer 210 is removed. In some embodiments, a process is performed to form a nitrogen-rich region 204 in order to introduce a nitrogen material that is more mobile than nitrogen in the deposited dielectric layer 210. The nitrogen-rich region 204 may include portions of insulating material 118, dielectric layer 210, and conductive contact 178. In some embodiments, a process, such as a nitriding process, is performed before removing the horizontal portion of dielectric layer 210. As a result, in some embodiments, the nitrogen-rich region 204 includes dielectric layer 210, and the top surfaces of insulating material 118 and conductive contact 178 do not have the nitrogen-rich region 204.

[0068] Next, as Figure 32 As shown, a seed layer 206 is deposited in opening 202. (As illustrated...) Figure 33 As shown, a conductive component 208 is then deposited in the opening 202. During the deposition of the conductive component 208, the nitrogen material in the dielectric layer 210 from the nitriding process is more fluid than the nitrogen material in the dielectric layer 210 from the deposition process. Therefore, more nitrogen material can diffuse through the seed layer 206 to form nitrogen-containing reaction sites, which increases the growth rate of the conductive component 208. In some embodiments, the conductive component 208 is seamless due to the dielectric layer 210 and the nitrogen-rich region 204.

[0069] In some embodiments, the seed layer 206 described in the above embodiments is replaced by a liner such as TiN or TaN, and the conductive component 208 is formed on the liner.

[0070] Embodiments of this disclosure provide semiconductor device structures and methods for forming the same. In some embodiments, the semiconductor device structure includes a first dielectric material (e.g., ILD layer 164), a second dielectric material different from the first dielectric material (e.g., CESL 162), a third dielectric material (e.g., insulating material 118), and a conductive component 208 disposed in the first, second, and third dielectric materials. A nitrogen-rich region 204 is disposed between the first, second, and third dielectric materials and the conductive component 208. Some embodiments may achieve advantages. For example, during the deposition of the conductive component 208, nitrogen material in the nitrogen-rich region 204 can diffuse to the surface of the seed layer 206 to form nitrogen-containing reaction sites, and the nitrogen-containing reaction sites increase the growth rate of the conductive component 208. As a result, the conductive component 208 is seamless or has gaps smaller than about 1 nm.

[0071] The embodiment is a method. The method includes forming an insulating material over a substrate, forming source / drain regions over the substrate, depositing a contact etch stop layer (CESL) over the source / drain regions and the insulating material, and depositing an interlayer dielectric (ILD) layer over the CESL and the insulating material. The dielectric constant of the CESL is greater than the dielectric constant of the insulating material or the ILD layer. The method also includes forming a gate structure over the top surface of the insulating material, and the formation of the gate structure includes depositing a gate dielectric layer and depositing a gate electrode layer over the gate dielectric layer. The method further includes forming conductive contacts over the source / drain regions, forming openings in the insulating material, the CESL, and the ILD layer, and exposing the conductive contacts. The method also includes introducing a nitrogen-containing gas into the openings and depositing conductive components in the openings.

[0072] In some embodiments, the nitrogen-containing gas is introduced to form a nitrogen-rich region along the sidewall of the opening. In some embodiments, the nitrogen-rich region is formed at the bottom surface of the insulating material and the bottom surface of the conductive contact. In some embodiments, the method further includes removing portions of the nitrogen-rich region formed at the bottom surface of the insulating material and the bottom surface of the conductive contact. In some embodiments, the method further includes depositing a seed layer in the opening, wherein the conductive component is deposited on the seed layer. In some embodiments, the seed layer is deposited using a first deposition process, and the conductive component is deposited using a second deposition process different from the first deposition process. In some embodiments, the first deposition process is a physical vapor deposition process, and the second deposition process is a chemical vapor deposition process. In some embodiments, the conductive component is deposited at a deposition temperature ranging from about 200 degrees Celsius to about 450 degrees Celsius.

[0073] Another embodiment is a method. The method includes forming a first fin structure and a second fin structure, wherein the first fin structure includes a first substrate portion and a first semiconductor layer disposed above the first substrate portion, and the second fin structure includes a second substrate portion and a second semiconductor layer disposed above the second substrate portion. The method further includes forming an insulating material between the first and second substrate portions, forming a first source / drain region in contact with the sidewalls of the first semiconductor layer, forming a second source / drain region in contact with the sidewalls of the second semiconductor layer, and depositing a contact etch stop layer (CESL). The CESL extends continuously from above the first source / drain region to above the second source / drain region. The method further includes depositing an interlayer dielectric (ILD) layer above the CESL, wherein the top surface of the insulating material is spaced from the ILD layer by the CESL. The method further includes depositing conductive contacts through the ILD layer, the conductive contacts being electrically coupled to the source / drain regions, and the conductivity of the conductive contacts being greater than the conductivity of the source / drain regions. The method further includes forming openings in the insulating material, the CESL, and the ILD layer, and exposing the conductive contacts. The method also includes forming a dielectric layer along the sidewalls of the insulating material, CESL and ILD layers in the opening, and depositing conductive components in the opening.

[0074] In some embodiments, the dielectric layer is formed by depositing the dielectric layer and removing portions of the dielectric layer. In some embodiments, the dielectric layer is deposited using an atomic layer deposition process. In some embodiments, the portions of the dielectric layer are removed using an anisotropic etching process. In some embodiments, the method further includes performing a processing step on the dielectric layer. In some embodiments, the processing step is performed before removing the portions of the dielectric layer. In some embodiments, the processing step is performed after removing the portions of the dielectric layer. In some embodiments, the processing step is a nitriding process.

[0075] Another embodiment is a semiconductor device structure. This structure includes an insulating material disposed adjacent to a substrate portion, a source / drain region disposed above the substrate portion, a contact etch stop layer (CESL) disposed above the source / drain regions, and an interlayer dielectric (ILD) layer disposed above the insulating material and the CESL. The dielectric constant of the CESL is greater than that of the insulating material or the ILD layer. The structure also includes conductive contacts extending through the ILD layer, electrically coupled to the source / drain regions, and having a conductivity greater than that of the source / drain regions. The structure further includes conductive components extending through the insulating material, the CESL, and the ILD layer, and electrically coupled to the conductive contacts. The structure also includes nitrogen-rich regions disposed along the sides of the conductive components, and these nitrogen-rich regions comprise different materials.

[0076] In some embodiments, the different materials of the nitrogen-rich regions include SiON and SiN. In some embodiments, the contact etch stop layer includes a portion of the nitrogen-rich regions. In some embodiments, the portion of the nitrogen-rich regions of the contact etch stop layer includes a first nitrogen concentration, and the remaining portion of the contact etch stop layer includes a second nitrogen concentration less than the first nitrogen concentration.

[0077] The foregoing outlines features of several embodiments to enable those skilled in the art to better understand aspects of this disclosure. Those skilled in the art should understand that they can readily use this disclosure as a basis to design or modify other processes and structures for implementing the same purposes and / or achieving the same advantages as the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and alterations can be made to them herein without departing from the spirit and scope of this disclosure.

Claims

1. A method for forming a semiconductor device structure, comprising: An insulating material is formed above the substrate; A source / drain region is formed above the substrate; A contact etch stop layer (CESL) is deposited over the source / drain region and the insulating material. An interlayer dielectric (ILD) layer is deposited over the contact etch stop layer and the insulating material, wherein the dielectric constant of the contact etch stop layer is greater than the dielectric constant of the insulating material or the interlayer dielectric layer; A gate structure is formed above the top surface of the insulating material, wherein the formation of the gate structure includes: Depositing the gate dielectric layer, and A gate electrode layer is deposited above the gate dielectric layer; A conductive contact is formed above the source / drain region; An opening is formed in the insulating material, the contact etch stop layer, and the interlayer dielectric layer, wherein the conductive contact is exposed; Introducing nitrogen-containing gas into the opening; and A conductive component is deposited in the opening.

2. The method according to claim 1, wherein, The nitrogen-containing gas is introduced to form a nitrogen-rich region along the sidewall of the opening.

3. The method according to claim 2, wherein, The nitrogen-rich region is formed on the bottom surface of the insulating material and on the bottom surface of the conductive contact.

4. The method of claim 3, further comprising removing portions of the nitrogen-rich regions formed on the bottom surface of the insulating material and on the bottom surface of the conductive contact.

5. The method of claim 1, further comprising depositing a seed layer in the opening, wherein, The conductive component is deposited on the seed layer.

6. The method according to claim 5, wherein, The seed layer is deposited using a first deposition process, and the conductive component is deposited using a second deposition process different from the first deposition process.

7. The method according to claim 6, wherein, The first deposition process is a physical vapor deposition process, and the second deposition process is a chemical vapor deposition process.

8. The method according to claim 1, wherein, The conductive component is deposited at a deposition temperature ranging from 200 degrees Celsius to 450 degrees Celsius.

9. A method for forming a semiconductor device structure, comprising: A first fin structure and a second fin structure are formed, wherein the first fin structure includes a first substrate portion and a first semiconductor layer disposed above the first substrate portion, and the second fin structure includes a second substrate portion and a second semiconductor layer disposed above the second substrate portion; An insulating material is formed between the first substrate portion and the second substrate portion; A first source / drain region is formed in contact with the sidewall of the first semiconductor layer; A second source / drain region is formed in contact with the sidewall of the second semiconductor layer; A contact etch stop layer (CESL) is deposited, wherein the contact etch stop layer extends continuously from above the first source / drain region to above the second source / drain region; An interlayer dielectric (ILD) layer is deposited above the contact etch stop layer, wherein the top surface of the insulating material is spaced apart from the interlayer dielectric layer by the contact etch stop layer; A conductive contact is deposited through the interlayer dielectric layer, wherein the conductive contact is electrically coupled to the source / drain region, and the conductivity of the conductive contact is greater than the conductivity of the source / drain region; An opening is formed in the insulating material, the contact etch stop layer, and the interlayer dielectric layer, wherein the conductive contact is exposed; A dielectric layer is formed in the opening along the sidewalls of the insulating material, the contact etch stop layer, and the interlayer dielectric layer; and A conductive component is deposited in the opening.

10. A semiconductor device structure, comprising: An insulating material is disposed adjacent to the substrate portion; The source / drain region is disposed above the substrate portion; A contact etch stop layer (CESL) is disposed above the source / drain region; An interlayer dielectric (ILD) layer is disposed above the insulating material and the contact etch stop layer, wherein the dielectric constant of the contact etch stop layer is greater than the dielectric constant of the insulating material or the interlayer dielectric layer; A conductive contact extends through the interlayer dielectric layer, wherein the conductive contact is electrically coupled to the source / drain region, and the conductivity of the conductive contact is greater than the conductivity of the source / drain region; A conductive component extending through the insulating material, the contact etch stop layer, and the interlayer dielectric layer, wherein the conductive component is electrically coupled to the conductive contact; and A nitrogen-rich region is provided along the side of the conductive component, wherein the nitrogen-rich region comprises different materials.

Images