Semiconductor structure and method of forming the same

Abstract

Methods of the present disclosure include forming a stack on a substrate, patterning the stack and the substrate to form first and second active regions, forming an isolation structure between the first and second active regions, forming a dummy gate stack across the first and second active regions, recessing the first and second active regions to form a first trench and a second trench, forming a first source / drain component and a second source / drain component in the first trench and the second trench, removing the dummy gate stack to form a gate trench, depositing a gate structure in the gate trench, thinning the substrate, forming a backside opening, and forming a backside via in the backside opening. The backside opening has a first via opening exposing the first source / drain component and a second via opening exposing the second source / drain component. The backside via spans a portion of the isolation structure stacked between the first source / drain component and the second source / drain component. Embodiments of the present disclosure also relate to semiconductor structures and methods of forming the same.

Description

Technical Field

[0001] Embodiments of this disclosure relate to semiconductor structures and methods of forming the same. Background Technology

[0002] The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advancements in IC materials and design have resulted in multiple generations of ICs, each featuring smaller and more complex circuitry than the previous generation. In the evolution of ICs, functional density (i.e., the number of interconnect devices per chip area) typically increases, while geometry (i.e., the smallest component (or line) that can be created using manufacturing processes) decreases. This scaling down process generally provides benefits through increased production efficiency and reduced associated costs. However, this scaling down also increases the complexity of handling and manufacturing ICs.

[0003] Traditionally, ICs are built in a stacked manner, with transistors formed in device layers and interconnect structures (e.g., vias and metal lines) formed on top of the device layers to provide connectivity. These interconnect structures include power rails (e.g., metal lines for voltage sources and ground planes) for communication between circuit elements and signal lines (e.g., metal lines for transmitting signals and control). While existing interconnect structures and manufacturing processes are generally sufficient for their intended purposes, they are not entirely satisfactory in every aspect. Therefore, further improvements are needed. Summary of the Invention

[0004] One embodiment of this disclosure provides a method for forming a semiconductor structure, comprising: forming a stack on a substrate, the stack having a plurality of channel layers interleaved by a plurality of sacrificial layers; patterning the stack and the substrate to form a first region and a second region, each of the first region and the second region extending longitudinally in a first direction, the first region including a first active region and a first substrate region, the second region including a second active region and a second substrate region; forming an isolation structure between the first substrate region and the second substrate region, wherein the isolation structure is in contact with the sidewalls of the first substrate region and the sidewalls of the second substrate region; forming a dummy gate stack spanning the first active region and the second active region; recessing the first active region and the second active region outside the dummy gate stack to form a first trench and a second trench, respectively; forming a first source / drain component in the first trench and a second source / drain component in the second trench. A second source / drain component is formed in the trench, a portion of the first source / drain component is suspended above the isolation structure along a second direction different from the first direction, and a portion of the second source / drain component is suspended above the isolation structure along the second direction; the dummy gate stack is removed to form a gate trench; the sacrificial layer is removed to release the channel layer; a gate structure is deposited in the gate trench, the gate structure enclosing at least one of the channel layers; a back-side opening is formed, the back-side opening having a first via opening exposing the bottom surface of the first source / drain component and a second via opening exposing the bottom surface of the second source / drain component; and a back-side via is formed in the back-side opening, and the back-side via is electrically coupled to the first source / drain component and the second source / drain component, wherein the back-side via spans a portion of the isolation structure stacked between the first source / drain component and the second source / drain component.

[0005] Another aspect of the embodiments of this disclosure provides a method for forming a semiconductor structure, comprising: providing a structure having a front side and a back side, the structure including a substrate located at the back side of the structure and a first fin structure and a second fin structure located at the front side of the structure; forming an isolation structure on the sidewalls of the first fin structure and the second fin structure; recessing a portion of the first fin structure to form a first trench, and recessing a portion of the second fin structure to form a second trench; epitaxially growing a first source / drain component in the first trench, and epitaxially growing a second source / drain component in the second trench; and epitaxially growing a first source / drain component in the first source / drain portion. A contact etch stop layer is deposited over the first fin and the second source / drain components; a first interlayer dielectric layer is deposited over the contact etch stop layer; a gate structure is formed extending across the first fin structure and the second fin structure; a gate dicing process is performed to form a gate dicing component that divides the gate structure, the gate dicing component extending laterally between the first source / drain component and the second source / drain component; a front-side source / drain contact is formed in the first interlayer dielectric layer to electrically couple to the first source / drain component and the second source / drain component; a second interlayer dielectric layer is deposited over the first interlayer dielectric layer, which... In this configuration, the thickness of the first interlayer dielectric layer is greater than the thickness of the second interlayer dielectric layer; a front contact via is formed in the second interlayer dielectric layer to electrically couple to the front source / drain contact; a first back-side via opening is formed to expose the first source / drain component; a second back-side via opening is formed to expose the second source / drain component; a first silicide layer is formed in the first back-side via opening, the conductivity of the first silicide layer being greater than the conductivity of the first source / drain component, and the first silicide layer includes a curved profile; a second silicide layer is formed in the second back-side via opening, the conductivity of the second silicide layer being greater than the conductivity of the second source / drain component. The conductivity of the electrode / drain components, the second silicide layer including a curved profile; a first back-side conductive component formed in the opening of the first back-side via, the first back-side conductive component being in contact with the first silicide layer; a second back-side conductive component formed in the opening of the second back-side via, the second back-side conductive component being in contact with the second silicide layer, the gate dicing component disposed between the first back-side conductive component and the second back-side conductive component; and a third back-side conductive component formed below the first back-side conductive component and the second back-side conductive component, the third back-side conductive component connecting the first back-side conductive component and the second back-side conductive component.

[0006] In another aspect, embodiments of this disclosure provide a semiconductor structure, including: a first source / drain component and a second source / drain component; a plurality of first nanostructures adjacent to the first source / drain component; a plurality of second nanostructures adjacent to the second source / drain component; a first gate structure enclosing at least one of the first nanostructures; a second gate structure enclosing at least one of the second nanostructures; and a gate spacer extending along the sidewalls of the first gate structure and the second gate structure, wherein the first gate structure and the second gate structure include a gate dielectric layer and a gate electrode located above the gate dielectric layer, the gate... The gate dielectric layer has a dielectric constant greater than that of the gate spacer, and the thickness of the gate dielectric layer is less than that of the gate spacer. The gate electrode comprises a titanium-containing material. A gate end dielectric component is connected to the end of the first gate structure and the end of the second gate structure. An isolation structure is disposed on the sidewall of the gate end dielectric component. A back-side conductive component spans the gate end dielectric component. The back-side conductive component includes a first leg electrically coupled to the first source / drain component, a second leg electrically coupled to the second source / drain component, and a bridging portion connecting the first leg and the second leg. Attached Figure Description

[0007] This disclosure is best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be emphasized that, in accordance with standard industry practice, the various parts are not drawn to scale and are for illustrative purposes only. In fact, the dimensions of the various parts may be arbitrarily increased or decreased for clarity of discussion.

[0008] Figure 1A and Figure 1B A flowchart of a method for forming a semiconductor device according to one or more aspects of this disclosure is shown.

[0009] Figure 2 The following are shown in accordance with one or more aspects of this disclosure: Figure 1A and Figure 1B A top view of a semiconductor device at an intermediate stage during the manufacturing process of the method.

[0010] Figure 3 , Figure 61 , Figure 64 , Figure 68 and Figure 72 The following are shown in accordance with one or more aspects of this disclosure: Figure 1A and Figure 1B A plan view of a semiconductor device at a corresponding intermediate stage during the manufacturing process of the method.

[0011] Figures 4 to 60 , Figures 62 to 63 , Figures 65 to 67, Figures 69 to 71 and Figures 73 to 75 The following are shown in accordance with one or more aspects of this disclosure: Figure 1A and Figure 1B Cross-sectional views of semiconductor devices at different stages during the manufacturing process of the method. Detailed Implementation

[0012] The following disclosure provides numerous different embodiments or examples for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below to simplify this disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first component on or over a second component may include embodiments where the first and second components are formed in direct contact, and may also include embodiments where an additional component may be formed between the first and second components, such that the first and second components may not be in direct contact. Furthermore, reference numerals and / or letters may be repeated in various examples. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0013] For ease of description, spatial relative terms such as “below,” “under,” “lower,” “above,” and “upper” are used herein to describe the relationship of one element or component to another, as shown in the figures. In addition to the orientations shown in the figures, spatial relative terms are intended to include different orientations of the device in use or operation. The device may be positioned in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein can be interpreted accordingly.

[0014] Additionally, when using terms such as "about," "approximately," etc., to describe numerical values ​​or ranges, the term is intended to encompass values ​​within a reasonable range, taking into account the inherent variations that occur during manufacturing as understood by those skilled in the art. For example, based on known manufacturing tolerances associated with manufacturing a part having characteristics associated with the value, the value or range encompasses a reasonable range including the described value, such as within + / -10% of the described value. For instance, a material layer with a thickness of "about 5 nm" can encompass dimensions ranging from 4.5 nm to 5.5 nm, where manufacturing tolerances associated with the deposited material layer are known to those skilled in the art to be + / -10%.

[0015] This disclosure generally relates to semiconductor devices and manufacturing processes, and more specifically, to semiconductor devices having transistors formed in a device layer, front-side interconnect structures disposed above the device layer, and back-side interconnect structures disposed below the device layer. The back-side interconnect structures include back-side metal lines and back-side vias, which provide improved electrical connections between the back-side vias and components within the transistors, and between the back-side vias and the back-side metal lines. The enhanced interconnects reduce resistance and parasitic capacitance in the semiconductor device, thereby improving overall device performance.

[0016] Over the past few decades, the density of IC devices has steadily increased. As density increases, the size of metal lines (including power rails and signal lines) decreases, leading to higher resistance, larger parasitic capacitance, and reduced circuit performance. The back side of an IC device provides additional routing space for power grids and / or signal paths to mitigate the increasing routing resistance and parasitic capacitance. For example, portions of the power grid and / or signal paths can be routed on the back side of the IC substrate, opposite the side where the active device is formed. Back-side vias are used to establish electrical connections between back-side metal lines and components within the transistor (e.g., source / drain components and / or gate structures). The resistance of these back-side vias has a significant impact on the overall resistance of the power grid and / or signal paths. While back-side routing generally allows for larger metal components, the size of back-side vias positioned adjacent to certain isolation components, such as cut-metal gate (CMG) components, can be limited. In some embodiments of this disclosure, two back-side vias disposed on opposite sides of a CMG component are combined to form a single, larger back-side via spanning the CMG component. Additionally or optionally, a single, larger back-side via spans the isolation structure therebetween. Furthermore, back-side routing can allow back-side metal lines to be formed with a greater width than their front-side counterparts. The enlarged back-side vias spanning the CMG components (and / or the isolation structure therebetween) along with the enlarged back-side metal lines provide increased contact area and help reduce routing resistance and parasitic capacitance.

[0017] The details of the structure and fabrication methods of this disclosure are described below with reference to the accompanying drawings, which illustrate the process of fabricating multi-gate transistors (particularly gate-all-around (GAA) transistors) according to some embodiments. A GAA transistor refers to a transistor having vertically stacked, horizontally oriented nanostructures as channel layers (also called channel components) (such as in the form of nanowires and / or nanosheets). Due to their superior gate control capabilities, lower leakage current, and full field-effect transistor (FET) layout compatibility, GAA transistors are promising candidates for bringing CMOS to the next stage of the roadmap. For simplicity, this disclosure uses GAA transistors as examples. Those skilled in the art will understand that they can readily use this disclosure as a basis for designing or modifying other processes and structures (such as FinFET transistors, forked transistors, and complementary FETs (CFETs)) to achieve the same purposes and / or benefits of the embodiments described herein.

[0018] Figure 1A and Figure 1B A flowchart of a method 100 for manufacturing an example semiconductor device (or semiconductor structure) 200 according to some embodiments of the present disclosure is shown. Method 100 is merely an example and is not intended to limit the present disclosure beyond the scope expressly referenced in the claims. Additional operations may be performed before, during, and after method 100, and some of the described operations may be replaced, eliminated, or rearranged for additional embodiments of the method. For simplicity, not all steps are described in detail herein. The following is in conjunction with... Figures 2 to 75 Describe the method, Figures 2 to 75 Various plan views, perspective views, and cross-sectional views of the semiconductor device 200 during intermediate steps of the method are shown.

[0019] For the purposes of the following discussion, Figure 2 A simplified top view of an intermediate structure forming a semiconductor device 200 according to some embodiments is provided. Figure 2 The semiconductor device 200 shown is in the manufacturing stage, during which certain front-side interconnect structures (such as source / drain contacts and gate vias) are disposed above transistors formed in the device layer. The semiconductor device 200 includes active regions 210A-210D (collectively referred to as active region 210), a gate structure 260, diced metal gate (CMG) components 270 that “cut” the gate structure 260 into segments, a dielectric gate 250 sandwiching the gate structure 260 in between, and gate spacers 226 extending along the sidewalls of the gate structure 260 and the dielectric gate 250.

[0020] As used herein, "active region" refers to the region that forms the source region, drain region, and channel region beneath the gate structure of the transistor. Multiple transistors may share a single active region. The active region may protrude upwards from the substrate. In some embodiments, the transistor is a GAA transistor, and the channel region of the active region is located in a vertically stacked, horizontally oriented nanostructure. In some embodiments, the transistor is a FinFET transistor, and the channel region of the active region is located in a fin-like structure protruding from the substrate.

[0021] The continuous polysilicon on oxide diffusion edge (CPODE) process can be used to form the dielectric gate 250. In forming the dielectric gate 250, the CPODE process replaces the selected gate structure with a dielectric filler. Therefore, the dielectric gate 250 is also referred to as a CPODE structure or a CPODE part.

[0022] Although Figure 2 The following figures show four active regions 210 (in the form of fin structures 212), but it should be understood that, depending on the design, any suitable number of active regions 210 can be formed in the semiconductor device 200. Similarly, any suitable number of gate structures 260, CMG parts 270, and dielectric gates 250 can be formed to realize the semiconductor device 200.

[0023] In the depicted embodiment, CMG component 270 extends longitudinally along the X direction and its width is along the Y direction, and dielectric gate 250 extends longitudinally along the Y direction and its width is along the X direction. When forming a grid of cells, dielectric gate 250 intersects with CMG component 270. The term "intersect" (or "crossing," "intersection") in this disclosure refers to a configuration in a top view where two components pass through each other. Each cell (e.g., cell 300, composed of...) Figure 2 The dashed rectangular box depicting cell 300 is bounded on two opposite edges defined by two dielectric gates 250 and on two additional opposite edges defined by two CMG components 270. The dielectric boundaries of cell 300 isolate the transistor formed therein from surrounding transistors, reducing interference between transistors. In the depicted embodiment, active regions 210A and 210D are formed on p-wells, and active regions 210B and 210C are formed on n-wells stacked between p-wells. Therefore, within cell 300, an n-type transistor (denoted as T) is formed... N When forming a p-type transistor (denoted as T), the gate structure 260 intersects with the active region 210A, and the p-type transistor is formed. P When the gate structure 260 intersects with the active region 210B, the gate structure 260 intersects with the active region 210B.

[0024] Within unit 300, semiconductor device 200 includes transistor T. N and T PThe corresponding source / drain contacts 280A-280C (collectively referred to as source / drain contacts 280) are located on the source / drain regions of transistor T. Source / drain contacts 280A are disposed on transistor T. N On the source region. The source / drain contact 280A extends beyond the boundary of cell 300 and also crosses the active region immediately adjacent to the active region 210A. Figure 2 (Not shown in the image). With this configuration, the source / drain contact 280A connects two n-type transistors T located in adjacent cells via corresponding source / drain contact vias 286 provided on the source / drain contact 280A. N The source region is electrically coupled to the ground reference voltage (VSS). Similarly, the source / drain contact 280B is located in transistor T. P On the source region. The source / drain contact 280B extends beyond the boundary of cell 300 and also spans the active region 210C. With this configuration, the source / drain contact 280B connects two p-type transistors T located in adjacent cells via corresponding source / drain contact vias 286 provided on the source / drain contact 280B. P The source region is electrically coupled to the supply voltage (VDD). The source / drain contact 280C is held within cell 300 and spans transistor T. N and T P The drain region extends. In the illustrated embodiment, transistor T N and T P Together, they form an inverter in cell 300. Within cell 300, semiconductor device 200 also includes a gate via 284 disposed on gate structure 260. Gate via 284 provides signal input to the inverter, while source / drain contacts 280C provide signal output to the inverter. Those skilled in the art will recognize that the inverter is merely an example, and multiple transistors can form various circuits beyond the inverter.

[0025] Figure 3 An example of a semiconductor device 200 from a perspective view according to some embodiments is shown. For example... Figure 3 The semiconductor device 200 shown is in the manufacturing stage, during which a dummy gate stack 220 is disposed across the fin structure 212. The fin structure 212 corresponds to... Figure 2The active regions 210A-210D are defined, and the dummy gate stack 220 is a position holder that reserves space for the gate structure 260 in the replacement gate process (also known as the post-gate process). The dummy gate stack 220 includes a dummy dielectric layer 216, a dummy electrode layer 218, and a gate top hard mask layer 222. Fin structures 212 protrude from the substrate 202. Each fin structure 212 includes a fin substrate 212B and an epitaxial stack of channel layers 208 and sacrificial layers 206 staggered in the vertical direction. The channel layers 208 are in the form of nanostructures (e.g., nanosheets or nanowires) and are staggered with the sacrificial layers 206. Source / drain regions 212SD are defined on opposite sides of the dummy gate stack 220. An isolation structure 214 and a top isolation structure protective layer 215 are formed on opposite sides of the fin structures 212.

[0026] Common Reference Figure 2 and Figure 3 These figures also show a first cleavage line (AA), a second cleavage line (BB), and a third cleavage line (CC) passing through the intermediate structure. The first cleavage line AA is aligned with the longitudinal axis of the dummy gate stack 220 (or gate structure 260) and is oriented, for example, perpendicular to the current flow direction between the source / drain regions 212SD of the corresponding GAA transistor of the semiconductor device 200. The second cleavage line BB is perpendicular to the first cleavage line AA and aligned with the longitudinal axis of one of the fin structures 212 (or active regions 210). The second cleavage line BB is oriented, for example, along the current flow direction between the source / drain regions 212SD of the corresponding GAA transistor. The third cleavage line CC is parallel to the first cleavage line AA and extends through the source / drain regions 212SD of the semiconductor device 200. Cross-sectional views of these cleavage lines are presented in the figures below to clarify the relative positions. To avoid ambiguity, Figures 2 to 75 The X, Y, and Z directions shown are perpendicular to each other.

[0027] refer to Figure 1A and Figure 4 Method 100 includes block 102, wherein a stack 204 of alternating semiconductor layers is formed over semiconductor device 200. (As...) Figure 3As shown, semiconductor device 200 includes substrate 202. In some embodiments, substrate 202 may be a semiconductor substrate, such as a silicon (Si) substrate. Depending on design requirements known in the art, substrate 202 may include various doping configurations. In embodiments where the semiconductor device is p-type, an n-type doping distribution (i.e., an n-type well or n-well) may be formed on substrate 202. In some embodiments, the n-type dopant used to form the n-type well may include phosphorus (P), arsenic (As), or antimony (Sb). In embodiments where the semiconductor device is n-type, a p-type doping distribution (i.e., a p-type well or p-well) may be formed on substrate 202. In some embodiments, the p-type dopant used to form the p-type well may include boron (B) or gallium (Ga). Suitable doping may include ion implantation and / or diffusion processes of the dopant. Substrate 202 may also include other semiconductors, such as germanium (Ge), silicon carbide (SiC), silicon germanium (SiGe), germanium tin (GeSn), or diamond. Optionally, substrate 202 may include compound semiconductors and / or alloy semiconductors. Additionally, the substrate 202 may optionally include an epitaxial layer (epi layer) that can be strained for performance enhancement, and may include a silicon-on-insulator (SOI) or germanium-on-insulator (GeOI) structure, and / or may have other suitable enhancement components.

[0028] In some embodiments, the stack 204 on top of the substrate 202 includes a channel layer 208 of a first semiconductor component interleaved with a sacrificial layer 206 of a second semiconductor component. Alternatively, the sacrificial layer 206 may be described as being interleaved with channel layers 208. The first semiconductor component and the second semiconductor component are different. In some embodiments, the sacrificial layer 206 comprises silicon-germanium (SiGe) or germanium-tin (GeSn), and the channel layer 208 comprises silicon (Si). It should be noted that, as Figure 4 As shown, the sacrificial layer 206 and the channel layer 208 are arranged alternately in three (3) layers. This is for illustrative purposes only and is not intended to limit the specific references in the claims. It will be understood that any number of epitaxial layers can be formed in the stack 204. The number of layers depends on the performance requirements of the semiconductor device 200. In some embodiments, the number of channel layers 208 is between 2 and 10.

[0029] The sacrificial layer 206 and the channel layer 208 in the stack 204 can be deposited using molecular beam epitaxy (MBE), vapor deposition (VPE), and / or other suitable epitaxial growth processes. As described above, in at least some examples, the sacrificial layer 206 comprises an epitaxially grown silicon-germanium (SiGe) layer, and the channel layer 208 comprises an epitaxially grown silicon (Si) layer. In some embodiments, the Ge% in the sacrificial layer 206 may be not less than about 20%, such as about 30% or higher. In some embodiments, the sacrificial layer 206 and the channel layer 208 are substantially dopant-free (i.e., having a dopant content of about 0 atoms / cm²). 3To approximately 1x10 17 atoms / cm 3 (external dopant concentration), where, for example, no intentional doping is performed during the epitaxial growth process for the stack 204.

[0030] refer to Figure 1A and Figure 5 Method 100 includes a frame 104 in which a fin structure 212 is formed from a stack 204 and a substrate 202. To pattern the stack 204, a hard mask layer may be deposited over the stack 204 to form an etching mask. The hard mask layer may be a single layer or multiple layers. For example, the hard mask layer may include a pad oxide layer and a pad nitride layer disposed over the pad oxide layer. The fin structure 212 may be patterned from the stack 204 and the substrate 202 using photolithography and etching processes. The photolithography process may include photoresist coating (e.g., spin coating), soft baking, mask alignment, exposure, post-exposure baking, photoresist development, rinsing, drying (e.g., spin drying and / or hard baking), other suitable photolithography techniques and / or combinations thereof. In some embodiments, the etching process may include dry etching (e.g., RIE etching), wet etching and / or other etching methods.

[0031] like Figure 5 As shown, the etching process at frame 104 forms a trench extending vertically through the stack 204 and a portion of the substrate 202. The trench defines a fin structure 212. In some embodiments, dual-patterning or multi-patterning processes can be used to define the fin structure, for example, the fin structure having a smaller pitch than that achievable using a single direct lithography process. For example, in one embodiment, a material layer is formed over the substrate, and the material layer is patterned using a photolithography process. Spacers are formed alongside the patterned material layer using a self-aligned process. The material layer is then removed, and the remaining spacers or mandrels can then be used to pattern the fin structure 212 by etching the stack 204 and a portion of the substrate 202. Figure 5 As shown, the fin structure 212 extends vertically along the Z direction and longitudinally along the X direction. The fin structure 212 provides an active region for the subsequently formed transistor, which includes a channel region (such as...). Figure 8 As shown, denoted as 212C) and the source / drain region (e.g. Figure 9 As shown, it is represented as 212SD). Figure 5 As shown, the fin structure 212 includes a fin-shaped substrate 212B patterned from the substrate 202 and a patterned stack 204 directly disposed above the fin-shaped substrate 212B. In... Figure 5 In the illustrated embodiment, the top portion of the patterned stack 204 and the fin base 212B has substantially straight sidewalls; while the bottom portion of the fin base 212B has tapered sidewalls due to the load effect during the patterning process.

[0032] refer to Figure 1A and Figure 6 Method 100 includes a frame 106, wherein an isolation structure 214 (or isolation member 214) is formed around the fin base 212B of the fin structure 212. Figure 5 In some embodiments shown, isolation structure 214 is disposed on the sidewall of fin substrate 212B. In some embodiments, isolation structure 214 may be formed in trenches to isolate adjacent active regions located in fin structure 212. In some embodiments, isolation structure 214 is a shallow trench isolation (STI) component. For example, in some embodiments, a dielectric layer is first deposited over substrate 202 to fill the trenches. In some embodiments, the dielectric layer may include silicon oxide, silicon carbon oxide, silicon carbonitride, silicon oxynitride, fluorine-doped silicate glass (FSG), low-k dielectric, combinations thereof, and / or other suitable materials. In various examples, the dielectric layer may be deposited by chemical vapor deposition (CVD), subatmospheric pressure CVD (SACVD), flowable CVD, spin coating, and / or other suitable processes. The deposited dielectric material is then thinned and planarized, for example, by chemical mechanical polishing (CMP). The planarized dielectric layer is further recessed or pulled back by dry etching, wet etching, and / or combinations thereof to form Figure 6 The isolation structure 214 is shown. In the illustrated embodiment, the top surface of the isolation structure 214 has a dish-shaped profile due to the load effect during the etching process. After recessing, the fin structure 212 rises above the isolation structure 214, while the fin substrate 212B is at least partially embedded or buried in the isolation structure 214. In the illustrated embodiment, the edge of the dish-shaped profile of the isolation structure 214 intersects the sidewall of the top portion of the fin substrate 212B.

[0033] Still referencing Figure 1A and Figure 6Method 100 includes frame 108, wherein an isolation structure protective layer 215 is formed over an isolation structure 214 and around the top portion of a finned substrate 212B. The composition of the isolation structure protective layer 215 differs from that of the isolation structure 214. In some embodiments, the isolation structure 214 comprises silicon oxide, and the isolation structure protective layer 215 comprises silicon nitride, silicon carbonitride, or silicon oxynitride. For example, in some embodiments, a nitride-containing material is first deposited over the isolation structure 214 to fill trenches with the nitride. In various examples, the nitride-containing material can be deposited using CVD processes, subatmospheric pressure CVD (SACVD) processes, flowable CVD processes, spin-coating processes, and / or other suitable processes. The deposited nitride-containing material is then thinned and planarized, for example, by a CMP process. The planarized nitride-containing material is further recessed or pulled back using dry etching processes, wet etching processes, and / or combinations thereof to form the isolation structure protective layer 215. In the illustrated embodiment, the top surface of the isolation structure protective layer 215 has a dish-shaped profile due to the loading effect during the etching process. After recessing, the fin structure 212 rises above the isolation structure protective layer 215. In the illustrated embodiment, the edge of the dish-shaped profile of the isolation structure protective layer 215 intersects with the sidewall of the top portion of the fin substrate 212B. The isolation structure 214 and the isolation structure protective layer 215 can be collectively referred to as the isolation structure. The thickness of the isolation structure protective layer 215 can range from about 10 nm to about 50 nm. This range is not arbitrary or negligible. If the thickness is less than about 10 nm, the isolation structure protective layer 215 itself may be etched through due to the limited etching contrast in the subsequent etching process, impairing its protective function for the isolation structure 214. If the thickness is greater than about 50 nm, the bottommost sacrificial layer 206 may be buried beneath it and difficult to remove in the subsequent gate replacement process.

[0034] refer to Figure 1A and Figures 7 to 8 Method 100 includes block 110, wherein a dummy gate stack 220 and gate spacers 226 are formed over the channel region 212C of the fin structure 212. The dummy gate stack 220 serves as a placeholder to undergo various processes and will be removed and replaced by a functional gate structure. Other processes and configurations are also possible. Figure 7 As shown, the dummy gate stack 220 and gate spacer 226 are formed above the fin structure 212, and the fin structure 212 can be divided into a channel region 212C located below the dummy gate stack 220 and gate spacer 226 and a source / drain region 212SD not located below the dummy gate stack 220 and gate spacer 226. The channel region 212C is adjacent to the source / drain region 212SD. Figure 8As shown, the channel region 212C is disposed along the X direction between the two source / drain regions 212SD. As used herein, the source / drain region or "S / D region" can refer to a region that provides a source and / or drain for one or more devices. It can also refer to the source or drain of one or more devices. Furthermore, in Figure 8 In the middle (and in the following figures showing the cross-sectional view in the XZ plane), the horizontal dashed line B 214 The position of the bottom surface of the isolation structure 214 is marked.

[0035] The formation of the dummy gate stack 220 may include the deposition of layers in the dummy gate stack 220 and the patterning of these layers. (See reference...) Figure 7 The dummy dielectric layer 216, dummy electrode layer 218, and gate top hard mask layer 222 can be blanket-deposited over the semiconductor device 200. The dummy dielectric layer 216 can be conformally deposited on the fin structure 212 using chemical vapor deposition (CVD), atomic layer deposition (ALD), oxygen plasma oxidation, or other suitable processes. For ease of description of layers having a substantially uniform thickness over various regions, the term "conformally" is used herein. In some cases, the dummy dielectric layer 216 may comprise silicon oxide. Subsequently, the dummy electrode layer 218 can be deposited over the dummy dielectric layer 216 using CVD, ALD, or other suitable processes. In some cases, the dummy electrode layer 218 may comprise polysilicon. The dummy electrode layer 218 can be formed by depositing polysilicon over the dummy dielectric layer 216, depositing amorphous silicon over the polysilicon in a PE-CVD process, followed by a CMP process to remove the amorphous silicon and an etch-back process to pull back the polysilicon. For patterning purposes, a gate top hard mask layer 222 can be deposited on the dummy electrode layer 218 using CVD, ALD, or other suitable processes. For example... Figure 8 As shown, the gate-top hard mask layer 222, dummy electrode layer 218, and dummy dielectric layer 216 can then be patterned to form a dummy gate stack 220. For example, the patterning process may include photolithography (e.g., photolithography or electron beam lithography) and etching. The photolithography process may also include photoresist coating (e.g., spin coating), soft baking, mask alignment, exposure, post-exposure baking, photoresist development, rinsing, drying (e.g., spin drying and / or hard baking), other suitable photolithography techniques, and / or combinations thereof. The photolithography process forms a patterned photoresist layer. The patterned photoresist layer is then applied as an etching mask in the etching process to pattern the gate-top hard mask layer 222, dummy electrode layer 218, and dummy dielectric layer 216. In some embodiments, the etching process may include dry etching (e.g., RIE etching), wet etching, and / or other etching methods. In some embodiments, the gate-top hard mask layer 222 is a bilayer structure, which may include a silicon oxide layer and a silicon nitride layer located above the silicon oxide layer.

[0036] The formation of gate spacer 226 may include depositing a gate spacer layer and etching back the gate spacer layer. In some embodiments, the gate spacer layer is conformally deposited over the semiconductor device 200, including over the top surface and sidewalls of the dummy gate stack 220. The gate spacer layer may be a single layer or multiple layers. At least one of the gate spacer layers may include silicon carbonitride, silicon carbon oxide, silicon carbonitride, or silicon nitride. The gate spacer layer may be deposited over the dummy gate stack 220 using processes such as CVD, subatmospheric pressure CVD (SACVD), ALD, or other suitable processes. Subsequently, an anisotropic etching process may be performed to remove the horizontal portion of the gate spacer layer from the top-facing surface of the semiconductor device 200, including from the top surface of the dummy gate stack 220. The remaining vertical portion of the gate spacer layer covers the sidewalls of the dummy gate stack 220 as gate spacer 226.

[0037] refer to Figure 1A and Figures 9 to 10 Method 100 includes block 112, wherein the source / drain regions 212SD of the fin structure 212 are anisotropically recessed to form source / drain trenches 228. Anisotropic etching may include dry etching or a suitable etching process that etches portions of the source / drain regions 212SD and the substrate 202. The resulting source / drain trenches 228 extend vertically through the depth of the stack 204 and partially into the substrate 202 (i.e., partially recessing the fin substrate 212B). An exemplary dry etching process for block 110 may employ oxygen-containing gases, fluorine-containing gases (e.g., CF4, SF6, CH2F2, CHF3, and / or C2F6), chlorine-containing gases (e.g., Cl2, CHCl3, CCl4, and / or BCl3), bromine-containing gases (e.g., HBr and / or CHBr3), iodine-containing gases, other suitable gases, and / or plasmas and / or combinations thereof. Figure 9 As shown, the source / drain region 212SD of the fin structure 212 is recessed to expose the sidewalls of the sacrificial layer 206 and the channel layer 208. Because the source / drain trench 228 extends into the substrate 202 below the stack 204, the source / drain trench 228 includes a bottom surface and lower sidewalls defined in the substrate 202.

[0038] like Figure 10As shown, above the source / drain region 212SD, most of the fin structure 212 is etched away, and the top surface of the fin substrate 212B is exposed in the source / drain region 212SD. Additionally, the recessed top surface of the fin substrate 212B can be lower than the top surface of the isolation structure protective layer 215. Because the gate spacer 226 is etched at a slower rate than the fin structure 212, the gate spacer 226 in the source / drain region 212SD rises above the top surface of the fin substrate 212B. The remaining gate spacer 226 in the source / drain region 212SD is also referred to as the fin spacer. The fin spacer protects the portion of the isolation structure protective layer 215 directly below it from being removed during the recess of the source / drain region 212SD.

[0039] refer to Figure 1A and Figure 11 Method 100 includes block 114, wherein a sacrificial layer 206 is selectively removed. Selective removal of the sacrificial layer 206 releases a channel layer 208. Depending on the design, the channel layer 208 may take the form of nanowires, nanorods, nanosheets, or other nanostructures. The selective removal of the sacrificial layer 206 creates spaces between and around adjacent channel layers 208. The selective removal of the sacrificial layer 206 can be achieved by a selective dry etching process. Example selective dry etching processes may include the use of one or more fluorine-containing (F) gases. In some embodiments, the fluorine-containing gas may include fluorine (F2), hydrogen fluoride (HF), chlorine trifluoride (ClF3), fluorine radicals (F2), etc. ) and nitrogen trifluoride free radicals ( In some embodiments, the sacrificial layer 206 can be etched by vapor-phase etching using fluorine-containing gases such as F2, HF, and ClF3. In some embodiments, it can be etched by using free radicals generated from fluorine-containing gases by a remote plasma system (such as...). , and The sacrificial layer 206 is etched using a radical phase etching process. The dry etching process may have byproducts such as silicon tetrafluoride (SiF4) and germanium tetrafluoride (GeF4). In some embodiments, the fluorinated gas may have a flow rate ranging from about 100 standard cubic centimeters per minute (sccm) to about 500 sccm. In some embodiments, the dry etching process may be performed at a temperature ranging from about -20°C to about 150°C and a pressure ranging from about 100 mTorr to about 1000 mTorr.

[0040] refer to Figure 1A and Figure 12Method 100 includes block 116, wherein a dielectric dummy layer 230 is deposited to fill the space between channel layers 208. The dielectric dummy layer 230 may first be deposited as a blanket layer, filling the space between channel layers 208 and covering the sidewalls of channel layers 208, as well as other exposed surfaces in the source / drain trench 228. Subsequently, portions of the dielectric dummy layer 230 in the source / drain trench 228 are removed in an anisotropic process, while other portions intersecting with the channel layers 208 in the channel region are retained as dielectric dummy layer 230. The dielectric dummy layer 230 may be an oxide, such as silicon oxide in some embodiments, and may be deposited using ALD, flowable chemical vapor deposition (FCVD), plasma-enhanced chemical vapor deposition (PECVD), or other suitable deposition processes. To improve gap-filling capability without leaving voids underneath, the deposition of the dielectric dummy layer 230 may include an ALD process to first form a thin dielectric layer on the exposed surface of the channel layer 208, followed by an FCVD process (e.g., approximately 10 cycles of FCVD oxide deposition) to form a thick dielectric layer on the now uniform material surface provided by the thin dielectric layer. The combination of the ALD and FCVD processes improves gap-filling capability without affecting production throughput. The thin and thick dielectric layers together define the dielectric dummy layer 230.

[0041] refer to Figure 1A and Figure 13 Method 100 includes a frame 118 in which an internal spacer recess 232 is formed. The dielectric dummy layer 230 is selectively and partially recessed to form the internal spacer recess 232. The internal spacer recess 232 may have a rectangular profile as shown. Alternatively, the internal spacer recess 232 may have a concave profile that curves away from the source / drain trench 228. In embodiments, selective wet etching or selective dry etching processes can be used to perform the selective recessing of the dielectric dummy layer 230. Example selective wet etching processes may include using diluted hydrofluoric acid (DHF) or a mixture of hydrofluoric acid (HF) and ammonium fluoride (NH4F). Example selective dry etching processes may include using anhydrous hydrogen fluoride (HF) vapor, trifluoromethane (CHF3), nitrogen trifluoride (NF3), hydrogen (H2), ammonia (NH3), carbon tetrafluoride (CF4), sulfur hexafluoride (SF6), or combinations thereof.

[0042] refer to Figure 1A and Figure 14Method 100 includes block 120, wherein an internal spacer 236 is formed in an internal spacer recess 232. Forming the internal spacer 236 may include depositing an internal spacer layer above an exposed surface of a source / drain trench 228, including filling the internal spacer recess 232. In some embodiments, the internal spacer layer may include silicon carbonitride (SiCN), silicon carbonitride oxynitride (SiOCN), silicon nitride (SiN), silicon carbonitride (SiOC), or silicon oxynitride (SiON). In some embodiments, the internal spacer layer may be deposited using CVD or ALD. Subsequently, the internal spacer layer is etched back to form the internal spacer 236 in the internal spacer recess 232. In some embodiments, the etch-back of the internal spacer layer may include using a dry etching process, such as a plasma-assisted reactive ion etching (RIE) process. Example dry etching processes may include the use of boron trichloride (BCl3), chlorine (Cl2), hydrogen chloride (HCl), methane (CH4), nitrogen trifluoride (NF3), carbon tetrafluoride (CF4), sulfur hexafluoride (SF6), nitrogen (N2), or combinations thereof. In the depicted embodiment, the internal spacer 236 is substantially maintained below the gate spacer 226 and does not extend directly below the dummy gate stack 220. Alternatively, the internal spacer 236 may extend laterally directly below the dummy gate stack 220.

[0043] refer to Figure 1A and Figures 15 to 16 Method 100 includes block 122, wherein a source / drain trench 228 is further extended downward by anisotropic etching. The additional extension of the source / drain trench 228 facilitates self-aligned back-side etching later when forming back-side via openings. Anisotropic etching may include dry etching with an oxygen-containing gas, a fluorine-containing gas (e.g., CF4, SF6, CH2F2, CHF3 and / or C2F6), a chlorine-containing gas (e.g., Cl2, CHCl3, CCl4 and / or BCl3), a bromine-containing gas (e.g., HBr and / or CHBr3), an iodine-containing gas, other suitable gases, and / or plasma and / or combinations thereof. Figure 16 As shown, above the source / drain region 212SD, the recessed top surface of the fin substrate 212B can be lower than the bottom surface of the isolation structure protective layer 215.

[0044] refer to Figure 1A and Figures 17 to 18 Method 100 includes block 124, wherein an interposer 238 is deposited at the bottom of a source / drain trench 228. The interposer 238 can be a single-layer / single-material structure, such as an epitaxial layer or a dielectric layer (also referred to as a bottom isolation layer). The dielectric layer can include SiN, SiON, SiOCN, SiO xOr other suitable dielectric materials. Optionally, the interposer 238 may be a multilayer structure, such as an epitaxial layer as a first sublayer and a bottom isolation layer disposed on the epitaxial layer as a second sublayer. In the depicted embodiment, the interposer 238 includes a bottom epitaxial layer 240 epitaxially grown from the top surface of the fin substrate 212B. The epitaxial growth of the bottom epitaxial layer 240 may include a cyclic process, wherein in each round of the cyclic process, the epitaxial layer (if any) grown from the sidewalls of the channel layer 208 is removed in a cleaning process, while the epitaxial layer 240 grown from the fin substrate 212B accumulates. For example, the epitaxial growth of the bottom epitaxial layer 240 may be performed by VPE, ultra-high vacuum CVD (UHV-CVD), MBE and / or other suitable epitaxial growth processes. In some embodiments, the bottom epitaxial layer 240 includes the same material as the substrate 202, such as silicon. In some alternative embodiments, the bottom epitaxial layer 240 includes a different semiconductor material other than silicon, such as SiGe, SiSn or other suitable semiconductor materials. In some embodiments, the bottom epitaxial layer 240 is dopant-free, wherein, for example, no intentional doping is performed during the epitaxial growth process. In contrast, in one example, the substrate 202 is lightly doped and has a higher doping concentration than the bottom epitaxial layer 240. The bottom epitaxial layer 240 provides a high-resistance path from the S / D region to the semiconductor substrate, thereby suppressing leakage current in the semiconductor substrate. In the depicted embodiment, the bottom isolation layer 242 may be connected to the bottommost inner spacer 236.

[0045] A bottom isolation layer 242 is formed above the bottom epitaxial layer 240. Because the bottom isolation layer 242 can be connected to the S / D component, and oxygen content can oxidize the S / D component, the bottom isolation layer 242 can be formed of an oxygen-free dielectric material, such as an oxygen-free nitride. In the example process, a chlorinated silicon nitride layer is deposited above the source / drain trench 228 (including above the top surface of the bottom epitaxial layer 240). Ammonia (NH3) and chlorinated silicon precursors (such as silicon tetrachloride (SiCl4), dichlorosilane (Si2H4Cl2), dichlorosilane (SiH2Cl2), or hexachlorosilane (SiCl4) can be used. xA chlorinated silicon nitride layer is deposited using Cl6. Plasma-enhanced atomic layer deposition (PEALD) or thermal ALD can be used to deposit the chlorinated silicon nitride layer. A directional plasma treatment process is then performed to remove chlorine from the bottom portion of the chlorinated silicon nitride layer. In some embodiments, the directional plasma treatment may include using argon (Ar) plasma, nitrogen (N2) plasma, and / or hydrogen (H2) plasma. After the directional plasma treatment, a dry etching process using a fluorinated etchant (e.g., trifluoromethane (CHF3), nitrogen trifluoride (NF3), hydrogen (H2), ammonia (NH3), carbon tetrafluoride (CF4), or sulfur hexafluoride (SF6)) can be performed. Because the dry etching process etches the chlorinated silicon nitride along the sidewalls at a faster rate than etching the relatively chlorine-free silicon nitride layer at the bottom of the source / drain trench 228, a bottom isolation layer 242 can be formed over the bottom epitaxial layer 240. In the depicted embodiment, the bottom isolation layer 242 may be in contact with the bottommost internal spacer 236. The top surface of the bottom isolation layer 242 is lower than the bottom surface of the bottom channel layer 208.

[0046] At the end of the operation at box 124, an intermediary component 238 is formed. In the depicted embodiment, the intermediary component 238 includes a bottom epitaxial layer 240 and a bottom isolation layer 242. It is worth noting that the formation of the bottom epitaxial layer 240 in the intermediary component 238 may be optional. That is, in some embodiments, the epitaxial layer may be omitted in the final structure, and the intermediary component 238 may be a single-layer structure including the bottom isolation layer 242. Alternatively, the formation of the bottom isolation layer 242 may be optional. That is, in some embodiments, the bottom isolation layer may be omitted in the final structure, and the intermediary component 238 may be a single-layer structure including the bottom epitaxial layer 240.

[0047] refer to Figure 1A and Figures 19 to 20 Method 100 includes block 126, wherein source / drain components 244 are epitaxially grown from exposed semiconductor surfaces (including sidewalls of channel layer 208) in source / drain trench 228. Although not explicitly shown, method 100 may include a cleaning process for cleaning the surface of semiconductor device 200 prior to the formation of any epitaxial layer. The cleaning process may include dry cleaning, wet cleaning, or a combination thereof. In some examples, wet cleaning may include using a mixture of deionized water, ammonium hydroxide and hydrogen peroxide, a mixture of deionized water, hydrochloric acid and hydrogen peroxide, a mixture of sulfuric acid peroxide, and / or hydrofluoric acid for oxide removal. Dry cleaning processes may include helium (He) and hydrogen (H2) treatment.

[0048] refer to Figure 19The source / drain component 244 can be n-type or p-type. When the source / drain component 244 is n-type, it can include silicon (Si) and n-type dopants such as phosphorus (P), arsenic (As), antimony (Sb), or combinations thereof. When the source / drain component 244 is p-type, it can include silicon germanium (SiGe) and p-type dopants such as boron (B), boron difluoride (BF2), or combinations thereof. Although not explicitly shown in the figures, in some embodiments, the source / drain component 244 can include multiple layers. For example, the source / drain component 244 can include a lightly doped epitaxial component above the bottom isolation layer 242 and a heavily doped epitaxial component above the lightly doped epitaxial component. The lightly doped epitaxial component has a smaller dopant concentration and impurity concentration to reduce crystal defects. The heavily doped epitaxial component occupies most of the volume to reduce contact resistance. The source / drain components 244 can be formed using vapor phase epitaxy (VPE), ultra-high vacuum CVD (UHV-CVD), or molecular beam epitaxy (MBE). In-situ doping can be used to achieve the doping of the source / drain components 244.

[0049] refer to Figure 20 , Figure 20 Includes a partial cross-sectional view of the 212SD spanning multiple adjacent source / drain regions. Figure 20 In some embodiments shown, the n-type source / drain component 244N may be adjacent to the p-type source / drain component 244P. The n-type source / drain component 244N may comprise silicon (Si) and an n-type dopant, such as phosphorus (P), arsenic (As), or antimony (Sb). The p-type source / drain component 244P may comprise silicon germanium (SiGe) and a p-type dopant, such as boron (B). Each of the n-type source / drain component 244N and the p-type source / drain component 244P may be in direct contact with the top surface of the bottom isolation layer 242. For ease of illustration and description, the n-type source / drain component 244N and the p-type source / drain component 244P may be collectively referred to as source / drain component 244. Similarly, as... Figure 20 As shown, in some embodiments, in the YZ plane, each source / drain component 244 may include a portion suspended above the isolation structure 214 and the isolation structure protective layer 215.

[0050] refer to Figure 1A and Figures 21 to 22 Method 100 includes block 128, wherein a contact etch stop layer (CESL) 246 and an interlayer dielectric (ILD) layer 248 are deposited in the source / drain region 212SD. Figure 21As shown, CESL 246 is deposited over source / drain components 244. CESL 246 may comprise silicon nitride or aluminum nitride. In some embodiments, CESL 246 may be deposited using CVD or ALD. An ILD layer 248 is then deposited over CESL 246. In some embodiments, ILD layer 248 comprises materials such as tetraethyl orthosilicate (TEOS) oxide, undoped silicate glass, or silicon-doped materials such as borosilicate glass (BPSG), fused silica glass (FSG), phosphosilicate glass (PSG), boron-doped silicon glass (BSG), and / or other suitable dielectric materials. ILD layer 248 may be deposited using CVD, flowable CVD (FCVD), spin coating, or suitable deposition techniques. Figure 22 As shown, the fin spacer 226 is also covered by CESL 246. Similarly, as... Figure 21 As shown, after depositing the ILD layer 248, the semiconductor device 200 can be planarized using a planarization process to remove the gate top hard mask layer 222 and expose the dummy gate stack 220. For example, the planarization process may include a CMP process. After planarization, the top surfaces of the CESL 246, ILD layer 248, gate spacer 226, and dummy gate stack 220 are coplanar.

[0051] refer to Figure 1A and Figure 23 Method 100 includes block 130, in which a dielectric gate 250 is formed to replace certain dummy gate stacks 220. In some embodiments, a continuous polysilicon on oxide diffusion edge (CPODE) process is used to replace selected dummy gate stacks 220 with the dielectric gate 250. Therefore, the dielectric gate 250 is also referred to as a CPODE structure or CPODE component. CPODE components provide isolation, suppress interference, and prevent adjacent gate structures from merging. In some embodiments, the formation of the dielectric gate 250 includes etching the dummy gate stacks 220 to form a CPODE trench, extending the CPODE trench downward through the channel layer 208 and the dielectric dummy layer 230 and further into the substrate 202, and filling the CPODE trench with one or more dielectric materials. In a top view, the dielectric gate 250 inherits the dimensions of the dummy gate stacks 220. The sidewalls of the dielectric gate 250 are in contact with the gate spacer 226, the internal spacer 236, and the end portions of the channel layer 208 (represented as semiconductor ends 208E).

[0052] refer to Figure 1A and Figures 24 to 25Method 100 includes block 132, in which dummy gate stack 220 and subsequently sacrificial layer 206 are selectively removed. Exposure of the dummy gate stack 220 after removal of the gate top hard mask layer 222 allows it to be removed. Removal of the dummy gate stack 220 may include one or more etching processes selectively targeting the material of the dummy gate stack 220. For example, selective wet etching, selective dry etching, or a combination thereof selectively targeting the dummy gate stack 220 may be used to perform the removal of the dummy gate stack 220. Removal of the dummy gate stack 220 forms a gate trench 252 that exposes a stack of channel layer 208 and sacrificial layer 206. After removal of the dummy gate stack 220, the sacrificial layer 206 in the channel region 212C is exposed and subsequently removed in a separate etching process. For example, a selective wet etching process or a selective dry etching process may be performed to remove the sacrificial layer 206. Example selective wet etching processes may include using diluted hydrofluoric acid (DHF) or a mixture of hydrofluoric acid (HF) and ammonium fluoride (NH4F). Example selective dry etching processes may include using anhydrous hydrogen fluoride (HF) vapor, trifluoromethane (CHF3), nitrogen trifluoride (NF3), hydrogen (H2), ammonia (NH3), carbon tetrafluoride (CF4), sulfur hexafluoride (SF6), or combinations thereof. After the sacrificial layer 206 is removed, the channel layer 208 is released as a channel member (hereinafter also referred to as channel member 208).

[0053] refer to Figure 1B and Figures 26 to 27 Method 100 includes block 134, wherein a gate structure 260 (e.g., a p-type gate structure 260P for a p-type transistor and an n-type gate structure 260N for an n-type transistor) is formed in a gate trench 252 to enclose each channel member 208. Due to its metal layer, the gate structure 260 is also referred to as a metal gate structure 260. In the depicted embodiment, the gate structure 260 includes an interface layer 262 adjoining the channel member 208, a high-k dielectric layer 264 above the interface layer 262, and a gate electrode 266 above the high-k dielectric layer 264. The interface layer 262 and the high-k dielectric layer 264 are collectively referred to as the gate dielectric layer. The dielectric constant of the gate dielectric layer is greater than the dielectric constant of the gate spacer 226. The thickness of the gate spacer 226 is greater than the thickness of the gate dielectric layer.

[0054] Interface layer 262 may include a dielectric material such as silicon oxide, hafnium silicate, or silicon oxynitride. Interface layer 262 may be formed by chemical oxidation, thermal oxidation, atomic layer deposition (ALD), chemical vapor deposition (CVD), and / or other suitable methods. In the illustrated embodiment, interface layer 262 is formed by thermal oxidation of the semiconductor material exposed in the gate trench 252. Therefore, interface layer 262 is formed on semiconductor surfaces (such as the exposed surface of channel member 208 and the top surface of fin substrate 212B), but not on dielectric surfaces (such as the sidewalls of internal spacer 236, the sidewalls of gate spacer 226, and the top surface of isolation structure protective layer 215). High-k dielectric layer 264 may include a high-k dielectric material such as hafnium oxide. Optionally, the gate dielectric layer may include other high-k dielectric materials, such as titanium oxide (TiO2), hafnium zirconium oxide (HfZrO), tantalum oxide (Ta2O5), hafnium silicon oxide (HfSiO4), zirconium oxide (ZrO2), zirconium silicon oxide (ZrSiO2), lanthanum oxide (La2O3), aluminum oxide (Al2O3), zirconium oxide (ZrO), yttrium oxide (Y2O3), hafnium lanthanum oxide (HfLaO), lanthanum silicon oxide (LaSiO), aluminum silicon oxide (AlSiO), hafnium tantalum oxide (HfTaO), hafnium titanium oxide (HfTiO), combinations thereof, or other suitable materials. The dielectric constant of the high-k dielectric layer 264 is greater than that of the gate spacer 226. The high-k dielectric layer 264 can be formed by ALD, physical vapor deposition (PVD), CVD, oxidation, and / or other suitable methods. Figure 25 As shown, the high-k dielectric layer 264 can be conformally deposited on the exposed dielectric surface exposed in the gate trench 252.

[0055] The gate electrode 266 includes a function metal layer and a metal filler layer above the function metal layer. The function metal layer is a p-type function metal layer in a p-type transistor or an n-type function metal layer in an n-type transistor. The p-type function metal layer includes a metal selected from, but not limited to, titanium nitride, tantalum nitride, ruthenium, molybdenum, tungsten, platinum, or combinations thereof. The n-type function metal layer includes a metal selected from, but not limited to, titanium, aluminum, tantalum carbide, tantalum carbonitride, tantalum silicon nitride, or combinations thereof. In some embodiments, the p-type or n-type function metal layer includes multiple layers deposited by CVD, PVD, and / or other suitable processes. The metal filler layer includes aluminum, tungsten, cobalt, copper, and / or other suitable materials, and is formed by CVD, PVD, plating, and / or other suitable processes.

[0056] refer to Figure 1B and Figures 28 to 29Method 100 includes block 136, in which a gate end dielectric component 270 is formed. The gate end dielectric component 270 segments an otherwise continuous gate structure 260; it may also be referred to as a cut metal gate (CMG) component 270. In the illustrated embodiment, the CMG component 270 isolates n-type and p-type GAA transistors, which function as dual transistors in a CMOS device, from other adjacent devices. The CMG component 270 may be a single-layer or multi-layer structure. For a multi-layer structure, the CMG component 270 may include a dielectric liner 272 and a dielectric fill layer 274. In an exemplary process flow, forming the CMG component 270 includes etching through the gate structure 260 to form a CMG trench, which may also extend through an isolation structure protective layer 215 and into an isolation structure 214 for better isolation; conformally depositing the dielectric liner 272 on the sidewalls and bottom surface of the CMG trench; depositing the dielectric fill layer 274 to fill the CMG trench; and performing a planarization process (e.g., CMP) to remove excess dielectric material. In some embodiments, the dielectric liner 272 is an oxide (e.g., silicon oxide), and the dielectric fill layer 274 is oxygen-free, such as a nitride (e.g., silicon nitride or silicon carbonitride). The dielectric fill layer 274 can be deposited by ALD, CVD, PVD, or other suitable processes. The dielectric liner 272 and the dielectric fill layer 274 together define the CMG component 270. Figure 29 As shown, CMG component 270 also extends along the X direction into the source / drain region.

[0057] refer to Figure 1B and Figures 30 to 31 Method 100 includes block 138, wherein a source / drain contact 280 and an optional silicide component 282 are formed in a source / drain region 212SD. In an exemplary process, contact vias are formed by etching through ILD layer 248 and CESL 246. Figure 30As shown, the etching process can be a self-aligned process, using the vertical sidewalls of CESL 246 as an etch stop layer to remove a portion of the ILD layer 248 above the source / drain components 244. Optionally, the upper portion of the source / drain components 244 can be etched to have a concave shape as the bottom of the contact hole. A silicide component 282 is formed at the bottom of the contact hole. The silicide component 282 may include titanium silicide (TiSi), nickel silicide (NiSi), molybdenum silicide (MoSi), tungsten silicide (WSi), nickel platinum silicide (NiPtSi), nickel platinum germanium silicide (NiPtGeSi), nickel germanium silicide (NiGeSi), ytterbium silicide (YbSi), platinum silicide (PtSi), iridium silicide (IrSi), erbium silicide (ErSi), cobalt silicide (CoSi), or other suitable compounds. Subsequently, source / drain contacts 280 are formed on the silicide component 282. Each source / drain contact 280 may include a conductive barrier layer and a body metal layer. The conductive barrier layer may include titanium (Ti), tantalum (Ta), tungsten (W), cobalt (Co), ruthenium (Ru), or conductive nitrides such as titanium nitride (TiN), titanium aluminum nitride (TiAlN), tungsten nitride (WN), tantalum nitride (TaN), or combinations thereof, and may be formed by CVD, PVD, ALD, and / or other suitable processes. The body metal layer may include tungsten (W), ruthenium (Ru), cobalt (Co), rhodium (Rh), copper (Cu), nickel (Ni), molybdenum (Mo), or other suitable metals, and may be formed by CVD, PVD, ALD, plating, or other suitable processes. The conductivity of the silicide component 282 is between that of the source / drain component 244 and the source / drain contact 280, and the conductivity of the source / drain contact 280 is greater than that of the source / drain component 244. The silicide component 282 and the source / drain contact 280 can be collectively referred to as the source / drain contact. For example... Figure 31 As shown, in cross section CC, the formation of the contact hole causes the CMG component 270 in the source / drain region to be recessed, and thus the source / drain contact 280 formed in the contact hole contacts the recessed top surface of the CMG component 27.

[0058] refer to Figure 1B and Figures 32 to 34Method 100 includes block 140, in which a gate via 284 and a source / drain contact via (also referred to as a contact via) 286 are formed. In an exemplary process, a capping layer 276 (also referred to as an etch stop layer 276) and a second ILD layer 278 are deposited on a semiconductor device 200. In some embodiments, the thickness of the ILD layer 248 is greater than the thickness of the second ILD layer 278. The via openings are then formed by etching through the second ILD layer 278 and the capping layer 276. In the via openings, the gate via opening exposes the top surface of the gate structure 260, and the contact via opening exposes the top surface of the source / drain contacts 280. Due to over-etching, the gate via openings may extend into the underlying gate structure 260. The gate via 284 is then formed within the respective gate via openings, and the contact via 286 is formed within the respective contact via openings. Figure 32 As shown, due to over-etching, the gate via 284 can be partially embedded in the gate structure 260, such that the bottom surface of the gate via 284 is lower than the bottom surface of the contact via 286. Each of the gate via 284 and the contact via 286 may include a conductive barrier layer and a body metal layer. The conductive barrier layer may include titanium (Ti), tantalum (Ta), tungsten (W), cobalt (Co), ruthenium (Ru), or conductive nitrides such as titanium nitride (TiN), titanium aluminum nitride (TiAlN), tungsten nitride (WN), tantalum nitride (TaN), or combinations thereof, and may be formed by CVD, PVD, ALD, and / or other suitable processes. The body metal layer may include tungsten (W), ruthenium (Ru), cobalt (Co), rhodium (Rh), copper (Cu), nickel (Ni), molybdenum (Mo), or other metals, and may be formed by CVD, PVD, ALD, plating, or other suitable processes. Figure 34 As shown, the contact via 286 corresponding to the n-type source / drain component 244N is electrically coupled to the ground reference voltage (VSS), and the contact via 286 corresponding to the p-type source / drain component 244P is electrically coupled to the power supply voltage (VDD) of the semiconductor device 200.

[0059] refer to Figure 1B and Figures 35 to 36 Method 100 includes block 142, in which the front side of the semiconductor device 200 is attached to a carrier 288 and flipped upside down. This allows access to the semiconductor device 200 from its back side for further processing. The operation at block 142 can use any suitable attachment process, such as direct bonding, hybrid bonding, using adhesives, or other bonding methods. The operation at block 142 may also include alignment, annealing, and / or other processes. In some embodiments, the carrier 288 may be a silicon wafer.

[0060] refer to Figure 1B and Figures 37 to 38Method 100 includes block 144, wherein a semiconductor device 200 is thinned from the back side. In some embodiments, the thinning process may involve mechanical polishing and / or chemical thinning. Initially, a significant amount of substrate material is removed from the substrate 202 by mechanical polishing. Subsequently, a chemical thinning process is employed, during which etch chemicals are applied to the back side of the substrate 202 for further thinning. In some embodiments, the thinning process utilizes an isolation structure 214 as a thinning stop layer, ensuring that the process stops at the bottom surface of the isolation structure 214. Due to the different material compositions of the isolation structure 214 and the substrate 202, the exposure of the isolation structure 214 results in a significant change in the endpoint signal, thereby providing high-precision thickness control. In some embodiments, a timer is used to control the thinning depth, such that the bottom portion of the isolation structure 214 can also be removed. Figure 37 As shown, since the tip of the dielectric gate 250 can extend below the bottom surface of the isolation structure 214, the thinning process can also remove the tip and expose the dielectric gate 250. Figure 38 As shown, after removing the substrate 202, the fin substrates 212B are separated from each other and are no longer connected through the substrate 202.

[0061] refer to Figure 1B and Figures 39 to 40 Method 100 includes block 146, wherein a hard mask 290 and a photoresist layer 292 are formed over the back side of a semiconductor device 200. The hard mask 290 may include oxides, nitrides, oxide oxynitrides, etc. In a further embodiment, the hard mask 290 is a silicon nitride layer. In some embodiments, the photoresist layer 292 is a three-layer photoresist layer, including a bottom layer, an intermediate layer above the bottom layer, and an upper layer above the intermediate layer. The bottom layer may be a bottom anti-reflective coating (BARC). The bottom layer may include an organic material. The intermediate layer may be formed of or include an inorganic material, which may be nitrides, oxide oxynitrides, oxides, etc. The upper layer is a photosensitive material. The intermediate layer has high etch selectivity relative to the upper and bottom layers. As a result, the upper layer serves as an etch mask for patterning the intermediate layer, and the intermediate layer serves as an etch mask for patterning the bottom layer. In some embodiments, the photoresist layer formed over the hard mask 290 may be another type of photoresist, such as a single-layer photoresist, a double-layer photoresist, etc. Pattern the photoresist layer 292 using any suitable photolithography technique to form the back-side opening 294 therein. For example... Figure 40 As shown, in the YZ plane, the back opening 294 spans over two adjacent source / drain components 244 of the same conductivity type and across the CMG component 270 stacked therebetween.

[0062] refer to Figure 1B and Figures 41 to 42Method 100 includes a frame 148 in which a back-side opening 294 extends to a hard mask 290. A pattern of a photoresist layer 292 is transferred to the hard mask 290 using a suitable etching process. During the etching process, the photoresist layer 292 can be consumed. In some embodiments, the etching process utilizes a bottom epitaxial layer 240 as an etch stop layer, ensuring that the process stops at the bottom surface of the bottom epitaxial layer 240. Because the material compositions of the bottom epitaxial layer 240 and the substrate 202 can be different (e.g., SiGe in the bottom epitaxial layer 240 and Si in the substrate 202), exposure of the bottom epitaxial layer 240 results in a significant change in the endpoint signal, thereby providing high-precision etch control. In some embodiments, a timer is used to control the depth of the back-side opening 294, such that the bottom portion of the bottom epitaxial layer 240 can also be removed. Figure 41 As shown, the back opening 294 exposes the bottom surface of the bottom epitaxial layer 240. (As indicated...) Figure 42 As shown, the extension of the dorsal opening 294 removes a portion of the fin-shaped base 212B located directly below the bottom epitaxial layer 240, and also thins a portion of the isolation structure 214 below the CMG component 270. As Figure 42 As shown, depending on the remaining thickness of the isolation structure 214, the CMG component 270 may also be exposed in the back opening 294.

[0063] refer to Figure 1B and Figures 43 to 46 Method 100 includes block 150, in which a bottom epitaxial layer 240 and a bottom isolation layer 242 are removed from a back-side opening 294 to form a back-side via opening in the back-side opening 294. After the bottom epitaxial layer 240 is exposed at the back-side opening 294, the operation at block 150 may apply a first etch process, which is tuned to be selective for the semiconductor material (e.g., SiGe) in the bottom epitaxial layer 240. The bottom isolation layer 242 serves as an etch stop layer to protect the source / drain components 244 from etching. The first etch process may be dry etching, wet etching, reactive ion etching, or other suitable etch methods. In some embodiments, the first etch process applies a wet etchant that completely removes the bottom epitaxial layer 240, while the materials of the fin substrate 212B, isolation structure 214, isolation structure protective layer 215, CMG component 270, and fin spacer 226 exposed in the back-side opening 294 remain substantially intact due to etch selectivity. In some embodiments, the wet etchant is different from the etchant used in the previous etching process applied at frame 148 (it may be a dry etchant). Figure 43As shown, the back opening 294 in the XZ plane presents a necking profile. The necking profile is created by a first sidewall portion extending through the hard mask 290 and a second sidewall portion formed by removing the bottom epitaxial layer 240. These two sidewall portions intersect at a turning point, referred to as "P," which defines the narrowest region of the necking profile. Figure 44 As shown, by removing the bottom epitaxial layer 240, the back-side opening 294 spans the CMG component 270. Subsequently, the operation at frame 150 can apply a second etching process, which is tuned to be selective for the material of the bottom isolation layer 242. The second etching process can be dry etching, wet etching, reactive ion etching, or other etching methods. Figure 45 and Figure 46 As shown, after removing the bottom isolation layer 242, the bottom surface of the source / drain component 244 is exposed in the back-side opening 294. (Reference) Figure 46 The back-side opening 294 can be considered to have two legs 294a corresponding to the back-side via opening and a trench portion (or bridging portion) 294b connecting the two legs 294a. The trench portion 294b extends across the CMG component 270 and along the isolation structure disposed on its sidewall. Compared to using the back-side via opening alone, the back-side opening 294 spanning the CMG component 270 provides a significantly larger opening. This enlarged opening, along with the reduced aspect ratio of the back-side via opening, widens the process window, facilitates the filling of conductive material into components that would otherwise exhibit a high aspect ratio, and mitigates cover inaccuracies during back-side lithography.

[0064] refer to Figure 1B and Figures 47 to 48 Method 100 includes a frame 152 in which a dielectric liner 296 is deposited on the sidewall of a back-side opening 294. The dielectric liner 296 also protects the gate structure from metal element diffusion when conductive elements are subsequently formed in the back-side opening 294. In the illustrated embodiment, the dielectric liner 296 is conformally deposited to have a substantially uniform thickness along the respective surfaces of the back side of the semiconductor device 200. In various embodiments, the dielectric liner 296 may include La2O3, Al2O3, SiOCN, SiOC, SiCN, SiO2, SiC, ZnO, ZrN, Zr2Al3O9, TiO2, TaO2, ZrO2, HfO2, Si3N4, Y2O3, AlON, TaCN, ZrSi, combinations thereof, or other suitable materials. The dielectric liner 296 can be deposited using ALD, CVD, or other suitable methods. Subsequently, an etching process is performed to break through and remove most of the horizontal portion of the dielectric liner 296. The etching process is also known as a breakthrough etching process. In some embodiments, the breakthrough etching process may include anisotropic dry etching, etc. For example... Figure 47As shown, the dielectric liner 296 is in contact with the sidewalls of the fin-shaped substrate 212B and the bottommost internal spacer 236. Figure 48 As shown, the dielectric liner 296 is also connected to the isolation structure 214, the isolation structure protective layer 215, and the fin spacer 226.

[0065] refer to Figure 1B and Figures 49 to 50 Method 100 includes a frame 154 in which a back-side via (also referred to as a back-side contact) 298 is formed in a back-side opening 294. In some embodiments, the back-side via 298 is formed by filling the back-side opening 294 (including the back-side via opening and the trench therebetween) with one or more conductive materials, and subsequently removing excess conductive material from the back side of the semiconductor device 200 in a planarization process. Figure 49 As shown, in the XZ plane, the back-side through-hole 298 inherits the sidewall profile of the back-side opening 294, which has a necked-down profile. The width of the back-side through-hole 298 first narrows downward along the Z direction and then expands after the inflection point P. Figure 50 As shown, the two legs of the back-side via 298, which fills the back-side via opening, rest on two source / drain components 244 of the same conductivity type (e.g., two P-type source / drain components 244P or two n-type source / drain components 244N), and the bridging portion of the back-side via 298 is in contact with the bottom surface of the isolation structure 214 and the CMG component 270 (if previously exposed). The legs and bridging portion of the back-side via 298 form a continuous conductive structure that connects the two source / drain components 244 to the same power line (e.g., VDD for the p-type source / drain component 244P or VSS for the n-type source / drain component 244N).

[0066] The back-side via 298 may include tungsten (W), ruthenium (Ru), cobalt (Co), rhodium (Rh), copper (Cu), molybdenum (Mo), nickel (Ni), titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), or other metals, and may be formed by CVD, PVD, ALD, plating, or other suitable processes. In the illustrated embodiment, the operation at frame 154 may optionally form a back-side silicide component 302 on the bottom surface of the source / drain component 244. The back-side silicide component 302 may include titanium silicide (TiSi), nickel silicide (NiSi), molybdenum silicide (MoSi), tungsten silicide (WSi), nickel platinum silicide (NiPtSi), nickel platinum germanium silicide (NiPtGeSi), nickel germanium silicide (NiGeSi), ytterbium silicide (YbSi), platinum silicide (PtSi), iridium silicide (IrSi), erbium silicide (ErSi), cobalt silicide (CoSi), or other suitable compounds. The back-side silicide component 302 reduces the contact resistance between the source / drain component 244 and the back-side via 298. The conductivity of the back-side silicide component 302 is between that of the source / drain component 244 and the back-side via 298, with the back-side via 298 having a higher conductivity than the source / drain component 244. The back-side silicide component 302 and the back-side via 298 can be collectively referred to as back-side contacts. Optionally, the back-side via 298 can directly contact the bottom surface of the source / drain component 244. Planarization operations (such as CMP processes) can be performed to remove excess conductive material and also thin the hard mask 290.

[0067] refer to Figure 1B and Figures 51 to 52Method 100 includes block 156, wherein a back-side ILD layer 304 and a photoresist layer 306 are formed over the back side of a semiconductor device 200. In some embodiments, the back-side ILD layer 304 comprises materials such as tetraethyl orthosilicate (TEOS) oxide, undoped silicate glass, or doped silicon oxide, such as borosilicate glass (BPSG), fused silica glass (FSG), phosphosilicate glass (PSG), boron-doped silicon glass (BSG), and / or other suitable dielectric materials. The back-side ILD layer 304 can be deposited using CVD, flowable CVD (FCVD), spin coating, or suitable deposition techniques. In some embodiments, the photoresist layer 306 is a three-layer photoresist layer comprising a bottom layer, an intermediate layer above the bottom layer, and a top layer above the intermediate layer. The bottom layer may be a bottom antireflective coating (BARC). The bottom layer may include an organic material. The intermediate layer may be formed of or comprise an inorganic material, which may be a nitride, oxynitride, oxide, etc. The top layer is a photosensitive material. The intermediate layer has high etch selectivity relative to the upper and lower layers. As a result, the upper layer is used as an etch mask for patterning the intermediate layer, and the intermediate layer is used as an etch mask for patterning the lower layer. In some embodiments, the photoresist layer formed above the back-side ILD layer 304 can be another type of photoresist, such as a single-layer photoresist, a double-layer photoresist, etc.

[0068] refer to Figure 1B and Figures 53 to 54 Method 100 includes a frame 158 in which a back-side trench 308 is formed in a back-side ILD layer 304. In some embodiments, a photoresist layer 306 is patterned using a suitable photolithography technique to form the back-side trench 308 therein, and the back-side trench 308 is subsequently extended to the back-side ILD layer 304 using a suitable etching process. The trench 308 exposes the bottom surface of a back-side via 298. In such cases... Figure 54 In the illustrated embodiment, each back-side trench 308 is located directly below the leg of the corresponding back-side via 298, and each back-side via 298 corresponds to two back-side trenches 308. At the end of the operation at frame 158, the photoresist layer 306 can be consumed.

[0069] refer to Figure 1B and Figures 55 to 56Method 100 includes a frame 160 in which a dielectric liner 310 and a back-side metal line 312 are deposited in a back-side trench 308. The dielectric liner 310 serves as a diffusion barrier layer, preventing metal elements in the back-side metal line 312 from diffusing into the back-side ILD layer 304. In the illustrated embodiment, the dielectric liner 310 is conformally deposited to have a substantially uniform thickness along the respective surfaces of the back side of the semiconductor device 200. In various embodiments, the dielectric liner 310 may include La2O3, Al2O3, SiOCN, SiOC, SiCN, SiO2, SiC, ZnO, ZrN, Zr2Al3O9, TiO2, TaO2, ZrO2, HfO2, Si3N4, Y2O3, AlON, TaCN, ZrSi, combinations thereof, or other suitable materials. The dielectric liner 310 may be deposited using ALD, CVD, or other suitable methods. In a further embodiment, the material composition and thickness of dielectric liner 296 and dielectric liner 310 may differ. Subsequently, a breakthrough etching process (such as anisotropic dry etching) is performed to break through and remove most of the horizontal portion of dielectric liner 310. Figure 56 As shown, the dielectric liner 310 is in contact with the sidewall of the back-side ILD layer 304. In some embodiments, the back-side metal line 312 can be formed using CVD, PVD, ALD, plating, or other suitable processes. The back-side metal line 312 may include tungsten (W), ruthenium (Ru), cobalt (Co), rhodium (Rh), copper (Cu), molybdenum (Mo), nickel (Ni), titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), or other metals, and can be deposited using CVD, PVD, ALD, plating, or other suitable processes. In the depicted embodiment, the back-side metal line 312 is a portion of the back-side power rail, which electrically couples the corresponding back-side via 298 to VDD or VSS.

[0070] Now for reference Figure 57 and Figure 58 . Figure 57 and Figure 58 An alternative embodiment is shown at the end of the operation at box 160. Figure 57 and Figure 58 Many aspects shown in the text are related to Figure 55 and Figure 56 The corresponding counterparts in [the original text] are basically similar, and their descriptions are omitted for brevity. The differences are discussed below. In [the original text], ... Figure 57 and Figure 58In the illustrated embodiment, the dielectric liner 296 disposed on the sidewall of the back-side via 298 is a double-layer structure, comprising a first liner 296a and a second liner 296b disposed on the first liner 296a. The first liner 296a stops at a turning point P, and the second liner 296b extends from the top to the bottom along the sidewall of the back-side via 298. The first liner 296a and the second liner 296b differ in material composition and thickness. Before selectively removing the bottom epitaxial layer 240 ( Figure 41 A first liner 296a is deposited on the sidewall of the back-side opening 294. The first liner 296a is first deposited as a conformal dielectric layer, and then the horizontal portion of the first liner 296a is removed in a breakthrough etching process. The deposition of the first liner 296a protects the boundary of the back-side opening 294 from further extension during the subsequent etching process that selectively removes the bottom epitaxial layer 240. Next, the back-side opening 294 is extended downwards by selectively removing the bottom epitaxial layer 240. The selective etching also produces the inflection point P discussed above. Figure 43 After the back opening 294 extends, the second liner 296b is deposited on the sidewall of the back opening 294 and covers the first liner 296a.

[0071] Now for reference Figure 59 and Figure 60 . Figure 59 and Figure 60 An alternative embodiment is shown at the end of the operation at box 160. Figure 59 and Figure 60 Many aspects shown in the text are related to Figure 55 and Figure 56 The corresponding counterparts in [the original text] are basically similar, and their descriptions are omitted for brevity. The differences are discussed below. In [the original text], ... Figure 59 and Figure 60In the illustrated embodiment, the previous operation of extending the source / drain trench 228 further downward at frame 122 can be skipped, resulting in a thinner bottom epitaxial layer 240 and a greater distance from the bottom surface of the isolation structure 214. Instead of performing the first etching process to form the backside opening 294 exposing the bottom epitaxial layer 240 and performing the second etching process to selectively remove the bottom epitaxial layer 240 to extend the backside opening 294 downward, as described above, the backside opening 294 can extend through the hard mask 290, the bottom epitaxial layer 240, and the bottom isolation layer 242 in a single etching process. The sidewalls of the backside opening 294, and thus the sidewalls of the backside via 298 formed in the backside opening 294, are sloped but straight, without turning point P. Additionally, residues of the bottom isolation layer 242 and the bottom epitaxial layer 240 can remain on the sidewalls of the backside via 298 and are in contact with the dielectric liner 296. Since selective removal of the bottom epitaxial layer 240 is not required, the material composition of the bottom epitaxial layer 240 does not need to differ from that of the substrate 202 in this case. In some embodiments, both the bottom epitaxial layer 240 and the substrate 202 comprise silicon, but with different dopant concentrations, such that the substrate 202 can be lightly doped and the bottom epitaxial layer 240 can be substantially dopant-free.

[0072] Figure 61 A simplified plan view of the semiconductor device 200 at the end of operation at box 160 is provided, corresponding to Figures 55 to 56 , Figures 57 to 58 and Figures 59 to 60 The cross-sectional view shown. (Compared to...) Figure 2 In contrast, the back-side interconnect structure provides additional power and / or signal routing for the transistors formed in the device layer. Specifically, the originally separate back-side vias on opposite sides of the CMG component 270 are connected to a bridging portion to form a larger back-side via 298, which spans the CMG component 270 and the isolation structure disposed on its sidewalls. The larger back-side via 298 is also electrically coupled to two corresponding back-side metal lines 312. The larger back-side via 298 effectively reduces contact resistance and parasitic capacitance for power routing. In the plan view shown, due to the selective removal of the bottom epitaxial layer 240, the edge of the back-side via 298 is aligned with the edge of the active region 210 and is also covered by the back-side metal lines 312. Optionally, depending on the size of the bridging portion connecting the legs of the back-side opening 294, the edge of the back-side via 298 in the plan view may extend beyond the edge of the active region and even beyond the edge of the back-side metal lines 312. Furthermore, although the back-side vias 298 above the n-well and p-well may have the same dimensions in the depicted embodiments, their widths (along the X direction) and / or lengths (along the Y direction) may differ depending on design requirements.

[0073] Now for reference Figures 62 to 64 . Figure 62 An alternative embodiment is shown at the end of operation at frame 158, wherein a back-side trench 308 is formed in the back-side ILD layer 304. With Figure 54 Different, such as Figure 54 The two previously separate back-side trenches 308 shown are now joined together by defining a larger opening in the photoresist layer 306. The span of the back-side trenches 308 now covers the back-side via 298. At frame 160, as... Figure 63 As shown, a dielectric liner 310 and a back metal line 312 are then deposited in the back trench 308. Figure 64 A simplified plan view of the semiconductor device 200 at the end of operation at box 160 is provided, corresponding to Figures 62 to 63 The cross-sectional view shown. (Compared to...) Figure 2 In contrast, the back-side interconnect structure provides additional power and / or signal routing for the transistors formed in the device layer. Specifically, previously separate back-side vias on opposite sides of the CMG component 270 are connected to a bridging portion to form a larger back-side via 298 spanning the CMG component 270. The larger back-side via 298 is also electrically coupled to a corresponding back-side metal line 312 with an increased width. Together with the increased back-side metal line 312, the increased back-side via 298 effectively reduces contact resistance and parasitic capacitance for power routing. In the illustrated plan view, due to the selective removal of the bottom epitaxial layer 240, the edge of the back-side via 298 is aligned with the edge of the active region 210 and is also covered by the increased back-side metal line 312. Optionally, depending on the size of the trench portion connecting the legs of the back-side opening 294, the edge of the back-side via 298 in the plan view may extend beyond the edge of the active region and even beyond the edge of the increased back-side metal line 312. Additionally, although the back-side vias 298 above the n-well and p-well may have the same dimensions in the depicted embodiments, their widths (along the X-direction) and / or lengths (along the Y-direction) may differ depending on design requirements. Furthermore, optional components (such as...) Figures 57 to 58 The depicted double-layer dielectric liner and / or as Figures 59 to 60 The depicted back-side via 298 with inclined and straight sidewalls and the residue of the bottom epitaxial layer 240 can also be applied to, for example... Figures 62 to 64 The optional embodiments shown are as follows.

[0074] Now for reference Figures 65 to 68 . Figure 65 An alternative embodiment is shown where the operation at frame 150 is completed, wherein the bottom epitaxial layer 240 and the bottom isolation layer 242 are removed to complete the formation of the back-side opening 294. Figure 46Unlike other components, the back-side opening 294 does not extend across the CMG component 270. Therefore, each source / drain component 244 has its corresponding back-side opening 294. Two source / drain components 244 located on opposite sides of the CMG component 270 do not share the same back-side opening 294. At the end of operation of block 154, as... Figure 66 As shown, a dielectric liner 296 and a back-side via 298 are formed in the back-side opening 294. Each source / drain component 244 has its corresponding back-side via 298. Since there is no back-side via 298 spanning the CMG component 270, two source / drain components 244 disposed on opposite sides of the CMG component 270 do not share the same back-side via 298. At the end of operation of the frame 160, as Figure 67 As shown, the back-side metal line 312 is deposited in the back-side ILD layer 304. Similar to... Figure 63 The enlarged back metal line 312 in the middle, Figure 67 The back-side metal line 312 also has an enlarged width, such that each back-side metal line 312 extends across the corresponding CMG component 270 and is electrically coupled to the two back-side vias 298. Figure 68 A simplified plan view of the semiconductor device 200 at the end of operation at box 160 is provided, corresponding to Figures 65 to 67 The cross-sectional view shown. (Compared to...) Figure 2 In contrast, the back-side interconnect structure provides additional power and / or signal routing for transistors formed in the device layer. Specifically, two originally separate back-side metal lines 312 combine to form an enlarged back-side metal line 312. The enlarged back-side metal line 312 electrically couples two back-side vias 298. The back-side interconnect structure, including the two back-side vias 298 and one back-side metal line 312, still spans the CMG component 270 as a whole. In the plan view shown, due to the selective removal of the bottom epitaxial layer 240, the two edges of the back-side vias 298 are aligned with the opposite edges of the active region 210 and are also covered by the enlarged back-side metal line 312. Additionally, optional components (such as...) Figures 57 to 58 The depicted double-layer dielectric liner and / or as Figures 59 to 60 The depicted back-side via 298 with inclined and straight sidewalls and the residue of the bottom epitaxial layer 240 can also be applied to, for example... Figures 65 to 68 The optional embodiments shown are as follows.

[0075] Now for reference Figures 69 to 72 . Figure 69 An alternative embodiment is shown at the end of the operation at frame 148, wherein, during the etching process, the back-side opening 294 extends downward to expose the bottom surface of the bottom epitaxial layer 240. Figure 42Unlike other etching processes, the etching process utilizes the isolation structure protective layer 215 as an etching stop layer, ensuring that the etching process stops at the bottom surface of the isolation structure protective layer 215. Due to the different material compositions of the isolation structure 214 and the isolation structure protective layer 215, the exposure of the isolation structure protective layer 215 results in a significant change in the endpoint signal, thereby providing high-precision etching depth control. As the isolation structure 214 is removed from the back-side opening 294, the tip of the CMG component 270 can protrude from the isolation structure protective layer 215. In the depicted embodiment, the dielectric liner 272 of the CMG component 270 is exposed in the back-side opening 294. In an alternative embodiment, due to the limited etching contrast relative to the isolation structure 214, the dielectric liner 272 can be etched, and the dielectric fill layer 274 is exposed in the back-side opening 294. At the end of the operation of frame 154, as... Figure 70 As shown, a dielectric liner 296 and a back-side via 298 are formed in the back-side opening 294. The back-side via 298 spans the CMG component 270 and is connected to the isolation structure protective layer 215 and the CMG component 270. At the end of the operation of the frame 160, as... Figure 71 As shown, a back-side metal line 312 is deposited in the back-side ILD layer 304. (The last sentence appears to be incomplete and possibly contains errors.) Figure 63 Similar to the enlarged back metal line 312 in the middle, Figure 67 The back-side metal line 312 also has an enlarged width, such that each back-side metal line 312 extends across the corresponding CMG component 270 and is electrically coupled to the enlarged back-side via 298. Figure 72 A simplified plan view of the semiconductor device 200 at the end of operation at box 160 is provided, corresponding to Figures 69 to 71 The cross-sectional view shown. (Compared to...) Figure 2In contrast, the back-side interconnect structure provides additional power and / or signal routing for the transistors formed in the device layer. Specifically, previously separate back-side vias on opposite sides of the CMG component 270 are connected by a bridging portion to form a larger back-side via 298 that spans the CMG component 270 and the isolation structure protective layer extending on its sidewalls. Two previously separate back-side metal lines 312 are also combined to form an enlarged back-side metal line 312. The enlarged back-side via 298, together with the enlarged back-side metal line 312, further reduces contact resistance and parasitic capacitance for power routing. In the illustrated plan view, due to the selective removal of the bottom epitaxial layer 240, the edge of the back-side via 298 is aligned with the edge of the active region 210 and is also covered by the back-side metal line 312. Optionally, depending on the size of the groove portion connecting the leg of the back-side opening 294, the edge of the back-side via 298 in the plan view may extend beyond the edge of the active region, and even beyond the edge of the back-side metal line 312. Additionally, although the back-side vias 298 above the n-well and p-well may have the same size in the depicted embodiment, their width (along the X direction) and / or length (along the Y direction) may differ depending on design requirements. Furthermore, optional components (such as...) Figures 57 to 58 The depicted double-layer dielectric liner and / or as Figures 59 to 60 The depicted back-side via 298 with inclined and straight sidewalls and the residue of the bottom epitaxial layer 240 can also be applied to, for example... Figures 69 to 72 The optional embodiments shown are as follows.

[0076] Now for reference Figures 73 to 75 . Figures 73 to 75 As shown Figures 69 to 72 The depicted semiconductor device 200 receives further fabrication processes, including forming one or more back-side interconnect layers 314 having back-side power rails embedded in a dielectric layer, flipping the semiconductor device 200, forming one or more interconnect layers 316 on the front side, and other processes to complete the final device. It should be understood that the same operations can be applied to... Figures 55 to 61 , Figures 62 to 64 and Figures 65 to 68 The structure shown.

[0077] While not intended to be limiting, embodiments of this disclosure may offer one or more advantages. For example, in some embodiments, back-side vias and back-side metal lines are configured to collectively form a back-side interconnect structure spanning the gate-cut dielectric component. This configuration results in a relatively large back-side contact area between the source / drain components and the back-side power rails, thereby reducing routing resistance and parasitic capacitance, and widening the process window. Furthermore, embodiments of this disclosure can be readily integrated into existing semiconductor manufacturing processes.

[0078] In one exemplary aspect, this disclosure relates to a method. The method includes: forming a stack on a substrate having a plurality of channel layers interleaved by a plurality of sacrificial layers; patterning the stack and the substrate to form a first region and a second region, each of the first and second regions extending longitudinally in a first direction; the first region including a first active region and a first base region; the second region including a second active region and a second base region; forming an isolation structure between the first and second base regions, wherein the isolation structure is in contact with the sidewalls of the first and second base regions; forming a dummy gate stack spanning the first and second active regions; recessing the first and second active regions outside the dummy gate stack to form a first trench and a second trench, respectively; forming a first source / drain component in the first trench; and forming a second source / drain component in the second trench. A gate / drain component is included, wherein a portion of a first source / drain component is suspended above an isolation structure along a second direction different from a first direction, and a portion of a second source / drain component is suspended above the isolation structure along the second direction. A dummy gate stack is removed to form a gate trench, a sacrificial layer is removed to release a channel layer, a gate structure is deposited in the gate trench, the gate structure encapsulates at least one of the channel layers, and a back-side opening is formed. The back-side opening has a first via opening exposing the bottom surface of the first source / drain component and a second via opening exposing the bottom surface of the second source / drain component. A back-side via is formed in the back-side opening and electrically coupled to the first and second source / drain components. The back-side via spans a portion of the isolation structure stacked between the first and second source / drain components. In some embodiments, the method further includes forming a dielectric component that divides the gate structure into a first segment engaging a first active region and a second segment engaging a second active region. A portion of the isolation structure is disposed on a sidewall of the dielectric component, and the back-side via also spans the dielectric component. In some embodiments, a back-side via is connected to a dielectric component. In some embodiments, forming an isolation structure includes depositing a first dielectric layer and depositing a second dielectric layer over the first dielectric layer, the first and second dielectric layers comprising different material compositions. Forming a back-side opening removes the first dielectric layer and exposes the second dielectric layer. In some embodiments, the back-side via includes a first leg disposed in a first via opening, a second leg disposed in a second via opening, and a bridging portion connecting the first and second legs. In some embodiments, the bridging portion is connected to the isolation structure. In some embodiments, the method further includes depositing a back-side dielectric layer below the back-side via and forming a back-side metal line in the back-side dielectric layer. The back-side metal line is connected to the bottom surface of the back-side via and extends from a first location below a first source / drain component to a second location below a second source / drain component.In some embodiments, the method further includes depositing a back-side dielectric layer below the back-side via and forming a first back-side metal line and a second back-side metal line in the back-side dielectric layer. The first back-side metal line and the second back-side metal line are in contact with the bottom surface of the back-side via. In some embodiments, the removal of the sacrificial layer is performed before the removal of the dummy gate stack, and the method further includes depositing a dummy dielectric layer in the space between the channel layers after removing the sacrificial layer, and removing the dummy dielectric layer after removing the dummy gate stack. In some embodiments, the method further includes depositing a first bottom epitaxial layer in a first trench and a second bottom epitaxial layer in a second trench before forming the first source / drain component and the second source / drain component. Forming the back-side opening includes performing a first etching process to recess the bottom surface of the isolation structure and expose the first bottom epitaxial layer and the second bottom epitaxial layer, and performing a second etching process to remove the first bottom epitaxial layer and the second bottom epitaxial layer, wherein the first etching process and the second etching process apply different etchants.

[0079] In another exemplary aspect, this disclosure relates to a method. The method includes providing a structure having a front side and a back side, the structure including a substrate located at the back side of the structure and a first fin structure and a second fin structure located at the front side of the structure, forming an isolation structure on the sidewalls of the first fin structure and the second fin structure such that a portion of the first fin structure is recessed to form a first trench, and a portion of the second fin structure is recessed to form a second trench, epitaxially growing a first source / drain component in the first trench, and epitaxially growing a second source / drain component in the second trench, and depositing a [missing information - likely a typo, should be "deposited"] over the first source / drain component and the second source / drain component. A contact etch stop layer is formed, and a first interlayer dielectric layer is deposited above the contact etch stop layer to form a gate structure extending across the first and second fin structures. A gate dicing process is performed to form gate dicing components that define the gate structure. The gate dicing components extend laterally between the first and second source / drain components. Front-side source / drain contacts are formed in the first interlayer dielectric layer to electrically couple to the first and second source / drain components. A second interlayer dielectric layer is deposited above the first interlayer dielectric layer. The thickness of the electrical layer is greater than the thickness of the second interlayer dielectric layer. A front contact via is formed in the second interlayer dielectric layer to electrically couple to the front source / drain contact. A first back-side via opening is formed to expose the first source / drain component, and a second back-side via opening is formed to expose the second source / drain component. A first silicide layer is formed in the first back-side via opening, and the conductivity of the first silicide layer is greater than the conductivity of the first source / drain component. The first silicide layer includes a curved profile. A second silicide layer is formed in the second back-side via opening, and the conductivity of the second silicide layer is greater than that of the second source / drain contact. The drain component has a conductivity of [missing information]. A second silicide layer includes a curved profile. A first back-side conductive component is formed in a first back-side via opening, and the first back-side conductive component is in contact with the first silicide layer. A second back-side conductive component is formed in a second back-side via opening, and the second back-side conductive component is in contact with the second silicide layer. A gate dicing component is disposed between the first and second back-side conductive components. A third back-side conductive component is formed below the first and second back-side conductive components, and the third back-side conductive component connects to the first and second back-side conductive components. In some embodiments, the third back-side conductive component is in contact with an isolation structure. The method further includes depositing a back-side interlayer dielectric layer below the third back-side conductive component and forming a back-side metal line in the back-side interlayer dielectric layer, the back-side metal line being in contact with the third back-side conductive component. In some embodiments, the back-side metal line is a first back-side metal line, and the method further includes forming a second back-side metal line in the back-side interlayer dielectric layer, the second back-side conductive component being in contact with the third back-side conductive component. In some embodiments, the method further includes depositing a back-side interlayer dielectric layer beneath the first back-side conductive component and the second back-side conductive component.A third back-side conductive component is disposed in a back-side interlayer dielectric layer and is spaced apart from the isolation structure. In some embodiments, the third back-side conductive component is connected to a gate dicing component. In some embodiments, the method further includes depositing a first liner on a sidewall of the isolation structure and depositing a second liner on the first liner, the second liner extending along the sidewall of the first back-side via opening and connected to the first back-side conductive component.

[0080] In another exemplary aspect, this disclosure relates to a semiconductor structure. The semiconductor structure includes: a first source / drain component and a second source / drain component; a plurality of first nanostructures adjacent to the first source / drain component; a plurality of second nanostructures adjacent to the second source / drain component; a first gate structure enclosing at least one of the first nanostructures; a second gate structure enclosing at least one of the second nanostructures; a gate spacer extending along the sidewalls of the first gate structure and the second gate structure; the first gate structure and the second gate structure include a gate dielectric layer and a gate electrode located above the gate dielectric layer, the dielectric constant of the gate dielectric layer being greater than the dielectric constant of the gate spacer, the thickness of the gate dielectric layer being less than the thickness of the gate spacer, and the gate electrode comprising a titanium-containing material; a gate end dielectric component connected to the end of the first gate structure and the end of the second gate structure; an isolation structure disposed on the sidewall of the gate end dielectric component; and a back-side conductive component spanning the gate end dielectric component, the back-side conductive component including a first leg electrically coupled to the first source / drain component, a second leg electrically coupled to the second source / drain component, and a bridging portion connecting the first leg and the second leg. In some embodiments, the semiconductor structure further includes a back-side metal line disposed below and connected to the back-side conductive member. The width of the back-side metal line is greater than the width of the back-side conductive member. In some embodiments, the bridging portion is connected to an isolation structure. In some embodiments, the bridging portion is connected to a gate end dielectric member.

[0081] The foregoing outlines features of several embodiments to enable those skilled in the art to better understand aspects of this disclosure. Those skilled in the art should understand that they can readily use this disclosure as a basis to design or modify other processes and structures for implementing the same purposes and / or achieving the same advantages as the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and alterations can be made to them herein without departing from the spirit and scope of this disclosure.

Claims

1. A method for forming a semiconductor structure, comprising: A stack is formed on a substrate, the stack having multiple channel layers interleaved with multiple sacrificial layers; The stack and the substrate are patterned to form a first region and a second region, each of the first region and the second region extending longitudinally in a first direction, the first region including a first active region and a first substrate region, and the second region including a second active region and a second substrate region; An isolation structure is formed between the first base region and the second base region, wherein the isolation structure is in contact with the sidewalls of the first base region and the sidewalls of the second base region; A pseudo-gate stack is formed spanning the first active region and the second active region; The first active region and the second active region outside the dummy gate stack are recessed to form a first trench and a second trench, respectively. A first source / drain component is formed in the first trench, and a second source / drain component is formed in the second trench. A portion of the first source / drain component is suspended above the isolation structure along a second direction different from the first direction, and a portion of the second source / drain component is suspended above the isolation structure along the second direction. Remove the dummy gate stack to form a gate trench; Remove the sacrificial layer to release the channel layer; A gate structure is deposited in the gate trench, the gate structure encapsulating at least one of the channel layers; A back-side opening is formed, the back-side opening having a first through-hole opening exposing the bottom surface of the first source / drain component and a second through-hole opening exposing the bottom surface of the second source / drain component; and A back-side via is formed in the back-side opening, and the back-side via is electrically coupled to the first source / drain component and the second source / drain component, wherein the back-side via spans a portion of the isolation structure stacked between the first source / drain component and the second source / drain component.

2. The method according to claim 1, further comprising: A dielectric component is formed, which divides the gate structure into a first segment that joins the first active region and a second segment that joins the second active region. The isolation structure is disposed on the sidewall of the dielectric component, and the back-side through-hole also spans the dielectric component.

3. The method according to claim 2, wherein, The back-side through-hole is connected to the dielectric component.

4. The method according to claim 1, wherein, The formation of the isolation structure includes depositing a first dielectric layer and depositing a second dielectric layer on top of the first dielectric layer, wherein the first dielectric layer and the second dielectric layer comprise different material compositions. The process of forming a back opening removes the first dielectric layer and exposes the second dielectric layer.

5. The method according to claim 1, wherein, The back through hole includes a first leg disposed in the opening of the first through hole, a second leg disposed in the opening of the second through hole, and a bridging portion connecting the first leg and the second leg.

6. The method according to claim 5, wherein, The bridging portion is connected to the isolation structure.

7. The method according to claim 1, further comprising: A back-side dielectric layer is deposited below the back-side via; as well as A back-side metal line is formed in the back-side dielectric layer, wherein the back-side metal line is connected to the bottom surface of the back-side via, and the back-side metal line extends from a first position below the first source / drain component to a second position below the second source / drain component.

8. The method according to claim 1, further comprising: A back-side dielectric layer is deposited below the back-side via; as well as A first back-side metal line and a second back-side metal line are formed in the back-side dielectric layer, wherein the first back-side metal line and the second back-side metal line are connected to the bottom surface of the back-side via.

9. A method for forming a semiconductor structure, comprising: A structure having a front side and a back side is provided, the structure including a substrate located at the back side of the structure and a first fin structure and a second fin structure located at the front side of the structure; An isolation structure is formed on the sidewalls of the first fin-shaped structure and the second fin-shaped structure; The first fin-shaped structure is partially recessed to form a first groove, and the second fin-shaped structure is partially recessed to form a second groove; A first source / drain component is epitaxially grown in the first trench, and a second source / drain component is epitaxially grown in the second trench; A contact etch stop layer is deposited over the first source / drain component and the second source / drain component; A first interlayer dielectric layer is deposited above the contact etch stop layer; A gate structure is formed that extends across the first fin structure and the second fin structure; A gate dicing process is performed to form a gate dicing portion that divides the gate structure, the gate dicing portion extending laterally between the first source / drain portion and the second source / drain portion; A front-side source / drain contact is formed in the first interlayer dielectric layer to electrically couple to the first source / drain component and the second source / drain component; A second interlayer dielectric layer is deposited above the first interlayer dielectric layer, wherein the thickness of the first interlayer dielectric layer is greater than the thickness of the second interlayer dielectric layer; A front-side contact via is formed in the second interlayer dielectric layer to electrically couple to the front-side source / drain contacts; A first back-side via opening is formed to expose the first source / drain component; A second back-side via opening is formed to expose the second source / drain component; A first silicide layer is formed in the opening of the first back-side via, the conductivity of the first silicide layer is greater than the conductivity of the first source / drain component, and the first silicide layer includes a curved profile. A second silicide layer is formed in the second back-side via opening, the conductivity of the second silicide layer being greater than the conductivity of the second source / drain component, and the second silicide layer including a curved profile; A first back-side conductive component is formed in the opening of the first back-side through-hole, and the first back-side conductive component is in contact with the first silicide layer; A second back-side conductive component is formed in the second back-side via opening, the second back-side conductive component being in contact with the second silicide layer, and the gate dicing component being disposed between the first back-side conductive component and the second back-side conductive component; and A third back-side conductive component is formed below the first back-side conductive component and the second back-side conductive component, and the third back-side conductive component connects the first back-side conductive component and the second back-side conductive component.

10. A semiconductor structure, comprising: First source / drain component and second source / drain component; Multiple first nanostructures are adjacent to the first source / drain components; Multiple second nanostructures are adjacent to the second source / drain components; A first gate structure encapsulates at least one of the first nanostructures; A second gate structure encapsulates at least one of the second nanostructures; A gate spacer extends along the sidewalls of the first gate structure and the second gate structure, the first gate structure and the second gate structure including a gate dielectric layer and a gate electrode located above the gate dielectric layer, the dielectric constant of the gate dielectric layer being greater than the dielectric constant of the gate spacer, the thickness of the gate dielectric layer being less than the thickness of the gate spacer, and the gate electrode comprising a titanium-containing material; A gate end dielectric component is connected to the end of the first gate structure and the end of the second gate structure; An isolation structure is disposed on the sidewall of the gate end dielectric component; as well as A back-side conductive component spanning the gate end dielectric component, the back-side conductive component including a first leg electrically coupled to the first source / drain component, a second leg electrically coupled to the second source / drain component, and a bridging portion connecting the first leg and the second leg.

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