Semiconductor device and method of forming the same

Abstract

A semiconductor device and a method of forming the same. The method includes depositing a multilayer stack on a semiconductor substrate, the multilayer stack including a plurality of sacrificial layers alternating with a plurality of channel layers; etching the multilayer stack and the semiconductor substrate to form a fin; forming a dummy gate on a top surface and sidewalls of the fin; forming a first recess in the fin adjacent to the dummy gate; etching end portions of the plurality of sacrificial layers exposed in the first recess to form a sidewall recess; forming an inner spacer in a respective one of the sidewall recesses, wherein each inner spacer includes alternating first spacer layers and second spacer layers, wherein the first spacer layers include a first material having a lower dielectric constant than a second material of the second spacer layers; and forming an epitaxial source / drain region in the first recess.

Description

Technical Field

[0001] This disclosure relates to a semiconductor device and a method for forming the same. Background Technology

[0002] Semiconductor devices are used in a variety of electronic applications, such as personal computers, cell phones, digital cameras, and other electronic devices. Semiconductor devices are generally manufactured by depositing insulating or dielectric layers, conductive layers, and semiconductor layers of material sequentially on a semiconductor substrate, and then using photolithography to pattern the various material layers to form circuit components and elements on them.

[0003] The semiconductor industry continues to improve the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by constantly reducing the minimum feature size, which allows more components to be integrated into a given area. However, as the minimum feature size decreases, additional problems arise that need to be addressed. Summary of the Invention

[0004] In some embodiments, a method of forming a semiconductor device includes the following operations: Depositing a multilayer stack on a semiconductor substrate, the multilayer stack including a plurality of sacrificial layers alternating with a plurality of channel layers; Etching the multilayer stack and the semiconductor substrate to form fins; Forming dummy gates on the top surface of the fins and a plurality of sidewalls; Forming a first recess in the fin adjacent to the dummy gates; Etching a plurality of ends of the sacrificial layers exposed in the first recesses to form a plurality of sidewall recesses; Forming a plurality of internal spacers in corresponding ones of the sidewall recesses, wherein each of the internal spacers includes a plurality of alternating first spacer layers and a plurality of second spacer layers, wherein the first spacer layers include a first material having a lower dielectric constant than a second material of the second spacer layers; Forming epitaxial source / drain regions in the first recesses, wherein the epitaxial source / drain regions are isolated from the sacrificial layers by the internal spacers.

[0005] In some embodiments, a method of forming a semiconductor device includes the following operations: Depositing a first sacrificial layer over a semiconductor substrate. Depositing a first channel layer over the first sacrificial layer. Etching a first groove extending through the first sacrificial layer, the first channel layer, and a top portion of the semiconductor substrate. Etching multiple ends of the first sacrificial layer exposed in the first groove to form multiple sidewall grooves, wherein multiple oxide regions are formed on multiple surfaces of the first channel layer in the sidewall grooves when etching the ends of the first sacrificial layer. Depositing a first spacer layer on multiple sidewalls and a bottom surface in the first groove. Depositing a second spacer layer over the first spacer layer in the first groove. Depositing a third spacer layer over the second spacer layer in the first groove, wherein the first and third spacer layers comprise a first material and the second spacer layer comprises a second material, and wherein the carbon concentration of the first material is higher than the carbon concentration of the second material. Performing an etching process to remove multiple portions of the first, second, and third spacer layers, wherein after performing the etching process, multiple remaining portions of the first, second, and third spacer layers form multiple internal spacers disposed in corresponding portions of the sidewall grooves. An epitaxial source / drain region is formed in the first groove, wherein the epitaxial source / drain region is isolated from the first sacrificial layer by an internal spacer.

[0006] In some embodiments, a semiconductor device includes a gate structure, a plurality of source / drain regions, a first channel layer, and a plurality of internal spacers. The gate structure is located above a semiconductor substrate. The source / drain regions are located above the semiconductor substrate and on a plurality of opposite sides of the gate structure. The first channel layer is disposed between the source / drain regions and above the semiconductor substrate. The internal spacers are located between a plurality of first ends of the first channel layer and the semiconductor substrate, wherein the gate structure is disposed between the internal spacers, wherein each of the internal spacers includes alternating plurality of first spacer layers and plurality of second spacer layers, wherein the first spacer layer comprises a first material, wherein the second spacer layer comprises a second material, wherein the first material has a lower dielectric constant than the second material, and wherein the carbon concentration of the second material is higher than the carbon concentration of the first material. Attached Figure Description

[0007] When read in conjunction with the accompanying figures, the following detailed description is the best way to understand the nature of this disclosure. It should be noted that, according to standard industrial practice, the features are not drawn to scale. In fact, for clarity of explanation, the dimensions of the features may be arbitrarily increased or decreased.

[0008] Figure 1 Examples of nanostructure field-effect transistors (nano-FETs) in three-dimensional view according to some embodiments are illustrated;

[0009] Figure 2 , Figure 3 , Figure 4 , Figure 5 , Figure 6A , Figure 6B , Figure 6C , Figure 7A , Figure 7B , Figure 7C , Figure 8A , Figure 8B , Figure 8C , Figure 9A , Figure 9B , Figure 10A , Figure 10B , Figure 11A , Figure 11B , Figure 11C , Figure 12A , Figure 12B , Figure 12C , Figure 13A , Figure 13B , Figure 13C , Figure 14A , Figure 14B , Figure 14C , Figure 15A , Figure 15B , Figure 15C , Figure 16A , Figure 16B , Figure 16C , Figure 16D , Figure 17A , Figure 17B , Figure 17C , Figure 18A , Figure 18B , Figure 18C , Figure 19A , Figure 19B , Figure 19C , Figure 20A , Figure 20B , Figure 20C , Figure 21A , Figure 21B , Figure 21C , Figure 22A , Figure 22B , Figure 22C , Figure 23A , Figure 23B , Figure 23C , Figure 24A , Figure 24B and Figure 24C This is a cross-sectional view of an intermediate stage in the fabrication of a nano-FET according to some embodiments.

[0010] [Symbol Explanation]

[0011] 10: Semiconductor devices

[0012] 20: Separator line

[0013] 50: Base plate, underlying base plate

[0014] 50N: n-type region, region

[0015] 50P: p-type area, area

[0016] 51: First semiconductor layer

[0017] 51A: First semiconductor layer

[0018] 51B: First semiconductor layer

[0019] 51C: First semiconductor layer

[0020] 52: First Nanostructure

[0021] 52A: First Nanostructure

[0022] 52B: First Nanostructure

[0023] 52C: First Nanostructure

[0024] 53: Second semiconductor layer

[0025] 53A: Second semiconductor layer

[0026] 53B: Second semiconductor layer

[0027] 53C: Second semiconductor layer

[0028] 54: Second Nanostructure

[0029] 54A: Second nanostructure, channel layer

[0030] 54B: Second nanostructure, channel layer

[0031] 54C: Second nanostructure, channel layer

[0032] 55: Nanostructures

[0033] 60: Passage Area

[0034] 64: Multi-layer stacking

[0035] 66: Fins

[0036] 68: Shallow trench isolation (STI) area, STI area, Shallow trench isolation (STI) area

[0037] 70: Virtual dielectric layer

[0038] 71: Virtual gate dielectric layer

[0039] 72: Virtual Gate Layer

[0040] 74: Masking layer

[0041] 76: Virtual Gate

[0042] 78: Mask

[0043] 81: First spacer

[0044] 82: Second spacer

[0045] 86: First Groove

[0046] 87: Region

[0047] 88: Sidewall groove

[0048] 89: Second spacer layer

[0049] 90: Internal spacers

[0050] 91: First spacer layer

[0051] 92: Epitaxial source / drain region

[0052] 92A: First semiconductor material layer

[0053] 92B: Second semiconductor material layer

[0054] 92C: Third semiconductor material layer

[0055] 93: Oxide region

[0056] 94: Contact etch stop layer (CESL)

[0057] 95: The treated area

[0058] 96: First interlayer dielectric (ILD), first ILD

[0059] 98: Groove

[0060] 102: Gate electrode

[0061] 104: Gate mask

[0062] 106: Second ILD

[0063] 108: Opening

[0064] 109: Opening

[0065] 110: Silicide region

[0066] 112: Source / Drain Contact

[0067] 114: Gate contact

[0068] 120: Gate dielectric layer

[0069] 130: Processing technology

[0070] 132: First processing technology

[0071] 134: Second processing technology

[0072] 136: First processing technology

[0073] 138: Second processing technology

[0074] 140: First processing technology

[0075] 142: Second Processing Technology

[0076] 144: Third Processing Technology

[0077] 146: Etching process

[0078] AA': Cross-section

[0079] BB': Cross-section

[0080] CC': Cross-section

[0081] T1: Thickness

[0082] T2: Thickness Detailed Implementation

[0083] The following disclosure provides numerous different embodiments or examples to implement various features of this disclosure. Specific examples of components and arrangements are described below to simplify the disclosure. These are merely examples and are not intended to be limiting. For instance, in the following description, the formation of a first feature above or on a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features such that the first and second features are not in direct contact. Furthermore, element symbols and / or letters may be repeated in various instances of this disclosure. This repetition is for simplicity and clarity and does not in itself define the relationship between the various embodiments and / or configurations discussed.

[0084] Furthermore, for ease of description, this document may use spatially relative terms (such as "below," "below," "down," "above," "up," and the like) to describe the relationship of one element or feature to another element or feature depicted in the figures. In addition to the orientations depicted in the figures, the spatially relative terms are intended to cover different orientations of the device in use or operation. The device may be oriented in other ways (rotated 90 degrees or otherwise), and the spatially relative descriptive terms used herein shall be interpreted accordingly.

[0085] Various embodiments provide semiconductor devices with improved performance and methods for forming the same. The semiconductor device may be a nano-FET (also known as a nanosheet field-effect transistor, nanowire field-effect transistor, or gate-all-around field-effect transistor, GAAFET). These embodiments include methods for forming internal spacers that act as isolation features between subsequently formed source / drain regions and subsequently formed gate structures. In one embodiment, the internal spacer may comprise a multilayer structure having alternating first and second spacer layers, wherein the first spacer layer comprises a first material (e.g., a low-dielectric-constant material) with a dielectric constant lower than that of a second material in the second spacer layer. In one embodiment, the second material of the second spacer layer may include silicon, carbon, oxygen, and / or nitrogen, and may include SiCN, SiN, SiCON, SiOC, SiON, or the like. The second spacer layer may have a higher carbon concentration and / or nitrogen concentration than the first spacer layer. In one embodiment, the first spacer layer may have a higher concentration of oxygen, fluorine, and / or boron compared to the second spacer layer, wherein the concentration of fluorine and / or boron in the first spacer layer may be higher than the concentration of fluorine and / or boron in the second spacer layer by a range from 0.1 atomic percent to 5 atomic percent.

[0086] Advantageous features of one or more embodiments disclosed herein may include forming internal spacers having alternating first and second spacer layers, wherein a first material of the first spacer layer has a lower dielectric constant than a second material of the second spacer layer. The second spacer layer has a higher carbon and / or nitrogen concentration than the first spacer layer, which enhances the etch resistance of the internal spacers during subsequent etch steps to form the gate structure. The first spacer layer has a higher oxygen, fluorine, and / or boron concentration, which allows for reduced parasitic capacitance between the gate structure and the source / drain regions. Therefore, improved control over the internal spacer profile can be achieved, allowing for reduced internal spacer loss and reduced formation of internal spacer dish profiles. Furthermore, the reduced parasitic capacitance between the gate structure and the source / drain regions allows for faster switching speeds and lower power consumption during device operation. This results in better device performance and improved reliability.

[0087] Figure 1 Examples of nano-FETs (e.g., nanowire field-effect transistors, nanosheet field-effect transistors, or the like) in a three-dimensional view according to some embodiments are illustrated. The nano-FET includes a nanostructure 55 (e.g., nanosheet, nanowire, or the like) above fins (or protrusions / substrate portions) 66 on a substrate 50 (e.g., a semiconductor substrate), wherein the nanostructure 55 acts as a channel region for the nano-FET. The nanostructure 55 may include p-type nanostructures, n-type nanostructures, or combinations thereof. Shallow trench isolation (STI) regions 68 are disposed between adjacent fins 66, which may protrude above and from adjacent STI regions 68. Although the STI regions 68 are described / illustrated as separate from the substrate 50, as used herein, the term "substrate" may refer to a single semiconductor substrate or a combination of a semiconductor substrate and an STI region. Additionally, although the bottom portion of fin 66 is depicted as a single continuous material with substrate 50, the bottom portion of fin 66 and / or substrate 50 may comprise a single material or a plurality of materials. In this context, fin 66 represents a portion extending between adjacent STI regions 68.

[0088] The gate dielectric layer 120 is located above the top surface of the fin 66 and extends along the top, sidewalls, and bottom surface of the nanostructure 55. The gate electrode 102 is located above the gate dielectric layer 120. Epitaxial source / drain regions 92 are disposed on the fin 66 on opposite sides of the gate dielectric layer 120 and the gate electrode 102. A first spacer 81 may be disposed on the sidewall of the gate dielectric layer.

[0089] Figure 1Further illustrations show reference cross sections used in later figures. Cross section A-A' is along the longitudinal axis of the gate electrode 102 and in a direction, for example, perpendicular to the current flow direction between the epitaxial source / drain regions 92 of the nano-FET. Cross section B-B' is parallel to cross section A-A' and extends through the epitaxial source / drain regions 92 of the plurality of nano-FETs. Cross section C-C' is perpendicular to cross section A-A' and parallel to the longitudinal axis of the nano-FET fin 66, and in a direction, for example, between the current flow directions between the epitaxial source / drain regions 92 of the nano-FET. For clarity, these reference cross sections are represented in subsequent figures. Some embodiments discussed herein are discussed in the context of nano-FETs formed using a post-gate process. In other embodiments, a pre-gate process may be used.

[0090] Figure 2 Until Figure 24C This is a cross-sectional view of an intermediate stage in the manufacture of a semiconductor device 10 including a nano-FET, according to some embodiments. Figure 2 Until Figure 5 , Figure 6A , Figure 7A , Figure 8A , Figure 16A , Figure 17A , Figure 18A , Figure 19A , Figure 20A , Figure 21A , Figure 22A , Figure 23A and Figure 24A draw Figure 1 The reference cross section A-A' is shown in the figure. Figure 6B , Figure 7B , Figure 8B , Figure 16B , Figure 16C , Figure 17B , Figure 18B , Figure 19B , Figure 20B , Figure 21B , Figure 22B , Figure 23B and Figure 24B draw Figure 1 The reference cross section B-B' is shown in the figure. Figure 6C , Figure 7C , Figure 8C , Figure 9A , Figure 9B , Figure 10A , Figure 10B , Figure 11A , Figure 11B , Figure 11C , Figure 12A , Figure 12B , Figure 12C , Figure 13A , Figure 13B , Figure 13C , Figure 14A , Figure 14B , Figure 14C , Figure 15A , Figure 15B , Figure 15C , Figure 16D , Figure 17C , Figure 18C , Figure 19C , Figure 20C , Figure 21C , Figure 22C , Figure 23C and Figure 24C draw Figure 1 The reference cross section C-C' is shown in the figure.

[0091] exist Figure 2 In this embodiment, a substrate 50 is provided. The substrate 50 may be a semiconductor substrate, such as a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, or the like, which may be doped (e.g., by p-type or n-type dopant) or undoped. The substrate 50 may be a wafer, such as a silicon wafer. Generally, an SOI substrate is a layer of semiconductor material formed on an insulating layer. The insulating layer may be, for example, a buried oxide (BOX) layer, a silicon oxide layer, or the like. The insulating layer is provided on a substrate (generally a silicon or glass substrate). Other substrates, such as multilayer or gradient substrates, may also be used. In some embodiments, the semiconductor material of the substrate 50 may include silicon; germanium; compound semiconductors, including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductors, including silicon germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide, and / or gallium indium arsenide phosphide; or combinations thereof.

[0092] The substrate 50 has an n-type region 50N and a p-type region 50P. The n-type region 50N can be used to form an n-type device, such as an NMOS transistor, for example, an n-type nano-FET, and the p-type region 50P can be used to form a p-type device, such as a PMOS transistor, for example, a p-type nano-FET. The n-type region 50N may be physically separated from the p-type region 50P (as shown by the separator line 20), and any number of device features (e.g., other active devices, doped regions, isolation structures, etc.) may be disposed between the n-type region 50N and the p-type region 50P. Although illustrated as one n-type region 50N and one p-type region 50P, any number of n-type regions 50N and p-type regions 50P may be provided.

[0093] Further in Figure 2In this configuration, a multilayer stack 64 is formed over the substrate 50. The multilayer stack 64 includes alternating layers of first semiconductor layers 51A to 51C (collectively referred to as first semiconductor layers 51) and second semiconductor layers 53A to 53C (collectively referred to as second semiconductor layers 53). For illustrative purposes and as discussed in more detail below, the first semiconductor layers 51A, 51B, and 51C (which may also be referred to as sacrificial layers) are removed, and the second semiconductor layers 53A, 53B, and 53C (which may also be referred to as channel layers) are patterned to form channel regions for nano-FETs in the n-type region 50N and the p-type region 50P. However, in some embodiments, the first semiconductor layer 51A, the first semiconductor layer 51B, and the first semiconductor layer 51C may be removed and the second semiconductor layer 53A, the second semiconductor layer 53B, and the second semiconductor layer 53C may be patterned to form a channel region of a nano-FET in the n-type region 50N, and the second semiconductor layer 53A, the second semiconductor layer 53B, and the second semiconductor layer 53C may be removed and the first semiconductor layer 51A, the first semiconductor layer 51B, and the first semiconductor layer 51C may be patterned to form a channel region of a nano-FET in the p-type region 50P. In some embodiments, the second semiconductor layers 53A, 53B, and 53C may be removed, and the first semiconductor layers 51A, 51B, and 51C may be patterned to form a channel region for a nano-FET in the n-type region 50N. Alternatively, the first semiconductor layers 51A, 51B, and 51C may be removed, and the second semiconductor layers 53A, 53B, and 53C may be patterned to form a channel region for a nano-FET in the p-type region 50P. In some embodiments, the second semiconductor layers 53A, 53B, and 53C may be removed, and the first semiconductor layers 51A, 51B, and 51C may be patterned to form a channel region for a nano-FET in both the n-type region 50N and the p-type region 50P.

[0094] For illustrative purposes, the multilayer stack 64 is illustrated as comprising three first semiconductor layers 51 and three second semiconductor layers 53. In some embodiments, the multilayer stack 64 may include two or more first semiconductor layers 51 and two or more second semiconductor layers 53. Each of the layers in the multilayer stack 64 may be epitaxially grown using processes such as chemical vapor deposition (CVD), atomic layer deposition (ALD), vapor phase epitaxy (VPE), molecular beam epitaxy (MBE), or similar methods. In various embodiments, the first semiconductor layer 51 may be formed of a first semiconductor material suitable for a p-type nano-FET (such as silicon germanium, or the like), and the second semiconductor layer 53 may be formed of a second semiconductor material suitable for an n-type nano-FET (such as silicon, silicon carbon, or the like). For illustrative purposes, the multilayer stack 64 is illustrated as having a bottom semiconductor layer suitable for a p-type nano-FET. In some embodiments, the multilayer stack 64 may be configured such that the bottommost layer is a semiconductor layer suitable for an n-type nano-FET.

[0095] The first semiconductor material and the second semiconductor material may be materials with high etch selectivity towards each other. Therefore, the first semiconductor layer 51 of the first semiconductor material can be removed without significantly removing the second semiconductor layer 53 of the second semiconductor material, thereby allowing the second semiconductor layers 53A, 53B, and 53C to be patterned to form the channel region of the nano-FET. Similarly, in embodiments where the second semiconductor layer 53 is removed and the first semiconductor layers 51A, 51B, and 51C are patterned to form the channel region, the second semiconductor layer 53 of the second semiconductor material can be removed without significantly removing the first semiconductor layer 51 of the first semiconductor material, thereby allowing the first semiconductor layers 51A, 51B, and 51C to be patterned to form the channel region of the nano-FET.

[0096] See now Figure 3According to some embodiments, fins 66 are formed in substrate 50 and nanostructures 55 are formed in multilayer stack 64. In some embodiments, nanostructures 55 and fins 66 may be formed in multilayer stack 64 and substrate 50 respectively by etching trenches in multilayer stack 64 and substrate 50. Etching may be any acceptable etching process, such as reactive ion etching (RIE), neutral beam etching (NBE), similar, or combinations thereof. Etching may be anisotropic. Forming nanostructures 55 by etching multilayer stack 64 may further define first nanostructures 52A to 52C (collectively referred to as first nanostructures 52) from first semiconductor layer 51 and second nanostructures 54A to 54C (collectively referred to as second nanostructures 54) from second semiconductor layer 53. First nanostructures 52 and second nanostructures 54 may be collectively referred to as nanostructure 55.

[0097] The fins 66 and nanostructures 55 can be patterned using any suitable method. For example, the fins 66 and nanostructures 55 can be patterned using one or more photolithography processes, including dual-patterning or multi-patterning processes. Generally, dual-patterning or multi-patterning processes combine photolithography and self-alignment processes, allowing the creation of patterns with, for example, smaller pitches than that achievable using a single direct photolithography process in other ways. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a photolithography process. Spacers are formed next to the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers can then be used to pattern the fins 66.

[0098] For illustrative purposes, Figure 3 The fins 66 in the n-type region 50N and the p-type region 50P are depicted as having substantially equal widths. In some embodiments, the width of the fins 66 in the n-type region 50N may be greater than or thinner than the width of the fins 66 in the p-type region 50P. Furthermore, while each of the fins 66 and nanostructures 55 is depicted as having a uniform width throughout, in other embodiments, the fins 66 and / or nanostructures 55 may have tapered sidewalls such that the width of each of the fins 66 and / or nanostructures 55 increases continuously in the direction toward the substrate 50. In such embodiments, each of the nanostructures 55 may have a different width and be trapezoidal in shape.

[0099] exist Figure 4In this embodiment, a shallow trench isolation (STI) region 68 is formed adjacent to the fin 66. The STI region 68 can be formed by depositing an insulating material over the substrate 50, the fin 66, and the nanostructure 55, and between adjacent fins 66. The insulating material may be an oxide (such as silicon oxide), a nitride, the like, or a combination thereof, and may be formed by high-density plasma CVD (HDP-CVD), flowable CVD (FCVD), the like, or a combination thereof. Other insulating materials formed by any acceptable process may be used. In the illustrated embodiment, the insulating material is silicon oxide formed by an FCVD process. Once the insulating material is formed, an annealing process can be performed. In one embodiment, the insulating material is formed such that an excess of insulating material covers the nanostructure 55. Although the insulating material is illustrated as a single layer, some embodiments may utilize multiple layers. For example, in some embodiments, a pad (not shown separately) may first be formed along the surfaces of the substrate 50, the fin 66, and the nanostructure 55. Subsequently, filler materials (such as those discussed above) can be formed on top of the padding.

[0100] Next, a removal process is applied to the insulating material to remove excess insulating material above the nanostructure 55. In some embodiments, planarization processes, such as chemical mechanical polishing (CMP), etch-back processes, combinations thereof, or similar methods, may be used. The planarization process exposes the nanostructure 55 such that, after the planarization process is completed, the top surfaces of the nanostructure 55 and the insulating material are flush.

[0101] The insulating material is then recessed to form the STI region 68. The insulating material is recessed such that the upper portions of the fins 66 in the n-type region 50N and p-type region 50P protrude between adjacent STI regions 68. Additionally, the top surface of the STI region 68 may have a flat surface, a convex surface, a concave surface (such as a dish shape), or a combination thereof, as illustrated. The top surface of the STI region 68 may be formed as flat, raised, and / or recessed by appropriate etching. The STI region 68 may be recessed using acceptable etching processes, such as processes that are selective to the material of the insulating material (e.g., etching the material of the insulating material at a faster rate compared to the materials of the fins 66 and nanostructures 55). For example, oxide removal may be used, employing, for example, diluted hydrofluoric (dHF) acid.

[0102] The above text is about Figure 2 Until Figure 4The described process is merely one example of how the fins 66 and nanostructures 55 can be formed. In some embodiments, the fins 66 and / or nanostructures 55 can be formed using masking and epitaxial growth processes. For example, a dielectric layer can be formed above the top surface of the substrate 50, and trenches can be etched through the dielectric layer to expose the underlying substrate 50. Epitaxial structures can be epitaxially grown in the trenches, and the dielectric layer can be recessed such that the epitaxial structures protrude from the dielectric layer to form the fins 66 and / or nanostructures 55. The epitaxial structures may comprise alternating semiconductor materials as discussed above, such as a first semiconductor material and a second semiconductor material. In some embodiments where the epitaxial structure is epitaxially grown, the epitaxially grown material may be in-situ doped during growth, which may eliminate the need for prior and / or subsequent implantation, although in-situ and implantation doping can be used together.

[0103] Additionally, for illustrative purposes only, the first semiconductor layer 51 (and the resulting first nanostructure 52) and the second semiconductor layer 53 (and the resulting second nanostructure 54) are illustrated and discussed herein as containing the same material in the p-type region 50P and the n-type region 50N. Therefore, in some embodiments, one or both of the first semiconductor layer 51 and the second semiconductor layer 53 may be different materials or formed in different orders in the p-type region 50P and the n-type region 50N.

[0104] Further in Figure 4 In this embodiment, suitable wells (not shown separately) may be formed in fin 66, nanostructure 55, and / or STI region 68. In embodiments with different well types, different placement steps for n-type region 50N and p-type region 50P may be implemented using photoresist or other masks (not shown separately). For example, photoresist may be formed over fin 66 and STI region 68 in n-type region 50N and p-type region 50P. The photoresist is patterned to expose p-type region 50P. The photoresist may be formed using spin coating techniques and may be patterned using acceptable photolithography techniques. Once the photoresist is patterned, n-type impurity placement is performed in p-type region 50P, and the photoresist may act as a mask to substantially prevent n-type impurities from being placed into n-type region 50N. n-type impurities (also referred to as dopants) may be placed in the region from about 10 13 atoms / cm 3 To about 10 14 atoms / cm 3 The concentration of phosphorus, arsenic, antimony, or similar substances is within a certain range. After application, the photoresist is removed via an acceptable ashing process.

[0105] After or before the implantation of the p-type region 50P, a photoresist or other mask (not shown separately) is formed over the fins 66, nanostructures 55, and STI regions 68 in both the p-type region 50P and the n-type region 50N. The photoresist is patterned to expose the n-type region 50N. The photoresist can be formed using spin coating techniques and can be patterned using acceptable photolithography techniques. Once the photoresist is patterned, p-type impurity implantation can be performed in the n-type region 50N, and the photoresist acts as a mask to substantially prevent the implantation of p-type impurities into the p-type region 50P. P-type impurities (also known as dopants) can be implanted in the region up to approximately 10 13 atoms / cm 3 To about 10 14 atoms / cm 3 The concentrations of boron, boron fluoride, indium, or the like are within a certain range. After implantation, the photoresist can be removed, such as through an acceptable ashing process.

[0106] After the implantation of the n-type region 50N and the p-type region 50P, annealing can be performed to repair implantation damage and activate the implanted p-type and / or n-type impurities. In some embodiments, the growth material of the epitaxial fins can be in-situ doped during growth, which may eliminate the need for implantation, although in-situ and implantation doping can be used together.

[0107] exist Figure 5In this configuration, a dummy dielectric layer 70 is formed on the fin 66 and / or nanostructure 55. The dummy dielectric layer 70 may be, for example, silicon oxide, silicon nitride, combinations thereof, or similar materials, and may be deposited or thermally grown according to acceptable techniques. A dummy gate layer 72 is formed over the dummy dielectric layer 70, and a masking layer 74 is formed over the dummy gate layer 72. The dummy gate layer 72 may be deposited over the dummy dielectric layer 70 and subsequently planarized, for example, by CMP. The masking layer 74 may be deposited over the dummy gate layer 72. The dummy gate layer 72 may be a conductive or non-conductive material and may be selected from the group including: amorphous silicon, polycrystalline silicon (polysilicon), polycrystalline silicon germanium (polySiGe), metal nitrides, metal silicides, metal oxides, and metals. The dummy gate layer 72 may be deposited by physical vapor deposition (PVD), CVD, sputtering deposition, or other techniques used for depositing the selected material. The dummy gate layer 72 may be made of other materials that have high etch selectivity compared to the etching of the isolation region. The mask layer 74 may include, for example, silicon nitride, silicon oxynitride, or the like. In this example, a single dummy gate layer 72 and a single mask layer 74 are formed across the n-type region 50N and the p-type region 50P. It should be noted that, for illustrative purposes only, the dummy dielectric layer 70 is shown as covering only the fin 66 and the nanostructure 55. In some embodiments, the dummy dielectric layer 70 may be deposited such that the dummy dielectric layer 70 covers the STI region 68, such that the dummy dielectric layer 70 extends between the dummy gate layer 72 and the STI region 68.

[0108] Figure 6A Until Figure 24C Various additional steps in the manufacture of the embodiment device are illustrated. Figure 6A Until Figure 24C Plot the characteristics of either the n-type region 50N or the p-type region 50P. Figure 6A Until Figure 6C In the middle, mask layer 74 (see Figure 5 The mask 78 can be patterned using acceptable photolithography and etching techniques. The pattern of the mask 78 can then be transferred to the dummy gate layer 72 and the dummy dielectric layer 70 to form the dummy gate 76 and the dummy gate dielectric layer 71, respectively. The dummy gate 76 covers the corresponding channel region 60 of the fin 66 and / or nanostructure 55. The pattern of the mask 78 can be used to separate each of the dummy gates 76 from the adjacent dummy gate 76 entities. The dummy gate 76 may also have a longitudinal orientation substantially perpendicular to the longitudinal direction of the corresponding fin 66.

[0109] exist Figure 7A Until Figure 7C In this process, a first spacer 81 and a second spacer 82 are formed on the sidewalls of the fin 66 and / or the nanostructure 55. The first spacer 81 and the second spacer 82 can be formed by... Figures 6A to 6C The structure illustrated is formed by successively forming a first spacer layer and a second spacer layer on top of it. The first and second spacer layers will subsequently be patterned to form a first spacer 81 and a second spacer 82, respectively, which will then be used to form self-aligned source / drain regions. The first spacer layer may be formed on the top surface of the STI region 68; the top surface and sidewalls of the fin 66, nanostructure 55, and mask 78; and the sidewalls of the dummy gate 76 and dummy gate dielectric layer 71. The second spacer layer is deposited over the first spacer layer. The first spacer layer may be formed from silicon oxide, silicon nitride, silicon oxynitride, or the like using techniques such as thermal oxidation, or deposited by CVD, ALD, or the like. The second spacer layer may be formed from a material having a different etch rate than the material of the first spacer layer, such as silicon oxide, silicon nitride, silicon oxynitride, or the like, and may be deposited by CVD, ALD, or the like.

[0110] After the formation of the first spacer layer and before the formation of the second spacer layer, placement for the lightly doped source / drain (LDD) regions (not shown separately) can be performed. In embodiments with different device types, this is similar to the above description. Figure 4 As described above, a mask (such as a photoresist) can be formed over the n-type region 50N, simultaneously exposing the p-type region 50P, and an appropriate type of impurity (e.g., p-type) can be implanted into the fins 66 and nanostructures 55 exposed in the p-type region 50P. The mask can then be removed. Subsequently, a mask (such as a photoresist) can be formed over the p-type region 50P, simultaneously exposing the n-type region 50N, and an appropriate type of impurity (e.g., n-type) can be implanted into the fins 66 and nanostructures 55 exposed in the n-type region 50N. The mask can then be removed. The n-type impurity can be any of the n-type impurities discussed above, and the p-type impurity can be any of the p-type impurities discussed above. The lightly doped source / drain regions can have a density of approximately 1 x 10⁻⁶. 15 atoms / cm 3 To approximately 1x10 19 atoms / cm 3 The range of impurity concentrations. Annealing can be used to repair implant damage and revitalize implanted impurities.

[0111] See further Figure 7A Until Figure 7CThe first spacer layer and the second spacer layer are etched to form the first spacer 81 and the second spacer 82, respectively. As will be discussed in more detail below, the first spacer 81 and the second spacer 82 function to self-aligned, subsequently formed source and drain regions, and to protect the sidewalls of the fin 66 and / or nanostructure 55 during subsequent processing. The first spacer layer and the second spacer layer can be etched using a suitable etching process, such as an isotropic etching process (e.g., wet etching process), anisotropic etching process (e.g., dry etching process), or the like. In some embodiments, the material of the second spacer layer has a different etching rate than the material of the first spacer layer, such that the first spacer layer can act as an etch stop layer when the second spacer layer is patterned, and such that the second spacer layer can act as a mask when the first spacer layer is patterned. For example, the second spacer layer can be etched using an anisotropic etching process, wherein the first spacer layer acts as an etch stop layer, and wherein the remaining portion of the second spacer layer forms as shown in the figure. Figure 7B The second spacer 82 is illustrated in the diagram. Subsequently, when etching the exposed portions of the first spacer layer, the second spacer 82 acts as a mask, thereby forming a shape as shown in the diagram. Figure 7B and Figure 7C The first spacer 81 is shown in the middle.

[0112] like Figure 7B As illustrated, the first spacer 81 and the second spacer 82 are disposed on the sidewalls of the fin 66 and / or the nanostructure 55. Figure 7C As illustrated, in some embodiments, the second spacer layer may be removed over the first spacer layer adjacent to the mask 78, dummy gate 76, and dummy gate dielectric layer 71, and the first spacer 81 is disposed on the sidewalls of the mask 78, dummy gate 76, and dummy gate dielectric layer 71. In other embodiments, a portion of the second spacer layer may remain over the first spacer layer adjacent to the mask 78, dummy gate 76, and dummy gate dielectric layer 71.

[0113] It should be noted that the above disclosure generally describes the process for forming spacers and LDD regions. Other processes and sequences can be used. For example, fewer or additional spacers can be used, different sequence of steps can be used (e.g., the first spacer 81 can be patterned before depositing the second spacer layer), additional spacers and / or the like can be formed and removed. Additionally, different structures and steps can be used to form n-type and p-type devices.

[0114] exist Figure 8A Until Figure 8CIn some embodiments, a first groove 86 is formed in the nanostructure 55 and the fin 66. Epitaxial material and epitaxial source / drain regions will subsequently be formed in the first groove 86. The first groove 86 may extend through the first nanostructure 52, the second nanostructure 54, and partially through the fin 66. In one embodiment, as... Figure 8B The illustration shows that the nanostructure 55 and fin 66 can be etched such that the bottom surface of the first groove 86 is disposed above the top surface of the STI region 68. In other embodiments, the top surface of the STI region 68 may be flush with or below the bottom surface of the first groove 86.

[0115] The first groove 86 can be formed by etching the nanostructure 55 and the fin 66 using an anisotropic etching process (such as RIE, NBE, or similar). During the etching process used to form the first groove 86, a first spacer 81, a second spacer 82, and a mask 78 shield portions of the fin 66, the nanostructure 55, and the substrate 50. A single etching process or multiple etching processes can be used to etch each layer of the nanostructure 55. After the first groove 86 reaches the desired depth, a timed etching process can be used to terminate the etching.

[0116] exist Figure 9A In this process, portions of the sidewalls of the layers of a multilayer stack 64 formed by the first semiconductor material (e.g., the first nanostructure 52) exposed by the first groove 86 are etched to form sidewall grooves 88. Figure 9B draw Figure 9A Region 87 of the semiconductor device 10 shown in the diagram. After the sidewall recess 88 is formed, the sidewalls of the first nanostructure 52 adjacent to the sidewall recess 88 may be straight (e.g., Figure 9A (Drawing), convex or concave (such as) Figure 9B (Illustrated). The sidewalls can be etched using an isotropic etching process, such as wet etching or the like. In one embodiment, wherein the first nanostructure 52 comprises, for example, SiGe, and the second nanostructure 54 comprises, for example, Si or SiC, the sidewalls of the first nanostructure 52 can be etched using a dry etching process using tetramethylammonium hydroxide (TMAH), ammonium hydroxide (NH4OH), or the like.

[0117] exist Figure 10A In the middle, the internal spacer 90 is formed in the side wall groove 88. Figure 10B draw Figure 10ARegion 87 of the semiconductor device 10 illustrated in the figure. An internal spacer 90 may comprise alternating first spacer layers 91 and second spacer layers 89. In one embodiment, the internal spacer 90 comprises at least two first spacer layers 91 and two second spacer layers 89. The first spacer layer 91 may comprise a first material having a lower dielectric constant than a second material of the second spacer layer 89. In one embodiment, each of the first material of the first spacer layer 91 and the second material of the second spacer layer 89 may comprise silicon, carbon, oxygen, and / or nitrogen, and may comprise SiCN, SiN, SiCON, SiOC, SiON, SiC, or the like. In one embodiment, the first material is different from the second material. In one embodiment, the first material and the second material are the same. In one embodiment, the first material of the first spacer layer 91 may comprise a low-k material with a dielectric constant value below about 3.5. In one embodiment, the second material of the second spacer layer 89 has a higher carbon concentration and / or nitrogen concentration than the first material of the first spacer layer 91. In one embodiment, the first material of the first spacer layer 91 has a higher concentration of oxygen, fluorine, and / or boron compared to the second material of the second spacer layer 89. In one embodiment, the fluorine and / or boron concentration in the first material of the first spacer layer 91 may be higher than the fluorine and / or boron concentration in the second material of the second spacer layer 89 by a range from 0.1 atomic percent to 5 atomic percent.

[0118] The alternating first spacer layer 91 and second spacer layer 89 can be achieved using conformal deposition processes (such as atomic layer deposition (ALD), chemical vapor deposition (CVD), or similar), by sequentially depositing the first material and the second material onto the substrate. Figure 9A The structure is formed above the previously illustrated structure. In one embodiment, a first spacer layer 91 or a second spacer layer 89 may be deposited first (e.g., as shown in the previous figure). Figure 10B Any of the elements shown in the diagram are then alternately deposited, with the second spacer layer 89 and the first spacer layer 91 deposited. For example, the first spacer layer 91 and the second spacer layer 89 may be deposited above the top surface of the STI region 68 and the mask 78, above the top surface and sidewalls of the first spacer 81, and on the sidewalls and bottom surfaces of the first recess 86 (e.g., on the exposed surfaces of the first nanostructure 52 and the second nanostructure 54 in the sidewall recess 88). After the formation of the first spacer layer 91 and the second spacer layer 89, an anisotropic etching process, such as RIE, NBE, or similar, is performed. The remaining portions of the first spacer layer 91 and the second spacer layer 89 in the sidewall recess 88 form the internal spacer 90. Figure 10BAs illustrated in the diagram, each of the second spacer layers 89 may have a thickness T1, and each of the first spacer layers 91 may have a thickness T2, wherein thickness T1 and thickness T2 may each be at least 3 Å. The internal spacer 90 serves as the subsequently formed source / drain region and the subsequently formed gate dielectric layer 120 and gate electrode 102. Figure 21A Until Figure 21C The isolation features between (see subsequent illustrations). The internal spacer 90 prevents damage to the subsequently formed source / drain regions during subsequent etching processes.

[0119] In other embodiments, the internal spacers 90 may be formed such that each of the internal spacers 90 comprises only a single spacer layer. For example, the internal spacers 90 may be formed by... Figure 9A An internal spacer layer (not shown separately) is deposited over the structure illustrated. The internal spacer layer can be deposited using a conformal deposition process (such as CVD, ALD, or the like). The internal spacer layer may comprise materials such as silicon carbonitride (SiCN) or silicon oxycarbonitride (SiOCN). In other embodiments, silicon nitride or silicon oxynitride, or any suitable material, such as a low dielectric constant (low k) material with a dielectric constant value less than about 3.5, may be used. The internal spacer layer can then be anisotropically etched to form internal spacers 90 in the sidewall recesses 88. The internal spacer layer can be etched using anisotropic etching processes (such as RIE, NBE, or the like).

[0120] Advantages can be achieved by forming an internal spacer 90 comprising alternating first spacer layers 91 and second spacer layers 89. The first spacer layer 91 may comprise a first material having a lower dielectric constant than the second material of the second spacer layer 89. Each of the first material of the first spacer layer 91 and the second material of the second spacer layer 89 may comprise silicon, carbon, oxygen, and / or nitrogen, and may comprise SiCN, SiN, SiCON, SiOC, SiON, SiC, or the like. The first material of the first spacer layer 91 may comprise a low-k material with a dielectric constant value below about 3.5. The second material of the second spacer layer 89 may have a higher carbon and / or nitrogen concentration than the first material of the first spacer layer 91. The first material of the first spacer layer 91 may have a higher oxygen, fluorine, and / or boron concentration compared to the second material of the second spacer layer 89. The fluorine and / or boron concentration in the first material of the first spacer layer 91 may be higher than the fluorine and / or boron concentration in the second material of the second spacer layer 89 by a range from 0.1 atomic percent to 5 atomic percent. Furthermore, each of the second spacer layers 89 may have a thickness T1, and each of the first spacer layers 91 may have a thickness T2, wherein thickness T1 and thickness T2 may each be at least 3 Å. These advantages include having alternating internal spacers 90 in the first spacer layers 91 and second spacer layers 89, wherein the second material of the second spacer layer 89 has a higher carbon and / or nitrogen concentration than the first material of the first spacer layer 91, which creates an etch rate difference between the first spacer layer 91 and the second spacer layer 89 and enhances the etching rate in subsequent etching steps (e.g., for removing...). Figure 20A Until Figure 20C During the etching processes of the first nanostructures 52A, 52B, and 52C described later, the etching resistance of the internal spacer 90 is overcome to perform these subsequent etching steps to form the gate dielectric layer 120 and the gate electrode 102 (in Figure 21A Until Figure 21C (See subsequent illustrations). The first spacer layer 91, having a higher concentration of oxygen, fluorine, and / or boron than the second spacer layer 89, reduces the dielectric constant of the first spacer layer 91. This allows for a reduction in parasitic capacitance between the gate dielectric layer 120 and the gate electrode 102 and the epitaxial source / drain region 92 (in...). Figure 16A Until Figure 16D (As described later). Therefore, improved control over the profile of the internal spacer 90 can be achieved, allowing for reduced internal spacer 90 losses and less formation of the internal spacer 90's dish-like profile. Furthermore, the reduced parasitic capacitance between the gate dielectric layer 120 and the gate electrode 102 and the epitaxial source / drain region 92 allows for faster switching speeds and lower power consumption during device operation. This results in better device performance and improved reliability.

[0121] Figure 11A Until Figure 11C Alternative embodiments are illustrated. Unless otherwise specified, similar element symbols are used in this embodiment (and the embodiments discussed below) to represent... Figure 1 Until Figure 10B The embodiments illustrated in the figure show similar parts formed by similar processes. Therefore, this document may not repeat process steps and applicable materials. The initial steps of this embodiment are essentially the same as those in the previous one. Figure 1 Until Figure 9B The same as the diagram in the image. Figure 11A Until Figure 11C In the middle, the internal spacer 90 is formed in the side wall groove 88. Figure 11A Until Figure 11C draw Figure 9B Region 87 of the semiconductor device 10 shown in the figure.

[0122] Figure 11A The illustration shows the process of performing an etching process to form sidewall grooves 88 (in Figure 9A During and after the previously described process, oxide regions 93 may be formed on the newly exposed surface of the second nanostructure 54 in the sidewall recess 88. Oxide regions 93 may contain silicon oxide and may be formed during and after the etching process when the newly exposed silicon-containing surface of the second nanostructure 54 is oxidized by exposure to environmental conditions.

[0123] exist Figure 11B In this process, process 130 is performed to expose oxide regions 93 within sidewall recesses 88 to a carbon-containing precursor, thereby transforming oxide regions 93 into treated regions 95. Process 130 may use carbon doping of oxide regions 93 to form treated regions 95 comprising silicon carbide oxide (SiCO). The carbon-containing precursor may comprise propylene (C3H6), ethylene (C2H4), acetylene (C2H2), or the like. In one embodiment, process 130 may include a hot-dip process performed at a temperature above 500°C to facilitate the transformation of oxide regions 93 into treated regions 95.

[0124] Figure 11C The illustration shows that after processing 130, an internal spacer 90 is formed in a sidewall groove 88. The internal spacer 90 can be used in... Figure 10A and Figure 10B The internal spacers 90 are formed using similar materials and processes as previously described for forming them. For example, each of the internal spacers 90 may be included in... Figure 10A and Figure 10B The previously described single spacer layer. In another example, each of the internal spacers 90 may be contained within... Figure 10A and Figure 10BThe previously described alternating first spacer layer 91 and second spacer layer 89. However, in other embodiments, the inner spacer 90 may comprise any number of spacer layers containing any suitable material, wherein the spacer layers are formed in any suitable configuration.

[0125] Advantages are achieved by exposing oxide regions 93 to a carbon-containing precursor through processing 130 to transform oxide regions 93 into treated regions 95 comprising silicon carbide oxide (SiCO). Internal spacers 90 are formed in sidewall recesses 88 after processing 130. The carbon-containing precursor may comprise propylene (C3H6), ethylene (C2H4), acetylene (C2H2), or the like. Processing 130 may include a hot-dip process performed at temperatures above 500°C to facilitate the transformation of oxide regions 93 into treated regions 95. These advantages include the treated regions 95 having properties that are advantageous in subsequent etching steps (e.g., for removing oxide oxide from silicon carbide oxide). Figure 20A Until Figure 20C The enhanced etching resistance during the etching processes of the first nanostructures 52A, 52B, and 52C described earlier, is used to perform these subsequent etching steps to form the gate dielectric layer 120 and the gate electrode 102 (in... Figure 21A Until Figure 21C (See subsequent illustrations). This prevents the formation of gaps between the internal spacer 90 and the second nanostructures 54A to 54C, which would otherwise allow etchant used during these subsequent etching steps to contact and potentially damage the epitaxial source / drain regions 92 (in... Figure 16A Until Figure 16D (As will be described later). Therefore, the device's performance and reliability can be improved.

[0126] Figure 12A Until Figure 12C Alternative embodiments are illustrated. Unless otherwise specified, similar element symbols are used in this embodiment (and the embodiments discussed below) to represent... Figure 1 Until Figure 11C The embodiments illustrated in the figure show similar parts formed by similar processes. Therefore, this document may not repeat process steps and applicable materials. The initial steps of this embodiment are essentially the same as those in the previous one. Figure 1 Until Figure 9B The same as the diagram in the image. Figure 12A Until Figure 12C In the middle, the internal spacer 90 is formed in the side wall groove 88. Figure 12A Until Figure 12C draw Figure 9B Region 87 of the semiconductor device 10 shown in the figure.

[0127] Figure 12A The illustration shows the process of performing an etching process to form sidewall grooves 88 (in Figure 9A During and after the previously described process, oxide regions 93 may be formed on the newly exposed surface of the second nanostructure 54 in the sidewall recess 88. Oxide regions 93 may contain silicon oxide and may be formed during and after the etching process when the newly exposed silicon-containing surface of the second nanostructure 54 is oxidized by exposure to environmental conditions.

[0128] exist Figure 12B In the process, a first processing step 132 and a second processing step 134 are performed to transform the oxide region 93 within the sidewall groove 88 into a treated region 95. The first processing step 132 may include exposing the oxide region 93 to ammonia plasma (NH3). + A first processing step 132 transforms oxide region 93 into a semi-treated region, wherein during the first processing step 132, the silicon oxide of oxide region 93 is transformed into silicon oxynitride (SiON). A second processing step 134 may include exposing the semi-treated region (or oxide region 93, if the first processing step 132 has not yet been performed) to a boron-containing precursor to dope the semi-treated region (or oxide region 93) with boron. The boron-containing precursor may include boron trichloride (BCl3), diborane (B2H6), or the like. In one embodiment, the second processing step 134 may include a hot-dip process performed at a temperature above 500°C. In one embodiment, the first processing step 132 and the second processing step 134 may be performed simultaneously. In one embodiment, the second processing step 134 may be performed before or after the first processing step 132. After performing the first processing step 132 and the second processing step 134, the treated region 95 may contain boron-doped silicon oxynitride (SiON).

[0129] Figure 12C The illustration shows an internal spacer 90 formed in a sidewall recess 88 after the execution of the first processing step 132 and the second processing step 134. The internal spacer 90 can be used in… Figure 10A and Figure 10B The internal spacers 90 are formed using similar materials and processes as previously described for forming them. For example, each of the internal spacers 90 may be included in... Figure 10A and Figure 10B The previously described single spacer layer. In another example, each of the internal spacers 90 may be contained within... Figure 10A and Figure 10B The previously described alternating first spacer layer 91 and second spacer layer 89. However, in other embodiments, the inner spacer 90 may comprise any number of spacer layers containing any suitable material, wherein the spacer layers are formed in any suitable configuration.

[0130] Advantages are achieved by performing a first processing step 132 and a second processing step 134 to transform the oxide region 93 into a treated region 95 comprising boron-doped silicon oxynitride (SiON). After performing the first processing step 132 and the second processing step 134, internal spacers 90 are formed in the sidewall recesses 88. The first processing step 132 may include exposing the oxide region 93 to ammonia plasma (NH3). + To form a semi-treated region, the second processing step 134 may include exposing the semi-treated region to a boron-containing precursor, such as boron trichloride (BCl3), diborane (B2H6), or the like. The second processing step 134 may include a hot-dip process performed at temperatures above 500°C. These advantages include the treated region 95, which has properties that are easily removed in subsequent etching steps (e.g., for removing...). Figure 20A Until Figure 20C The enhanced etching resistance during the etching processes of the first nanostructures 52A, 52B, and 52C described earlier, is used to perform these subsequent etching steps to form the gate dielectric layer 120 and the gate electrode 102 (in... Figure 21A Until Figure 21C (See subsequent illustrations). This prevents the formation of gaps between the internal spacer 90 and the second nanostructures 54A to 54C, which could otherwise allow etchant used during subsequent etching steps to contact and potentially damage the epitaxial source / drain regions 92. Boron doping of the treated region 95 may help compensate for possible boron accumulation that could occur in the internal spacer 90 containing silicon oxynitride (SiON), which could otherwise reduce the subsequent formation of the epitaxial source / drain regions 92 (in... Figure 16A Until Figure 16D The boron concentration (as described in the text) is thus adjusted. Therefore, the device's efficiency and reliability can be improved.

[0131] Figure 13A Until Figure 13C Alternative embodiments are illustrated. Unless otherwise specified, similar element symbols are used in this embodiment (and the embodiments discussed below) to represent... Figure 1 Until Figure 12C The embodiments illustrated in the figure show similar parts formed by similar processes. Therefore, this document may not repeat process steps and applicable materials. The initial steps of this embodiment are essentially the same as those in the previous one. Figure 1 Until Figure 9B The same as the diagram in the image. Figure 13A Until Figure 13C In the middle, the internal spacer 90 is formed in the side wall groove 88. Figure 13A Until Figure 13C draw Figure 9B Region 87 of the semiconductor device 10 shown in the figure.

[0132] Figure 13A The illustration shows the process of performing an etching process to form sidewall grooves 88 (in Figure 9A During and after the previously described process, oxide regions 93 may be formed on the newly exposed surface of the second nanostructure 54 in the sidewall recess 88. Oxide regions 93 may contain silicon oxide and may be formed during and after the etching process when the newly exposed silicon-containing surface of the second nanostructure 54 is oxidized by exposure to environmental conditions.

[0133] exist Figure 13B In this process, a first processing step 136 and a second processing step 138 are performed to transform the oxide region 93 within the sidewall recess 88 into a treated region 95. The first processing step 136 and the second processing step 138 may be performed simultaneously, or alternatively, the second processing step 138 may be performed before or after the first processing step 136. For example, the first processing step 136 may include exposing the oxide region 93 to a carbon-containing precursor to transform the oxide region 93 into a semi-treated region, wherein during the first processing step 136, the silicon oxide of the oxide region 93 is converted into silicon carbide oxide (SiCO). The carbon-containing precursor may include propylene (C3H6), ethylene (C2H4), acetylene (C2H2), or the like. In one embodiment, the first processing step 136 may include a hot-dip process performed at a temperature above 500°C. After performing the first processing step 136, the second processing step 138 may be performed, wherein the second processing step 138 includes exposing the semi-treated region to ammonia plasma (NH3). + This further transforms the semi-processed region into a processed region 95 containing silicon oxynitride (SiCON). In another example, a second processing step 138 is first performed, wherein the second processing step 138 includes exposing the oxide region 93 to ammonia plasma (NH3). + The oxide region 93 is then converted into a semi-treated region containing silicon oxynitride (SiON). After performing the second processing step 138, a first processing step 136 is performed, wherein the first processing step 136 includes exposing the semi-treated region to a carbon-containing precursor to convert the semi-treated region into a treated region 95 containing silicon oxynitride (SiCON).

[0134] Figure 13C The illustration shows an internal spacer 90 formed in a sidewall recess 88 after the execution of the first processing step 136 and the second processing step 138. The internal spacer 90 can be used in… Figure 10A and Figure 10B The internal spacers 90 are formed using similar materials and processes as previously described for forming them. For example, each of the internal spacers 90 may be included in... Figure 10A and Figure 10BThe previously described single spacer layer. In another example, each of the internal spacers 90 may be contained within... Figure 10A and Figure 10B The previously described alternating first spacer layer 91 and second spacer layer 89. However, in other embodiments, the inner spacer 90 may comprise any number of spacer layers containing any suitable material, wherein the spacer layers are formed in any suitable configuration.

[0135] Advantages can be achieved by performing a first processing step 136 and a second processing step 138 to transform the oxide region 93 into a treated region 95 comprising silicon carbide oxide (SiCO). After performing the first processing step 136 and the second processing step 138, internal spacers 90 are formed in the sidewall recesses 88. The first processing step 136 can be performed first, wherein the first processing step 136 includes exposing the oxide region 93 to a carbon-containing precursor to form a semi-treated region comprising silicon carbide oxide (SiCO), and the second processing step 138 can include exposing the semi-treated region to ammonia plasma (NH3). + Alternatively, a second processing step 138 may be performed first, wherein the second processing step 138 may include exposing the oxide region 93 to ammonia plasma (NH3). + To form a semi-treated region comprising silicon oxynitride (SiON), and the first processing step 136 includes exposing the semi-treated region to a carbon-containing precursor. The first processing step 136 may include a hot-dip process performed at temperatures above 500°C. These advantages include the treated region 95 having properties that, in subsequent etching steps (e.g., for removing...) Figure 20A Until Figure 20C The enhanced etching resistance during the etching processes of the first nanostructures 52A, 52B, and 52C described earlier, is used to perform these subsequent etching steps to form the gate dielectric layer 120 and the gate electrode 102 (in... Figure 21A Until Figure 21C (See subsequent illustrations). This prevents the formation of gaps between the internal spacer 90 and the second nanostructures 54A to 54C, which would otherwise allow etchant used during these subsequent etching steps to come into contact and potentially damage the epitaxial source / drain regions 92. Therefore, device performance and reliability can be improved.

[0136] Figure 14A Until Figure 14C Alternative embodiments are illustrated. Unless otherwise specified, similar element symbols are used in this embodiment (and the embodiments discussed below) to represent... Figure 1 Until Figure 13CThe embodiments illustrated in the figure show similar parts formed by similar processes. Therefore, this document may not repeat process steps and applicable materials. The initial steps of this embodiment are essentially the same as those in the previous one. Figure 1 Until Figure 9B The same as the diagram in the image. Figure 14A Until Figure 14C In the middle, the internal spacer 90 is formed in the side wall groove 88. Figure 14A Until Figure 14C draw Figure 9B Region 87 of the semiconductor device 10 shown in the figure.

[0137] Figure 14A The illustration shows the process of performing an etching process to form sidewall grooves 88 (in Figure 9A During and after the previously described process, oxide regions 93 may be formed on the newly exposed surface of the second nanostructure 54 in the sidewall recess 88. Oxide regions 93 may contain silicon oxide and may be formed during and after the etching process when the newly exposed silicon-containing surface of the second nanostructure 54 is oxidized by exposure to environmental conditions.

[0138] exist Figure 14B In this process, a first processing step 140, a second processing step 142, and a third processing step 144 are performed to transform the oxide region 93 within the sidewall groove 88 into a treated region 95. In one embodiment, the first processing step 140, the second processing step 142, and the third processing step 144 may be performed simultaneously. In one embodiment, the first processing step 140, the second processing step 142, and the third processing step 144 may be performed in any order. In one embodiment, the first processing step 140 may include exposing the sidewalls and bottom surfaces of the first groove 86 to a carbon-containing precursor, wherein the carbon-containing precursor may include propylene (C3H6), ethylene (C2H4), acetylene (C2H2), or the like. In one embodiment, the first processing step 140 may include a hot-dip process performed at a temperature above 500°C. In one embodiment, the second processing step 142 may include exposing the sidewalls and bottom surfaces of the first groove 86 to ammonia plasma (NH3). + In one embodiment, the third processing step 144 may include exposing the sidewalls and bottom surface of the first groove 86 to a boron-containing precursor, wherein the boron-containing precursor may include boron trichloride (BCl3), diborane (B2H6), or the like. In one embodiment, the third processing step 144 may include a hot-dip process performed at a temperature above 500°C. In one embodiment, after performing the first processing step 140, the second processing step 142, and the third processing step 144, the oxide region 93 is transformed into a treated region 95, which may contain boron-doped silicon oxycarbonitride (SiCON).

[0139] Figure 14CThe illustration shows an internal spacer 90 formed in a sidewall recess 88 after the execution of the first processing step 140, the second processing step 142, and the third processing step 144. The internal spacer 90 can be used in… Figure 10A and Figure 10B The internal spacers 90 are formed using similar materials and processes as previously described for forming them. For example, each of the internal spacers 90 may be included in... Figure 10A and Figure 10B The previously described single spacer layer. In another example, each of the internal spacers 90 may be contained within... Figure 10A and Figure 10B The previously described alternating first spacer layer 91 and second spacer layer 89. However, in other embodiments, the inner spacer 90 may comprise any number of spacer layers containing any suitable material, wherein the spacer layers are formed in any suitable configuration.

[0140] Advantages can be achieved by performing a first processing step 140, a second processing step 142, and a third processing step 144 to transform the oxide region 93 into a treated region 95 comprising boron-doped silicon oxynitride (SiCON). After performing the first processing step 140, the second processing step 142, and the third processing step 144, internal spacers 90 are formed in sidewall recesses 88. The first processing step 140 may include exposing the sidewalls and bottom surfaces of the first recess 86 to a carbon-containing precursor, such as propylene (C3H6), ethylene (C2H4), acetylene (C2H2), or the like. The second processing step 142 may include exposing the sidewalls and bottom surfaces of the first recess 86 to ammonia plasma (NH3). + The third processing step 144 may include exposing the sidewalls and bottom surface of the first groove 86 to a boron-containing precursor, such as boron trichloride (BCl3), diborane (B2H6), or the like. In one embodiment, one or more of these processing steps may include a hot-dip process performed at a temperature above 500°C. These advantages include carbon-doped treated regions 95, which have the advantages of being easily removed in subsequent etching steps (e.g., for removing carbon from the surface of the groove). Figure 20A Until Figure 20C The enhanced etching resistance during the etching processes of the first nanostructures 52A, 52B, and 52C described earlier, is used to perform these subsequent etching steps to form the gate dielectric layer 120 and the gate electrode 102 (in... Figure 21A Until Figure 21C(See subsequent illustrations). This prevents the formation of gaps between the internal spacer 90 and the second nanostructures 54A to 54C, which could otherwise allow etchant used during subsequent etching steps to contact and potentially damage the epitaxial source / drain regions 92. Boron doping of the treated region 95 may help compensate for possible boron accumulation that could occur in the internal spacer 90 containing silicon oxynitride (SiCON), which could otherwise reduce the subsequent formation of the epitaxial source / drain regions 92 (in... Figure 16A Until Figure 16D The boron concentration (as described in the text) is thus adjusted. Therefore, the device's efficiency and reliability can be improved.

[0141] Figure 15A Until Figure 15C Alternative embodiments are illustrated. Unless otherwise specified, similar element symbols are used in this embodiment (and the embodiments discussed below) to represent... Figure 1 Until Figure 14C The embodiments illustrated in the figure show similar parts formed by similar processes. Therefore, this document may not repeat process steps and applicable materials. The initial steps of this embodiment are essentially the same as those in the previous one. Figure 1 Until Figure 9B The same as the diagram in the image. Figure 15A Until Figure 15C In the middle, the internal spacer 90 is formed in the side wall groove 88. Figure 15A Until Figure 15C draw Figure 9B Region 87 of the semiconductor device 10 shown in the figure.

[0142] Figure 15A The illustration shows the process of performing an etching process to form sidewall grooves 88 (in Figure 9A During and after the previously described process, oxide regions 93 may be formed on the newly exposed surface of the second nanostructure 54 in the sidewall recess 88. Oxide regions 93 may contain silicon oxide and may be formed during and after the etching process when the newly exposed silicon-containing surface of the second nanostructure 54 is oxidized by exposure to environmental conditions.

[0143] exist Figure 15BIn this process, etching process 146 is performed to remove oxide regions 93 within the sidewall recess 88. In one embodiment, etching process 146 may comprise performing an in-situ dry etching process in the same processing chamber where the sidewall recess 88 was previously formed, wherein the dry etching process includes exposing the oxide regions 93 to a fluorine-based etchant, such as hydrogen fluoride (HF) gas, nitrogen trifluoride (NF3) gas, or the like. In one embodiment, during etching process 146, the sidewall surfaces of the first nanostructure 52 in the sidewall recess 88 may also be trimmed and reshaped (e.g., by removing portions of the material of the first nanostructure 52). For example, during etching process 146, the sidewall surfaces of the first nanostructure 52 may be reshaped to have a smoother surface, including smoother end faces and smoother sidewall profiles. In one embodiment, after etching process 146, the end faces of the first nanostructure 52 may be less rounded than before etching process 146.

[0144] Figure 15C The illustration shows that after etching process 146, internal spacers 90 are formed in the sidewall recesses 88. Internal spacers 90 can be used in… Figure 10A and Figure 10B The internal spacers 90 are formed using similar materials and processes as previously described for forming them. For example, each of the internal spacers 90 may be included in... Figure 10A and Figure 10B The previously described single spacer layer. In another example, each of the internal spacers 90 may be contained within... Figure 10A and Figure 10B The previously described alternating first spacer layer 91 and second spacer layer 89. However, in other embodiments, the inner spacer 90 may comprise any number of spacer layers containing any suitable material, wherein the spacer layers are formed in any suitable configuration. For example, in one embodiment, each of the inner spacers 90 may comprise at least one first spacer layer 91 and one second spacer layer 89. In one embodiment, the second spacer layer 89 may contain boron in the range of 0.1 atomic percent to 2 atomic percent.

[0145] Advantages are achieved by performing etching process 146 to remove oxide regions 93 within the sidewall recesses 88. Internal spacers 90 are formed in the sidewall recesses 88 after etching process 146. Etching process 146 may comprise an in-situ dry etching process performed in the same processing chamber where the sidewall recesses 88 were previously formed, wherein the dry etching process uses a fluorine-based etchant, such as hydrogen fluoride (HF) gas, nitrogen trifluoride (NF3) gas, or the like. During etching process 146, the sidewall surfaces of the first nanostructure 52 in the sidewall recesses 88 can be trimmed and reshaped to obtain a smoother surface. These advantages include the removal of oxide regions 93, which might otherwise be lost during subsequent etching steps (e.g., in the process of removing oxide regions 93). Figure 20A Until Figure 20C During the etching processes of the first nanostructures 52A, 52B, and 52C described later, they were unintentionally removed, and these subsequent etching steps were performed to form the gate dielectric layer 120 and the gate electrode 102 (in Figure 21A Until Figure 21C (See subsequent illustrations), and to prevent the formation of gaps between the internal spacer 90 and the second nanostructures 54A to 54C, which could otherwise allow etchant used during these subsequent etching steps to come into contact and potentially damage the epitaxial source / drain regions 92. Furthermore, the smoother surface of the first nanostructure 52, achieved through trimming and reshaping during etching process 146, provides a better surface for subsequent formation of the internal spacer 90. This may help reduce the formation of a dish-shaped profile in the internal spacer 90. Therefore, device performance and reliability can be improved.

[0146] exist Figure 16A Until Figure 16D In this configuration, an epitaxial source / drain region 92 is formed in the first groove 86. In some embodiments, the epitaxial source / drain region 92 can apply stress to the second nanostructures 54A, 54B, and 54C, thereby improving performance. Figure 16D The illustration shows that epitaxial source / drain regions 92 are formed in a first recess 86, such that each dummy gate 76 is disposed between corresponding adjacent pairs of epitaxial source / drain regions 92. In some embodiments, a first spacer 81 is used to separate the epitaxial source / drain regions 92 from the dummy gates 76, and an inner spacer 90 is used to separate the epitaxial source / drain regions 92 from the first nanostructures 52A, 52B, and 52C by an appropriate lateral distance, such that the epitaxial source / drain regions 92 do not short-circuit with the gate subsequently formed in the resulting nano-FET.

[0147] Epitaxial source / drain regions 92 in the n-type region 50N (e.g., an NMOS region) can be formed by shielding the p-type region 50P (e.g., a PMOS region). The epitaxial source / drain regions 92 are then epitaxially grown in a first recess 86 in the n-type region 50N. The epitaxial source / drain regions 92 can comprise any acceptable material suitable for an n-type nano-FET. For example, if the second nanostructure 54 is silicon, the epitaxial source / drain regions 92 can comprise materials to which tensile strain is applied to the second nanostructures 54A, 54B, and 54C, such as silicon, silicon carbide, phosphorus-doped silicon carbide, silicon phosphide, or the like. The epitaxial source / drain regions 92 may have surfaces protruding from the corresponding upper surface of the nanostructure 55 and may have facets.

[0148] The epitaxial source / drain region in the p-type region 50P (e.g., a PMOS region) can be formed by shielding the n-type region 50N (e.g., an NMOS region). Next, the epitaxial source / drain region 92 is epitaxially grown in a first recess 86 in the p-type region 50P. The epitaxial source / drain region 92 can include any acceptable material suitable for a p-type nano-FET. For example, if the first nanostructure 52 is silicon-germanium, the epitaxial source / drain region 92 can include a material that applies compressive strain to the first nanostructures 52A, 52B, and 52C, such as silicon-germanium, boron-doped silicon-germanium, germanium, germanium-tin, or the like. The epitaxial source / drain region 92 can also have a surface protruding from the corresponding surface of the nanostructure 55 and can have facets.

[0149] Epitaxial source / drain regions 92, first nanostructures 52, second nanostructures 54, and / or substrate 50 can be doped to form source / drain regions, similar to the previously discussed process for forming lightly doped source / drain regions, followed by annealing. The source / drain regions may have a density of approximately 1 x 10⁻⁶. 19 atoms / cm 3 With approximately 1x10 21 atoms / cm 3 The impurity concentrations between these values. The n-type and / or p-type impurities used in the source / drain regions can be any of the impurities discussed previously. In some embodiments, the epitaxial source / drain regions 92 can be doped in situ during growth.

[0150] Due to the epitaxial process used to form the epitaxial source / drain regions 92 in the n-type region 50N and the p-type region 50P, the upper surface of the epitaxial source / drain regions 92 has facets that extend laterally outward beyond the sidewalls of the nanostructure 55. In some embodiments, these facets cause adjacent epitaxial source / drain regions 92 of the same nano-FET to merge, as by Figure 16BIllustration. In other embodiments, adjacent epitaxial source / drain regions 92 remain separated after the epitaxial process is completed, as illustrated by... Figure 16C Illustration. In Figure 16B and Figure 16C In the illustrated embodiment, a first spacer 81 may be formed to the top surface of the STI region 68, thereby blocking epitaxial growth. In some other embodiments, the first spacer 81 may cover a portion of the sidewalls of the nanostructure 55, thereby further blocking epitaxial growth. In some other embodiments, the spacer etching used to form the first spacer 81 may be adjusted to remove spacer material to allow the epitaxial growth region to extend to the surface of the STI region 68.

[0151] The epitaxial source / drain region 92 may comprise one or more semiconductor material layers. For example, the epitaxial source / drain region 92 may comprise a first semiconductor material layer 92A, a second semiconductor material layer 92B, and a third semiconductor material layer 92C. Any number of semiconductor material layers may be used in the epitaxial source / drain region 92. Each of the first semiconductor material layer 92A, the second semiconductor material layer 92B, and the third semiconductor material layer 92C may be formed of different semiconductor materials and may be doped to different dopant concentrations. In some embodiments, the first semiconductor material layer 92A may have a dopant concentration less than that of the second semiconductor material layer 92B and greater than that of the third semiconductor material layer 92C. In embodiments in which the epitaxial source / drain region 92 comprises three semiconductor material layers, the first semiconductor material layer 92A may be deposited, the second semiconductor material layer 92B may be deposited over the first semiconductor material layer 92A, and the third semiconductor material layer 92C may be deposited over the second semiconductor material layer 92B.

[0152] exist Figure 17A Until Figure 17C In the middle, the first interlayer dielectric (ILD) 96 is in Figure 16A Until Figure 16DThe first ILD 96 is deposited above the structure illustrated in the figure. It may be formed of a dielectric material and can be deposited by any suitable method, such as CVD, plasma-enhanced CVD (PECVD), or FCVD. The dielectric material may include phospho-silicate glass (PSG), boro-silicate glass (BSG), boron-doped phospho-silicate glass (BPSG), undoped-silicate glass (USG), or the like. Other insulating materials formed by any acceptable process may be used. In some embodiments, a contact etch stop layer (CESL) 94 is disposed between the first ILD 96 and the epitaxial source / drain region 92, the mask 78, and the first spacer 81. CESL 94 may contain a dielectric material, such as silicon nitride, silicon oxide, silicon oxynitride, or similar, which has a different etch rate than the material of the overlying first ILD 96.

[0153] exist Figure 18A Until Figure 18C In this process, a planarization process (such as chemical mechanical polishing) can be performed to make the top surface of the first ILD 96 flush with the top surface of the dummy gate 76 or the mask 78. The planarization process may also remove the mask 78 on the dummy gate 76 and a portion of the first spacer 81 along the sidewall of the mask 78. After the planarization process, the top surfaces of the dummy gate 76, the first spacer 81, and the first ILD 96 are flush. Therefore, the top surface of the dummy gate 76 is exposed through the first ILD 96. In some embodiments, the mask 78 may remain, in which case the planarization process makes the top surface of the first ILD 96 flush with the top surfaces of the mask 78 and the first spacer 81.

[0154] exist Figure 19A Until Figure 19CIn the etching step, the dummy gate 76 and mask 78 (if present) are removed, forming a recess 98. A portion of the dummy gate dielectric layer 71 in the recess 98 may also be removed. In some embodiments, only the dummy gate 76 is removed, and the dummy gate dielectric layer 71 remains and is exposed by the recess 98. In some embodiments, the dummy gate dielectric layer 71 is removed from the recess 98 in a first region of the die (e.g., a core logic region) and remains in the recess 98 in a second region of the die (e.g., an input / output region). In some embodiments, the dummy gate 76 is removed by an anisotropic dry etching process. For example, the etching process may include a dry etching process using reactive gases that selectively etches the dummy gate 76 without etching the first ILD 96 and the first spacer 81. Each recess 98 exposes and / or covers a multilayer stack 64. A portion of the multilayer stack 64 is disposed between adjacent pairs of epitaxial source / drain regions 92. During removal, the dummy gate dielectric layer 71 may be used as an etch stop layer as the dummy gate 76 is etched. The dummy gate dielectric layer 71 may then be removed, as appropriate, after the dummy gate 76 has been removed.

[0155] exist Figure 20A Until Figure 20C In this process, first nanostructures 52A, 52B, and 52C are removed from regions 50N and 50P. First nanostructures 52A, 52B, and 52C can be removed by isotropic etching processes, such as wet etching, dry etching, or similar methods. The etchant used to remove first nanostructures 52A, 52B, and 52C may be selective for the materials of second nanostructures 54A, 54B, and 54C. Second nanostructures 54A, 54B, and 54C may also be subsequently referred to as channel layers 54A, 54B, and 54C, respectively. Second nanostructures 54A, 54B, and 54C between adjacent epitaxial source / drain regions 92 may additionally be referred to as channel regions 60. In one embodiment, the first nanostructures 52A, 52B, and 52C comprise a first semiconductor material (e.g., SiGe or the like), and the second nanostructures 54A, 54B, and 54C comprise a second semiconductor material (e.g., Si, SiC, or the like). A fluorine-based etchant (such as hydrogen fluoride (HF) or the like) can be used to remove layers of the multilayer stack 64 in regions 50N and 50P.

[0156] exist Figure 21A Until Figure 21CIn this process, a gate dielectric layer 120 and a gate electrode 102 are formed to replace the gate. The gate dielectric layer 120 is conformally deposited in the groove 98. The gate dielectric layer 120 may be formed on the top surface, sidewalls, and bottom surface of the second nanostructures 54A, 54B, and 54C. The gate dielectric layer 120 may also be deposited on the top surface of the first ILD 96, CESL 94, the first spacer 81, and the STI region 68, and on the sidewalls of the first spacer 81 and the inner spacer 90.

[0157] According to some embodiments, the gate dielectric layer 120 includes one or more dielectric layers, such as oxides, metal oxides, the like, or combinations thereof. For example, in some embodiments, the gate dielectric layer may include a silicon oxide layer and a metal oxide layer above the silicon oxide layer. In some embodiments, the gate dielectric layer 120 includes a high dielectric constant dielectric material, and in these embodiments, the gate dielectric layer 120 may have a dielectric constant greater than about 7.0, and may include metal oxides or silicates of hafnium, aluminum, zirconium, lanthanum, manganese, barium, titanium, lead, and combinations thereof. The structure of the gate dielectric layer 120 may be the same or different in the n-type region 50N and the p-type region 50P. Methods for forming the gate dielectric layer 120 may include molecular beam deposition (MBD), ALD, PECVD, and the like.

[0158] Gate electrodes 102 are deposited over gate dielectric layer 120 and fill the remaining portion of trench 98. Gate electrode 102 may include a metallic material such as titanium nitride, titanium oxide, tantalum nitride, tantalum carbide, cobalt, ruthenium, aluminum, tungsten, combinations thereof, or multiples thereof. For example, although in Figure 21A Until Figure 21C The diagram illustrates a single-layer gate electrode 102, but the gate electrode 102 may comprise any number of pad layers, any number of work function tuning layers, and filler material. Any combination of layers constituting the gate electrode 102 may be deposited between adjacent second nanostructures in the second nanostructure 54.

[0159] The formation of the gate dielectric layer 120 in the n-type region 50N and the p-type region 50P can occur simultaneously, such that the gate dielectric layer 120 in each region is formed of the same material, and the formation of the gate electrode 102 can occur simultaneously, such that the gate electrode 102 in each region is formed of the same material. In some embodiments, the gate dielectric layer 120 in each region can be formed by different processes, such that the gate dielectric layer 120 can be made of different materials and / or have different numbers of layers, and / or the gate electrode 102 in each region can be formed by different processes, such that the gate electrode 102 can be made of different materials and / or have different numbers of layers. When different processes are used, various masking steps can be used to mask and expose appropriate areas.

[0160] After filling the trench 98, a planarization process (such as chemical mechanical polishing) can be performed to remove excess material from the gate dielectric layer 120 and the gate electrode 102, which are located above the top surface of the first ILD 96. The remaining material of the gate electrode 102 and the gate dielectric layer 120 thus forms the replacement gate structure of the resulting nano-FET. The gate electrode 102 and the gate dielectric layer 120 may be collectively referred to as the "gate structure". The gate electrode 102 and the gate dielectric layer 120 may also be collectively referred to as the "gate stack".

[0161] exist Figure 22A Until Figure 22C In this process, the gate structure (including the gate dielectric layer 120 and the corresponding overlying gate electrode 102) is recessed such that a groove is formed directly above the gate structure and between the opposing portions of the first spacer 81. A gate mask 104 comprising one or more layers of dielectric material (such as silicon nitride, silicon oxynitride, or the like) fills the groove, followed by a planarization process to remove excess dielectric material extending over the first ILD 96. The subsequently formed gate contacts (such as those described below) Figure 24A Until Figure 24C The gate contact 114 penetrates the gate shield 104 to contact the top surface of the recessed gate electrode 102.

[0162] like Figure 22A Until Figure 22C Further illustration shows that the second ILD 106 is deposited over the first ILD 96 and over the gate mask 104. In some embodiments, the second ILD 106 is a flowable film formed by FCVD. In some embodiments, the second ILD 106 is formed of a dielectric material (such as PSG, BSG, BPSG, USG, or the like) and can be deposited by any suitable method (such as CVD, PECVD, or the like).

[0163] exist Figure 23A Until Figure 23C In, used for gate contact 114 (in Figure 24A Until Figure 24C The opening 108 (as shown in subsequent figures) is formed by the second ILD 106 and the gate shield 104, and is used for the source / drain contacts 112 (in... Figure 24BThe opening 109 (as shown in subsequent illustrations) is formed by the second ILD 106 and the first ILD 96. Openings 108 and 109 can be formed using acceptable photolithography and etching techniques. Opening 108 exposes the surface of the gate structure, and opening 109 exposes the surface of the epitaxial source / drain region 92. The silicide region 110 is formed above the epitaxial source / drain region 92 by first depositing a metal (not shown separately) capable of reacting with the underlying semiconductor material (e.g., silicon, silicon-germanium, germanium) of the epitaxial source / drain region 92 to form a silicide or germanide region, such as nickel, cobalt, titanium, tantalum, platinum, tungsten, other noble metals, other refractory metals, rare earth metals, or alloys thereof, above the exposed portion of the epitaxial source / drain region 92, and then performing a thermal annealing process to form the silicide region 110. Unreacted portions of the deposited metal are then removed, for example, by an etching process. The silicide region 110 can have a higher conductivity than the epitaxial source / drain region 92. The silicide region 110 is located between the epitaxial source / drain region 92 and the subsequently formed source / drain contact 112 (in...). Figure 24B A low-resistance interface is formed between the source / drain contacts 112 and the epitaxial source / drain region 92. Therefore, the contact resistance between the source / drain contacts 112 and the epitaxial source / drain region 92 can be reduced.

[0164] exist Figure 24A Until Figure 24C In this configuration, pads (such as a diffusion barrier layer, adhesive layer, or the like) and conductive material are formed in openings 108 and 109. The pads may include titanium, titanium nitride, tantalum, tantalum nitride, or the like. The conductive material may be copper, copper alloy, silver, gold, tungsten, cobalt, aluminum, nickel, or the like. A planarization process, such as chemical mechanical polishing, may be performed to remove excess material from the surface of the second ILD 106. The remaining pads and conductive material form gate contacts 114 in opening 108 and source / drain contacts 112 in opening 109. Gate contacts 114 are solid and electrically coupled to gate electrode 102, and source / drain contacts 112 are solid and electrically coupled to epitaxial source / drain regions 92.

[0165] The embodiments disclosed herein have several advantageous features. These embodiments include methods for forming internal spacers that act as isolation features between subsequently formed source / drain regions and subsequently formed gate structures. In one embodiment, the internal spacer may comprise a multilayer structure having alternating first and second spacer layers, wherein the first spacer layer comprises a first material (e.g., a low-dielectric-constant material) having a dielectric constant lower than that of a second material of the second spacer layer. In one embodiment, the second material of the second spacer layer may comprise silicon, carbon, oxygen, and / or nitrogen, and may comprise SiCN, SiN, SiCON, SiOC, SiON, or the like. The second spacer layer may have a higher carbon and / or nitrogen concentration than the first spacer layer. In one embodiment, the first spacer layer may have a higher oxygen, fluorine, and / or boron concentration than the second spacer layer, wherein the fluorine and / or boron concentration in the first spacer layer may be higher than the fluorine and / or boron concentration in the second spacer layer by a range from 0.1 atomic percent to 5 atomic percent. These advantages include the formation of internal spacers with alternating first and second spacer layers, wherein a first material of the first spacer layer has a lower dielectric constant than a second material of the second spacer layer. The second spacer layer has a higher carbon and / or nitrogen concentration than the first spacer layer, which enhances the etch resistance of the internal spacers during subsequent etch steps to form the gate structure. The first spacer layer has a higher oxygen, fluorine, and / or boron concentration, which allows for reduced parasitic capacitance between the gate structure and the source / drain regions. Therefore, improved control over the internal spacer profile can be achieved, allowing for reduced internal spacer losses and less formation of internal spacer dish profiles. Furthermore, the reduced parasitic capacitance between the gate structure and the source / drain regions allows for faster switching speeds and lower power consumption during device operation. This results in better device performance and improved reliability.

[0166] According to one embodiment, a method of forming a semiconductor device includes depositing a multilayer stack on a semiconductor substrate, the multilayer stack including a plurality of sacrificial layers alternating with a plurality of channel layers; etching the multilayer stack and the semiconductor substrate to form fins; forming dummy gates on the top surface and sidewalls of the fins; forming a first recess in the fin adjacent to the dummy gate; etching the ends of a plurality of sacrificial layers exposed in the first recess to form sidewall recesses; forming internal spacers in corresponding portions of the sidewall recesses, wherein each internal spacer includes alternating first spacer layers and second spacer layers, wherein the first spacer layers include a first material having a first material having a lower dielectric constant than a second material of the second spacer layers; and forming epitaxial source / drain regions in the first recess, wherein the epitaxial source / drain regions are isolated from the plurality of sacrificial layers by the internal spacers. In one embodiment, the method further includes removing the plurality of sacrificial layers to form a second recess; and forming a gate structure in the second recess, wherein the epitaxial source / drain regions are isolated from the gate structure by the internal spacers. In one embodiment, the first material of the first spacer layer and the second material of the second spacer layer comprise SiCN, SiN, SiCON, SiOC, SiON, or SiC. In one embodiment, the first material of the first spacer layer is different from the second material of the second spacer layer. In one embodiment, the carbon concentration of the second material of the second spacer layer is higher than the carbon concentration of the first material of the first spacer layer. In one embodiment, the nitrogen concentration of the second material of the second spacer layer is higher than the nitrogen concentration of the first material of the first spacer layer. In one embodiment, the boron concentration of the first material of the first spacer layer is higher than the boron concentration of the second material of the second spacer layer.

[0167] According to one embodiment, a method of forming a semiconductor device includes depositing a first sacrificial layer over a semiconductor substrate; depositing a first channel layer over the first sacrificial layer; etching a first groove extending through the first sacrificial layer, the first channel layer, and a top portion of the semiconductor substrate; etching an end of the first sacrificial layer exposed in the first groove to form a sidewall groove, wherein, while etching the end of the first sacrificial layer, oxide regions are formed on the surface of the first channel layer in the sidewall groove; depositing a first spacer layer on the sidewall and bottom surfaces of the first groove; depositing a second spacer layer over the first spacer layer in the first groove; and depositing a second spacer layer in the first groove. A third spacer layer is deposited above the first spacer layer, wherein the first and third spacer layers comprise a first material and the second spacer layer comprises a second material, and wherein the carbon concentration of the first material is higher than that of the second material; an etching process is performed to remove portions of the first, second, and third spacer layers, wherein after the etching process, the remaining portions of the first, second, and third spacer layers form internal spacers disposed in corresponding portions of the sidewall recesses; and an epitaxial source / drain region is formed in the first recess, wherein the epitaxial source / drain region is isolated from the first sacrificial layer by the internal spacers. In one embodiment, the method further includes replacing the first sacrificial layer with a gate structure, wherein the epitaxial source / drain region is isolated from the gate structure by the internal spacers. In one embodiment, the first and second materials comprise SiCN, SiN, SiCON, SiOC, SiON, or SiC. In one embodiment, the nitrogen concentration of the first material is higher than that of the second material. In one embodiment, the method further includes performing a first processing process to convert the oxide region into a processed region comprising silicon carbide oxide (SiCO). In one embodiment, performing the first processing step includes exposing the oxide region to a carbon-containing precursor, wherein the carbon-containing precursor includes propylene (C3H6), ethylene (C2H4), or acetylene (C2H2). In one embodiment, performing the first processing step includes performing a hot-dip process at a temperature above 500°C. In one embodiment, the second material has a lower dielectric constant than the first material.

[0168] According to one embodiment, a semiconductor device includes a gate structure above a semiconductor substrate; source / drain regions above the semiconductor substrate and on opposite sides of the gate structure; a first channel layer disposed between the source / drain regions and above the semiconductor substrate; and internal spacers between a first end of the first channel layer and the semiconductor substrate, wherein the gate structure is disposed between the internal spacers, wherein each internal spacer includes alternating first spacer layers and second spacer layers, wherein the first spacer layer includes a first material, wherein the second spacer layer includes a second material, wherein the first material has a lower dielectric constant than the second material, and wherein the carbon concentration of the second material is higher than the carbon concentration of the first material. In one embodiment, the nitrogen concentration of the second material is higher than the nitrogen concentration of the first material. In one embodiment, the boron concentration of the first material is higher than the boron concentration of the second material. In one embodiment, the boron concentration of the second material is in the range of 0.1 atomic percent to 2 atomic percent. In one embodiment, the first spacer layer includes at least two spacer layers, and the second spacer layer includes at least two spacer layers.

[0169] The foregoing outlines features of several embodiments to enable those skilled in the art to better understand the nature of this disclosure. Those skilled in the art should understand that they can readily use this disclosure as a basis for designing or modifying other processes and structures to achieve the same objectives and / or benefits as the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made herein without departing from the spirit and scope of this disclosure.

Claims

1. A method for forming a semiconductor device, characterized in that, Include: A multilayer stack is deposited on a semiconductor substrate, the multilayer stack comprising multiple sacrificial layers alternating with multiple channel layers; Etch the multilayer stack and the semiconductor substrate to form a fin; A virtual gate is formed on one top surface and multiple sidewalls of the fin; A first groove is formed in the fin adjacent to the virtual gate; Etching multiple ends of the plurality of sacrificial layers exposed in the first groove to form a plurality of sidewall grooves; A plurality of internal spacers are formed in corresponding portions of the plurality of sidewall recesses, each of the plurality of internal spacers comprising alternating layers of first spacers and layers of second spacers, wherein the plurality of first spacers comprises a first material having a dielectric constant lower than that of a second material of the plurality of second spacers; and An epitaxial source / drain region is formed in the first groove, wherein the epitaxial source / drain region is isolated from the plurality of sacrificial layers by the plurality of internal spacers.

2. The method as described in claim 1, characterized in that, Further includes: Remove the plurality of sacrificial layers to form a second groove; and A gate structure is formed in the second groove, wherein the epitaxial source / drain region is isolated from the gate structure by the plurality of internal spacers.

3. The method as described in claim 1, characterized in that, The first material of the plurality of first spacer layers and the second material of the plurality of second spacer layers comprise silicon carbonitride, silicon nitride, silicon carbonoxynitride, silicon carbon oxynitride, silicon oxynitride, or silicon carbide.

4. A method for forming a semiconductor device, characterized in that, Include: A first sacrificial layer is deposited over a semiconductor substrate; A first channel layer is deposited above the first sacrificial layer; The etching extends through a first groove in a top portion of the first sacrificial layer, the first channel layer, and the semiconductor substrate. Multiple ends of the first sacrificial layer exposed in the first groove are etched to form multiple sidewall grooves, wherein multiple oxide regions are formed on multiple surfaces of the first channel layer in the multiple sidewall grooves during the etching of the multiple ends of the first sacrificial layer; A first spacer layer is deposited on multiple sidewalls and a bottom surface in the first groove; A second spacer layer is deposited above the first spacer layer in the first groove; A third spacer layer is deposited above the second spacer layer in the first groove, wherein the first spacer layer and the third spacer layer comprise a first material and the second spacer layer comprises a second material, and wherein the carbon concentration of the first material is higher than the carbon concentration of the second material; An etching process is performed to remove multiple portions of the first spacer layer, the second spacer layer, and the third spacer layer, wherein after the etching process, multiple remaining portions of the first spacer layer, the second spacer layer, and the third spacer layer form multiple internal spacers disposed in corresponding portions of the multiple sidewall recesses; and An epitaxial source / drain region is formed in the first groove, wherein the epitaxial source / drain region is isolated from the first sacrificial layer by the plurality of internal spacers.

5. The method as described in claim 4, characterized in that, Further includes: A first processing step is performed to convert the plurality of oxide regions into a plurality of processed regions comprising silicon carbide oxide.

6. The method as described in claim 5, characterized in that, Performing the first processing step includes exposing the plurality of oxide regions to a carbon-containing precursor, wherein the carbon-containing precursor comprises propylene, ethylene, or acetylene.

7. The method as described in claim 4, characterized in that, The second material has a lower dielectric constant than the first material.

8. A semiconductor device, characterized in that, Include: A gate structure is located above a semiconductor substrate; Multiple source / drain regions are located above the semiconductor substrate and on multiple opposite sides of the gate structure; A first channel layer is disposed between the plurality of source / drain regions and above the semiconductor substrate; as well as A plurality of internal spacers are disposed between a plurality of first ends of the first channel layer and the semiconductor substrate, wherein the gate structure is disposed between the plurality of internal spacers, wherein each of the plurality of internal spacers comprises an alternating plurality of first spacer layers and a plurality of second spacer layers, wherein the plurality of first spacer layers comprises a first material, wherein the plurality of second spacer layers comprises a second material, wherein the first material has a lower dielectric constant than the second material, and wherein the carbon concentration of the second material is higher than the carbon concentration of the first material.

9. The semiconductor device as claimed in claim 8, characterized in that, The nitrogen concentration of the second material is higher than that of the first material.

10. The semiconductor device as claimed in claim 8, characterized in that, The boron concentration of the first material is higher than that of the second material.

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