Semiconductor device and method of manufacturing the same

Abstract

Methods include forming a first stack and a second stack of nanosheets over a substrate. A first opening is formed between the first stack and the second stack. A first semiconductor layer is formed in the opening. A first source / drain region is formed over the semiconductor layer. A first gate structure and a second gate structure are formed over the first stack and the second stack, where the first gate structure and the second gate structure extend in a second direction. A first interlayer dielectric layer is formed over the gate structures. An etch stop layer is formed over the interlayer dielectric layer. A second interlayer dielectric layer is formed over the etch stop layer. An interconnect wiring layer is formed in the second interlayer dielectric layer. An opening is formed in a second major surface that exposes a portion of the first source / drain region. A dopant is introduced through the opening into the exposed portion of the first source / drain region, where introducing the dopant converts the exposed portion of the first source / drain region to a dielectric layer. The dielectric layer is etched to expose the first source / drain region, and a conductive material is deposited in the opening. Embodiments of the present application also relate to semiconductor devices and methods of manufacturing the same.

Description

Technical Field

[0001] Embodiments of this application relate to semiconductor devices and methods of manufacturing the same. Background Technology

[0002] As the semiconductor industry has advanced to nanometer technology nodes in pursuit of higher device density, higher performance, and lower cost, challenges arising from manufacturing and design issues have led to the development of three-dimensional designs, such as multi-gate field-effect transistors (FETs), including FinFETs and Gate All-Around (GAA) FETs. In a FinFET, the gate electrode is adjacent to the three side surfaces of the channel region, with the gate dielectric layer in between. Because the gate structure surrounds (wraps) the fins on three surfaces, the transistor essentially has three gates controlling the current flowing through the fins or channel region. In a GAA FET, all side surfaces of the channel region are surrounded by the gate electrode, which allows for more complete depletion in the channel region and results in less short-channel effect due to a steeper subthreshold current swing (SS) and a smaller drain-induced barrier reduction (DIBL). As transistor dimensions continue to shrink to sub-20-25 nm technology nodes, further improvements to GAA FETs are needed. Summary of the Invention

[0003] Some embodiments of this application provide a method for manufacturing a semiconductor device, comprising: forming a fin structure extending in a first direction above a first main surface of a substrate, wherein the fin structure includes a first semiconductor layer and a second semiconductor layer alternately stacked along a second direction intersecting the first direction; forming a first source / drain trench and a second source / drain trench in the fin structure; forming a first epitaxial layer and a second epitaxial layer in the first source / drain trench and the second source / drain trench, respectively; forming a first source / drain region having a first conductivity and a second source / drain region having a second conductivity above the first epitaxial layer and the second epitaxial layer, respectively; removing the first source / drain region... A semiconductor layer; a gate structure is formed along the second semiconductor layer, wherein the gate structure extends upward in a third direction intersecting the first direction and the second direction; a first opening is formed in a second main surface of the substrate opposite to the first main surface to expose a portion of the first source / drain region; a first ion treatment is performed to convert the exposed portion of the first source / drain region into a bottom dielectric layer; a portion of the bottom dielectric layer is removed to expose the first source / drain region; and a conductive material having a third conductivity is deposited in the first opening to form a source / drain via contact, wherein the third conductivity is greater than the first conductivity and the second conductivity.

[0004] Other embodiments of this application provide a method for manufacturing a semiconductor device, comprising: forming a first channel region above a first main surface of a substrate; forming a second channel region spaced apart from the first channel region along a first direction above the first main surface; forming a first epitaxial layer between the first channel region and the second channel region in the first main surface of the substrate; forming a first source / drain region having a first conductivity above the first epitaxial layer; forming a first gate structure above the first channel region and forming a second gate structure above the second channel region, wherein the first gate structure and the second gate structure extend in a second direction intersecting the first direction, and the first gate structure and the second gate structure include a first dielectric material. The method comprises: a gate electrode layer above a gate dielectric layer having a constant dielectric constant; an insulating gate spacer having a second dielectric constant disposed on the sidewall of the gate electrode layer, wherein the first dielectric constant is greater than the second dielectric constant; an interlayer dielectric layer being formed above the first source / drain region and the first gate structure and the second gate structure; a first opening being formed in the interlayer dielectric layer above the first source / drain region to expose a portion of the first source / drain region; the exposed portion of the first source / drain region being converted into a front-side dielectric layer; a portion of the front-side dielectric layer being removed to expose the first source / drain region; and a conductive material having a second conductivity being deposited in the first opening to form a front-side conductive via, wherein the second conductivity is greater than the first conductivity.

[0005] Some embodiments of this application provide a semiconductor device, including: a channel region extending in a first direction and disposed above a first main surface of a substrate; a gate structure disposed above the channel region and extending in a second direction intersecting the first direction; a first source / drain region and a second source / drain region, each having a first conductivity and a second conductivity, disposed in the substrate on opposite sides of the gate structure along the first direction, as seen in the cross-sectional view; a conductive contact having a third conductivity, disposed between the second main surface of the substrate opposite the first main surface and the first source / drain region; and a silicide layer having a third conductivity. A third conductivity, disposed between the conductive contact and the first source / drain region, wherein the third conductivity is greater than the first conductivity, the second conductivity, and the fourth conductivity, and the fourth conductivity is greater than the first conductivity; a first insulating sidewall layer, disposed above the sidewall of the conductive contact, as seen in the cross-sectional view along the first direction; and a first dielectric layer, including a dopant, disposed between the insulating sidewall layer and the source / drain region along a third direction intersecting the first and second directions, wherein the surface of the first dielectric layer is located closer to the substrate than any portion of the silicide layer. Attached Figure Description

[0006] The embodiments of this disclosure are best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be emphasized that, in accordance with standard industry practice, the various components are not drawn to scale and are for illustrative purposes only. In practice, the dimensions of the various components may be arbitrarily increased or decreased for clarity of discussion.

[0007] Figure 1 A cross-sectional view is shown of one of the various stages of manufacturing a GAA FET semiconductor device according to an embodiment of the present disclosure.

[0008] Figure 2A A cross-sectional view of one of the various stages in the fabrication of a GAA FET semiconductor device according to embodiments of the present disclosure is shown, and Figure 2B An isometric view of one of the various stages of manufacturing a GAA FET semiconductor device according to an embodiment of the present disclosure is shown.

[0009] Figure 3A A cross-sectional view of one of the various stages in the fabrication of a GAA FET semiconductor device according to embodiments of the present disclosure is shown, and Figure 3B An isometric view of one of the various stages of manufacturing a GAA FET semiconductor device according to an embodiment of the present disclosure is shown.

[0010] Figure 4A cross-sectional view is shown of one of the various stages of manufacturing a GAA FET semiconductor device according to an embodiment of the present disclosure.

[0011] Figure 5 A cross-sectional view is shown of one of the various stages of manufacturing a GAA FET semiconductor device according to an embodiment of the present disclosure.

[0012] Figure 6 A cross-sectional view is shown of one of the various stages of manufacturing a GAA FET semiconductor device according to an embodiment of the present disclosure.

[0013] Figure 7 A cross-sectional view is shown of one of the various stages of manufacturing a GAA FET semiconductor device according to an embodiment of the present disclosure.

[0014] Figure 8 A cross-sectional view is shown of one of the various stages of manufacturing a GAA FET semiconductor device according to an embodiment of the present disclosure.

[0015] Figure 9A , Figure 9B and Figure 9C Cross-sectional views of various stages in the fabrication of a GAA FET semiconductor device according to embodiments of the present disclosure are shown, and Figure 9D Isometric views of various stages of manufacturing a GAA FET semiconductor device according to embodiments of the present disclosure are shown.

[0016] Figure 10 A cross-sectional view is shown of one of the various stages of manufacturing a GAA FET semiconductor device according to an embodiment of the present disclosure.

[0017] Figure 11 A cross-sectional view is shown of one of the various stages of manufacturing a GAA FET semiconductor device according to an embodiment of the present disclosure.

[0018] Figure 12 A cross-sectional view is shown of one of the various stages of manufacturing a GAA FET semiconductor device according to an embodiment of the present disclosure.

[0019] Figure 13 A cross-sectional view is shown of one of the various stages of manufacturing a GAA FET semiconductor device according to an embodiment of the present disclosure.

[0020] Figure 14 A cross-sectional view is shown of one of the various stages of manufacturing a GAA FET semiconductor device according to an embodiment of the present disclosure.

[0021] Figure 15 A cross-sectional view is shown of one of the various stages of manufacturing a GAA FET semiconductor device according to an embodiment of the present disclosure.

[0022] Figure 16 A cross-sectional view is shown of one of the various stages of manufacturing a GAA FET semiconductor device according to an embodiment of the present disclosure.

[0023] Figure 17 A cross-sectional view is shown of one of the various stages of manufacturing a GAA FET semiconductor device according to an embodiment of the present disclosure.

[0024] Figure 18 A cross-sectional view is shown of one of the various stages of manufacturing a GAA FET semiconductor device according to an embodiment of the present disclosure.

[0025] Figure 19 A cross-sectional view is shown of one of the various stages of manufacturing a GAA FET semiconductor device according to an embodiment of the present disclosure.

[0026] Figure 20 A cross-sectional view is shown of one of the various stages of manufacturing a GAA FET semiconductor device according to an embodiment of the present disclosure.

[0027] Figure 21 A cross-sectional view is shown of one of the various stages of manufacturing a GAA FET semiconductor device according to an embodiment of the present disclosure.

[0028] Figure 22 A cross-sectional view is shown of one of the various stages of manufacturing a GAA FET semiconductor device according to an embodiment of the present disclosure.

[0029] Figure 23 A cross-sectional view is shown of one of the various stages of manufacturing a GAA FET semiconductor device according to an embodiment of the present disclosure.

[0030] Figure 24 A cross-sectional view is shown of one of the various stages of manufacturing a GAA FET semiconductor device according to an embodiment of the present disclosure.

[0031] Figure 25 A cross-sectional view is shown of one of the various stages of manufacturing a GAA FET semiconductor device according to an embodiment of the present disclosure.

[0032] Figure 26A A schematic outline of the source / drain regions prior to ion processing operations according to embodiments of the present disclosure is shown. Figure 26B , Figure 26C , Figure 26D , Figure 26E , Figure 26F , Figure 26G , Figure 26H and Figure 26IA schematic outline of the source / drain regions after an ion processing operation is shown according to an embodiment of the present disclosure.

[0033] Figure 27 A cross-sectional view is shown of one of the various stages of manufacturing a GAA FET semiconductor device according to an embodiment of the present disclosure.

[0034] Figure 28 A cross-sectional view is shown of one of the various stages of manufacturing a GAA FET semiconductor device according to an embodiment of the present disclosure.

[0035] Figure 29 A cross-sectional view is shown of one of the various stages of manufacturing a GAA FET semiconductor device according to an embodiment of the present disclosure.

[0036] Figure 30 A cross-sectional view is shown of one of the various stages of manufacturing a GAA FET semiconductor device according to an embodiment of the present disclosure.

[0037] Figure 31 A cross-sectional view is shown of one of the various stages of manufacturing a GAA FET semiconductor device according to an embodiment of the present disclosure.

[0038] Figure 32 A cross-sectional view is shown of one of the various stages of manufacturing a GAA FET semiconductor device according to an embodiment of the present disclosure.

[0039] Figure 33 A cross-sectional view is shown of one of the various stages of manufacturing a GAA FET semiconductor device according to an embodiment of the present disclosure.

[0040] Figure 34 A cross-sectional view is shown of one of the various stages of manufacturing a GAA FET semiconductor device according to an embodiment of the present disclosure.

[0041] Figure 35 A detailed cross-sectional view of one of the various stages of manufacturing a GAA FET semiconductor device according to an embodiment of the present disclosure is shown.

[0042] Figure 36 A cross-sectional view is shown of one of the various stages of manufacturing a GAA FET semiconductor device according to an embodiment of the present disclosure.

[0043] Figure 37 A cross-sectional view is shown of one of the various stages of manufacturing a GAA FET semiconductor device according to an embodiment of the present disclosure.

[0044] Figure 38 A cross-sectional view is shown of one of the various stages of manufacturing a GAA FET semiconductor device according to an embodiment of the present disclosure.

[0045] Figure 39 A cross-sectional view is shown of one of the various stages of manufacturing a GAA FET semiconductor device according to an embodiment of the present disclosure.

[0046] Figure 40 A cross-sectional view is shown of one of the various stages of manufacturing a GAA FET semiconductor device according to an embodiment of the present disclosure.

[0047] Figure 41 A schematic plan view of a semiconductor device according to an embodiment of the present disclosure is shown.

[0048] Figure 42 A cross-sectional view of a semiconductor device according to an embodiment of the present disclosure is shown.

[0049] Figure 43 A cross-sectional view of a semiconductor device according to an embodiment of the present disclosure is shown.

[0050] Figure 44 A flowchart illustrating a method for manufacturing a semiconductor device according to an embodiment of the present disclosure is shown.

[0051] Figure 45 A flowchart illustrating a method for manufacturing a semiconductor device according to an embodiment of the present disclosure is shown.

[0052] Figure 46 A flowchart illustrating a method for manufacturing a semiconductor device according to an embodiment of the present disclosure is shown. Detailed Implementation

[0053] It should be understood that the following disclosure provides many different embodiments or instances for implementing various features of the embodiments of this disclosure. Specific embodiments or instances of components and arrangements are described below to simplify the embodiments of this disclosure. Of course, these are merely examples and are not intended to be limiting. For example, the dimensions of elements are not limited to the disclosed range or values, but may depend on process conditions and / or desired characteristics of the device. Furthermore, in the following description, forming a first component on or above a second component may include embodiments where the first and second components are in direct contact, and may also include embodiments where one or more additional components may be formed between the first and second components, such that the first and second components are not in direct contact. For simplicity and clarity, the various components may be drawn at any scale.

[0054] Furthermore, for ease of description, this document may use spatial relative terms such as “below,” “under,” “lower,” “above,” and “upper” to describe the relationship between one element or component and another (or other elements or components) as shown in the figures. In addition to the orientations depicted in the figures, spatial relative terms are intended to include different orientations of the device in use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein may be interpreted accordingly. Furthermore, the term “made of” may mean either “comprising” or “consisting of.”

[0055] Furthermore, in the following manufacturing processes, one or more additional operations may exist between the described operations, and the order of operations may be changed. In embodiments of this disclosure, the phrase "one of A, B, and C" means "A, B, and / or C" (A, B, C, A and B, A and C, B and C, or A, B, and C), and does not mean an element from A, an element from B, and an element from C, unless otherwise described. Throughout the disclosure, source and drain are used interchangeably, and source / drain refers to one or both of the source and drain. A source / drain configuration may refer to either a source or a drain, individually or jointly, depending on the context. In the following embodiments, materials, configurations, dimensions, processes, and / or operations as described with respect to one embodiment (e.g., one or more figures) may be employed, and their detailed descriptions may be omitted.

[0056] The disclosed embodiments relate to semiconductor devices, particularly full-ring gate field-effect transistors (GAA FETs) and stacked channel FETs with back-side vias or super power rails, and methods for fabricating them.

[0057] As semiconductor devices shrink in size, the spacing for back-side vias becomes smaller, which increases the contact resistance of the back-side contacts. In embodiments of this disclosure, back-side via contacts and feedthrough vias with reduced resistivity are provided. Therefore, embodiments of this disclosure provide semiconductor devices that can operate at higher power with increased efficiency.

[0058] Figures 1 to 25 This is a schematic illustration showing the various stages of manufacturing a semiconductor FET device according to embodiments of the present disclosure. It should be understood that... Figures 1 to 25 Additional operations are provided before, during, and after the process shown, and some of the operations described below may be replaced or eliminated for additional embodiments of the method. The order of operations / processes may be interchangeable.

[0059] like Figure 1As shown, a first semiconductor layer 20 and a second semiconductor layer 25 are alternately formed over a substrate 10. The first semiconductor layer 20 and the second semiconductor layer 25 are made of materials with different lattice constants and may include one or more layers of Si, Ge, SiGe, GaAs, InSb, GaP, GaSb, InAlAs, InGaAs, GaSbP, GaAsSb, or InP.

[0060] In some embodiments, the first semiconductor layer 20 and the second semiconductor layer 25 are made of Si, a Si compound, SiGe, Ge, or a Ge compound. In some embodiments, the first semiconductor layer 20 is made of Si. 1-x Ge x It is fabricated such that x is equal to or greater than about 0.1 and equal to or less than about 0.6, and the second semiconductor layer 25 is Si or Si 1-y Ge y , where y is less than x and equal to or less than about 0.2. In embodiments of this disclosure, "M compound" or "M-based compound" means that the majority of the compound is M.

[0061] In other embodiments, the second semiconductor layer 25 is made of Si 1-x Ge x Fabricated where x is equal to or greater than about 0.1 and equal to or less than about 0.6, and the first semiconductor layer 20 is made of Si or Si 1-y Ge y It is made such that y is less than x and equal to or less than about 0.2.

[0062] In some embodiments, the second semiconductor layer 25 is made of the same material as the semiconductor substrate 10.

[0063] In some embodiments, the thickness of the semiconductor layer 25 in the Z direction ranges from about 5 nm to about 60 nm, and the width of the semiconductor layer 25 in the Y direction ranges from about 5 nm to about 80 nm. In some embodiments, the width of the semiconductor layer is greater than its thickness. In some embodiments, the width is up to two or five times the thickness of the semiconductor nanostructure 25.

[0064] In some embodiments, substrate 10 includes a single-crystal semiconductor layer at least on its surface portion. Substrate 10 may include single-crystal semiconductor materials such as, but not limited to, Si, Ge, SiGe, GaAs, InSb, GaP, GaSb, InAlAs, InGaAs, GaSbP, GaAsSb, and InP. Substrate 10 may include various regions that have been appropriately doped with impurities (e.g., p-type or n-type conductivity). In some embodiments, the dopant is, for example, boron difluoride (BF2) for n-type FETs and phosphorus for p-type FETs. In some embodiments, substrate 10 is made of crystalline silicon.

[0065] Substrate 10 may include one or more buffer layers (not shown) in its surface region. The buffer layers can be used to gradually change the lattice constant from that of the substrate to the lattice constant of the source / drain structure. The buffer layers may be formed from epitaxially grown single-crystal semiconductor materials, such as, but not limited to, Si, Ge, GeSn, SiGe, GaAs, InSb, GaP, GaSb, InAlAs, InGaAs, GaSbP, GaAsSb, GaN, GaP, and InP. In a particular embodiment, substrate 10 includes a silicon-germanium (SiGe) buffer layer epitaxially grown on silicon substrate 10. The germanium concentration of the SiGe buffer layer can be increased from 30 atomic% germanium for the bottom buffer layer to 70 atomic% germanium for the top buffer layer.

[0066] The first semiconductor layer 20 and the second semiconductor layer 25 may be formed by one or more epitaxial or epitaxial (epi) processes. Epitaxial processes include chemical vapor deposition (CVD) deposition techniques (e.g., vapor phase epitaxy (VPE) and / or ultra-high vacuum CVD (UHV-CVD)), molecular beam epitaxy, and / or other suitable processes.

[0067] A first semiconductor layer 20 and a second semiconductor layer 25 are alternately epitaxially formed over a substrate 10. The thickness of the first semiconductor layer 20 may be equal to or greater than the thickness of the second semiconductor layer 25, and in some embodiments ranges from about 3 nm to about 30 nm, and in other embodiments ranges from about 4 nm to about 15 nm. The thickness of the second semiconductor layer 25 ranges from about 3 nm to about 30 nm in some embodiments, and in other embodiments ranges from about 4 nm to about 15 nm. The thickness of the first semiconductor layer 20 may be the same as or different from the thickness of the second semiconductor layer 25. Although in Figure 1 The diagram shows three first semiconductor layers 20 and three second semiconductor layers 25, but the number is not limited to three and can be one, two, or more than three and less than twenty. In some embodiments, the number of first semiconductor layers 20 is one greater than the number of second semiconductor layers 25 (i.e., the top and bottom layers are first semiconductor layers).

[0068] In some embodiments, an etch stop layer 115 is formed in the substrate 10 before the formation of the first semiconductor layer 20 and the second semiconductor layer 25. The etch stop layer 115 may be made of a semiconductor material having a different etch selectivity than the substrate 10. For example, if the substrate 10 is a silicon substrate, the etch stop layer 115 may be made of SiGe.

[0069] After forming the stacked semiconductor layers, the fin structure 29 is formed using one or more photolithography and etching operations, such as... Figure 2A and Figure 2B As shown. In Figures 2A to 12 The structure is shown above the etch stop layer 115 for simplification. The fin structure can be patterned using any suitable method. For example, the fin structure can be patterned using one or more photolithography processes, including dual-patterning or multi-patterning processes. Typically, dual-patterning or multi-patterning processes combine photolithography and self-alignment processes, allowing the creation of patterns with a pitch, for example, smaller than that achievable using a single, direct photolithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a photolithography process. Spacers are formed alongside the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers can then be used to pattern the fin structure.

[0070] like Figure 2A As shown, fin structure 29 extends in the X direction and is arranged in the Y direction. The number of fin structures is not limited to... Figure 2A The two shown can be as small as one and three or more (as shown in the image). Figure 2B (As shown in the diagram). In some embodiments, one or more pseudo-fin structures are formed on both sides of the fin structure 29 to improve pattern fidelity during patterning operations. Figure 2A As shown, the fin structure 29 has an upper portion (mesa structure) consisting of stacked semiconductor layers 20, 25 and a well portion 11.

[0071] The width of the upper portion of the fin structure 29 along the Y direction ranges from about 5 nm to about 80 nm in some embodiments, and from about 10 nm to about 40 nm in other embodiments.

[0072] In some embodiments, after forming the fin structure 29, an insulating material layer comprising one or more layers of insulating material is formed over the substrate, such that the fin structure is completely embedded in the insulating layer. The insulating material used for the insulating layer may include silicon oxide, silicon nitride, silicon oxynitride (SiON), SiOCN, SiCN, fluorine-doped silicate glass (FSG), or a low-k dielectric material formed by low-pressure CVD (LPCVD), plasma-enhanced CVD (PECVD), or flowable CVD (FCVD). An annealing operation may be performed after forming the insulating layer. Then, planarization operations, such as chemical mechanical polishing (CMP) and / or etching-back methods, are performed to expose the upper surface of the uppermost second semiconductor layer 25 from the insulating material layer.

[0073] Then, as Figure 2A As shown, the insulating material layer is recessed to form an insulating layer 15, exposing the upper portion of the fin structure 29. Using this operation, the fin structures 29 are separated from each other by the insulating layer 15, also known as shallow trench isolation (STI). The insulating layer 15 can be made of: suitable dielectric materials, such as silicon oxide, silicon nitride, silicon oxynitride, fluorine-doped silicate glass (FSG); low-k dielectrics, such as carbon-doped oxides; very low-k dielectrics, such as porous carbon-doped silicon dioxide; polymers, such as polyimide; combinations of these, etc. In some embodiments, the insulating layer 15 is formed by a process such as CVD, FCVD, or spin-coating glass, but any acceptable process can be used.

[0074] In some embodiments, the insulating layer 15 is recessed until the upper portion of the fin structure (well layer) 11 is exposed. In some embodiments, the insulating layer 15 is recessed below the lowermost first semiconductor layer 20, exposing a portion of the fin structure. In other embodiments, the upper portion of the fin structure 11 is not exposed, and in some embodiments, the insulating layer 15 is recessed to the level of the interface between the first semiconductor layer 20 and the fin structure 11. The first semiconductor layer 20 is a sacrificial layer that is subsequently partially removed, and the second semiconductor layer 25 is subsequently formed as a semiconductor line, nanostructure, or nanosheet as the channel layer of the GAA FET. In other embodiments, the second semiconductor layer 25 is a sacrificial layer that is subsequently partially removed, and the first semiconductor layer 20 is subsequently formed as a semiconductor line, nanostructure, or nanosheet as the channel layer.

[0075] Figure 2B This is an isometric view showing a plurality of fin structures 29 separated by shallow trench isolation 15 after a sacrificial gate dielectric layer 41 is formed above fin structure 29 and above shallow trench isolation 15.

[0076] After the isolation insulating layer 15 is formed, one or more sacrificial (pseudo) gate structures 40 are formed. Figure 3Aand Figure 3B The structure is shown after one or more sacrificial gate structures 40 are formed above the exposed fin structure 29. Figure 3B This is an isometric view of the structure. A sacrificial gate structure 40 is formed over a portion of the fin structure 29 that will become the channel region. The sacrificial gate structure 40 defines the channel region of the GAA FET. The sacrificial gate structure 40 includes a sacrificial gate dielectric layer 41 and a sacrificial gate electrode layer 42. The sacrificial gate dielectric layer 41 includes one or more layers of insulating material, such as a silicon oxide-based material. In one embodiment, silicon oxide formed by CVD is used as the sacrificial gate dielectric layer. The thickness of the sacrificial gate dielectric layer 41 ranges from about 1 nm to about 5 nm in some embodiments.

[0077] The sacrificial gate structure 40 is formed by first blanket-depositing a sacrificial gate dielectric layer 41 over the fin structure 29. In some embodiments, a sacrificial gate electrode layer 42 is then blanket-deposited on the sacrificial gate dielectric layer and over the fin structure, such that the fin structure is fully embedded in the sacrificial gate electrode layer. In some embodiments, the sacrificial gate electrode layer 42 comprises silicon, such as polycrystalline silicon or amorphous silicon. The thickness of the sacrificial gate electrode layer ranges from about 100 nm to about 200 nm in some embodiments. In some embodiments, the sacrificial gate electrode layer undergoes a planarization operation. The sacrificial gate dielectric layer and the sacrificial gate electrode layer are deposited using CVD (including LPCVD and PECVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or other suitable processes. Subsequently, a mask layer is formed over the sacrificial gate electrode layer. In some embodiments, the mask layer comprises a silicon nitride pad layer 43 and a silicon oxide mask layer 44.

[0078] Next, a patterning operation is performed on the mask layer, and the sacrificial gate electrode layer is patterned into a sacrificial gate structure 40, such as... Figure 3A and Figure 3B As shown in the illustration. In an embodiment, the sacrificial gate structure includes a sacrificial gate dielectric layer 41, a sacrificial gate electrode layer 42 (e.g., polysilicon), a pad silicon nitride layer 43, and a silicon oxide mask layer 44. By patterning the sacrificial gate structure, a stacked layer of the first semiconductor layer and the second semiconductor layer is partially exposed on opposite sides of the sacrificial gate structure, thereby defining source / drain regions, as shown in the illustration. Figure 3A and Figure 3B As shown in the figure. In some embodiments, a sacrificial gate structure is formed over one or more fin structures, but the number of sacrificial gate structures for each fin structure is not limited to one. Two or more sacrificial gate structures are arranged in the X direction in some embodiments. In some embodiments, one or more dummy sacrificial gate structures are formed on both sides of the sacrificial gate structure to improve pattern fidelity.

[0079] After forming the sacrificial gate structure 40, a first capping layer 45 for gate sidewall spacers is formed above the sacrificial gate structure 40, such as... Figure 4 As shown in the diagram. In some embodiments, the first capping layer 45 is deposited conformally such that it is formed to have substantially equal thicknesses on the vertical surfaces (such as sidewalls), horizontal surfaces, and top of the sacrificial gate structure, respectively. In some embodiments, the first capping layer 45 has a thickness ranging from about 5 nm to about 20 nm. The first capping layer 45 comprises one or more of silicon nitride, silicon oxide, SiON, SiCN, SiCO, SiOCN, or any other suitable dielectric material. The capping layer 45 can be formed by ALD or CVD or any other suitable method. In some embodiments, one or more additional capping layers are formed over the first capping layer to form a multilayer gate sidewall spacer.

[0080] Next step, such as Figure 5 As shown, the first capping layer 45 is anisotropically etched to remove the first capping layer 45 disposed on the source / drain region, while leaving the first capping layer 45 as a sidewall spacer on the side of the sacrificial gate structure 40. Figure 5 A cross-sectional view along the X direction is shown. Then, by using one or more photolithography and etching operations, a stacked structure of the first semiconductor layer 20 and the second semiconductor layer 25 is etched downwards at the source / drain regions to form the source / drain spacing 21. In some embodiments, the substrate 10 (or the bottom portion of the fin structure 11) is also partially etched to form a mesa structure. In some embodiments, n-type FETs and p-type FETs are fabricated separately, and in such cases, the regions for one type of FET are processed, while the regions for the other type of FET are covered by a protective layer such as a silicon nitride layer. In some embodiments, as... Figure 5 As shown, the recessed fin structure has a U-shape. In other embodiments, the recessed fin structure has a V-shape that shows the (111) facets of the silicon crystal. In other embodiments, the groove has an inverted trapezoidal or rectangular shape.

[0081] In some embodiments, the grooves are formed by a dry etching process, which can be anisotropic. Anisotropic etching processes can be implemented using a mixture of process gases including BF2, Cl2, CH3F, CH4, HBr, O2, Ar, and other etchant gases. The process gases can be activated into plasma by any suitable method of generating plasma, such as transformer-coupled plasma (TCP) systems, inductively coupled plasma (ICP) systems, or magnetically enhanced reactive ion technology. In some embodiments, the plasma is a remote plasma generated in a separate plasma generation chamber connected to the processing chamber. The process gases used in the plasma etching process include etchant gases such as H2, Ar, other gases, or combinations of gases. In some embodiments, a carrier gas such as N2, Ar, He, or Xe is combined with the plasma etching process gas using hydrogen (H) radicals. H radicals can be formed by infusing H2 gas into the plasma generation chamber and igniting the plasma within the plasma generation chamber. In some embodiments, additional gases, such as Ar, can be ignited into plasma within the plasma generation chamber. The H radicals can selectively etch the (100) plane relative to either the (111) or (110) plane. In some cases, the etching rate of the (100) plane is about three times greater than that of the (111) plane. Due to this selectivity, during the second patterning process, etching by H radicals may tend to slow down or stop along the (111) or (110) plane of silicon.

[0082] In addition, such as Figure 6 As shown, a first semiconductor layer 20 is laterally etched in the X direction within the source / drain spacing 21 to form a cavity 22. When the first semiconductor layer 20 is SiGe and the second semiconductor layer 25 is Si, the first semiconductor layer 20 can be selectively etched using a wet etchant such as, but not limited to, a mixed solution of H2O2, CH3COOH, and HF, followed by H2O cleaning. In some embodiments, the etching with the mixed solution and the cleaning with water are repeated 10 to 20 times. The etching time with the mixed solution ranges from about 1 minute to about 2 minutes in some embodiments. The mixed solution is used in some embodiments at a temperature ranging from about 60°C to about 90°C. In some embodiments, other etchants are used.

[0083] In some embodiments, cavity 22 has a curved end shape (transverse U-shaped cross section) protruding toward the first semiconductor layer 20. In other embodiments, cavity 22 has a transverse V-shaped cross section having a vertex at the first semiconductor layer 20.

[0084] Next step, such as Figure 7As shown, a first insulating layer 30 is formed on the etched lateral ends of the first semiconductor layer 20 and the end faces of the second semiconductor layer 25 in the source / drain spacing 21, and over the sacrificial gate structure 40. In some embodiments, the first insulating layer 30 is conformally formed such that a gap is left in the source / drain spacing 21. In some embodiments, the first insulating layer 30 comprises one of silicon nitride (including SiN and Si3N4), silicon oxide (including SiO and SiO2), SiON, SiOC, SiCN, and SiOCN, or any other suitable dielectric material. In some embodiments, the first insulating layer 30 is made of a different material than the sidewall spacer (first cover layer) 45, and in other embodiments, it is made of the same material as the sidewall spacer 45. The first insulating layer 30 can be formed by ALD or any other suitable method. In some embodiments, by forming the first insulating layer 30, the cavity 22 is completely filled with the first insulating layer 30.

[0085] After the first insulating layer 30 is formed, an etching operation is performed to partially remove the first insulating layer 30, thereby forming the internal spacer 35, such as Figure 8 As shown in the diagram. In some embodiments, the end face of the inner spacer 35 is recessed more than the end face of the second semiconductor layer 25. The recess amount ranges from about 0.2 nm to about 3 nm, and in other embodiments from about 0.5 nm to about 2 nm. In other embodiments, the recess amount is less than 0.5 nm and may be equal to zero (i.e., the end face of the inner spacer 35 and the end face of the second semiconductor layer 25 are flush with each other). In some embodiments, an additional insulating layer having a thickness smaller than that of the first insulating layer 30 is formed before the first insulating layer 30 is formed, and thus the inner spacer 35 has a two-layer structure. In some embodiments, the width (lateral length) of the inner spacer 35 is not constant.

[0086] In some embodiments, a bottom semiconductor layer 110 is formed at the bottom of the source / drain spacing 21, such as... Figure 9A As shown in the diagram. The bottom semiconductor layer 110 is an epitaxial layer in some embodiments. In some embodiments, the bottom semiconductor layer is made of SiGeB, SiP, SiAs, SiGe, or Si. The bottom semiconductor layer 110 may be doped or undoped.

[0087] In some embodiments, a bottom isolation layer or a flexible bottom isolation layer 105 is formed above the bottom semiconductor layer, such as... Figure 9AAs shown in the figure. In some embodiments, the bottom isolation layer 105 is made of SiC, LaO, aluminum oxide (including Al2O3), aluminum oxynitride (AlON), ZrO2, HfO2, silicon nitride (including Si3N4 and SiN), Si, ZnO, ZrN, ZrAlO, titanium oxide (including TiO2), tantalum oxide (including Ta2O5 and TaO), Zr, yttrium oxide (including Y2O3), TaCN, zirconium silicide (including ZrSi2 and ZrSi), SiOCN, SiOC, SiCN, hafnium silicide (including HfSi and HfSi2), and silicon oxide (including SiO2 and SiO). The bottom isolation layer 105 can be formed by CVD or PVD operations. In some embodiments, the bottom isolation layer 105 is formed by oxidizing the surface of the bottom semiconductor layer 110.

[0088] In some embodiments, after forming the bottom semiconductor layer 110 and / or the bottom isolation layer 105, in some embodiments, an end-face epitaxial layer 92 is formed on the lateral end face of the second semiconductor layer 25 and the exposed surface of the lower fin structure 11, such as... Figure 9B As shown in the figure. In some embodiments, the end-face epitaxial layer 92 includes Si doped with P or As for an n-type FET and Si doped with B for a p-type FET. In some embodiments, the dopant concentration of the end-face epitaxial layer 92 is higher than the dopant concentration of the second semiconductor layer 25. In some embodiments, the dopant concentration of the end-face epitaxial layer 92 gradually increases from the interface between the end-face epitaxial layer 92 and the second semiconductor layer 25 or the lower fin structure 11 to the source / drain spacing 21. In some embodiments, the thickness of the deposited end-face epitaxial layer 92 is in the range of about 1 nm to about 10 nm. In some embodiments, during the epitaxial formation of the end-face epitaxial layer 92, some of the dopant elements diffuse to a depth of about 0.5 nm to about 2 nm in the second semiconductor layer 25 or the lower fin structure 11.

[0089] In some embodiments, a source / drain structure 50 is formed in the source / drain spacing 21, such as Figure 9C As shown in the figure. The source / drain structure 50 includes one or more layers of SiC, SiP, SiAs, and / or SiCP for an n-type FET. In some embodiments, SiC or SiCP is used. In some embodiments, the source / drain structure 50 includes SiGe, SiGeSn, Ge, GeSn, and / or SiSn for a p-type FET. When SiGe is used, the Ge content is about 60 atomic% to about 80 atomic% in some embodiments. In some embodiments, the source / drain structure 50 is formed by an epitaxial process. In some embodiments, tensile stress is applied to the second semiconductor layer 25 for the n-type FET and compressive stress is applied to the second semiconductor layer 25 for the p-type FET. Figure 9Dyes Figure 9C Isometric view.

[0090] Then, an interlayer dielectric (ILD) layer 70 is formed over the source / drain structure 50 and the sacrificial gate structure 40. In some embodiments, a contact etch stop layer 68 is formed prior to the formation of the ILD layer 70. Next, the interlayer dielectric layer 70 is planarized by CMP to expose the sacrificial gate electrode layer 42, as shown below. Figure 10 As shown in the diagram. Materials used for the ILD layer 70 may include compounds comprising Si, O, C, and / or H, such as silicon oxide, SiCOH, and SiOC. Organic materials, such as polymers, including polyimides, may be used for the ILD layer 70. Materials used for the contact etch stop layer 68 may include silicon nitride, silicon oxide, SiCN, SiON, and SiOCN. In some embodiments, the materials used for the ILD layer 70 and the etch stop layer 68 are different from each other and therefore have different etch selectivity.

[0091] Then, as Figure 11 As shown, the sacrificial gate electrode layer 42 and the sacrificial gate dielectric layer 41 are removed to form a gate spacer 72. The ILD layer 70 protects the source / drain structure 50 during the removal of the sacrificial gate structure. The sacrificial gate structure can be removed using plasma dry etching and / or wet etching. When the sacrificial gate electrode layer 42 is polysilicon and the ILD 70 is silicon oxide, a wet etchant such as a TMAH solution can be used to selectively remove the sacrificial gate electrode layer 42. Subsequently, the sacrificial gate dielectric layer 41 can be removed using plasma dry etching and / or wet etching.

[0092] After removing the sacrificial gate structure, the first semiconductor layer 20 is removed, thereby forming nanosheets, nanowires, or nanostructures (channel regions) of a second semiconductor layer 25 stacked along the Z direction, such as... Figure 11 As shown in the diagram. The first semiconductor layer 20 can be removed or etched using an etchant that can selectively etch the first semiconductor layer 20 relative to the second semiconductor layer 25, as explained above. Because the internal spacer 35 has been previously formed, the etching of the first semiconductor layer 20 stops at the internal spacer 35. In other words, the internal spacer 35 can be used as an etch stop layer for etching the first semiconductor layer 20.

[0093] After forming the semiconductor nanowires or nanosheets (channel region) of the second semiconductor layer 25, a metal gate structure 80 is formed, such as... Figure 12 As shown in the image. Figure 12This is a cross-sectional view along the X direction. In some embodiments, the metal gate structure 80 includes a gate dielectric layer 82 disposed above the channel region 25, one or more power function adjustment layers 84 disposed above the gate dielectric layer 82, and a gate electrode layer 86 disposed above the power function adjustment layer 84 or the gate dielectric layer 82. In some embodiments, the structure and / or material of the gate electrode for an n-type GAA FET differs from the structure and / or material of the gate electrode for a p-type GAA FET.

[0094] In some embodiments, the gate dielectric layer 82 comprises one or more layers of dielectric material, such as silicon oxide, silicon nitride, or a high-k dielectric material, other suitable dielectric materials, and / or combinations thereof. High-k dielectric materials have a dielectric constant greater than that of silicon dioxide or greater than about 3.9. Examples of high-k dielectric materials include HfO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, zirconium oxide, aluminum oxide, titanium oxide, lanthanum oxide, hafnium dioxide-alumina (HfO2-Al2O3) alloys, other suitable high-k dielectric materials, and / or combinations thereof. In some embodiments, the gate dielectric layer 82 includes an interface layer 96 formed between the channel layer and the dielectric material. In some embodiments, the gate dielectric layer 82 has a higher dielectric constant than the internal spacer 35.

[0095] The gate dielectric layer 82 can be formed by CVD, ALD, or any suitable method. In one embodiment, the gate dielectric layer is formed using a highly conformal deposition process such as ALD to ensure that a gate dielectric layer with a uniform thickness is formed around each channel layer. The thickness of the gate dielectric layer 82 ranges from about 1 nm to about 6 nm in one embodiment.

[0096] In some embodiments, the metal gate structure includes one or more power function adjustment layers 84 disposed above the gate dielectric layer 82. In some embodiments, the power function adjustment layer 84 is made of a conductive material, such as a single layer of TiN, TaN, TaAlC, TiC, TaC, Co, Al, TiAl, HfTi, TiSi, TaSi, or TiAlC, or a multilayer of two or more of these materials. In some embodiments, one or more of TiAlC, Al, TiAl, TaN, TaAlC, TiN, TiC, and Co are used as the power function adjustment layer for a p-channel FET. According to some embodiments, for an n-channel FET, one or more of TaN, TaAlC, TiN, TiC, Co, TiAl, HfTi, TiSi, and TaSi are used as the power function adjustment layer. The power function adjustment layer can be formed by ALD, PVD, CVD, electron beam evaporation, or other suitable processes. Furthermore, the power function adjustment layer can be formed separately for both n-channel and p-channel FETs that can use different metal layers.

[0097] A gate electrode layer 86 is formed on a power function adjustment layer 84 (if present) or a gate dielectric layer 82 to surround each channel layer 25. In some embodiments, the gate electrode layer 86 comprises one or more layers of conductive material, such as polysilicon, aluminum, copper, titanium, tantalum, tungsten, cobalt, molybdenum, ruthenium, tantalum nitride, nickel silicide, cobalt silicide, TiN, WN, TiAl, TiAlN, TaCN, TaC, TaSiN, metal alloys, other suitable materials, and / or combinations thereof.

[0098] The gate electrode layer 86 can be formed by CVD, ALD, electroplating, or other suitable methods. In some embodiments, the gate electrode layer is also deposited above the upper surface of the ILD layer 70. The gate dielectric layer, power function adjustment layer, and gate electrode layer formed above the ILD layer 70 are then planarized by, for example, CMP until the top surface of the ILD layer 70 is exposed.

[0099] Although three nanosheets 25 are shown in each transistor, the number of nanosheets in each transistor ranges from about 2 to about 20 in some embodiments and from about 2 to about 10 in other embodiments. The drive current of the GAA FET device can be adjusted by changing the number of semiconductor nanostructures (nanowires, nanosheets, etc.).

[0100] In some embodiments, after the planarization operation, the gate electrode 86 is recessed, and a cap insulating layer 220 is formed over the recessed gate electrode 86, such as... Figure 13 As shown in the figure. In some embodiments, the cap insulating layer 220 comprises one or more layers of a silicon nitride-based material, such as silicon nitride. In some embodiments, the cap insulating layer 220 is formed by depositing an insulating material in a groove and a subsequent planarization operation. The cap insulating layer 220 can be deposited by any suitable deposition technique, including CVD, ALD, or PVD.

[0101] A front conductive contact 145 is formed over the source / drain region 50. The front conductive contact 145 is electrically connected to the source / drain region 50. In some embodiments, the front conductive contact 145 is formed by photolithography, etching, and material deposition techniques. In some embodiments, the front contact 145 is made of W, Ru, Co, Cu, Mo, combinations thereof, or any suitable conductive material. In some embodiments, a metal silicide layer 140 is formed to contact the source / drain region 50. In some embodiments, the metal silicide layer 140 is formed by depositing a metal layer over the source / drain region 50 and then heating the source / drain region 50 and the metal layer to react the metal with silicon in the source / drain region. The metal layer may include one or more of Ti, Mo, Ru, W, Rh, Nb, Ir, Y, Sb, Sc, Zr, Mo, Ni, and Co. The metal layer may be formed by any suitable technique including physical vapor deposition. In some embodiments, the metal silicide layer 140 includes TiSi, TiSi2, MoSi, MoSi2, YSi, WSi, WSi2, YSi2, ZrSi, ZrSi2, NbSi, NbSi2, Ru x Si y (where 1≤x≤5 and 1≤y≤5), Ni x Si y (where 1≤x≤31 and 1≤y≤12), one or more of RhSi, IrSi, SbSi, and ScSi. In other embodiments, the silicide layer is deposited over the sidewalls of the source / drain region 50 and the source / drain spacing 21 by CVD or metal-organic CVD (MOCVD).

[0102] In some embodiments, an upper dielectric pad layer 380 is formed above the sidewall of the etch stop layer 68 prior to the front conductive contact 145. The upper dielectric pad layer 380 may be a silicon nitride-based layer, such as silicon nitride, silicon oxynitride, or silicon carbonitride; or a silicon oxide-based material, such as silicon oxide, silicon carbonitride, or SiO2:F. The upper dielectric pad layer 380 may be formed by any suitable technique, including CVD, ALD, or PVD. In some embodiments, the upper dielectric pad layer 380 has a thickness ranging from about 0.5 nm to about 10 nm, and in other embodiments from about 1 nm to about 5 nm. At thicknesses below the disclosed range, the upper dielectric pad layer 380 may not provide sufficient protection, and at thicknesses above the disclosed range, the conductivity of the front conductive contact 145 may be compromised due to the reduced size of the front conductive contact.

[0103] In some embodiments, one or more interconnect wiring layers and vias or contacts are formed on the front side of the semiconductor device structure. For example, in some embodiments, via contacts 270 are formed to connect front-side conductive contacts to interconnect wiring 290. The via contacts 270 are formed in one or more interlayer dielectric layers 260, 265, such as... Figure 13 As shown in the diagram. Interconnect wiring 290 is formed in another dielectric layer 280 in some embodiments. In some embodiments, a conductive pad layer 285 is formed around wiring layer 290. In some embodiments, an upper conductive contact 305 is formed on interconnect wiring 295. The upper conductive contact is formed in an upper dielectric layer 300. A conductive pad layer 310 may be formed between the conductive contact 305 and the upper dielectric layer 300 and interconnect wiring 290. In some embodiments, etch stop layers 275 and 295 are formed between dielectric layers 265, 280, and 300. Dielectric layers 260, 265, and 300 may be made of any of the materials disclosed herein for forming interlayer dielectric layers. Etch stop layers 270 and 295 may be made of any of the materials disclosed herein for forming contact etch stop layers. In some embodiments, dielectric layers 265, 280, and 300 are made of a silicon oxide-based material, and etch stop layers 275 and 295 are made of a silicon nitride-based material. The conductive pad layers 285 and 310 can be made of any suitable conductive material. In some embodiments, the conductive pad layers 285 and 310 are made of titanium nitride or tantalum nitride. The through-hole contact 270, the interconnect wiring 290, and the upper conductive contact 305 can be made of any suitable conductive material. In some embodiments, the through-hole contact 270, the interconnect wiring 290, and the upper conductive contact 305 are independently made of W, Ru, Co, Cu, Mo, combinations thereof, or any suitable conductive material. The interconnect wiring / through-hole contact / upper conductive contact structure can be formed using suitable photolithography, etching, and deposition techniques.

[0104] Figures 14 to 25 This is a schematic illustration showing the various stages of forming a back-side via contact in a semiconductor FET device according to embodiments of the present disclosure. It should be understood that... Figures 14 to 25 Additional operations are provided before, during, and after the processes shown, and for additional embodiments of the method, some of the operations described below may be replaced or eliminated. The order of operations / processes may be interchangeable. It should be understood that some components of some embodiments may not be shown in each figure to simplify the diagram and to better illustrate other components of the disclosed embodiments.

[0105] like Figure 14As shown, the back side of the semiconductor device structure is thinned. The back side can be thinned by an etching operation or by CMP. In some embodiments, the back side is thinned down to the etch stop layer 115, and then the etch stop layer 115 is removed by a suitable etching technique.

[0106] In some embodiments, hard mask layers 120, 125 are formed above the back side of the semiconductor device structure, such as... Figure 15 As shown in the figure. In some embodiments, the hard mask layer includes a silicon oxide layer 125 formed over the silicon nitride layer 120 using a suitable deposition technique.

[0107] In some embodiments, the back side is thinned, and hard mask layers 120, 125 are formed above the back side of the semiconductor device structure before the interconnects / via contacts / overhead conductive structures are formed.

[0108] Then, a photoresist layer 315 is formed above the hard mask layers 120 and 125, such as... Figure 17 As shown in the figure. In some embodiments, the photoresist layer 315 is a three-layer resist, including an organic bottom layer 320, a silicon-containing intermediate layer 325, and a photosensitive upper layer 330. The photoresist layer 315 is patterned using a suitable photolithography technique to form openings 335 in the photoresist layer, and the openings 335 in the photoresist layer extend through the hard mask layers 125, 120 using a suitable etching technique and etchant.

[0109] In some embodiments, the photoresist layer 315 is removed using a suitable photoresist stripping operation or plasma ashing operation, and a wet cleaning operation is performed. Then, openings in the hard mask layers 120, 125 extend through the substrate 10, the bottom semiconductor layer 110, the flexible bottom isolation layer 105, and into the source / drain region 50 to form openings 155, such as... Figure 18 As shown in the figure. In some embodiments, a portion of the flexible bottom isolation layer 105 remains at the sidewall of the opening 155. In some embodiments, the flexible bottom isolation layer 105 is not etched during this etching operation and is etched in a subsequent etching operation. The opening 155 is formed using a suitable etching technique. The etching technique and etchant can vary depending on the layer being etched.

[0110] In some embodiments, a dielectric liner layer 130 is formed on the sidewall of the opening 155 and above the source / drain region 50 to form a sidewall dielectric layer, such as Figure 19As shown in the diagram. The dielectric pad layer 130 may be a silicon nitride-based layer; such as silicon nitride, silicon oxynitride, or silicon carbonitride; or a silicon oxide-based material, such as silicon oxide, silicon carbonitride, or SiO2:F. The dielectric pad layer 130 may be formed by any suitable technique, including CVD, ALD, or PVD. In some embodiments, the dielectric pad layer 130 has a thickness ranging from about 0.5 nm to about 10 nm, and in other embodiments, a thickness ranging from about 1 nm to about 5 nm. At thicknesses below the disclosed range, the dielectric pad layer 130 may not provide sufficient protection, and at thicknesses above the disclosed range, the conductivity of the conductive back-side via 160 discussed herein may be compromised due to the reduced size of the conductive back-side via.

[0111] In some embodiments, the dielectric sidewall layer 130 is then anisotropically etched to expose the source / drain region 50 and the hard mask layer 125, such as Figure 20 As shown in the figure. In some embodiments, the flexible bottom isolation layer 105 is not etched during the bottom semiconductor layer etching operation, but is etched during the dielectric sidewall layer etching operation.

[0112] An ion processing operation is then performed to introduce ions into the source / drain regions, including the corners of the source / drain regions. The corners (or epitaxial angles) of the source / drain regions are the edge portions of the source / drain regions that occur when the surface of the source / drain region has a concave shape. In some embodiments, the ion processing is performed via ion implantation 355, such as... Figure 21 As shown in the diagram. Ion implantation 355 can be angled implantation to implant ions in the epitaxial corner and / or any remaining portion of the flexible bottom isolation layer 105.

[0113] In some embodiments, ions or dopants are introduced into the source / drain region, including the epitaxial corner, via plasma processing 360, such as... Figure 22 As shown in the figure. In some embodiments, the plasma is an inductively coupled plasma. In some embodiments, the plasma treatment 360 is performed in the same chamber as the dielectric sidewall layer etching operation. In some embodiments, the plasma gas is one or more of argon, oxygen, nitrogen, ammonia, carbon dioxide, or water.

[0114] In some embodiments, the dopant implanted into the source / drain region 50 during ion implantation operation 355 includes at least one selected from He, Ne, Ar, Kr, Xe, Si, Ge, N, N2, O, P, As, Sn, B, BF2, or In. In some embodiments, ion implantation is performed at a temperature ranging from about 60°C to about 450°C. In some embodiments, depending on the implanted dopant, the ion treatment provides additional doping to the source / drain region 50, thereby improving the performance of the source / drain region 50. For example, performance can be improved by using n-type or p-type dopants (e.g., P, As, B, BF2, In). When doped with a p-type dopant, the n-type region can be masked, and when doped with an n-type dopant, the p-type region can be masked. On the other hand, when ion implantation is performed with N, N2, and O, the top portion (including the epitaxial corner) of the source / drain region can be converted into a dielectric material (e.g., SiO2). x SiO x N y When ion implantation is performed with other materials, the top portions (including the epitaxial corners) of the source / drain regions may become amorphous. During wafer loading into the wafer cassette and during transfer of the wafer cassette between different tools, the amorphous top portions may oxidize and form oxides, or, when the material used for ion implantation includes N, form nitrogen-containing oxides.

[0115] In some embodiments, the implanted dopant forms an ion-processed portion 340 of the source / drain region, such as Figure 23 As shown in the figure. In some embodiments, the dopant is in a concentration greater than 1 × 10⁻⁶. 20 cm -3 The concentration of the dopant is implanted into the doped region of the source / drain region 50. In some embodiments, the concentration of the dopant in the ion processing portion 340 of the source / drain region ranges from about 1 × 10⁻⁶. 19 cm -3 To approximately 1×10 21 cm -3 Furthermore, the concentration of the dopant in other embodiments ranges from approximately 5 × 10⁻⁶. 19 cm -3 Approximately 5×10 20 cm -3 Dopant can also be implanted into the hard mask layers 125, 120 during ion processing operations. Ion processing operations 355, 360, in some embodiments, transform or convert conductive exposed portions of the source / drain regions into dielectric ion-processed portions 340. For example... Figure 23As shown, a small portion of the source / drain region 50 is transformed into the dielectric layer 340. In some embodiments, the thickness of the dielectric ion treatment portion 340 ranges from about 0.5 nm to about 10 nm, and in other embodiments from about 1 nm to about 5 nm. At thicknesses below the disclosed range, a dielectric layer 340 of sufficient thickness may not be formed to significantly enhance device performance. At thicknesses above the disclosed range, too much source / drain region may be consumed, thereby impairing device performance.

[0116] The dielectric ion treatment portion 340 is then etched to expose the source / drain region 50. In some embodiments, damage to the source / drain region 50 caused by dopant implantation is repaired by an annealing operation.

[0117] In some embodiments, a back-side metal silicide layer 345 is formed over the source / drain region 50 in the opening 155, such as Figure 24 As shown in the diagram. The back-side metal silicide layer 345 can be formed using any of the techniques disclosed herein for forming the front-side metal silicide layer 140. In some embodiments, the back-side metal silicide layer 345 is formed by depositing a metal layer over the source / drain region 50. In some embodiments, the metal includes at least one of Ti, Mo, Ru, W, Rh, Nb, Ir, Y, Sb, Sc, Zr, Mo, Ni, or Co. The source / drain region 50 and the metal layer are then heated to react the source / drain region 50 and the metal layer to form the back-side metal silicide layer 345. In some embodiments, a wet cleaning operation is performed after the silicide layer formation operation.

[0118] In some embodiments, the surface of the ion processing portion 340 is located closer to the substrate than any portion of the source / drain region 50. In some embodiments, the surface of the ion processing portion 340 is located closer to the substrate 10 than any surface of the back-side metal silicide layer 345. In some embodiments, the surface of the back-side metal silicide layer 345 extends further vertically into the source / drain region 50 than any surface of the ion processing portion 340.

[0119] Then, a back-side through-hole contact 160 is subsequently formed in the opening 155, as follows: Figure 24As shown in the figure. In some embodiments, a conductive filler layer 160 is deposited in the opening 155 to fill the opening 155. In some embodiments, the conductive filler layer 160 is a metal filler layer 160. The conductive filler layer 160 can be formed by CVD, ALD, PVD, electroplating or other suitable methods to form a back-side via contact. In some embodiments, the back-side via contact 160 is formed of any of the materials used to form the front-side conductive contact 145. In some embodiments, the back-side via contact is made of W, Ru, Co, Rh, Cu, TiN, TaN or combinations thereof. In some embodiments, the back-side via contact 160 has a higher conductivity than the silicide layer 135 and a higher conductivity than the source / drain region 50. Excess back-side contact material and hard mask layers 120, 125 are then removed, and in some embodiments the back side is planarized by a CMP operation or an etch-back operation. In some embodiments, a portion of the hard mask layers 120, 125 is retained after the CMP or etch-back operation.

[0120] Figure 25 The location of the semiconductor device structure Figure 24 A detailed view of the portion within box A.

[0121] Figure 24 and Figure 25 The diagram illustrates a back-side via contact 160 (or super power rail structure); however, the semiconductor device according to embodiments of this disclosure is not limited to a single back-side via contact. The semiconductor device according to embodiments of this disclosure may include multiple back-side via contact structures.

[0122] Figure 26A The shape of the epitaxial angle before the ion treatment operation is shown. Figure 26A The concave shape of the source / drain region is shown. Figures 26B to 26I Various configurations following the ion processing operations disclosed herein are shown. These configurations are caused by variations in the parameters of the doping operation, including the implantation angle, the type of dopant, and the temperature of the doping operation. Figure 26B In the process, the upper portion of the epitaxial corner does not transform into a dielectric material, while the lower portion of the epitaxial corner does. Figure 26C In the process, the upper part of the epitaxial angle is converted into dielectric material, and the epitaxial angle becomes smaller on one side, while the lower part of the epitaxial angle is not converted into dielectric material. Figures 26D to 26I The various shapes of the epitaxial angle after doping are shown. Figure 26D In the middle, the depression becomes shallower, while... Figure 26E In the middle, the angle increases in size. Figures 26F to 26I In the middle, the angles become asymmetrical, with one of the extension angles becoming larger in size, while the relative extension angle becomes smaller.

[0123] Figures 27 to 35 This is a schematic illustration of the various stages of forming a back-side via contact in a semiconductor FET device according to other embodiments of the present disclosure. Figures 27 to 35 The operation shown is similar to Figures 17 to 25 The operation implemented in [the previous section] differs in that the structure does not include a flexible bottom insulating layer. It should be understood that [this can be achieved / performed]... Figures 27 to 35 Additional operations are provided before, during, and after the processes shown, and for additional embodiments of the method, some of the operations described below may be replaced or eliminated. The order of operations / processes may be interchangeable. It should be understood that some components of some embodiments may not be shown in each figure to simplify the diagram and to better illustrate other components of the disclosed embodiments.

[0124] Figure 27 Patterned photoresist layer 315 and hard mask layers 125, 120 are shown to form opening 335. The patterning operation is as described herein. Figure 17 The implementation is as described. Then, as Figure 28 As shown, the opening extends through the substrate 10 and the bottom semiconductor layer 110 to expose the source / drain regions, as referenced herein. Figure 18 As disclosed. In some embodiments, the edge portion of the bottom semiconductor layer 110 is retained along the opening sidewall. A dielectric sidewall layer 130 is then formed, as... Figure 29 As shown, and as referenced herein Figure 19 As disclosed. The dielectric sidewall layer 130 is anisotropically etched to expose the source / drain region 50 and the hard mask layer 125, as... Figure 30 As shown, and as referenced herein Figure 20 It has been made public. Figure 31 Ion implantation operation 355 is shown, as referenced herein. Figure 21 What is made public Figure 32 Plasma processing operation 360 is shown, as referenced herein. Figure 22 The disclosed method involves introducing dopant into the source / drain regions. In some embodiments, the dopant is also introduced into the remainder of the bottom semiconductor layer 110. In some embodiments, the implanted dopant forms ion-processed portions 340 of the source / drain regions, such as... Figure 33 As shown, and as referenced herein Figure 23As disclosed. In some embodiments, dopants are also implanted into the remainder of the bottom semiconductor layer 110, and the remainder of the bottom semiconductor layer 110, together with the upper portion of the source / drain region, is converted into a dielectric layer. In some embodiments, an ion processing operation is performed before the deposition of material for the sidewall dielectric layer 130 to convert the top portion of the source / drain region 50 into a dielectric layer (or ion-processed layer) 340. Then, a material layer for the sidewall dielectric layer 130 is deposited. Subsequently, the ion-processed layer 340 is etched to expose the source / drain region 50, and a back-side silicide layer 345 and conductive back-side via contacts 160 are formed, as shown. Figure 34 As shown, and as referenced herein Figure 24 It has been made public. Figure 35 The location of the semiconductor device structure Figure 34 A detailed view of the portion within box A.

[0125] In some embodiments, the surface of the ion processing portion 340 is located closer to the substrate than any portion of the source / drain region 50. In some embodiments, the surface of the ion processing portion 340 is located closer to the substrate 10 than any surface of the back-side metal silicide layer 345. In some embodiments, the surface of the back-side metal silicide layer 345 extends further vertically into the source / drain region 50 than any surface of the ion processing portion 340.

[0126] Figure 34 and Figure 35 The diagram illustrates a back-side via contact 160 (or super power rail structure); however, the semiconductor device according to embodiments of this disclosure is not limited to a single back-side via contact. The semiconductor device according to embodiments of this disclosure may include multiple back-side via contact structures.

[0127] Figures 36 to 40 This is a schematic illustration showing the various stages of forming a front-side via contact in a semiconductor FET device according to embodiments of the present disclosure. Figures 36 to 40 The operation shown is similar to the operation disclosed herein for forming a back-side through-hole contact. It should be understood that it is possible to... Figures 36 to 40 Additional operations are provided before, during, and after the processes shown, and for additional embodiments of the method, some of the operations described below may be replaced or eliminated. The order of operations / processes may be interchangeable. It should be understood that some components of some embodiments may not be shown in each figure to simplify the diagram and to better illustrate other components of the disclosed embodiments.

[0128] In some embodiments, an opening 385 is formed in the interlayer dielectric layer 70 to expose the source / drain region 50, such as Figure 36 As shown in some embodiments, for Figure 12The structure is designed to perform this operation. An ion treatment operation is performed to form an ion-treated region 365 in the upper surface of the source / drain region 50, such as... Figure 37 As shown in the figure. Ion treatment operations can be referenced in this article. Figure 21 , Figure 22 , Figure 31 or Figure 32 Any of the disclosed ion implantation or plasma treatment operations. The ion treatment region 365 is, in some embodiments, a dielectric layer.

[0129] Then, as Figure 38 As shown, an upper dielectric pad layer 380 is formed above the sidewall etch stop layer 68 and above the ion processing region 365. The upper dielectric pad layer 380 can be described herein with reference to... Figure 38 The material disclosed in the upper dielectric liner 380 formed in the middle and referenced herein are as follows: Figure 38 The upper dielectric pad layer 380 is formed using the disclosed technique. Then, the upper dielectric pad layer 380 and the ion-processed region 365 are isotropically etched to expose the source / drain region 50.

[0130] A front-side silicide layer 350 is formed above the exposed source / drain region 50, such as Figure 39 As shown herein, the front silicide layer 350 can be formed from any of the materials disclosed herein for forming the metal silicide layer 140 or the back silicide layer 345 and by any of the techniques disclosed herein for forming the metal silicide layer 140 or the back silicide layer 345, as referenced herein. Figure 13 and Figure 34 As disclosed. Then, a front conductive via 145 is formed above the front silicide layer 350 and the dielectric pad layer 380, as shown. Figure 40 As shown in the image.

[0131] In some embodiments, the surface of the front silicide layer 350 extends further in the vertical direction into the source / drain region 50 compared to any surface of the ion processing region 360.

[0132] Figure 41 A schematic plan view of the back side of a semiconductor device according to an embodiment of the present disclosure is shown. A back-side contact via 160 is aligned above the fin structure FS and located between the gate structures GS. The location of the front-side conductive contact 145 is shown between the gate structure GS pairs.

[0133] The embodiments of this disclosure are not limited to nanosheet transistor semiconductor devices. The methods and back-side via contact structures disclosed herein can be used in other semiconductor devices, such as other transistors. Embodiments of this disclosure include back-side via contact structures and methods for forming them in other GAA FETs, including forked FETs and complementary FETs (CFETs). Figure 42 This is a schematic cross-sectional view of a forked FET 225 according to an embodiment of the present disclosure. The forked FET is a GAA FET having dielectric walls 240 separating adjacent n-channel 235 and p-channel 230 devices. The dielectric walls 240 allow for closer spacing between devices, reduce parasitic capacitance, and enable higher performance, lower power consumption, and smaller cell size compared to nanosheet GAA FETs. Figure 43 This is a schematic cross-sectional view of a CFET 245 according to an embodiment of the present disclosure. A CFET is a GAA FET consisting of vertically stacked transistors with different conductivity types. For example, an n-type transistor 255 is stacked on top of a p-type transistor 250, and vice versa. Vertically stacking different transistor types enables increased transistor density and smaller devices.

[0134] Figure 44A flowchart of a method 4400 for manufacturing a semiconductor device according to an embodiment of the present disclosure is shown. The method includes operation S4405 of forming a fin structure 29 extending in a first direction above a first main surface of a substrate 10. The fin structure 29 includes a first semiconductor layer 20 and a second semiconductor layer 25 alternately stacked along a second direction intersecting the first direction. In operation S4410, a first source / drain (S / D) trench 21 and a second S / D trench 21 are formed in the fin structure 29. Then, in operation S4415, a first epitaxial layer 110 and a second epitaxial layer 110 are formed in the first S / D trench 21 and the second S / D trench 21, respectively. In operation S4420, a first S / D region 50 having a first conductivity and a second S / D region 50 having a second conductivity are formed above the first epitaxial layer 110 and the second epitaxial layer 110, respectively. In operation S4425, the first semiconductor layer 20 is removed. Then, in operation S4430, a gate structure is formed along the second semiconductor layer, wherein the gate structure extends upward in a third direction intersecting the first and second directions. In operation S4435, a first opening 155 is formed in the second main surface of the substrate 10 opposite to the first main surface to expose a portion of the first S / D region 50. In operation S4440, a first ion treatment 355, 360 is performed to convert the exposed portion of the first S / D region 55 into a bottom dielectric layer 340. In operation S4445, a portion of the bottom dielectric layer 340 is removed. Then, in operation S4450, a conductive material having a third conductivity is deposited in the first opening 155 to form an S / D via contact 160, wherein the third conductivity is greater than the first conductivity and the second conductivity. In some embodiments, in operation S4455, the first ion treatment includes an ion implantation operation 355. In some embodiments, in operation S4460, a first bottom isolation layer 105 is formed over the first epitaxial layer 110. In operation S4465, in some embodiments, a sidewall material layer 130 is formed in the first opening 155, above the sidewall of the first opening, and above the exposed first S / D region 155. Then, in operation S4470, a portion of the sidewall material layer 130 is etched to form a sidewall dielectric layer 130 and expose the first S / D region 50, wherein the etching of the portion of the sidewall material layer also removes a portion of the first bottom isolation layer 105. In operation S4475, hard mask layers 120, 125 are formed above the second main surface of the substrate, and in some embodiments, in operation S4480, the hard mask layers 120, 125, the substrate 10, and the first epitaxial layer 110 are etched. In some embodiments, in operation S4485, an interlayer dielectric (ILD) layer 260 is formed above the first S / D region 50 above the first main surface of the substrate 10. In operation S4490, a second opening 21 is formed extending through the ILD layer 260 and into the first S / D region 50.Then, in operation S4495, a second ion treatment 355, 360 is performed to convert the exposed portion of the first S / D region 50 in the second opening into a second dielectric layer 365. In operation S4497, a second conductive material is deposited in the second opening S21 to form an S / D contact 145.

[0135] Figure 45A flowchart of a method 4500 for manufacturing a semiconductor device according to an embodiment of the present disclosure is shown. The method for manufacturing a semiconductor device includes operation S4505 of forming a first channel region above a first main surface of a substrate 10. In operation S4510, a second channel region spaced apart from the first channel region along a first direction is formed above the first main surface. In operation S4515, a first epitaxial layer 110 is formed between the first channel region and the second channel region in the first main surface of the substrate. In operation S4520, a first source / drain region 50 having a first conductivity is formed above the first epitaxial layer. In operation S4525, a first gate structure 80 is subsequently formed above the first channel region, and a second gate structure is formed above the second channel region. The first gate structure and the second gate structure extend in a second direction intersecting the first direction. The first gate structure 80 and the second gate structure 80 include a gate electrode layer 86 disposed above a gate dielectric layer 82 having a first dielectric constant, and an insulating gate spacer 45 having a second dielectric constant disposed on the sidewall of the gate electrode layer 86, wherein the first dielectric constant is greater than the second dielectric constant. In operation S4530, an interlayer dielectric (ILD) layer is formed above the first source / drain region and the first and second gate structures. In operation S4535, a first opening 385 is formed in the second main surface of the substrate 10 opposite to the first main surface to expose a portion of the first source / drain region 50. In operation S4540, the exposed portion of the first source / drain region 50 is transformed into a front dielectric layer 340. Then, in operation S4545, a portion of the front dielectric layer 340 is removed to expose the first source / drain region 50. In operation S4550, a conductive material having a second conductivity is deposited in the first opening 155 to form a front-side conductive via 160, wherein the second conductivity is greater than the first conductivity. In some embodiments, changing the exposed portion of the first source / drain region includes operation S4555 of introducing a dopant into the first source / drain region. In operation S4560, the dopant is introduced by an ion implantation operation or a plasma treatment operation. In operation S4565, in some embodiments, a first bottom isolation layer 105 is formed over the first epitaxial layer 110 before forming the first source / drain region 50, wherein the first source / drain region 50 is formed over the first bottom isolation layer 105. In some embodiments, in operation S4570, a dielectric sidewall layer 130 is formed in the first opening 155, over the sidewalls of the first opening, and over the exposed first source / drain region 50.

[0136] Figure 46A flowchart of a method 4600 for manufacturing a semiconductor device according to an embodiment of the present disclosure is shown. The method for manufacturing a semiconductor device includes operation S4605 of forming a first stack of nanosheets 25 above a first main surface of a substrate 10. In operation S4610, a second stack of nanosheets 25 spaced apart from the first stack along a first direction is formed above the first main surface. Operation S4615 includes forming a first opening 21 in the first main surface between the first and second stacks. Then, operation S4620 includes forming a first semiconductor layer 110 in the first opening 21. In operation S4625, a first source / drain region 50 is formed over the first semiconductor layer 110. In operation S4630, a first gate structure 80 is subsequently formed over the first stack of nanosheets 25, and a second gate structure 80 is formed over the second stack of nanosheets 25, wherein the first gate structure and the second gate structure extend in a second direction intersecting the first direction. In operation S4635, a first interlayer dielectric layer 265 is formed over the first gate structure 80 and the second gate structure 80. In operation S4640, a first etch stop layer 270 is formed over the first interlayer dielectric layer 265. Then, in operation S4645, a second interlayer dielectric layer 280 is formed over the first etch stop layer 275. In operation S4650, an interconnect wiring layer 290 is formed in the second interlayer dielectric layer 280. In operation S4655, a second opening 155 is formed in the second main surface of the substrate 10 opposite to the first main surface to expose a portion of the first source / drain region 50. In operation S4660, a dopant is introduced through the second opening 155 into the exposed portion of the first source / drain region, wherein the introduced dopant transforms the exposed portion of the first source / drain region 50 into a dielectric layer 340. In operation S4665, the dielectric layer 340 is etched to expose the first source / drain region 50. In operation S4670, a conductive material 160 is deposited in the second opening 155. In some embodiments, in operation S4675, the second main surface of the substrate 10 is planarized. In operation S4680, an insulating layer 130 is formed over the sidewall of the second opening 155. In operation S4685, a dopant is introduced by ion implantation or plasma implantation.

[0137] Additional operations can be performed on the structure disclosed herein, such as forming additional insulating layers and metal wiring layers, including interconnects and vias formed over the disclosed structure. The disclosed structure may be part of a larger integrated circuit, including additional devices and components.

[0138] Embodiments of this disclosure provide back-side via contacts or super power rails with reduced contact resistance, thereby providing devices capable of operating with increased efficiency and at higher power. Embodiments of this disclosure reduce edge capacitance (Cgdh). Embodiments of this disclosure eliminate epitaxial corners. Embodiments of this disclosure convert epitaxial corners into dielectric material to reduce capacitance. Embodiments of this disclosure improve DC performance. Plasma processing that introduces dopant into the epitaxial corners can be performed in the same chamber as the etching operation. The disclosed methods provide a reliable and economical process for achieving epitaxial corner elimination and edge capacitance reduction.

[0139] It should be understood that not all advantages need to be discussed herein, no particular advantage is required for all embodiments or instances, and other embodiments or instances may provide different advantages.

[0140] Embodiments of this disclosure describe a method of manufacturing a semiconductor device, comprising forming a fin structure extending in a first direction above a first main surface of a substrate. The fin structure includes a first semiconductor layer and a second semiconductor layer alternately stacked along a second direction intersecting the first direction. A first source / drain (S / D) trench and a second S / D trench are formed in the fin structure. A first epitaxial layer and a second epitaxial layer are formed in the first S / D trench and the second S / D trench, respectively. A first S / D region having a first conductivity and a second S / D region having a second conductivity are formed above the first and second epitaxial layers, respectively. The first semiconductor layer is removed, and a gate structure is formed along the second semiconductor layer. The gate structure extends upward in a third direction intersecting the first and second directions. A first opening is formed in a second main surface of the substrate opposite to the first main surface to expose a portion of the first S / D region. A first ion treatment is performed to convert the exposed portion of the first source / drain region into a bottom dielectric layer. A portion of the bottom dielectric layer is removed to expose the first S / D region. A conductive material having a third conductivity is deposited in the first opening to form an S / D via contact. The third conductivity is greater than the first and second conductivity. In an embodiment, the first ion treatment includes an ion implantation operation. In an embodiment, the dopant implanted during the ion implantation operation includes at least one selected from He, Ne, Ar, Kr, Xe, Si, Ge, N, N2, O, P, As, Sn, B, BF2, or In. In an embodiment, the dopant is at a concentration greater than 1 × 10⁻⁶. 20 cm -3The method includes the following steps: In one embodiment, the method includes forming a first bottom isolation layer over a first epitaxial layer before forming a first S / D region, wherein the first S / D region is formed over the first bottom isolation layer. In another embodiment, the method includes forming a sidewall material layer in a first opening, over the sidewalls of the first opening, and over the exposed first S / D region before performing a first ion treatment. In another embodiment, the method includes etching a portion of the sidewall material layer to form a sidewall dielectric layer and expose the first S / D region, wherein the etching of the portion of the sidewall material layer also removes a portion of the first bottom isolation layer. In another embodiment, forming the first opening includes forming a hard mask layer over a second main surface of the substrate; and etching the hard mask layer, the substrate, and the first epitaxial layer. In one embodiment, the method includes: forming an interlayer dielectric (ILD) layer over a first S / D region above a first main surface of a substrate before forming a first opening; forming a second opening extending through the ILD layer and into the first S / D region; performing a second ion treatment to convert an exposed portion of the first S / D region in the second opening into a second dielectric layer; and depositing a second conductive material in the second opening to form an S / D contact. Another embodiment of this disclosure is a method of manufacturing a semiconductor device, including forming a first channel region above a first main surface of a substrate. A second channel region spaced apart from the first channel region along a first direction is formed above the first main surface. A first epitaxial layer is formed between the first channel region and the second channel region in the first main surface of the substrate. A first source / drain region having a first conductivity is formed over the first epitaxial layer. A first gate structure is formed over the first channel region, and a second gate structure is formed over the second channel region. The first gate structure and the second gate structure extend in a second direction intersecting the first direction. The first gate structure and the second gate structure include a gate electrode layer disposed above a gate dielectric layer having a first dielectric constant, and an insulating gate spacer having a second dielectric constant disposed on the sidewall of the gate electrode layer. The first dielectric constant is greater than the second dielectric constant. An interlayer dielectric (ILD) layer is formed above the first source / drain region and the first and second gate structures. A first opening is formed in the ILD layer above the first source / drain region to expose a portion of the first source / drain region. The exposed portion of the first source / drain region is transformed into a front-side dielectric layer. A portion of the front-side dielectric layer is removed to expose the first source / drain region. A conductive material having a second conductivity is deposited in the first opening to form a front-side conductive via, wherein the second conductivity is greater than the first conductivity. In an embodiment, transforming the exposed portion of the first source / drain region includes introducing a dopant into the first source / drain region. In an embodiment, the dopant is introduced by an ion implantation operation or a plasma processing operation. In the embodiments, the dopant includes at least one selected from He, Ne, Ar, Kr, Xe, Si, Ge, N, N2, O, P, As, Sn, B, BF2 or In.In one embodiment, the method includes forming a first bottom isolation layer over a first epitaxial layer before forming a first source / drain region, wherein the first source / drain region is formed over the first bottom isolation layer. In another embodiment, the method includes forming a dielectric sidewall layer in a first opening, over the sidewalls of the first opening, and over the exposed first source / drain region before converting the exposed portion of the first source / drain region into a front dielectric layer.

[0141] Another embodiment of this disclosure is a method of manufacturing a semiconductor device, comprising: forming a first stack of nanosheets above a first main surface of a substrate; and forming a second stack of nanosheets spaced apart from the first stack along a first direction above the first main surface. A first opening is formed in the first main surface between the first and second stacks. A first semiconductor layer is formed in the first opening. A first source / drain region is formed above the first semiconductor layer. A first gate structure is formed above the first stack of nanosheets, and a second gate structure is formed above the second stack of nanosheets, wherein the first and second gate structures extend in a second direction intersecting the first direction. A first interlayer dielectric layer is formed above the first and second gate structures. A first etch stop layer is formed above the first interlayer dielectric layer. A second interlayer dielectric layer is formed above the first etch stop layer. An interconnect wiring layer is formed in the second interlayer dielectric layer. A second opening is formed in the second main surface of the substrate opposite to the first main surface to expose a portion of the first source / drain region. A dopant is introduced into the exposed portion of the first source / drain region through a second opening, wherein the introduction of the dopant transforms the exposed portion of the first source / drain region into a dielectric layer. The dielectric layer is etched to expose the first source / drain region, and a conductive material is deposited in the second opening. In an embodiment, the method includes planarizing a second main surface of the substrate after depositing the conductive material. In an embodiment, the method includes forming an insulating layer above the sidewall of the first opening before introducing the dopant. In an embodiment, the dopant is introduced by ion implantation or plasma implantation. In an embodiment, the dopant is at least one selected from He, Ne, Ar, Kr, Xe, Si, Ge, N, N2, O, P, As, Sn, B, BF2, or In.

[0142] Another embodiment of this disclosure is a semiconductor device, comprising: a channel region extending in a first direction and disposed above a first main surface of a substrate; a gate structure disposed above the channel region and extending in a second direction intersecting the first direction; a first source / drain (S / D) region having a first conductivity and a second S / D region having a second conductivity, respectively, disposed in the substrate on opposite sides of the gate structure along the first direction, as seen in the cross-sectional view; a conductive contact having a third conductivity disposed between a second main surface of the substrate opposite the first main surface and the first source / drain region; and a silicide layer having a fourth conductivity disposed between the conductive contact and the first source / drain region. The third conductivity is greater than the first and second conductivity, and the fourth conductivity is greater than the first conductivity. A first insulating sidewall layer is disposed above the sidewall of the conductive contact, as seen in the cross-sectional view along the first direction. A first dielectric layer including a dopant is disposed between an insulating sidewall layer and a source / drain region along a third direction intersecting the first and second directions, wherein the surface of the first dielectric layer is located closer to the substrate than any portion of the silicide layer. In an embodiment, the dopant is at least one selected from He, Ne, Ar, Kr, Xe, Si, Ge, N, N2, O, P, As, Sn, B, BF2, or In. In an embodiment, the dopant has a dopant density greater than 1 × 10⁻⁶. 20 cm -3 The semiconductor device includes a silicide layer disposed between a conductive contact and a first source / drain region. In an embodiment, the semiconductor device includes a bottom isolation layer disposed between a first dielectric layer and an insulating sidewall layer. In an embodiment, the semiconductor device includes a first interlayer dielectric (ILD) layer disposed above a first S / D region above a first main surface of the substrate. In an embodiment, the semiconductor device includes a front conductive contact disposed between the first ILD layer and the first source / drain region. In an embodiment, the semiconductor device includes a second insulating sidewall layer disposed above the sidewall of the front conductive contact, as seen in a cross-sectional view along a first direction. In an embodiment, the semiconductor device includes a second dielectric layer disposed between a second insulating sidewall and the first source / drain region. In an embodiment, the semiconductor device includes a silicide layer disposed between the front conductive contact and the first source / drain region.

[0143] Another embodiment of this disclosure is a semiconductor device, comprising: a first channel region disposed above a first main surface of a substrate; and a second channel region disposed above the first main surface and spaced apart from the first channel region along a first direction. A first epitaxial layer is disposed between the first channel region and the second channel region in the first main surface of the substrate. A first source / drain region having a first conductivity is disposed above the first epitaxial layer. A first gate structure is disposed above the first channel region, and a second gate structure is disposed above the second channel region, wherein the first gate structure and the second gate structure extend in a second direction intersecting the first direction. The first gate structure and the second gate structure include a gate electrode layer disposed above a gate dielectric layer having a first dielectric constant, and an insulating gate spacer having a second dielectric constant disposed on a sidewall of the gate electrode layer, wherein the first dielectric constant is greater than the second dielectric constant. A back-side conductive contact is disposed between the second main surface of the substrate and the first source / drain region. A first doped dielectric layer including a dopant surrounding the back-side conductive contact is disposed above the first source / drain region, wherein the first doped dielectric layer is closer to the second main surface of the substrate than the first source / drain region. The dopant is greater than 1×10 20 cm -3 The concentration is selected from at least one of He, Ne, Ar, Kr, Xe, Si, Ge, N, N2, O, P, As, Sn, B, BF2, or In. In an embodiment, the semiconductor device includes a first bottom isolation layer surrounding a back-side conductive contact and disposed between a first epitaxial layer and a first source / drain region. In an embodiment, the semiconductor device includes an insulating sidewall layer disposed above the sidewalls of the back-side conductive contact, as seen in the cross-sectional view. In an embodiment, the semiconductor device includes a silicide layer disposed between the back-side conductive contact and the first source / drain region. In an embodiment, the semiconductor device includes a first interlayer dielectric (ILD) layer disposed above the first source / drain region above a first main surface of the substrate. In an embodiment, the semiconductor device includes a front-side conductive contact disposed between the first ILD layer and the first source / drain region.

[0144] Another embodiment of this disclosure is a semiconductor device, comprising: a first stack of nanosheets disposed above a first main surface of a substrate; and a second stack of nanosheets disposed above the first main surface and spaced apart from the first stack along a first direction. A first source / drain region is disposed between the first and second stacks of nanosheets. A first gate structure is disposed above the first stack of nanosheets, and a second gate structure is disposed above the second stack of nanosheets, wherein the first gate structure and the second gate structure extend in a second direction intersecting the first direction. A first interlayer dielectric layer is disposed above the first gate structure and the second gate structure. A first etch stop layer is disposed above the first interlayer dielectric layer. A second interlayer dielectric layer is disposed above the first etch stop layer. An interconnect wiring layer is disposed in the second interlayer dielectric layer. A first conductive contact is disposed between a second main surface of the substrate opposite to the first main surface and the first source / drain region. A doped dielectric layer including a dopant surrounds the first conductive contact and is disposed above the source / drain region. The dopant is greater than 1 × 10⁻⁶. 20 cm -3 The concentration is selected from at least one of He, Ne, Ar, Kr, Xe, Si, Ge, N, N2, O, P, As, Sn, B, BF2, or In. In an embodiment, the semiconductor device includes a silicide layer disposed between a first conductive contact and a first source / drain region. In an embodiment, the semiconductor device includes an insulating layer disposed above the sidewall of the first conductive contact, wherein a doped dielectric layer is disposed between the insulating layer and the first source / drain region. In an embodiment, the semiconductor device includes a front conductive contact disposed between a first main surface of the substrate and the first source / drain region. In an embodiment, the semiconductor device includes a second doped dielectric layer surrounding the front conductive contact and disposed above the first source / drain region.

[0145] Some embodiments of this application provide a method for manufacturing a semiconductor device, comprising: forming a fin structure extending in a first direction above a first main surface of a substrate, wherein the fin structure includes a first semiconductor layer and a second semiconductor layer alternately stacked along a second direction intersecting the first direction; forming a first source / drain trench and a second source / drain trench in the fin structure; forming a first epitaxial layer and a second epitaxial layer in the first source / drain trench and the second source / drain trench, respectively; forming a first source / drain region having a first conductivity and a second source / drain region having a second conductivity above the first epitaxial layer and the second epitaxial layer, respectively; removing the first source / drain region... A semiconductor layer; a gate structure is formed along the second semiconductor layer, wherein the gate structure extends upward in a third direction intersecting the first direction and the second direction; a first opening is formed in a second main surface of the substrate opposite to the first main surface to expose a portion of the first source / drain region; a first ion treatment is performed to convert the exposed portion of the first source / drain region into a bottom dielectric layer; a portion of the bottom dielectric layer is removed to expose the first source / drain region; and a conductive material having a third conductivity is deposited in the first opening to form a source / drain via contact, wherein the third conductivity is greater than the first conductivity and the second conductivity.

[0146] In some embodiments, the first ion treatment includes an ion implantation operation. In some embodiments, the dopant implanted during the ion implantation operation includes at least one selected from He, Ne, Ar, Kr, Xe, Si, Ge, N, N2, O, P, As, Sn, B, BF2, or In. In some embodiments, the dopant is at a concentration greater than 1 × 10⁻⁶. 20 cm -3The concentration of implantation. In some embodiments, the method further includes: forming a first bottom isolation layer over the first epitaxial layer before forming the first source / drain region, wherein the first source / drain region is formed over the first bottom isolation layer. In some embodiments, the method further includes forming a sidewall material layer in the first opening, over the sidewalls of the first opening, and over the exposed first source / drain region before performing the first ion treatment. In some embodiments, the method further includes etching a portion of the sidewall material layer to form a sidewall dielectric layer and expose the first source / drain region, wherein the etching of the portion of the sidewall material layer also removes a portion of the first bottom isolation layer. In some embodiments, forming the first opening further includes: forming a hard mask layer over the second main surface of the substrate; and etching the hard mask layer, the substrate, and the first epitaxial layer. In some embodiments, the method further includes: forming an interlayer dielectric layer over the first source / drain region above the first main surface of the substrate before forming the first opening; forming a second opening extending through the interlayer dielectric layer and into the first source / drain region; performing a second ion treatment to convert the exposed portion of the first source / drain region in the second opening into a second dielectric layer; and depositing a second conductive material in the second opening to form a source / drain contact.

[0147] Other embodiments of this application provide a method for manufacturing a semiconductor device, comprising: forming a first channel region above a first main surface of a substrate; forming a second channel region spaced apart from the first channel region along a first direction above the first main surface; forming a first epitaxial layer between the first channel region and the second channel region in the first main surface of the substrate; forming a first source / drain region having a first conductivity above the first epitaxial layer; forming a first gate structure above the first channel region and forming a second gate structure above the second channel region, wherein the first gate structure and the second gate structure extend in a second direction intersecting the first direction, and the first gate structure and the second gate structure include a first dielectric material. The method comprises: a gate electrode layer above a gate dielectric layer having a constant dielectric constant; an insulating gate spacer having a second dielectric constant disposed on the sidewall of the gate electrode layer, wherein the first dielectric constant is greater than the second dielectric constant; an interlayer dielectric layer being formed above the first source / drain region and the first gate structure and the second gate structure; a first opening being formed in the interlayer dielectric layer above the first source / drain region to expose a portion of the first source / drain region; the exposed portion of the first source / drain region being converted into a front-side dielectric layer; a portion of the front-side dielectric layer being removed to expose the first source / drain region; and a conductive material having a second conductivity being deposited in the first opening to form a front-side conductive via, wherein the second conductivity is greater than the first conductivity.

[0148] In some embodiments, transforming the exposed portion of the first source / drain region includes introducing a dopant into the first source / drain region. In some embodiments, the dopant is introduced by an ion implantation operation or a plasma treatment operation. In some embodiments, the dopant includes at least one selected from He, Ne, Ar, Kr, Xe, Si, Ge, N, N2, O, P, As, Sn, B, BF2, or In. In some embodiments, the method further includes forming a first bottom isolation layer over the first epitaxial layer before forming the first source / drain region, wherein the first source / drain region is formed over the first bottom isolation layer. In some embodiments, the method further includes forming a dielectric sidewall layer in the first opening, over the sidewall of the first opening, and over the exposed first source / drain region before transforming the exposed portion of the first source / drain region into the front dielectric layer.

[0149] Some embodiments of this application provide a semiconductor device, including: a channel region extending in a first direction and disposed above a first main surface of a substrate; a gate structure disposed above the channel region and extending in a second direction intersecting the first direction; a first source / drain region and a second source / drain region, each having a first conductivity and a second conductivity, disposed in the substrate on opposite sides of the gate structure along the first direction, as seen in the cross-sectional view; a conductive contact having a third conductivity, disposed between the second main surface of the substrate opposite the first main surface and the first source / drain region; and a silicide layer having a third conductivity. A third conductivity, disposed between the conductive contact and the first source / drain region, wherein the third conductivity is greater than the first conductivity, the second conductivity, and the fourth conductivity, and the fourth conductivity is greater than the first conductivity; a first insulating sidewall layer, disposed above the sidewall of the conductive contact, as seen in the cross-sectional view along the first direction; and a first dielectric layer, including a dopant, disposed between the insulating sidewall layer and the source / drain region along a third direction intersecting the first and second directions, wherein the surface of the first dielectric layer is located closer to the substrate than any portion of the silicide layer.

[0150] In some embodiments, the dopant is at least one selected from He, Ne, Ar, Kr, Xe, Si, Ge, N, N2, O, P, As, Sn, B, BF2, or In. In some embodiments, the dopant has a dopant concentration greater than 1 × 10⁻⁶. 20 cm -3 The concentration of implantation. In some embodiments, the semiconductor device further includes a silicide layer disposed between the conductive contact and the first source / drain region. In some embodiments, the semiconductor device further includes a bottom isolation layer disposed between the dielectric layer and the insulating sidewall layer.

[0151] The foregoing outlines features of several embodiments to enable those skilled in the art to better understand various aspects of the embodiments of this disclosure. Those skilled in the art should understand that they can readily use the embodiments of this disclosure as a basis to design or modify other processes and structures for performing the same purposes and / or achieving the same advantages as the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of the embodiments of this disclosure, and that various changes, substitutions, and alterations can be made therein without departing from the spirit and scope of the embodiments of this disclosure.

Claims

1. A method for manufacturing a semiconductor device, comprising: A fin structure extending in a first direction is formed above the first main surface of the substrate. The fin structure includes a first semiconductor layer and a second semiconductor layer that are alternately stacked along a second direction that intersects the first direction; A first source / drain trench and a second source / drain trench are formed in the fin structure; A first epitaxial layer and a second epitaxial layer are formed in the first source / drain trench and the second source / drain trench, respectively; A first source / drain region having a first conductivity and a second source / drain region having a second conductivity are respectively formed above the first epitaxial layer and the second epitaxial layer; Remove the first semiconductor layer; A gate structure is formed along the second semiconductor layer. The gate structure extends upward at a third direction intersecting the first and second directions. A first opening is formed in a second main surface of the substrate opposite to the first main surface to expose a portion of the first source / drain region; A first ion treatment is performed to convert the exposed portion of the first source / drain region into the bottom dielectric layer; Removing a portion of the bottom dielectric layer to expose the first source / drain region; and A conductive material with a third conductivity is deposited in the first opening to form a source / drain via contact. The third conductivity is greater than the first conductivity and the second conductivity.

2. The method according to claim 1, wherein, The first ion treatment includes an ion implantation operation.

3. The method according to claim 2, wherein, The dopant implanted during the ion implantation operation includes at least one selected from He, Ne, Ar, Kr, Xe, Si, Ge, N, N2, O, P, As, Sn, B, BF2, or In.

4. The method according to claim 3, wherein, The dopant has a concentration greater than 1 × 10 20 cm -3 The concentration of the injection.

5. The method according to claim 1, further comprising: Before forming the first source / drain region, a first bottom isolation layer is formed above the first epitaxial layer. The first source / drain region is formed above the first bottom isolation layer.

6. The method of claim 5, further comprising forming a sidewall material layer in the first opening, above the sidewall of the first opening, and above the exposed first source / drain region prior to performing the first ion treatment.

7. The method of claim 6, further comprising etching a portion of the sidewall material layer to form a sidewall dielectric layer and expose the first source / drain region. in, The etching of the portion of the sidewall material layer also removes a portion of the first bottom isolation layer.

8. The method according to claim 1, wherein, Forming the first opening further includes: A hard mask layer is formed above the second main surface of the substrate; and Etch the hard mask layer, the substrate, and the first epitaxial layer.

9. A method for manufacturing a semiconductor device, comprising: A first channel region is formed above the first main surface of the substrate; A second channel region is formed above the first main surface, spaced apart from the first channel region along a first direction; A first epitaxial layer is formed between the first channel region and the second channel region in the first main surface of the substrate; A first source / drain region with a first conductivity is formed above the first epitaxial layer; A first gate structure is formed above the first channel region, and a second gate structure is formed above the second channel region. The first gate structure and the second gate structure extend in a second direction that intersects the first direction. The first gate structure and the second gate structure include a gate electrode layer disposed above a gate dielectric layer having a first dielectric constant, and an insulating gate spacer having a second dielectric constant disposed on the sidewall of the gate electrode layer. The first dielectric constant is greater than the second dielectric constant; An interlayer dielectric layer is formed over the first source / drain region and the first gate structure and the second gate structure; A first opening is formed in the interlayer dielectric layer above the first source / drain region to expose a portion of the first source / drain region; The exposed portion of the first source / drain region is transformed into a front dielectric layer; Removing a portion of the front dielectric layer to expose the first source / drain region; and A conductive material with a second conductivity is deposited in the first opening to form a front conductive via. Wherein, the second conductivity is greater than the first conductivity.

10. A semiconductor device, comprising: The channel region extends in a first direction and is disposed above the first main surface of the substrate; A gate structure is disposed above the channel region and extends in a second direction intersecting the first direction; The first source / drain region and the second source / drain region, having a first conductivity and a second conductivity respectively, are disposed in the substrate on opposite sides of the gate structure along the first direction, as seen in the cross-sectional view; A conductive contact having a third conductivity is disposed between a second main surface of the substrate opposite to the first main surface and the first source / drain region. A silicide layer, having a fourth conductivity, is disposed between the conductive contact and the first source / drain region. Wherein, the third conductivity is greater than the first conductivity, the second conductivity, and the fourth conductivity, and The fourth conductivity is greater than the first conductivity; A first insulating sidewall layer is disposed above the sidewall of the conductive contact, as seen in the cross-sectional view along the first direction; and A first dielectric layer, including a dopant, is disposed between the insulating sidewall layer and the source / drain region along a third direction intersecting the first and second directions. The surface of the first dielectric layer is located closer to the substrate than any part of the silicide layer.

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