Device structures and methods of manufacturing the same

Abstract

Methods of manufacturing an isolation structure hardmask are disclosed herein. In some embodiments, the method includes forming an isolation structure between a first active region and a second active region; and forming an isolation structure hardmask over the isolation structure. A top of the isolation structure is disposed a distance below a top of a first base of the first active region and a top of a second base of the second active region. A thickness of the isolation structure hardmask is less than the distance, and forming the isolation structure hardmask is configured to provide an isolation structure hardmask having a convex top. Forming the isolation structure hardmask can also provide an isolation structure hardmask having a first step height at an end and a second step height less than the first step height in a middle. Embodiments of the present application also relate to device structures and methods of manufacturing the same.

Description

Technical Field

[0001] The embodiments of this application relate to device structures and methods of manufacturing the same. Background Technology

[0002] Multi-gate devices have been introduced to improve gate control. These devices have gates that extend partially or completely around the channel to provide access to the channel on multiple sides. Exemplary multi-gate devices include FinFETs and gate-all-around (GAA) transistors, such as nanowire transistors. Multi-gate devices enable integrated circuit (IC) technology to be scaled down massively while maintaining gate control, mitigating short-channel effects (SCE), and seamlessly integrating into existing IC manufacturing processes, technologies, and / or designs. As multi-gate devices continue to scale, advanced techniques are needed to optimize their reliability and / or performance. Summary of the Invention

[0003] Some embodiments of this application provide a method for manufacturing a device structure, comprising: forming an isolation structure between a first active region and a second active region, wherein the top of the isolation structure is disposed at a certain distance below the top of a first substrate of the first active region and the top of a second substrate of the second active region; and forming an isolation structure hard mask above the isolation structure, wherein the thickness of the isolation structure hard mask is less than the distance, and the formation of the isolation structure hard mask is configured to provide the isolation structure hard mask having a convex top.

[0004] Other embodiments of this application provide a method for manufacturing a device structure, comprising: forming a first multilayer stack and a second multilayer stack, wherein the first multilayer stack includes a first semiconductor protrusion, the second multilayer stack includes a second semiconductor protrusion, and the first multilayer stack and the second multilayer stack include a corresponding sacrificial layer and a corresponding semiconductor layer respectively disposed above the first semiconductor protrusion and the second semiconductor protrusion; forming a dielectric structure between the first semiconductor protrusion of the first multilayer stack and the second semiconductor protrusion of the second multilayer stack, wherein the first multilayer stack includes a first active region, the second multilayer stack includes a second active region, and the dielectric structure has a curved top profile; forming a hard mask structure above the dielectric structure and between the first semiconductor protrusion of the first multilayer stack and the second semiconductor protrusion of the second multilayer stack, wherein the hard mask structure is configured to provide an end of the hard mask structure having a first stepped height and an intermediate portion of the hard mask structure having a second stepped height less than the first stepped height; and replacing the corresponding sacrificial layers of the first multilayer stack and the second multilayer stack with gate stacks, wherein the gate stacks are formed above the hard mask structure.

[0005] Some embodiments of this application provide a device structure including: a semiconductor protrusion; a semiconductor layer disposed above the semiconductor protrusion; an isolation structure disposed adjacent to the semiconductor protrusion, wherein the top of the isolation structure is disposed at a certain distance below the top of the semiconductor protrusion, and the top of the isolation structure is non-planar; an isolation structure hard mask disposed on the isolation structure, wherein the thickness of the isolation structure hard mask is less than the distance, the end of the isolation structure hard mask has a first step height, the middle of the isolation structure hard mask has a second step height, and the second step height is less than the first step height; and a gate stack disposed between the semiconductor protrusion and the semiconductor layer, wherein the gate stack at least covers the semiconductor layer, the gate stack extends above the isolation structure hard mask, and the gate stack includes a gate dielectric and a gate electrode. Attached Figure Description

[0006] The embodiments of this disclosure are best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be emphasized that, in accordance with standard industry practice, the various components are not drawn to scale and are for illustrative purposes only. In practice, the dimensions of the various components may be arbitrarily increased or decreased for clarity of discussion.

[0007] Figure 1A This is a flowchart of part or all of a method for manufacturing a multi-gate device according to various aspects of embodiments of the present disclosure.

[0008] Figure 1B This is an isolation structure hard mask for fabricating multi-gate devices according to various aspects of embodiments of this disclosure (which can be used in...). Figure 1A A flowchart of part or all of the method implemented in the method.

[0009] Figure 2 It is possible to obtain various aspects of the embodiments according to this disclosure. Figure 1A A top view of part or all of a device manufactured by a certain method.

[0010] Figures 3A to 3R It is based on various aspects of the embodiments of this disclosure. Figure 2 The device at each stage of manufacturing (such as with Figure 1A (Those methods related to this) A schematic cross-sectional view of part or all of line AA.

[0011] Figures 4A to 4R It is based on various aspects of the embodiments of this disclosure. Figure 2 The device at each stage of manufacturing (such as with Figure 1A (Those methods related to this) A schematic cross-sectional view of part or all of the BB line.

[0012] Figures 5A to 5C It is based on various aspects of the embodiments of this disclosure. Figure 2 The device at each stage of manufacturing (such as with Figure 1A (Those methods related to this) A schematic cross-sectional view of part or all of the CC line.

[0013] Figures 6A to 6C and Figures 7A to 7C This is based on various aspects of the embodiments of this disclosure when implemented according to different process parameters. Figure 1B The method Figure 2 The device in relation to Figure 3E and Figure 4E A schematic cross-sectional view of part or all of the BB along the relevant manufacturing stage.

[0014] Figure 6D and Figure 7D It is based on various aspects of the embodiments of this disclosure. Figure 2 The device in relation to Figure 3J and Figure 4J A schematic cross-sectional view of part or all of the BB along the relevant manufacturing stage.

[0015] Figure 8 It is based on various aspects of the embodiments of this disclosure. Figure 2 The device in relation to Figure 3J and Figure 4JAnother enlarged, schematic cross-sectional view of part or all of BB along the relevant manufacturing stage.

[0016] Figure 9A , Figure 9B and Figure 10 This illustrates various aspects of embodiments of the present disclosure that can be achieved by adjusting process parameters (such as those related to...). Figure 1B The various isolation structure hard mask profiles obtained by the methods related to those methods.

[0017] Figure 11 The graph shows experimental results for devices fabricated with different isolation structure hard mask profiles according to various aspects of embodiments of the present disclosure.

[0018] Figure 12 This is a flowchart, in part or in whole, of another method for manufacturing a multi-gate device according to various aspects of embodiments of the present disclosure. Detailed Implementation

[0019] This disclosure generally relates to isolation structures for multi-gate devices and methods for manufacturing the same, and more particularly to the contours of hard masks for isolation structures that can improve device performance and methods for manufacturing the same.

[0020] The following disclosure provides numerous different embodiments or instances for implementing various features of the embodiments of this disclosure. Specific examples of components and arrangements are described below to simplify the embodiments of this disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first component above or on a second component may include embodiments where the first and second components are in direct contact, and may also include embodiments where an additional component may be formed between the first and second components, such that the first and second components are not in direct contact. Furthermore, spatially relative terms such as “lower,” “upper,” “horizontal,” “vertical,” “above,” “above,” “below,” “under,” “upward,” “downward,” “top,” “bottom,” and their derivatives (e.g., “horizontally,” “downward,” “upward,” etc.) are used to facilitate understanding of the relationship between one component and another in the embodiments of this disclosure. Spatially relative terms are intended to cover different orientations of the device including the components. Furthermore, when numerical values ​​or ranges of values ​​are described using terms such as “about,” “approximately,” “substantially,” etc., as will be understood by those skilled in the art, the term is intended to cover values ​​within a reasonable range that takes into account variations inherent during manufacturing. For example, based on known manufacturing tolerances associated with manufacturing components having numerically related characteristics, the numerical value or range of numerical values ​​encompasses a reasonable range including the described numerical value, such as within + / - 20% of the described numerical value. For example, a material layer having a thickness of “about 5 nm” can include a size range from 4.25 nm to 5.75 nm, where the manufacturing tolerance associated with the deposited material layer is + / - 15%, as is known to those skilled in the art. Furthermore, reference numerals and / or characters may be repeated in various instances of embodiments of this disclosure. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0021] This disclosure provides embodiments of an isolation structure hard mask configured with a convex profile (e.g., a convex top / top surface) and a method for manufacturing the same, which can improve the performance and / or uniformity of multi-gate devices. In some embodiments, the method for forming the isolation structure hard mask includes performing a deposition process, a modification process, and a nitriding process. The deposition process may include depositing a hard mask material over the top of the isolation structure, the modification process may include performing a hydrogen plasma treatment (e.g., H2 plasma) on the hard mask material, and the nitriding process may include performing a nitrogen plasma treatment (e.g., N2 plasma) on the hard mask material. Parameters of the deposition process, modification process, nitriding process, or combinations thereof may be adjusted to provide a hard mask material (and thus an isolation hard mask) with a convex top surface. In some embodiments, the hard mask material is amorphous silicon, and the nitriding process converts the amorphous silicon into amorphous silicon nitride. In some embodiments, the hard mask material is formed over the top of the isolation structure and along the sidewalls of the active region, and the method may further include removing the hard mask material from the sidewalls of the active region (e.g., sidewalls over a substrate such as the active region). In such embodiments, forming the isolation structure hard mask may include performing an etching process. In some embodiments, the etching process is performed after the nitriding process. In some embodiments, the isolation hard mask is formed adjacent to and abuts the substrate of the active region. In some embodiments, the isolation structure is recessed before forming the isolation hard mask, such that the top of the isolation structure is located a distance below the top of the substrate of the active region. In some embodiments, one or more pads (e.g., silicon pads and / or oxide pads) are formed above the top of the isolation structure before forming the isolation hard mask. In such embodiments, the isolation hard mask may be wrapped by one or more pads in some embodiments. Providing an isolation hard mask with a convex top, stepped height, and / or other contour characteristics described herein can improve device performance (e.g., by reducing effective capacitance), device reliability, and / or device uniformity (e.g., by reducing stepped height variation). Details of the proposed isolation hard mask and its fabrication method are described on the following pages. From the description herein, it will be apparent that multi-gate devices fabricated according to the methods described in the embodiments of this disclosure offer advantages over multi-gate devices fabricated according to other methods. However, it should be understood that other embodiments may provide additional advantages, not all of which need to be disclosed herein, and no particular advantage is necessary for all embodiments.

[0022] Figure 1AFlowcharts of part or all of a method 10 for fabricating a multi-gate device according to various aspects of embodiments of the present disclosure are provided. In block 15, method 10 includes forming an active region comprising a multilayer stack disposed over a substrate (e.g., a portion of a substrate). The multilayer stack includes a sacrificial layer (e.g., a sacrificial semiconductor layer, such as a silicon-germanium layer) and a semiconductor layer (e.g., a silicon layer). In block 20, an isolation structure is formed around the active region (e.g., around its substrate). In block 25, an isolation structure hard mask is formed over the isolation structure. The isolation structure hard mask is formed adjacent to the substrate and is formed to have a raised top and profile that can improve device performance and / or device reliability, as described herein. In some embodiments, the isolation structure and the isolation structure hard mask are disposed below the top of the substrate of the active region (e.g., below the top of its protrusion in a channel region), and the isolation structure hard mask may not extend above the top of the substrate of the active region. In block 30, a gate structure may be formed over the multilayer stack in the channel region. The gate structure may include dummy gate stacks and gate spacers. The gate structure may extend over and interface with the isolation structure hard mask. In block 35, source / drain etching is performed to form source / drain trenches in the multilayer stack in the source / drain region. The source / drain trenches can be formed by removing portions of the semiconductor layer, the sacrificial layer, and the substrate in the source / drain region. In some embodiments, method 10 may further include: in block 40, recessing the sacrificial layer to form internal spacer notches between the ends of the semiconductor layers of the multilayer stack in the channel region; and in block 45, forming internal spacers in the internal spacer notches. In block 50, method 10 includes forming a source / drain structure in the source / drain trench. Method 10 may further include: in block 55, forming a dielectric layer (e.g., an interlayer dielectric layer and / or a contact etch stop layer) over the isolation structure hard mask and the source / drain structure. Method 10 may further include: in block 60, removing a dummy gate stack to form a gate opening; in block 65, removing a sacrificial layer to form a gap between the semiconductor layers of the multilayer stack in the channel region; and in block 70, forming a gate stack in the gate opening and the gap. Embodiments of this disclosure contemplate additional processing. Additional steps may be provided before, during, and after method 10, and for additional embodiments of method 10, some of the described steps may be moved, replaced, or eliminated.

[0023] Figure 1B Hard masks for forming isolation structures (which can be used) are provided according to various aspects of embodiments of the present disclosure. Figure 1AThe flowchart describes part or all of the method implemented in block 25 of method 10. In some embodiments, the method may include: in block 25A, forming an isolation hard mask liner over an isolation structure. In some embodiments, the method includes: in block 25B, performing a deposition process to form a first isolation hard mask material over an isolation structure; in block 25C, performing a processing process on the first isolation hard mask material; in block 25D, performing a nitriding process to transform the first isolation hard mask material into a second isolation hard mask material; in block 25E, performing an etching process on the second isolation hard mask material; and in block 25F, adjusting the deposition process, processing process, nitriding process, etching process, or combinations thereof to provide a second isolation hard mask material having a convex top and / or other contours as described herein. Embodiments of this disclosure contemplate additional processing. Additional steps may be provided before, during, and after block 25, and for additional embodiments of block 25, some of the described steps may be moved, replaced, or eliminated.

[0024] Figure 2 It is possible to obtain various aspects of the embodiments according to this disclosure. Figure 1A A top view of part or all of the device 100 processed by method 10. Figures 3A to 3R The device 100 according to various aspects of embodiments of this disclosure is manufactured at various stages (such as with...) Figure 1A Method 10 (related to those) along Figure 2 A partial or complete cross-sectional view of line AA. Figures 4A to 4R The device 100 according to various aspects of embodiments of this disclosure is manufactured at various stages (such as with...) Figure 1A Method 10 (related to those) along Figure 2 A partial or complete cross-sectional view of line BB. Figures 4A to 4R respectively with Figures 3A to 3R The corresponding manufacturing stage. Figures 5A to 5C The device 100 according to various aspects of embodiments of this disclosure is manufactured at various stages (such as with...) Figure 1A Method 10 (related to those) along Figure 2 A partial or complete cross-sectional view of line CC. Figure 5A and Figure 3L and Figure 4L Corresponding to the manufacturing stage, Figure 5B and Figure 3Q and Figure 4Q Corresponding to the manufacturing stage, and Figure 5C and Figure 3R and Figure 4R The corresponding manufacturing stage. Figures 6A to 6C and Figures 7A to 7C This is based on various aspects of the embodiments of this disclosure when different process parameters are used. Figure 1B The method (e.g., in box 25) Figure 2 Device 100 in relation to Figure 3E and Figure 4E A schematic cross-sectional view of part or all of the BB along the relevant manufacturing stage. Figure 6D and Figure 7D It is based on various aspects of the embodiments of this disclosure. Figure 2 Device 100 in relation to Figure 3J and Figure 4J The relevant manufacturing stages and undergoing separate processes with Figures 6A to 6C and Figures 7A to 7C A schematic cross-sectional view of part or all of the BB line after relevant processing. Figure 8 It is based on various aspects of the embodiments of this disclosure. Figure 2 Device 100 in relation to Figure 3J and Figure 4J Another enlarged, schematic cross-sectional view of part or all of BB along the relevant manufacturing stage. Figure 9A , Figure 9B and Figure 10 This illustrates various aspects of embodiments of the present disclosure that can be achieved by adjusting process parameters (such as those related to...). Figure 1B The methods (e.g., those related in box 25) obtain various isolated structure hard mask profiles. Figure 11 These are graphs showing experimental results for devices fabricated using hard mask profiles with different isolation structures, according to various aspects of embodiments of this disclosure. For ease of description and understanding, this document also discusses... Figure 2 , Figures 3A to 3R , Figures 4A to 4R , Figures 5A to 5C , Figures 6A to 6D , Figures 7A to 7D , Figure 8 , Figure 9A , Figure 9B , Figure 10 and Figure 11 For clarity, it has been simplified. Figure 2 , Figures 3A to 3R , Figures 4A to 4R , Figures 5A to 5C , Figures 6A to 6D , Figures 7A to 7D , Figure 8 , Figure 9A , Figure 9B , Figure 10 and Figure 11 To better understand the inventive concept of the embodiments of this disclosure. Additional components may be added to device 100, and in other embodiments of device 100, some of the components described below may be replaced, modified, or eliminated.

[0025] In experience and Figure 2 , Figures 3A to 3R , Figures 4A to 4R , Figures 5A to 5C and Figures 6A to 6D Following the relevant processing, device 100 may include at least one GAA transistor (i.e., a transistor having a gate that at least partially surrounds a channel (e.g., nanowire, nanosheet, nanorod, etc.) extending between the source and drain). Device 100 may be processed to form a p-type transistor, an n-type transistor, or both (e.g., a complementary metal-oxide-semiconductor (CMOS) transistor). Device 100 may be included in a microprocessor, memory, other IC devices, or combinations thereof. In some embodiments, device 100 is part of an IC chip, a system-on-a-chip (SoC), or a portion thereof, and device 100 may include a variety of passive and / or active electronic devices, such as resistors, capacitors, inductors, diodes, p-type field-effect transistors (PFETs), n-type FETs (NFETs), metal-oxide-semiconductor FETs (MOSFETs), CMOS transistors, bipolar junction transistors (BJTs), laterally diffused MOS (LDMOS) transistors, high-voltage transistors, high-frequency transistors, other suitable components, or combinations thereof.

[0026] refer to Figure 2 , Figure 3A , Figure 4A , Figure 3B and Figure 4B Fabrication of device 100 may include forming and / or receiving a device precursor, which may include a substrate 105 and a multilayer stack 110. The multilayer stack 110 may include a sacrificial semiconductor layer 115 (which may be referred to as a pseudo (and / or one-time) semiconductor interposer (DSI)) and a semiconductor layer 120, and the multilayer stack 110 may be disposed above a substrate layer 105', which may be and / or form a portion of the substrate 105, such as its protrusions, extensions, and / or mesas. The multilayer stack 110 may correspond to and / or define an active region AR of device 100. The active region AR extends longitudinally along the x-direction (i.e., length along the x-direction, width along the y-direction, and height along the z-direction), and the active region AR may be substantially parallel to other active region orientations. The active region AR may include a channel region (C), a source region, and a drain region. The source region and drain region may be collectively referred to as the source / drain region (S / D).

[0027] Substrate 105 includes: elemental semiconductors, such as silicon and / or germanium; compound semiconductors, such as silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, indium antimonide, or combinations thereof; alloy semiconductors, such as SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, GaInAsP, or combinations thereof; or combinations thereof. In some embodiments, substrate 105 is a silicon substrate. In some embodiments, substrate 105 is a semiconductor-on-insulator substrate, such as a silicon-on-insulator (SOI) substrate, a silicon-germanium-on-insulator (SGOI) substrate, or a germanium-on-insulator (GOI) substrate. Substrate 105 (and substrate layer 105') may include various doped regions, such as p-type doped regions (e.g., p-wells), n-type doped regions (e.g., n-wells), or combinations thereof. n-type doped regions include n-type dopants, such as phosphorus, arsenic, other n-type dopants, or combinations thereof. p-type doped regions include p-type dopants, such as boron, indium, gallium, other p-type dopants, or combinations thereof. In some embodiments, the doped region includes p-type dopant and n-type dopant.

[0028] In some embodiments, the multilayer stack 110 is constructed by depositing a sacrificial semiconductor layer 115 and a semiconductor layer 120 over a substrate 105 (see, for example...). Figure 3A and Figure 4A ) and patterned sacrificial semiconductor layer 115 and semiconductor layer 120 (see, for example) Figure 3B and Figure 4B The pattern is formed by extending the pattern to the substrate 105 to form its base layer 105' (also referred to as an extension). Sacrificial semiconductor layers 115 and 120 are vertically stacked from the top of the substrate 105 in an alternating and / or staggered configuration (e.g., along the z-direction). In some embodiments, the deposition includes epitaxially growing the sacrificial semiconductor layers 115 and 120 in the depicted alternating / staggered configuration. For example, a first of the sacrificial semiconductor layers 115 is epitaxially grown on the substrate 105, a first of the semiconductor layers 120 is epitaxially grown on the first of the sacrificial semiconductor layers 115, a second of the sacrificial semiconductor layers 115 is epitaxially grown on the first of the semiconductor layers 120, and so on, until the multilayer stack 110 has a desired number of sacrificial semiconductor layers 115 and semiconductor layers 120. In such embodiments, the sacrificial semiconductor layers 115 and 120 may be referred to as epitaxial layers. In some embodiments, the epitaxial growth of the sacrificial semiconductor layer 115 and the semiconductor layer 120 is achieved by molecular beam epitaxy (MBE), chemical vapor deposition (CVD), metal-organic CVD (MOCVD), other suitable epitaxial growth processes, or combinations thereof.

[0029] The composition of the sacrificial semiconductor layer 115 differs from that of the semiconductor layer 120 to achieve etch selectivity. For example, the sacrificial semiconductor layer 115 and the semiconductor layer 120 may comprise different materials, atomic percentages of components, weight percentages of components, other properties, or combinations thereof to achieve etch selectivity. In some embodiments, the sacrificial semiconductor layer 115 comprises silicon germanium, the semiconductor layer 120 comprises silicon, and for a given etchant, the etch rate of the semiconductor layer 120 differs from that of the sacrificial semiconductor layer 115. In some embodiments, the sacrificial semiconductor layer 115 and the semiconductor layer 120 may comprise the same material but have different atomic percentages of components. For example, the sacrificial semiconductor layer 115 and the semiconductor layer 120 may comprise silicon germanium, and the sacrificial semiconductor layer 115 and the semiconductor layer 120 may have different percentages of germanium atoms to provide etch selectivity. The sacrificial semiconductor layer 115 and the semiconductor layer 120 may comprise any combination of materials that provide desired etch selectivity, desired difference in oxidation rate, desired performance characteristics (e.g., materials that maximize current), or combinations thereof.

[0030] Semiconductor layer 120, or a portion thereof, can form the channel of a transistor. In the depicted embodiment, the multilayer stack 110 includes three sacrificial semiconductor layers 115 and three semiconductor layers 120. Thus, the multilayer stack 110 includes three pairs of semiconductor layers disposed over substrate 105, each having a corresponding sacrificial semiconductor layer 115 and a corresponding semiconductor layer 120. After processing the multilayer stack 110, this configuration can produce a transistor with three channels. In some embodiments, the multilayer stack 110 includes a different number of semiconductor layers 120, depending on, for example, the desired number of channels for the transistor. For example, the multilayer stack 110 may include two to six pairs of semiconductor layers, each of which may include a corresponding sacrificial semiconductor layer 115 and a corresponding semiconductor layer 120.

[0031] After patterning, the multilayer stack 110 may include a semiconductor layer stack (i.e., sacrificial semiconductor layer 115 and semiconductor layer 120) disposed above the substrate layer 105' (also referred to as substrate extension, substrate fin portion, fin portion, protrusion, etched substrate portion, etc.). The multilayer stack 110 may be referred to as a fin, fin structure, fin element, active fin region, active region, etc. In some embodiments, the substrate layer 105' may be considered as a portion of the multilayer stack 110. The multilayer stack 110 extends substantially along the x-direction and has a length along the x-direction, a width along the y-direction, and a height along the z-direction. In some embodiments, photolithography and / or etching processes are performed to pattern the sacrificial semiconductor layer 115, semiconductor layer 120, and substrate 105 to form the multilayer stack 110. In some embodiments, the multilayer stack 110 is formed using multiple patterning processes, such as dual patterning lithography (DPL) processes (e.g., lithography-etch-lithography-etch (LELE) process, self-aligned dual patterning (SADP) process, spacer-dielectric (SID) process, other dual patterning processes, or combinations thereof), triple patterning processes (e.g., lithography-etch-lithography-etch-lithography-etch (LELELE) process, self-aligned triple patterning (SATP) process, other triple patterning processes, or combinations thereof), other multiple patterning processes (e.g., self-aligned quadruple patterning (SAQP) process), or combinations thereof. In some embodiments, directional self-assembly (DSA) technology is implemented. In some embodiments, the multilayer stack 110 is formed using a fin manufacturing process.

[0032] refer to Figure 2 , Figure 3C and Figure 4C An isolation structure 122 is formed around the lower portion of the multilayer stack 110 (e.g., around its base layer 105') adjacent to the lower portion of the multilayer stack 110, and the multilayer stack 110 can be separated from other multilayer stacks and / or other device regions by the isolation structure 122. The isolation structure 122 can electrically isolate active device regions (e.g., multilayer stack 110) from other device regions that may be defined by and / or include other multilayer stacks. The isolation structure 122 includes silicon oxide, silicon nitride, silicon oxynitride, other suitable isolation materials (including silicon, oxygen, nitrogen, carbon, other suitable isolation components, or combinations thereof) or combinations thereof. The size and / or characteristics of the isolation structure 122 (also referred to in some embodiments as a substrate isolation structure) can be configured to provide a shallow trench isolation (STI) structure, a deep trench isolation (DTI) structure, a localized oxidation of silicon (LOCOS) structure, other isolation structure types, or combinations thereof. In some embodiments, as depicted, the isolation structure 122 is configured as an STI.

[0033] The isolation structure 122 may include isolation pads 124 and isolation blocks 125, each of which may have a multilayer structure. Isolation block 125 includes a dielectric material. For example, isolation block 125 may be an oxide layer (e.g., silicon oxide). In some embodiments, isolation pad 124 includes pads 124A, 124B, and 124C, and pads 124A-124C have different compositions. For example, pads 124A and 124C may include dielectric materials, and pad 124B may include a semiconductor material (e.g., silicon). In some embodiments, pad 124A is an oxide pad, pad 124B is a silicon pad, and pad 124C is a nitride pad. The oxide pad may include oxygen (e.g., silicon oxide, silicon oxynitride, and / or silicon carbonitride) bonded to silicon, carbon, and / or nitrogen. The nitride pad may include nitrogen (e.g., silicon nitride, silicon carbonitride, and / or silicon carbonitride) bonded to silicon, carbon, and / or nitrogen. In some embodiments, the isolation pad 124 includes a doped dielectric pad (e.g., one or more of pads 124A-124C may be doped), such as a borosilicate glass (BSG) pad and / or a phosphosilicate glass (PSG) pad.

[0034] In some embodiments, the isolation structure 122 is formed by: depositing one or more isolation pads over device 100 to partially fill trenches between multilayer stacks 110; depositing isolation block material (e.g., oxide) over device 100 to fill the remaining portion of the trenches; performing a planarization process; and recessing (e.g., etching back) the isolation pads and isolation block material. The remaining portions of the isolation pads and isolation block material (i.e., after recessing) can form isolation pads 124 and isolation blocks 125 of the isolation structure 122, respectively. In some embodiments, the isolation structure 122 is recessed until a target distance and / or target depth of the isolation structure 122 is achieved below the substrate layer 105' of the multilayer stack 110. For example, a distance d1 is located between the top of the isolation structure 122 and the top of the substrate layer 105', and the distance d1 can be adjusted based on the target thickness of the isolation structure hard mask 126 subsequently formed over the isolation structure 122 and / or the target profile of the isolation trenches subsequently formed in the isolation structure 122. In some embodiments, the distance d1 is less than about 10 nm. Planarization processes, such as chemical mechanical polishing (CMP), can be implemented until a planarization stop layer is reached / exposed, such as a mask layer above the multilayer stack 110 (which may have been used to pattern the semiconductor layer 120 and the sacrificial semiconductor layer 115) and / or the topmost semiconductor layer 120 of the multilayer stack 110. The planarization process may partially or completely remove the mask layer.

[0035] The isolation liner can be formed using atomic layer deposition (ALD), CVD, physical vapor deposition (PVD), high-density plasma CVD (HDPCVD), MOCVD, RPCVD, PECVD, LPCVD, atomic layer CVD (ALCVD), atmospheric pressure CVD (APCVD), subatmospheric pressure CVD (SACVD), or combinations thereof. In some embodiments, the isolation block material is formed by flowable CVD (FCVD), which may include: depositing a flowable oxide material (e.g., in a liquid state) over device 100; and, for example, converting the flowable oxide material into a solid oxide material via an annealing process. In some embodiments, the flowable oxide material is a flowable silicon and oxygen material, and the annealing process converts the flowable silicon and oxygen material into a silicon and oxygen-containing layer, such as a silicon oxide layer. In some embodiments, the annealing process is thermal annealing that heats device 100 and / or the flowable oxide material to a temperature that promotes the conversion of the flowable oxide material into a solid oxide material. In some embodiments, the annealing process exposes the flowable oxide material to UV radiation. In some embodiments, the FCVD process includes a curing process. In some embodiments, the spacer material is formed using a high aspect ratio deposition (HARP) process. In some embodiments, the spacer material is formed using HDPCVD. In some embodiments, an annealing process is performed before and / or after a planarization process to cure and / or densify the spacer material.

[0036] refer to Figure 2 , Figures 3D to 3N and Figures 4D to 4N An isolation structure hard mask 126 is formed above the isolation structure 122. The isolation structure hard mask 126 ( Figure 4NThe device includes an isolation hard mask 128, and in some embodiments, includes isolation hard mask pads 127, each of which may have a multilayer structure. Isolation hard mask pads 127 are located between the isolation hard mask 128 and the isolation structure 122 and / or between the isolation hard mask 128 and the substrate layer 105'. The composition of the isolation hard mask 128 differs from the composition of the multilayer stack 110 and the isolation block 125. In some embodiments, the isolation hard mask 128 comprises silicon nitride, silicon oxynitride, silicon carbonitride, silicon carbonitride, other suitable isolation hard mask materials, or combinations thereof. For example, the isolation hard mask 128 may be a silicon nitride mask. The composition of the isolation hard mask 128 may differ from the composition of the isolation hard mask pads 127. In some embodiments, the isolation pads 127 include pads 127A and 127B, and pads 127A and 127B have different compositions. For example, pad 127A may include a semiconductor material, and pad 127B may include a dielectric material. In some embodiments, pad 127A is a silicon pad, and pad 127B is an oxide pad. The oxide pad may include oxygen (e.g., silicon oxide, silicon oxynitride, and / or silicon carbonitride) bonded to silicon, carbon, and / or nitrogen. For example, pad 127B may be a silicon oxide pad.

[0037] refer to Figure 3D and Figure 4DThe hard mask 126 forming the isolation structure may include: forming a pad material 127A' over the device 100 (including over the multilayer stack 110 and the isolation structure 122) that partially fills the trenches between the multilayer stack 110; and forming a pad material 127B' over the pad material 127A' (including over the multilayer stack 110 and the isolation structure 122) that partially fills the trenches between the multilayer stack 110. In some embodiments, the pad material 127A' (e.g., silicon) is formed by an ALD process, and the pad material 127B' (e.g., silicon oxide) is formed by a thermal oxidation process. In some embodiments, the thermal oxidation process may include exposing the pad material 127A' to an oxygen environment (e.g., an oxygen-containing gas) at a high temperature, which may oxidize the exposed surface of the pad material 127A', thereby converting a portion of the pad material 127A' into the pad material 127B'. In such embodiments, the thickness of the deposited pad material 127A' can be greater than the thickness of the pad material 127A' after the formation of the pad material 127B' (e.g., the target thickness of the pad 127A). The "high temperature" can be selected based on the thermal budget associated with the processing of the device 100. In some embodiments, the high temperature is from about 75°C to about 500°C. For example, the temperature can be from about 255°C to about 275°C. Embodiments of this disclosure contemplate implementing other processes for forming the pad material 127A' and / or the pad material 127B', such as CVD, PVD, HDPCVD, MOCVD, RPCVD, PECVD, LPCVD, ALCVD, APCVD, SACVD, other suitable methods, or combinations thereof. In some embodiments, padding materials 127A' and / or 127B' are formed using a conformal process, such that padding materials 127A' and / or 127B' have a uniform thickness (e.g., the thickness of the padding material along the sidewalls of the multilayer stack 110 is substantially the same as the thickness of the padding material above the isolation structure 122). In some embodiments, a cleaning process is performed prior to the formation of padding material 127A'. The cleaning process can remove any contaminants and / or other defects (e.g., native oxides, residues of material used to form the isolation structure 122, etc.) from the multilayer stack 110 and / or isolation structure 122. In some embodiments, a thermal process (e.g., annealing) may be performed after the formation of padding material 127A' and before the formation of padding material 127B'.

[0038] refer to Figure 3E and Figure 4EForming the isolation structure hard mask 126 may include forming an isolation hard mask material 128' that partially fills the trenches between the multilayer stack 110 over the pad material 127B' (including over the multilayer stack 110 and the isolation structure 122). The isolation hard mask material 128' (e.g., silicon nitride) is formed by CVD (e.g., PECVD), other suitable methods (such as those described herein), or combinations thereof. In some embodiments, the isolation hard mask material 128' has a non-uniform thickness, such that the thickness over the sidewalls of the respective components of device 100 is less than the thickness over the top of the respective components of device 100. For example, the isolation hard mask material 128' has a thickness t1 over the top of the isolation structure 122, a thickness t2 over the top of the multilayer stack 110, and a thickness t3 along the sidewalls of the multilayer stack 110. Thickness t1 is greater than thickness t3, and thickness t2 is greater than thickness t3. Thickness t2 may be greater than, less than, or approximately equal to thickness t1. The thickness t1 is less than approximately the distance d1 (i.e., t1 ≤ d1), thereby providing an isolation hard mask material 128' with a bottom hard mask portion that fills the bottom of the trenches between the multilayer stacks 110 (e.g., between their substrates in some embodiments, the substrates being formed by protrusions of the base layer 105') and covers the top of the isolation structure 122, without extending over the top of the base layer 105' (e.g., the top of its protrusions, which may form the substrate of the multilayer stack 110). Unfilled portions of the trenches between the multilayer stacks 110 provide a spacing S1 between the sidewall hard mask portions of the isolation hard mask material 128' that cover the sidewalls of the multilayer stacks 110. In some embodiments, the spacing S1 is approximately 33 nm to approximately 95 nm.

[0039] As described herein, the isolation hard mask formation process is designed to provide a bottom portion of the isolation hard mask material 128' with a convex top surface 128S' to improve device performance (e.g., by reducing effective capacitance). The convex top surface 128S' may project upward relative to the top of the substrate 105, and the bottom portion of the isolation hard mask material 128' has a thicker middle portion disposed between thinner ends / edges. Reference Figures 6A to 6C In some embodiments, forming the isolation hard mask material 128' includes a deposition process ( Figure 6A ), Modify the process ( Figure 6B ) and nitriding process ( Figure 6CEach of these can be configured and / or adjusted to facilitate the formation of the convex dome 128S'. In some embodiments, a deposition process forms an amorphous silicon layer 128a' over the multilayer stack 110 and the isolation structure 122; a modification process modifies the profile of the amorphous silicon layer 128a' (e.g., by reducing its thickness) and / or improves the quality of the amorphous silicon layer 128a' (e.g., by reducing silicon dangling bonds, removing native oxides and / or other surface contaminants, improving structural properties, or a combination thereof), thereby providing a modified / treated amorphous silicon layer 128b'; and a nitriding process transforms the modified amorphous silicon layer 128b' into a silicon nitride layer 128c', which provides the isolation hard mask material 128'.

[0040] In some embodiments, the deposition process is a CVD process, which may include exposing device 100 to a silicon-containing precursor gas (i.e., the deposition gas) comprising silane (SiH4) and / or other suitable silicon-containing precursor gases. In some embodiments, the CVD process also includes exposing device 100 to a hydrogen-containing precursor gas comprising diatomic hydrogen (H2) and / or other suitable hydrogen-containing precursor gases. In some embodiments, the CVD process includes exposing device 100 to a silicon-containing plasma, a hydrogen-containing plasma, or a combination thereof (e.g., a SiH4-H2 plasma), which can be generated by applying plasma power (e.g., radio frequency (RF) power) to the silicon-containing precursor gas and / or the hydrogen-containing precursor gas. In such embodiments, the CVD process may be referred to as a PECVD process. The silicon-containing plasma may be a SiH4 plasma, and the silicon-containing plasma may include silicon-excited neutral molecules, silicon-ionized molecules, silicon atoms, ionized silicon atoms, or combinations thereof (all of which are collectively referred to as plasma-excited silicon-containing material). Hydrogen-containing plasma can be H2 plasma, and can include hydrogen-excited neutral molecules, hydrogen-ionized molecules, hydrogen atoms, ionized hydrogen atoms, or combinations thereof (all of these collectively refer to plasma-excited hydrogen-containing matter, and...). Figure 6A The overall description is as follows In some embodiments, the CVD process utilizes a carrier gas, such as argon and / or other suitable inert gas.

[0041] CVD process parameters can be adjusted to provide different deposition rates on different surfaces. For example, the CVD process can be adjusted to deposit amorphous silicon faster on the top surface (e.g., above the top of the multilayer stack 110 and above the top of the isolation structure 122) than on the sidewall surface (e.g., above the sidewalls of the multilayer stack 110), thereby providing amorphous silicon layers 128a' with different thicknesses. In some embodiments, the amorphous silicon layer 128a' has a thickness t4 above the top of the isolation structure 122, a thickness t5 above the top of the multilayer stack 110, and a thickness t6 above the sidewalls of the multilayer stack 110. Thickness t4 is greater than thickness t1, thickness t5 is greater than thickness t2, and thickness t6 is greater than thickness t3. In some embodiments, different deposition rates can be adjusted to provide the bottom portion of the amorphous silicon layer 128a' with a convex top surface 128s1' (i.e., those portions that fill the bottom of the trenches between the substrates of the multilayer stack 110 (e.g., the protrusions of the substrate layer 105')). The CVD process parameters can also be adjusted to control the deposition of amorphous silicon above and around the corners of the multilayer stack 110 and along the sidewalls of the multilayer stack 110, thereby providing an overhang OH1 of the amorphous silicon layer 128a' at the top corner of the multilayer stack 110A and / or providing a gap S1' between the sidewall portions of the amorphous silicon layer 128a', which can facilitate improved modifications to the amorphous silicon layer 128a' (e.g., an increase in its top convexity) and / or improved nitriding (e.g., complete (and / or increased) nitriding of the bottom portion of the amorphous silicon layer 128a').

[0042] CVD process parameters include the flow rate of silicon-containing precursor gas, the flow rate of hydrogen-containing precursor gas, the flow rate of carrier gas, the ratio of silicon-containing precursor gas flow rate to carrier gas flow rate, the ratio of hydrogen-containing precursor gas flow rate to carrier gas flow rate, the ratio of silicon-containing precursor gas flow rate to hydrogen-containing precursor gas flow rate, the power of the RF source (RF power), the power of the DC source (DC power), the bias voltage (e.g., the RF bias voltage and / or DC bias voltage used to excite and / or accelerate the plasma), the tilt angle, the pressure, the duration, other CVD process and / or other deposition parameters, or combinations thereof. In some embodiments, the CVD process implements one or more of the following process parameters: a flow rate of silicon-containing precursor gas (e.g., SiH4) of less than about 25 standard cubic centimeters per minute (sccm) (e.g., about 20 sccm); a flow rate of hydrogen-containing precursor gas (e.g., H2) of about 1400 sccm to about 1600 sccm (e.g., about 1500 sccm); an RF power of about 75 W to about 85 W (e.g., about 80 W); a pressure of about 0.4 Torr to about 0.8 Torr (e.g., about 0.6 Torr); and a duration of more than about 15 seconds (e.g., about 16 seconds).

[0043] In some embodiments, the modified process is a hydrogen plasma treatment, which includes exposing the amorphous silicon layer 128a' to a hydrogen-containing plasma. The hydrogen-containing plasma can be generated by applying plasma power to a hydrogen-containing precursor gas (i.e., a reactant gas) containing diatomic hydrogen (H2) and / or other suitable hydrogen-containing precursor gases. Therefore, the hydrogen-containing plasma can be an H2 plasma, and can include hydrogen-excited neutral molecules, hydrogen-ionized molecules, hydrogen atoms, ionized hydrogen atoms, or combinations thereof (all of which are collectively referred to as plasma-excited hydrogen-containing material, and...). Figure 6B The overall description is as follows In some embodiments, hydrogen plasma treatment (e.g., H2 plasma treatment) can convert amorphous silicon (e.g., in solid form) into silane gas (g), as shown in the following chemical reaction:

[0044] (1) .

[0045] In such an embodiment, plasma-excited hydrogen-containing substances ( It can react with amorphous silicon, adsorb onto amorphous silicon, and / or diffuse into amorphous silicon, and react with silicon hydride (e.g., SiH) of amorphous silicon. x (e.g., on its surface) reacts, thereby allowing silane (e.g., SiH4) to be released from the amorphous silicon, thereby removing and / or etching the amorphous silicon.

[0046] The hydrogen plasma processing parameters can be adjusted to reduce the thickness of the amorphous silicon layer 128a', reduce the dangling of the amorphous silicon layer 128a', increase the spacing between the sidewall portions of the amorphous silicon layer 128a', passivate the amorphous silicon layer 128a' (e.g., by reducing dangling bonds), improve the structural properties of the amorphous silicon layer 128a', obtain other targeted improvements, or combinations thereof. For example, the hydrogen plasma processing parameters can be adjusted to provide etching of the amorphous silicon layer 128a', thereby providing a modified amorphous silicon layer 128b' with a thickness less than that of the deposited amorphous silicon layer 128a'. In some embodiments, the modified amorphous silicon layer 128b' has a thickness t7 above the top of the isolation structure 122, a thickness t8 above the top of the multilayer stack 110, and a thickness t9 above the sidewalls of the multilayer stack 110. Thickness t7 is less than thickness t4, thickness t8 is less than thickness t5, and thickness t9 is less than thickness t6. In some embodiments, thicknesses t7, t8, and t9 may respectively provide the thicknesses t1, t2, and t3 of the isolation hard mask material 128'. In some embodiments, hydrogen plasma processing parameters are adjusted to provide targeted etching / removal of the amorphous silicon sidewall portions. In such embodiments, hydrogen plasma processing can etch / remove the amorphous silicon sidewall portions (e.g., those on the sidewalls of the multilayer stack 110) faster than the bottom portions of the amorphous silicon and the top portions of the amorphous silicon (e.g., those located on top of the isolation structure 122 and above the top of the multilayer stack 110, respectively).

[0047] In some embodiments, hydrogen plasma processing parameters are adjusted to reduce the overhang of amorphous silicon and / or increase the spacing between the sidewall portions of amorphous silicon. For example, because hydrogen plasma processing can reduce the thickness of amorphous silicon, it can provide a modified amorphous silicon layer 128b' with an overhang OH2 smaller than the overhang OH1, and a modified amorphous silicon layer 128b' with a spacing S1 greater than the spacing S1' between its sidewall portions. In some embodiments, hydrogen plasma processing parameters can be adjusted to provide targeted removal of amorphous silicon from the corners c of trenches between multilayer stacks 110, such that the hydrogen plasma processing removes more amorphous silicon from the ends of the bottom portions of amorphous silicon (e.g., those above the isolation structure 122) than from the middle of the bottom portions of amorphous silicon. Different removal / etching amounts can increase the convexity of the bottom portion of the amorphous silicon, thereby providing an amorphous silicon layer 128b' with a modified convex top surface 128s1”. In some embodiments, the curvature of the modified convex top surface 128s1” is greater than the curvature of the convex top surface 128s1' (and therefore the radius of curvature of the modified convex top surface 128s1” can be smaller than the radius of curvature of the convex top surface 128s1'). In some embodiments, the convex top surface 128s1” can provide a convex top surface 128S' that isolates the hard mask material 128', such as Figure 4E As described herein, hydrogen plasma processing parameters include the flow rate of the hydrogen-containing precursor gas, the flow rate of the carrier gas, the ratio of the flow rate of the hydrogen-containing precursor gas to the flow rate of the carrier gas, RF power, DC power, bias voltage, tilt angle, pressure, duration, other hydrogen plasma processing and / or other modified parameters, or combinations thereof. In some embodiments, the hydrogen plasma processing implements one or more of the following process parameters: a flow rate of hydrogen-containing gas (e.g., H2) of about 2000 sccm to about 3000 sccm (e.g., about 2500 sccm); an RF power of less than about 200 W (e.g., about 110 W to about 130 W (e.g., about 120 W)); a pressure of less than about 2 Torr (e.g., about 2 Torr); and a duration of more than about 10 seconds (e.g., about 20 seconds).

[0048] In some embodiments, the nitriding process is a nitrogen plasma treatment, which includes exposing the modified amorphous silicon layer 128b' to a nitrogen-containing plasma. The nitrogen-containing plasma can be generated by applying plasma power (e.g., RF power) to a nitrogen-containing precursor gas (i.e., a reactive gas), including nitrogen (N2), ammonia (NH3), other suitable nitrogen-containing precursor gases, or combinations thereof. Therefore, the nitrogen-containing plasma can be an N2 plasma, an NH3 plasma, or an N2 / NH3 plasma, and can include nitrogen-excited neutral molecules, nitrogen-ionized molecules, nitrogen atoms, ionized nitrogen atoms, or combinations thereof (all of which are collectively referred to as plasma-excited nitrogen-containing material, and...). Figure 6C The overall description is as follows In some embodiments, nitrogen plasma treatment (e.g., N2 plasma treatment) can convert amorphous silicon (e.g., in solid form) into amorphous silicon nitrides, as shown by the following chemical reaction:

[0049] (2) .

[0050] In such an embodiment, plasma-excited nitrogen-containing substances ( Hydrogen can react with, adsorb onto, and / or diffuse into amorphous silicon, thereby forming silicon-nitrogen bonds. In some embodiments, hydrogen (e.g., in gaseous form) can be released from the amorphous silicon as a chemical reaction occurs to convert it into amorphous silicon nitride. For example, when the amorphous silicon includes silicon-hydrogen bonds (which can be formed during exposure to hydrogen plasma processing), plasma-excited nitrogen-containing substances ( This process can break the silicon-hydrogen bonds in amorphous silicon, thereby releasing hydrogen. Because the modified process increases the spacing between the sidewall portions of the amorphous silicon (e.g., from S1' to S1), plasma-excited nitrogen-containing materials can more easily reach and react with the bottom portions of the amorphous silicon (e.g., those portions above the isolation structure 122 that will form the isolation hard mask 128), including the bottom portions of the amorphous silicon in the corners of the trenches between the multilayer stacks 110. Therefore, the amount of nitriding at the bottom portion of the amorphous silicon layer 128b' is greater than the amount of nitriding at the bottom portion of the amorphous silicon layer 128a' (i.e., without modification). Therefore, the nitrogen content of the silicon nitride layer 128c' formed by performing a nitriding process on the modified amorphous silicon layer 128b' can be greater than the nitrogen content of the silicon nitride layer formed by performing a nitriding process on the unmodified (e.g., reducing the sidewall thickness) amorphous silicon layer 128a'.

[0051] The parameters of the nitrogen plasma treatment are adjusted to provide uniform nitriding across device 100, a uniform amount of nitriding across different patterns (e.g., the same amount of nitriding on the bottom portion of amorphous silicon regardless of the active region spacing and / or active region height), targeted nitriding of the bottom portion of amorphous silicon (e.g., those portions above isolation structure 122), nitrogen content of silicon nitride layer 128c' and / or its bottom portion, other targeted improvements and / or properties, or combinations thereof. Nitrogen plasma treatment parameters include the flow rate of the nitrogen-containing precursor gas, the flow rate of the carrier gas, the ratio of the nitrogen-containing precursor gas flow rate to the carrier gas flow rate, RF power, DC power, bias voltage, tilt angle, pressure, duration, other nitrogen plasma treatment and / or other nitriding parameters, or combinations thereof. In some embodiments, nitrogen plasma treatment is implemented with one or more of the following process parameters: a flow rate of nitrogen-containing gas (e.g., N2) of about 2000 sccm to about 3000 sccm (e.g., about 2500 sccm); an RF power of about 450 W to about 550 W (e.g., about 500 W); a pressure of less than about 5 Torr (e.g., about 3.5 Torr); and a duration of less than about 60 seconds (e.g., about 40 seconds).

[0052] refer to Figures 6A to 6C and Figures 7A to 7C ( Figures 7A to 7C It shows the use of and Figures 6A to 6C The same process (i.e., deposition process) Figure 7A ), Modify the process ( Figure 7B ) and nitriding process ( Figure 7C However, when forming the isolation hard mask material 128' with different process parameters, the disclosed process parameters are not randomly selected but specifically configured to achieve the target profile (e.g., convex top surface) and / or characteristics of the isolation hard mask material 128' and the isolation hard mask 128. In some embodiments, the deposition process is specifically adjusted (e.g., with a longer duration and a slower flow rate of silicon-containing gas) to minimize the spacing load (i.e., ensuring sufficient spacing between the sidewall portions of amorphous silicon) and / or to provide an amorphous silicon deposition rate above the sidewall surfaces (e.g., the sidewalls of the multilayer stack 110) that is lower than the amorphous silicon deposition rate above the top surface (e.g., the top of the isolation structure 122 and the top of the multilayer stack 110). For example, refer to Figure 6A and Figure 7A When deposition processes (such as with) Figure 7A When the corresponding deposition process is implemented for too short a duration (e.g., less than 15 seconds, such as about 11 seconds) and / or at too fast a flow rate of silicon-containing gas (e.g., greater than 25 sccm, such as about 30 sccm), the deposition process forms a thicker amorphous silicon layer with greater overhang. In other words, Figure 7AThe thicknesses t10, t11, and t12 of the amorphous silicon layer 128a' are respectively greater than Figure 6A The thicknesses t4, t5, and t6 of the amorphous silicon layer 128a'. Figure 7A The thicker amorphous silicon layer 128a' also provides a larger overhang OH3 than OH1 and a smaller spacing S2' than spacing S1'. The larger overhang OH3 and / or smaller spacing S2' can hinder the modification process, for example, by preventing its plasma (and / or its etch components) from easily entering the trenches between the multilayer stack 110. In contrast, because Figure 6A The deposition process provides smaller overhangs OH1 and larger spacing S1', so Figure 6A The deposition process allows the modified process to provide more targeted shaping of the amorphous silicon layer 128a', especially the bottom portion of the amorphous silicon layer 128a' above the top of the isolation structure 122.

[0053] In some embodiments, the process is specifically modified (e.g., with a longer duration and lower power) to reduce overhang (i.e., ensure sufficient spacing between the sidewall portions of the amorphous silicon) and / or to provide targeted shaping of the bottom portions of the amorphous silicon (e.g., those portions above the top of the isolation structure 122). For example, refer to Figure 6B and Figure 7B When modifying the process (such as with) Figure 7B When the corresponding modified process is implemented for too short a duration (e.g., less than 10 seconds, such as about 7 seconds) and / or too high a power (e.g., greater than 200 W, such as about 240 W), the modified process removes less amorphous silicon, thereby providing a thicker modified amorphous silicon layer with greater overhang. In other words, Figure 7B The thicknesses t13, t14, and t15 of the modified amorphous silicon layer 128b' are respectively greater than Figure 6B The thicknesses t7, t8, and t9 of the modified amorphous silicon layer 128b'. Figure 7B The thicker modified amorphous silicon layer 128b' can also provide a larger overhang OH4 than OH2 and a smaller spacing S2 than spacing S1. A larger overhang OH4 and / or a smaller spacing S2 can, for example, hinder the nitriding process by preventing its plasma from easily entering the trenches between the multilayer stack 110, thereby making... Figure 7C The nitriding process may not completely nitride. Figure 7B The bottom portion of the modified amorphous silicon layer 128b' (e.g., Figure 7C The silicon nitride layer 128c' may include an amorphous silicon portion. In contrast, because Figure 6B The modified process provides smaller overhangs of OH2 and larger spacing S1, so Figure 6B The modified process can make Figure 6CThe nitriding process can completely nitrid the bottom portion of the modified amorphous silicon layer 128b' (e.g., Figure 6C The silicon nitride layer 128c' may include negligible amorphous silicon. Therefore, the isolation hard mask material 128' can have a more uniform composition, which can improve the etching uniformity of the isolation hard mask material 128' and thus minimize the variation of the isolation hard mask 128, as described herein.

[0054] also, Figure 7B A modified process with shorter duration and higher power may not be sufficient to remove amorphous silicon from the corner c of the trench between the multilayer stack 110, thus making Figure 7B Modified processes may not (or negligibly) increase the convexity of the bottom portion of the amorphous silicon. For example, although Figure 7B The curvature of the convex surface 128S2” of the modified amorphous silicon layer 128b' can be greater than 1 / 2. Figure 7A The curvature of the convex surface 128S2' of the amorphous silicon layer 128a', but Figure 7B The modified process may not increase the curvature of the convex surface 128S2” sufficiently to withstand the load. Figure 7D The subsequent etching. Therefore, Figures 7A to 7C The process parameters may undesirably lead to Figure 7D The isolation hard mask 128 has a concave top surface 128S-1 after etching, such as a reference. Figure 3J and Figure 4J The etching described. In contrast, Figures 6A to 6C The process parameters provide a convex surface 128s1” with a curvature greater than that of the convex surface 128S2” and a curvature that can withstand subsequent etching, thereby enabling Figure 6D The isolation hard mask 128 has a convex top surface 128S after etching. In some embodiments, because Figure 6A deposition process and / or Figure 6B The modified process improved access to the bottom portion of the isolation hard mask material 128', so Figure 6C The nitriding process can be tailored to have a shorter duration, lower power, and / or lower pressure, which can mitigate the impact of the nitriding process on device 100. In contrast, because Figure 7A deposition process and / or Figure 7B The modified process provides greater overhang and / or smaller spacing, so Figure 7C The nitriding process must be carried out for a longer duration (e.g., greater than 60 seconds, such as about 80 seconds), with higher power (e.g., greater than 900 W, such as about 1000 W) and / or higher pressure (e.g., greater than 5 Torr, such as about 5.5 Torr) to ensure nitriding of the bottom portion of the isolated hard mask material 128', which increases the impact of the nitriding process on device 100.

[0055] Implementing different process parameters can produce silicon nitride layers 128c' with different compositions. For example, by using... Figures 7A to 7C The silicon nitride layer 128c' formed by the corresponding process can have a silicon content of less than 49% (Si%), a nitrogen content of at least 46% (N%), and an oxygen content of less than 5% (O%). And through... Figures 6A to 6C The silicon nitride layer 128c' formed by the corresponding process can have a silicon content of at least 49% (Si%), a nitrogen content of less than 46% (N%), and an oxygen content of at least 5% (O%). In other words, implementing a slower deposition rate (e.g., by implementing a longer deposition time and / or a slower flow rate of silicon-containing gas), a longer, lower power modification / processing process, and a shorter, lower power nitriding process to provide an isolation hard mask material 128' with a more silicon content, a lower nitrogen content, and / or a greater oxygen content can provide an isolation hard mask material 128'.

[0056] refer to Figure 3F and Figure 4F The formation of the isolation structure hard mask 126 may include forming a sacrificial material 130' (also referred to as a dummy material) over the isolation hard mask material 128'. The sacrificial material 130' may fill the remaining portion of the trenches between the multilayer stacks 110, as depicted, and the sacrificial material 130' is disposed over the top of the multilayer stacks 110 (including the portion of the isolation hard mask material 128' disposed over the top of the multilayer stacks 110). The composition of the sacrificial material 130' differs from that of the isolation hard mask material 128' (e.g., silicon nitride) to promote etch selectivity between them. In some embodiments, the sacrificial material 130' is a dielectric material comprising silicon and oxygen and / or carbon (e.g., silicon oxide and / or silicon carbide). In some embodiments, as depicted, the sacrificial material 130' is a bottom antireflective coating (BARC) material that may comprise silicon and oxygen and / or carbon. In some embodiments, the BARC material comprises a siloxane polymer. The sacrificial material 130' may be formed by spin coating, other deposition processes (e.g., CVD), or combinations thereof.

[0057] refer to Figure 3G and Figure 4GForming the isolation structure hard mask 126 may include recessing (e.g., etching back) a sacrificial material 130' to expose a portion of the isolation hard mask material 128' disposed above the top of the multilayer stack 110. In some embodiments, the remaining portion of the sacrificial material 130' may provide a sacrificial layer 130 between the multilayer stacks 110. In some embodiments, as depicted, the sacrificial material 130' is recessed below the top of the portion of the isolation hard mask material 128' disposed above the top of the multilayer stack 110, but not below the top of the multilayer stack 110. Thus, the recess reduces the height of the sacrificial material 130', such that the top of the sacrificial layer 130 is below the top of the portion of the isolation hard mask material 128' disposed above and above the top of the multilayer stack 110. The recess may be an etching process that selectively removes the sacrificial material 130' relative to the isolation hard mask material 128'. For example, an etching process may remove the sacrificial material 130' without (or negligibly remove) the isolation hard mask material 128'. In some embodiments, the etchant in the etching process etches the sacrificial material 130' (e.g., a BARC material, which may include silicon and oxygen and / or carbon) at a higher rate than the isolation hard mask material 128' (e.g., silicon nitride). In some embodiments, a cleaning process is performed after the recessing process, for example, to remove contaminants and / or other defects (e.g., native oxides, etchant residues, etc.).

[0058] refer to Figure 3H and Figure 4HForming the isolation structure hard mask 126 may include removing a portion of the isolation hard mask material 128' disposed above the top of the multilayer stack 110. The remaining portion of the isolation hard mask material 128' may provide an isolation hard mask 128 including sidewall portions and a bottom portion between the multilayer stacks 110. The sidewall portions of the isolation hard mask 128 partially fill the upper portion of the trench between the multilayer stacks 110 and extend along the sidewalls of the sacrificial semiconductor layer 115 and the semiconductor layer 120. The bottom portion of the isolation hard mask 128 fills the lower portion of the trench between the multilayer stacks 110 and extends along the sidewall of the substrate layer 105'. The sacrificial layer 130 protects the bottom portion of the isolation hard mask 128 from modification during the removal of the portion of the isolation hard mask material 128' disposed above the top of the multilayer stack 110. For example, the sacrificial layer 130 can prevent unintentional etching of the bottom portion of the isolation hard mask 128 and the resulting loss and / or modification, thereby preserving the concave top surface 128S of the isolation hard mask 128 and the target profile. In some embodiments, a removal process (e.g., an etching process and / or a planarization process (e.g., CMP)) removes the portion of the isolation hard mask material 128' disposed above the top of the multilayer stack 110 and the portion of the sacrificial layer 130 extending above the top of the multilayer stack 110. The removal process may be performed until a removal stop layer (e.g., an etching stop layer and / or a planarization stop layer) is reached / exposed, such as the portion of pad material 127B' covering the top of the multilayer stack 110. In some embodiments, pad material 127B' and pad material 127A' may remain covering the top of the multilayer stack 110, and the isolation hard mask 128 (e.g., its sidewall portions) and the sacrificial layer 130 may extend above the top of the multilayer stack 110. In some embodiments, the pad material 127B', the isolation hard mask 128, and the sacrificial layer 130 may form the top surface of the device 100, which may be a flat and / or planarized surface in some embodiments. In some embodiments, negligible residue of the isolation hard mask 128 (e.g., less than about 2 nm thick) may remain on top of the pad material 127B'.

[0059] refer to Figure 3I and Figure 4IForming the isolation structure hard mask 126 may include removing the sacrificial layer 130. In some embodiments, the etching process selectively removes the sacrificial layer 130 relative to the isolation hard mask 128. The etching process may further selectively remove the sacrificial layer 130 relative to the pad material 127B'. For example, the etching process may remove the sacrificial layer 130 without (or negligibly) removing the isolation hard mask 128, and in some embodiments, without (or negligibly) removing the pad material 127B'. In some embodiments, the etchant of the etching process etches the sacrificial layer 130 (e.g., a BARC material, which may include silicon and oxygen and / or carbon) at a higher rate than that of the isolation hard mask 128 (e.g., silicon nitride) and the pad material 127B' (e.g., silicon oxide). In some embodiments, a cleaning process is performed after etching, for example, to remove contaminants and / or other defects (e.g., native oxides, etchant residues, etc.).

[0060] refer to Figure 3J and Figure 4J Forming the isolation structure hard mask 126 may include removing sidewall portions of the isolation hard mask 128. In some embodiments, the etching process selectively removes the isolation hard mask 128 relative to the pad material 127B'. For example, the etching process may remove the isolation hard mask 128 without removing (or negligibly remove) the pad material 127B'. Because the thickness of the sidewall portions of the isolation hard mask 128 is less than the thickness of the bottom portion of the isolation hard mask 128, the etching process may remove the sidewall portions of the isolation hard mask 128 without removing (or negligibly remove) the bottom portion of the isolation hard mask 128. In some embodiments, etching parameters are adjusted to achieve targeted removal of the sidewall portions of the isolation hard mask 128. In some embodiments, the etchant of the etching process etches the isolation hard mask 128 (e.g., silicon nitride) at a higher rate than the pad material 127B' (e.g., silicon oxide). The padding material 127B' can protect the multilayer stack 110 from the etching process, and in some embodiments, it can protect the padding material 127A' from the etching process. For example, the padding material 127B' can prevent unintentional etching of the multilayer stack 110 (e.g., its semiconductor layer 120 and / or sacrificial semiconductor layer 115) and the resulting loss and / or modification.

[0061] After the etching process ( Figure 4J and Figure 6DThe isolation hard mask 128 has a convex surface 128S and a thickness T1. In some embodiments, the bottom portion of the isolation hard mask 128 is not affected by the etching process, and the thickness T1 of the isolation hard mask 128 may be approximately the same as the thickness t1 of the isolation hard mask material 128', and / or the convex surface 128S may be approximately the same as the convex surface 128S' of the isolation hard mask material 128' (e.g., the convex surfaces 128S and 128S' may have approximately the same curvature). In some embodiments, the etching process may slightly reduce the thickness of the bottom portion of the isolation hard mask 128, such that the thickness T1 may be less than the thickness t1, and / or slightly modify the convexity of the isolation hard mask 128, such that the curvature of the convex surface 128S may be less than the curvature of the convex surface 128S'.

[0062] refer to Figure 4J and Figure 8 The thickness T1 of the isolation hard mask 128 can vary along the width of the isolation hard mask 128, which can be along the gate longitudinal direction (e.g., the y-direction). For example, in Figure 8 In this design, the isolation hard mask 128 has a thickness TE at its ends / edges and a thickness TM at its center, and the thickness TE may be less than the thickness TM. The ends / edges of the isolation hard mask 128 are located adjacent to corresponding active regions (e.g., multilayer stack 110). In some embodiments, the thickness T1 may increase from the thickness TE (near the first active region) to the thickness TM, and then decrease from the thickness TM back to the thickness TE (near the second active region). In some embodiments, the thickness TE is the minimum thickness of the isolation hard mask 128, and the thickness TM is the maximum thickness of the isolation hard mask 128. In some embodiments, the thickness TE is about 5 nm to about 6 nm, and the thickness TM is about 7 nm to about 8 nm. In some embodiments, the thicknesses TE and TM may be proportional to the distance D and / or spacing between the active regions (e.g., multilayer stack 110). In other words, the thicknesses TE and TM may increase as the distance D between the active regions increases. In some embodiments, the distance D is greater than about 30 nm (e.g., about 34 nm to about 42 nm). In some embodiments, the top of the isolation hard mask 128 protrudes upward from the edge / end of the isolation hard mask 128 at an angle σ. The angle σ can be between the top of the end of the isolation hard mask 128 and the xz plane (i.e., the plane defined by the x and z directions) (e.g., provided by the sidewalls of the isolation hard mask 128). In some embodiments, the angle σ is less than 90° and is at least 80° (e.g., 80° ≤ σ < 90°).

[0063] Because the isolation hard mask material 128' is formed with targeted characteristics (e.g., thickness, sag, spacing, etc.) and a bottom portion with targeted convexity as described herein (e.g., according to...). Figures 6A to 6D (related processing), so the isolation hard mask 128, after its sidewall portions are removed by an etching process, presents a convex top surface 128S, thereby providing a step height SH_E between the top of the edge / end of the isolation hard mask 128 and the top of the base layer 105'. The step height SH_E is greater than the step height SH_M between the top of the middle of the isolation hard mask 128 and the top of the base layer 105', such as... Figure 4J , Figure 8 , Figure 9A and Figure 10 As depicted in [the text]. Therefore, the step height of the isolation hard mask 128 having the convex top surface 128S can increase and then decrease as the distance from the active region (e.g., the base layer 105' of the multilayer stack 110) increases. Furthermore, because the convex top surface 128S resembles a frown, the profile of the isolation hard mask 128 having the convex top surface 128S can be referred to as a crying (and / or frowning) profile. In some embodiments, the step height SH_E is at least 5.0 nm, and the step height SH_M is at least 0 nm and less than 5 nm. In some embodiments, the step height SH_E is from about 5.9 nm to about 7.9 nm.

[0064] In comparison, reference Figure 9B and Figure 10 When forming an isolation hard mask 128 without considering convexity (e.g., according to the relationship with Figures 7A to 7D (Related processing), the isolation hard mask 128 may undesirably present a concave top surface 128S-1, such as Figure 9B and Figure 10As depicted, this provides a step height SH_E that is less than the step height SH_M. Therefore, the step height of the isolation hard mask 128 with a concave top surface 128S-1 can decrease and then increase with increasing distance from the active region. Furthermore, because the concave top surface 128S-1 resembles a smile, the profile of the isolation hard mask 128 with the concave top surface 128S-1 can be referred to as a smile profile. It has been observed that, compared to the isolation hard mask 128 with the concave top surface 128S-1, the isolation hard mask 128 with the convex top surface 128S-1 can ideally provide less local step height variation (e.g., the difference between step heights SH_E and SH_M) and less global step height variation (e.g., the step height difference between isolation hard masks of different sizes, which can vary based on the active region spacing), which can improve device uniformity and / or device reliability. In some embodiments, because the isolation hard mask material 128' is formed with an increased spacing between its sidewall portions (e.g., spacing S1 instead of spacing S2), the bottom portion of the isolation hard mask material 128' can be completely nitrided by a nitriding process (i.e., to the point that no amorphous silicon portion remains), which can improve the etching uniformity of the bottom portion of the isolation hard mask material 128' and thus reduce the step height variation.

[0065] refer to Figure 3K and Figure 4K The hard mask 126 forming the isolation structure may include removing portions of pad material 127B', such as portions disposed above the sacrificial semiconductor layer 115 and the semiconductor layer 120. The remaining portions of pad material 127B' form pad 127B of the hard mask 126. Pad 127B is disposed above the isolation structure 122 and along the sidewalls of the substrate layer 105', between the hard mask 128 and pad material 127A', and below the top of the substrate layer 105'. In some embodiments, the etching process selectively removes pad material 127B' relative to the hard mask 128 and pad material 127A'. For example, the etching process may remove pad material 127B' without (or negligibly remove) the hard mask 128 and pad material 127A'. In some embodiments, the etchant in the etching process etches the pad material 127B' (e.g., silicon oxide) at a higher rate than that used to isolate the hard mask 128 (e.g., silicon nitride) and the pad material 127A' (e.g., silicon). The pad material 127A' can protect the multilayer stack 110 from the effects of the etching process. For example, the pad material 127A' can prevent unintentional etching of the multilayer stack 110 (e.g., its semiconductor layer 120 and / or sacrificial semiconductor layer 115) and the resulting loss and / or modification.

[0066] refer to Figure 2, Figure 3L , Figure 4L , Figure 5A , Figure 3M and Figure 4M A gate structure 130 can be formed over the channel region (C) of the active region AR and between the corresponding source / drain regions (S / D) of the active region AR. One or more gate structures 130 may include corresponding dummy gate stacks 132 and corresponding gate spacers 134. The dummy gate stacks 132 extend longitudinally in a direction different from (e.g., orthogonal to) the longitudinal direction of the multilayer stack 110. For example, the dummy gate stacks 132 extend in the y-direction, having a length in the y-direction, a width in the x-direction, and a height in the z-direction. The dummy gate stacks 132 may extend substantially parallel to each other. (Reference) Figure 3L (For example, along the gate lateral direction), a dummy gate stack 132 is disposed on top of the corresponding channel region, and the dummy gate stack 132 is disposed between the corresponding source / drain regions. Reference Figure 5A (For example, along the gate longitudinal direction), the dummy gate stack 132 may enclose the corresponding channel region (e.g., disposed above its top and sidewalls), and the dummy gate stack 132 may be disposed above the top of the isolation structure 122 and / or the top of the isolation structure hard mask 126 (e.g., its isolation hard mask 128). The dummy gate stack 132 may include a corresponding dummy gate dielectric 135, a corresponding dummy gate block 136, and a corresponding hard mask 138. The dummy gate dielectric 135 includes a dielectric material, such as silicon oxide and / or other suitable dielectric materials. The dummy gate block 136 includes a suitable placeholder / sacrificial material, such as polysilicon. In some embodiments, forming the dummy gate stack 132 includes: depositing a dummy gate dielectric layer over the multilayer stack 110; depositing a polysilicon layer over the dummy gate dielectric layer; and depositing a hard mask layer over the polysilicon layer. Then, one or more photolithography and etching processes can be performed to pattern the hard mask layer, polysilicon layer and dummy gate dielectric layer, and the remainder of the hard mask layer, polysilicon layer and dummy gate dielectric layer can form dummy gate dielectric 135, dummy gate block 136 and hard mask 138, as depicted.

[0067] refer to Figure 3M and Figure 4M Gate spacer 134 is adjacent to dummy gate stack 132 and formed along the sidewall of dummy gate stack 132. In some embodiments, spacer 139 may be formed above isolation structure hard mask 126 adjacent to (e.g., along the sidewall) the multilayer stack 110 in the source / drain region, such as Figure 4MAs depicted in [the original text]. Gate spacers 134 and 139 can be formed by any suitable process, and in some embodiments, gate spacers 134 and 139 are formed simultaneously. In some embodiments, the height of fin spacer 139 may initially be substantially the same as the height of the multilayer stack 110 above the isolation structure hard mask 126, such that fin spacer 139 covers the entire sidewall of multilayer stack 110, and the height of fin spacer 139 may be reduced to a target fin spacer height (e.g., a fin spacer height corresponding to a desired source / drain profile), such that fin spacer 139 covers a portion of the sidewall of multilayer stack 110 (e.g., the lower portion of fin spacer 139 may be retained after removing its upper portion). Gate spacers 134 and 139 comprise a dielectric material that may include silicon, oxygen, carbon, nitrogen, other suitable dielectric components, or combinations thereof (e.g., silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, silicon carbonoxynitride, silicon carbonoxynitride, silicon carbonitride, or combinations thereof). In some embodiments, gate spacer 134 and / or spacer 139 have a multilayer structure, such as two or more dielectric layers with different compositions. In some embodiments, gate spacer 134 and / or spacer 139 include more than one group of spacers, such as sealing spacers, offset spacers, sacrificial spacers, dummy spacers, main spacers, or combinations thereof. In such embodiments, the respective groups of spacers may have different compositions.

[0068] refer to Figure 3N and Figure 4N Source / drain etching removes portions of the multilayer stack 110 not covered by the gate structure 130, thereby forming a source / drain trench 140 (also referred to as a source / drain recess). For example, source / drain etching removes the semiconductor layer 120 and the sacrificial semiconductor layer 115 in the source / drain region, thereby exposing the substrate layer 105'. Source / drain etching may also remove some, but not all, of the substrate layer 105' in the source / drain region, thereby causing the source / drain trench 140 to extend to a target distance and / or target depth in the substrate layer 105'. In some embodiments, source / drain etching may remove portions of the pad material 127A', such as the portion disposed above the sacrificial semiconductor layer 115 and the semiconductor layer 120, thereby forming the pad 127A of the isolation structure hard mask 126 (i.e., the remaining portion of the pad material 127A' forms the pad 127A). Pad 127A is disposed above the isolation structure 122 and along the sidewall of the base layer 105'. Pad 127A is disposed between the isolation structure 122 and pad 127B, and is disposed below the top of the base layer 105'. In some embodiments, pad 127A and / or spacer 139 may form a portion of the sidewall of the source / drain trench 140 (e.g., Figure 4N ).

[0069] In some embodiments, source / drain etching of semiconductor layer 120 and sacrificial semiconductor layer 115 may remove semiconductor layer 120, sacrificial semiconductor layer 115, and pad material 127A', without (or negligibly) removing spacer 139, isolation hard mask 128, pad 127B, gate spacer 134, and hard mask 138. In some embodiments, the etchant in the etching process etches the semiconductor material (e.g., semiconductor layer 120, sacrificial semiconductor layer 115, and pad material 127A') at a rate higher than that of the dielectric material (e.g., spacer 139, isolation hard mask 128, pad 127B, gate spacer 134, and hard mask 138). In some embodiments, source / drain etching may remove portions of isolation structure hard mask 126 not covered by spacer 139 (e.g., isolation hard mask 128 and its pad 127), thereby forming isolation trenches (also referred to as isolation recesses). In some embodiments, source / drain etching exposes isolation structure 122, and source / drain etching may remove some of the exposed isolation structure (e.g., its isolation block 125), such that the isolation trench extends a target distance and / or target depth below the top of substrate layer 105'. After source / drain etching, protrusions of sacrificial semiconductor layer 115, semiconductor layer 120, and substrate layer 105' remain in the channel region, and source / drain trench 140 may expose the sidewalls of sacrificial semiconductor layer 115, semiconductor layer 120, and substrate layer 105' remaining in the channel region. In some embodiments, source / drain etching removes some, but not all, of the dummy gate stack 132 (e.g., its hard mask 138), gate spacers 134, spacers 139, or combinations thereof. In such embodiments, source / drain etching may reduce the height of dummy gate stack 132 (e.g., by reducing the thickness of hard mask 138), gate spacers 134, and / or spacers 139.

[0070] refer to Figure 3O and Figure 4OThe process may include forming an internal spacer 149. The internal spacer 149 may replace the edge / end of the sacrificial semiconductor layer 115. In such an embodiment, after forming the internal spacer 149, the sidewalls of the source / drain trench 140 may be formed by the semiconductor layer 120 and the internal spacer 149 instead of the sacrificial semiconductor layer 115. The internal spacer 149 is disposed below the gate spacer 134 along the sidewall of the sacrificial semiconductor layer 115. Furthermore, the internal spacer 149 is disposed between the ends of the respective semiconductor layers 120, and a bottom internal spacer 149 is disposed between the end of the respective bottom semiconductor layer 120 and the respective substrate layer 105'. In some embodiments, the formation of the internal spacer 149 (including the manufacturing steps associated with and described below) is optional. That is, the formation of the internal spacer 149 may be omitted, and the internal spacer 149 may not be present in the device 100 and / or the transistors of the device 100.

[0071] Forming the internal spacer 149 may include a first internal spacer etching, internal spacer deposition, and a second internal spacer etching. The first internal spacer etching (e.g., anisotropic etching) may laterally recess the sacrificial semiconductor layer 115 to form a notch beneath the gate structure 130 (e.g., beneath its gate spacer 134). For example, the etching process may laterally etch (e.g., along the x and / or y directions) the sacrificial semiconductor layer 115 to reduce its length, such that the length of the sacrificial semiconductor layer 115 is less than the length of the semiconductor layer 120. The sacrificial semiconductor layer 115 may be removed from the ends of the semiconductor layer 120, thereby exposing the ends of the semiconductor layer 120 (e.g., its top and bottom), and the remaining portion of the sacrificial semiconductor layer 115 may be referred to as a pseudo semiconductor interposer (DSI). In some embodiments, the notch extends laterally beneath the pseudo gate stack 132 (e.g., along the x direction). In some embodiments, the etching process may recess the isolation structure hard mask 126 (e.g., isolation hard mask 128).

[0072] Internal spacer deposition can form an internal spacer layer that at least partially fills a slot over device 100. In some embodiments, a single deposition process is performed to form the internal spacer layer that fills the slot. In some embodiments, the internal spacer 149 has a multilayer structure, and the internal spacer deposition includes more than one deposition process to form multiple internal spacer layers, such as a first deposition process forming a first internal spacer sublayer and a second deposition process forming a second internal spacer sublayer. The first internal spacer sublayer partially fills the slot, and the second internal spacer sublayer may partially or completely fill the slot. The composition of the first internal spacer sublayer may be the same as or different from the composition of the second internal spacer sublayer.

[0073] The second internal spacer etch can selectively remove the internal spacer layer while negligibly (or not at all) removing the semiconductor layer 120, the substrate layer 105', the dummy gate stack 132 (e.g., its hard mask 138), the gate spacers 134, the spacers 139, the isolation structure hard mask 126 (e.g., its isolation hard mask 128), or combinations thereof. The remaining portion of the internal spacer layer provides the internal spacers 149, as depicted. To achieve the desired etch selectivity, the internal spacer layer (and therefore the internal spacers 149) has a composition different from that of the semiconductor layer 120, the substrate layer 105', the dummy gate stack 132 (e.g., its hard mask 138), the gate spacers 134, the spacers 139, the isolation structure hard mask 126 (e.g., its isolation hard mask 128), or combinations thereof. In some embodiments, the internal spacer layer comprises a dielectric material. For example, the internal spacer layer may be a silicon carbide layer, a silicon carbonitride layer, a silicon carbonitride layer, a silicon carbonitride layer, or a combination thereof. In some embodiments, the parameters of the internal spacer deposition and / or internal spacer etching are adjusted to provide an internal spacer 149 with an air gap.

[0074] In addition, refer to Figure 3O and Figure 4O A source / drain structure 150 is formed in the source / drain recess 140. Each source / drain structure 150 may include an interposer structure disposed between a respective substrate layer 105' and a respective doped semiconductor layer 156. The interposer structure may include an undoped semiconductor layer, an insulating layer, other suitable interposers, or combinations thereof. In some embodiments, the interposer structure has a multilayer structure, such as a respective undoped semiconductor layer 152 and a respective insulating layer 154. In some embodiments, the interposer structure includes an undoped semiconductor layer 152 but does not include an insulating layer 154, or includes an insulating layer 154 but does not include an undoped semiconductor layer 152. In some embodiments, the doped semiconductor layer 156 has a multilayer structure, such as a respective doped semiconductor layer 158 and a respective doped semiconductor layer 160. In some embodiments, the source / drain structure 150 forms the source / drain of a p-type transistor, and the source / drain structure 150 may include a semiconductor material doped with a p-type dopant (e.g., boron, gallium, other p-type dopants, or combinations thereof). In some embodiments, the source / drain structure 150 forms the source / drain of an n-type transistor, and the source / drain structure 150 may include a semiconductor material doped with an n-type dopant (e.g., carbon, phosphorus, arsenic, antimony, other n-type dopants, or combinations thereof). As used herein, source / drain, source / drain region, source / drain structure, source / drain component, epitaxial source / drain, epitaxial source / drain component, etc., may refer to the source of device 100, the drain of device 100, or the source and / or drain of multiple devices (including device 100).

[0075] An undoped semiconductor layer 152 (also referred to as an unintentionally doped (UID) semiconductor layer) may be formed in the bottom of the source / drain recess 140. The undoped semiconductor layer 152 is disposed below (e.g., below) the bottom of the bottommost semiconductor layer 120. In some embodiments, the undoped semiconductor layer 152 may extend slightly above the top of the substrate layer 105'. In some embodiments, the top surface of the undoped semiconductor layer 152 is substantially flush with or below the top surface of the substrate layer 105' (i.e., the undoped semiconductor layer 152 may not extend beyond the top surface of the substrate layer 105'). The undoped semiconductor layer 152 is free of dopants (i.e., substantially free of n-type and p-type dopants). For example, no intentional doping is performed when the undoped semiconductor layer 152 is formed. The undoped semiconductor layer 152 comprises silicon, germanium, silicon-germanium, other suitable semiconductor materials, or combinations thereof. In some embodiments, the undoped semiconductor layer 152 is a dopant-free silicon-germanium layer, a dopant-free silicon layer, or a combination thereof.

[0076] An undoped semiconductor layer 152 may be deposited on and / or grown from a substrate 105, a base layer 105', or a combination thereof. In some embodiments, the undoped semiconductor layer 152 is formed by a selective epitaxial growth (SEG) process, which selectively deposits / grows semiconductor material on / from an exposed semiconductor surface. Therefore, the undoped semiconductor layer 152 may be referred to as an undoped epitaxial layer. The SEG process may use CVD techniques (e.g., vapor phase epitaxy (VPE), ultra-high vacuum CVD (UHV-CVD), LPCVD, PECVD, etc.), molecular beam epitaxy, other suitable processes, or combinations thereof. In some embodiments, the undoped semiconductor layer 152 is formed by a bottom-up deposition process. For example, semiconductor material may be deposited / grown on the base layer 105', while minimal (or no) semiconductor material may be deposited / grown on the semiconductor layer 120. In some embodiments, post-deposition etching may be performed to remove any semiconductor material that may have formed on the semiconductor layer 120.

[0077] An insulating layer 154 may be formed in the source / drain trench 140 above the undoped semiconductor layer 152. The insulating layer 154 partially fills the source / drain trench 140 and is disposed below the bottommost semiconductor layer 120. The insulating layer 154 may be disposed on the bottommost internal spacer 149 and / or the substrate layer 105'. The insulating layer 154 includes an electrically insulating material, such as a dielectric material, which can reduce unwanted leakage currents, such as currents that may undesirably flow through the substrate layer 105' between the doped semiconductor layers 156. In some embodiments, the insulating layer 154 includes a dielectric material, such as silicon nitride, silicon oxynitride, silicon carbonitride, silicon carbon oxynitride, silicon carbon oxynitride, other suitable dielectric materials, or combinations thereof. For example, the insulating layer 154 may be a silicon nitride layer.

[0078] The insulating layer 154 can be formed by depositing an insulating material over the device 100 (e.g., by CVD, PVD, other suitable processes, or combinations thereof) and etching the insulating material, such that the remaining portion of the insulating material is disposed over the undoped semiconductor layer 152. The deposited insulating material can be disposed on the sidewalls of the internal spacer 149, the top and sidewalls of the spacer 139, the top of the gate structure 130 (e.g., the top of the gate spacer 134 and the dummy gate stack 132), the sidewalls of the gate structure 130 (e.g., the gate spacer 134), the top and sidewalls of the isolation structure hard mask 126 (e.g., its isolation hard mask 128), the sidewalls of the semiconductor layer 120, and the sidewalls of the substrate layer 105'. In some embodiments, the thickness of the deposited insulating material over horizontally oriented surfaces (e.g., the top of components of the device 100) can be greater than the thickness of the deposited insulating material over vertically oriented surfaces (e.g., the sidewalls of components of the device 100). Therefore, the etching parameters can be adjusted to remove the vertically oriented portion of the insulating material. In such embodiments, due to the etch load effect, etching may also remove horizontally oriented portions of the insulating material located on top of the gate structure 130, top of the spacer 139, and top of the isolation hard mask 128, but does not (or negligibly) remove horizontally oriented and / or vertically oriented portions of the insulating material located at the bottom of the source / drain trench 140 (e.g., on the undoped semiconductor layer 152) (i.e., the etching process may thin such portions). In some embodiments, the deposited insulating material fills the source / drain trench 140, and etching recesses the insulating material at least to the bottom semiconductor layer 120.

[0079] A doped semiconductor layer 156 may be formed in the source / drain trench 140 above the insulating layer 154 and / or the undoped semiconductor layer 152. The doped semiconductor layer 156 fills the remaining portion of the source / drain trench 140 and is coupled to the edge / end of the semiconductor layer 120. As noted above, the doped semiconductor layer 156 may include a doped semiconductor layer 158 and a doped semiconductor layer 160. The doped semiconductor layer 158 may be formed above the semiconductor layer 120 and partially fill the source / drain trench 140, and the doped semiconductor layer 160 may be formed above the doped semiconductor layer 158 and / or the insulating layer 154 and fill the remaining portion of the source / drain trench 140. The doped semiconductor layer 158 may be located between the semiconductor layer 120 and the doped semiconductor layer 160, and the insulating layer 154 may be located between the doped semiconductor layer 160 and the undoped semiconductor layer 152. In some embodiments (e.g., Figure 3O The doped semiconductor layer 158 is discontinuous and formed of discrete and separate portions, each disposed at an end of a corresponding semiconductor layer 120. In other words, portions of the doped semiconductor layer 158 on adjacent semiconductor layers 120 are not connected to each other. In such embodiments, the doped semiconductor layer 160 may wrap around the doped semiconductor layer 158 and / or extend to and be disposed on the inner spacer 149. In some embodiments, one or more of the discrete, separate portions of the doped semiconductor layer 158 may wrap around the corresponding semiconductor layer 120, such that the discrete, separate portions are formed above the top and / or bottom of the corresponding semiconductor layer 120. In some embodiments, the discrete, separate portions may extend over and / or to the inner spacer 149. In some embodiments, one or more of the discrete, separate portions of the doped semiconductor layer 158 may be connected, and the doped semiconductor layer 160 may be partially or completely separated from the inner spacer 149 by the doped semiconductor layer 158. In some embodiments, the doped semiconductor layer 158 may be disposed between the inner spacer 149 and the doped semiconductor layer 160.

[0080] Doped semiconductor layers 158 and 160 comprise silicon, germanium, silicon-germanium, other suitable semiconductor materials, or combinations thereof. In some embodiments, doped semiconductor layers 158 and 160 comprise the same semiconductor material with different concentrations. For example, doped semiconductor layers 158 and 160 may comprise silicon-germanium and p-type dopants (e.g., boron and / or gallium), but with different germanium concentrations and / or different p-type dopant concentrations, such as in the case where the source / drain structure 150 is a p-type transistor. In such instances, doped semiconductor layer 158 may have a smaller germanium concentration (e.g., Ge%) and / or a smaller p-type dopant concentration (e.g., B%) than doped semiconductor layer 160. In other words, doped semiconductor layer 160 may be a heavily doped semiconductor layer, and doped semiconductor layer 158 may be a lightly doped semiconductor layer. In another example, doped semiconductor layers 158 and 160 may comprise silicon and n-type dopants (e.g., phosphorus and / or arsenic), but with different n-type dopant concentrations, such as in the case where the source / drain structure 150 is an n-type transistor. In such an example, doped semiconductor layer 158 may have a smaller n-type dopant concentration (e.g., P%) than doped semiconductor layer 160. In some embodiments, doped semiconductor layers 158 and 160 are formed of different semiconductor materials. In some embodiments, doped semiconductor layer 156 is formed of a material that provides compressive stress in channel layer 120' and / or includes dopants that provide compressive stress in channel layer 120', such as in the case where the source / drain structure 150 is a p-type transistor. In some embodiments, doped semiconductor layer 156 is formed of a material that provides tensile stress in channel layer 120' and / or includes dopants that provide tensile stress in channel layer 120', such as in the case where the source / drain structure 150 is an n-type transistor.

[0081] A doped semiconductor layer 158 may be deposited on and / or grown from semiconductor layer 120, and a doped semiconductor layer 160 may be deposited on and / or grown from doped semiconductor layer 158. In some embodiments, doped semiconductor layers 158 and 160 are formed by appropriate SEG processes, which may implement CVD deposition techniques (e.g., VPE, UHV-CVD, LPCVD, PECVD, etc.), molecular beam epitaxy, other suitable SEG processes, or combinations thereof. The SEG process may use gaseous and / or liquid precursors that interact with the composition of semiconductor layer 120, doped semiconductor layer 158, or combinations thereof. Epitaxial growth / deposition conditions can be adjusted to selectively deposit (grow) semiconductor materials (e.g., silicon-germanium and / or silicon) on semiconductor surfaces (e.g., semiconductor layer 120 and / or doped semiconductor layer 158) while restricting (or preventing) the growth of semiconductor materials from dielectric surfaces and / or non-semiconductor surfaces (e.g., internal spacers 149, dummy gate stacks 132, gate spacers 134, spacers 139, isolation hard mask structures 126 (e.g., their isolation hard mask 128) or combinations thereof). In some embodiments, doped semiconductor layer 158 and / or doped semiconductor layer 160 are doped during deposition (i.e., in-situ doping), such as by adding dopant to the source material of the SEG process. In some embodiments, doped semiconductor layer 158 and / or doped semiconductor layer 160 are doped after deposition, such as by an ion implantation process. In some embodiments, annealing is performed to activate the dopant in doped semiconductor layer 158, doped semiconductor layer 160, other source / drain regions / parts (such as source / drain junction implantation), or combinations thereof. The source / drain structure 150 can be fabricated to provide source / drain structures 150 with various dimensions. For example, in some embodiments, the width (e.g., along the y-direction) of the source / drain structure 150 differs from the thickness (e.g., along the z-direction) of the source / drain structure 150. In some embodiments, such dimensional differences are provided to the doped semiconductor layer 160 (e.g., its width may be greater than its thickness). In some embodiments, the width of the source / drain structure is greater than the width of the source / drain trench 140, such that the source / drain structure 150 (e.g., its doped semiconductor layer 160) extends over and / or beyond the outer sidewall of the spacer 139. In some embodiments, the source / drain structure 150 may extend over the isolation hard mask structure 126 (e.g., along the y-direction).

[0082] refer to Figure 3P and Figure 4PFabrication of device 100 may include forming a dielectric layer 170 over source / drain structures 150. The dielectric layer 170 may fill the gaps between adjacent gate structures 130 (such as the gaps between their gate spacers 134) and the gaps between adjacent source / drain structures 150. In some embodiments, as depicted, the dielectric layer 170 may cover an isolation structure hard mask 126 (e.g., its isolation hard mask 128). Forming the dielectric layer 170 may include: depositing a contact etch stop layer (CESL) 172; depositing an interlayer dielectric (ILD) layer 174 over the CESL 172; and performing CMP and / or other planarization processes until reaching the dummy gate stack 132 (e.g., its hard mask 138). In some embodiments, the planarization process may partially remove the hard mask 138 to expose the underlying dummy gate block 136 (e.g., a polysilicon gate). In some embodiments, the planarization process may reduce the height of the dummy gate stack 132 and / or the gate spacers 134.

[0083] ILD layer 174 includes a dielectric material comprising, for example, silicon oxide, carbon-doped silicon oxide, silicon nitride, silicon oxynitride, oxides formed from tetraethyl orthosilicate (TEOS), BSG, PSG, borosilicate glass, fluorosilicate glass, degel, aerogel, amorphous fluorinated carbon, parylene, benzocyclobutenyl (BCB) dielectric material, polyimide, other suitable dielectric materials, or combinations thereof. In some embodiments, ILD layer 174 includes a material having a dielectric constant (e.g., low k) that is less than the dielectric constant of the gate dielectric of the subsequently formed gate stack (e.g., less than the dielectric constant of its high k dielectric layer). In some embodiments, ILD layer 174 comprises a dielectric material having a dielectric constant of less than about 2.5 (i.e., an extremely low-k (ELK) dielectric material), such as porous silica, silicon carbide, carbon-doped oxides (e.g., SiCOH-based materials having, for example, Si–CH3 bonds), or combinations thereof, each adjusted / configured to exhibit a dielectric constant of less than about 2.5. CESL 172 comprises a material different from ILD layer 174, such as a dielectric material different from the dielectric material of ILD layer 174. For example, in the case where ILD layer 174 comprises a low-k dielectric material containing silicon and oxygen, CESL 172 may comprise silicon and nitrogen, such as silicon nitride or silicon oxynitride. ILD layer 174 and / or CESL 172 may have a multilayer structure and / or comprise multiple dielectric materials.

[0084] refer to Figure 3Q , Figure 4Q , Figure 3R , Figure 4R , Figure 5B and Figure 5CThe fabrication of device 100 may include a gate replacement process that replaces dummy gate stack 132 and sacrificial semiconductor layer 115 with gate stack 180. Gate stack 180 (referred to in some embodiments as a high-k / metal gate) is disposed between respective gate spacers 134, between respective internal spacers 149, between respective semiconductor layers 120 (also referred to as channel layers 120'), and between respective channel layers 120' and respective base layers 105'. One or more gate stacks 180 may include respective gate dielectrics 182 and respective gate electrodes 184. In the depicted embodiments, gate stacks 180 may, for example, surround and bond respective channel layers 120' in the YZ plane (see example...). Figure 5C In some embodiments, the gate stack 180 may wrap around and / or partially surround the respective channel layer 120' (i.e., disposed on at least both sides thereof).

[0085] refer to Figure 3Q , Figure 4Q and Figure 5B The etch process removes the dummy gate stack 132 from the gate structure 130 to form a gate opening 175. The gate opening 175 exposes a channel region including a semiconductor layer 120 and a sacrificial semiconductor layer 115. The gate opening 175 may further expose an isolation structure hard mask 126 (e.g., its isolation hard mask 128). In some embodiments, the etching process selectively removes the dummy gate block 135 (e.g., a polysilicon gate) while negligibly (or not at all) removing the dielectric layer 170 (e.g., ILD layers 174 and CESL 172), gate spacer 134, isolation hard mask 128, sacrificial semiconductor layer 115, semiconductor layer 120, or combinations thereof. In some embodiments, the etching process uses a patterned mask layer as an etching mask, wherein the patterned mask layer covers the dielectric layer 170 and / or the gate spacer 134. In some embodiments, the etching process also removes the dummy gate dielectric 135 (e.g., a dummy oxide layer) of the dummy gate stack 132. In some embodiments, the dummy gate dielectric 135 is retained after the etching process.

[0086] Furthermore, in some embodiments, the etching process selectively removes the sacrificial semiconductor layer 115 exposed by the gate opening 175, thereby forming a gap 178 in the channel region. The etching process may selectively remove the sacrificial semiconductor layer 115 relative to the substrate layer 105', semiconductor layer 120, isolation structure hard mask 126 (e.g., its isolation hard mask 128), gate spacer 134, or combinations thereof. In other words, the etching process removes the sacrificial semiconductor layer 115 while negligibly (or not at all) removing the substrate layer 105', semiconductor layer 120, isolation structure hard mask 126 (e.g., its isolation hard mask 128), gate spacer 134, or combinations thereof. In some embodiments, the etchant removes silicon germanium (e.g., the sacrificial semiconductor layer 115) at a higher rate than silicon (e.g., semiconductor layer 120 and substrate layer 105') and dielectric materials (e.g., isolation structure hard mask 126, gate spacer 134, etc.). In some embodiments, prior to the etching process, an oxidation process may be performed to convert the sacrificial semiconductor layer 115 into a semiconductor oxide layer (e.g., a silicon germanium oxide layer), and the etching process may remove the semiconductor oxide layer to form gaps 178.

[0087] After the sacrificial semiconductor layer 115 is removed, the semiconductor layer 120 remaining in the channel region is disposed above the substrate layer 105' (e.g., above its protrusions). In some embodiments, as depicted, each channel region includes three semiconductor layers 120, which may be referred to as channel layers 120'. The channel layers 120' are stacked vertically along the z-direction, and the channel layers 120' can provide three channels through which current can flow between the respective source / drain structures 150. In some embodiments, after the sacrificial semiconductor layer 115 is removed, an etching process may be performed to modify the profile of the channel layers 120' to provide its target size and / or target shape. For example, the etching process may provide the channel layers 120' having a cylindrical profile (e.g., nanowire), a rectangular profile (e.g., nanorod), a sheet profile (e.g., nanosheet), or any other suitable shape profile. In some embodiments, the channel layers 120' have nanoscale dimensions and may be referred to as "nanostructures". In some embodiments, the channel layers 120' have subnanoscale dimensions and / or other suitable dimensions.

[0088] refer to Figure 3R , Figure 4R and Figure 5CGate stack 180 is formed in gate opening 175 and / or gap 178. For example, gate dielectric 182 is formed in and partially fills gate opening 175 and gap 178. Gate dielectric 182 is disposed on a corresponding channel layer 120', a corresponding internal spacer 149, a corresponding gate spacer 134, an isolation structure hard mask 126 (e.g., its isolation hard mask 128), or a combination thereof. Gate dielectric 182 includes at least one dielectric layer, such as an interface layer and / or a high-k dielectric layer. The interface layer includes a dielectric material, such as SiO2, SiGeO x High-k dielectric layers consist of HfSiO, SiON, other dielectric materials, or combinations thereof. The interface layer is formed by thermal oxidation, chemical oxidation, ALD, CVD, other processes, or combinations thereof. High-k dielectric layers include high-k dielectric materials, which typically refer to dielectric materials with a dielectric constant greater than that of silicon dioxide, such as HfO2, HfSiO, HfSiO4, HfSiON, HfLaO, HfTaO, HfTiO, HfZrO, and HfAlO. x The high-k dielectric layer comprises ZrO, ZrO2, ZrSiO2, AlO, AlSiO, Al2O3, TiO, TiO2, LaO, LaSiO, LaO3, La2O3, Ta2O3, Ta2O5, Y2O3, SrTiO3, BaZrO, BaTiO3, (Ba,Sr)TiO3 (BST), HfO2-Al2O3, other high-k dielectric materials, or combinations thereof. The high-k dielectric layer is formed by ALD, CVD, PVD, oxide-based deposition processes, other processes, or combinations thereof. In some embodiments, the high-k dielectric layer comprises a hafnium-based oxide (e.g., HfO2) layer and / or a zirconium-based oxide (e.g., ZrO2) layer.

[0089] This disclosure also considers various configurations of the dielectric constant of the gate dielectric 182 (e.g., the dielectric constant of its high-k dielectric layer), the dielectric constant of the CESL 172, the dielectric constant of the ILD layer 174, and the dielectric constant of the gate spacer 134. In some embodiments, the dielectric constant of the CESL 172 is less than the dielectric constant of the gate dielectric 182. In some embodiments, the dielectric constant of the ILD layer 174 is less than the dielectric constant of the gate dielectric 182. In some embodiments, the dielectric constant of the gate dielectric 182 is at least twice the dielectric constant of the ILD layer 174. In some embodiments, the dielectric constant of the gate dielectric 182 is greater than the dielectric constants of the gate spacer 134, the CESL 172, and the ILD layer 174. In such an embodiment, the dielectric constant of CESL 172 may be greater than the dielectric constant of gate spacer 134 and / or the dielectric constant of ILD layer 174, and the dielectric constant of gate spacer 134 may be greater than, less than, or approximately the same as the dielectric constant of ILD layer 174.

[0090] A gate electrode 184 is formed in the gate opening 175 and the gap 178 and fills the remaining portions of the gate opening 175 and the gap 178. The gate electrode 184 is disposed on the gate dielectric 182. The gate electrode 184 includes a conductive layer formed of a conductive material, such as Al, Cu, Ti, Ta, W, Mo, Co, TaN, NiSi, CoSi, TiN, WN, TiAl, TiAlN, TaCN, TaC, TaSiN, other conductive materials, or combinations thereof. In some embodiments, the conductive layer includes a work function layer adjusted to have a desired work function (e.g., n-type work function or p-type work function). The function layer includes a function metal and / or alloy thereof, such as Ti, Ta, Al, Ag, Mn, Zr, W, Ru, Mo, TiC, TiAl, TiAlC, TiAlSiC, TaC, TaCN, TaSiN, TiSiN, TiN, TaN, TaSN, WN, WCN, ZrSi2, MoSi2, TaSi2, NiSi2, TaAl, TaAlC, TaSiAlC, TiAlN, or combinations thereof. In some embodiments, the conductive layer includes a bulk layer located above the gate dielectric and / or the function layer. The bulk layer may include Al, W, Cu, Ti, Ta, TiN, TaN, polysilicon, other suitable metals and / or alloys thereof, or combinations thereof. In some embodiments, the conductive layer includes a barrier layer located above the function layer and / or the gate dielectric. The barrier layer includes materials that can prevent component diffusion and / or reaction between adjacent layers and / or promote adhesion between adjacent layers, such as between the function layer and the bulk layer. In some embodiments, the barrier layer comprises a metal and nitrogen, such as titanium nitride, tantalum nitride, tungsten nitride, titanium silicon nitride, tantalum silicon nitride, other suitable metal nitrides, or combinations thereof.

[0091] Forming the gate stack 180 may include: depositing a gate dielectric material (e.g., an interface layer, a high-k dielectric layer, etc.) partially filling the gate opening 175 and / or gap 178; depositing a gate electrode material (e.g., a power function layer, a barrier layer, a bulk layer, etc.) over the gate dielectric material to fill the remaining portion of the gate opening 175 and / or gap 178; and performing a planarization process (e.g., CMP) to remove portions of the gate dielectric material above the dielectric layer 170 and / or portions of the gate electrode material above the dielectric layer 170. In some embodiments, fabrication of the device 100 may further include etching back the gate stack 180 and forming a hard mask (e.g., a self-aligned cover (SAC) structure) over the etched-back gate stack 180. The composition of the SAC structure differs from that of the dielectric layer 170 and / or the subsequently formed dielectric layer to achieve etch selectivity. In some embodiments, the SAC structure comprises silicon and nitrogen and / or carbon, such as silicon nitride, silicon oxynitride, silicon carbide, silicon carbide, silicon carbonitride, silicon carbonitride, silicon carbonitride, other silicon nitrides, other silicon carbides, or combinations thereof. In some embodiments, the SAC structure comprises metal and oxygen and / or nitrogen, such as aluminum oxide, aluminum nitride, aluminum oxynitride, zirconium oxide, zirconium nitride, hafnium oxide, zirconium alumina, other metal oxides, other metal nitrides, or combinations thereof.

[0092] Therefore, device 100 may include at least one transistor T. Transistor T may include a corresponding channel (e.g., channel layer 120'), a corresponding source / drain (e.g., source / drain structure 150), and a corresponding gate (e.g., gate stack 180). In some embodiments, transistor T is a p-type transistor. For example, transistor T may include a silicon channel (e.g., channel layer 120' may be a silicon layer) and a silicon-germanium epitaxial source / drain (e.g., doped semiconductor layer 156 may be a p-doped silicon-germanium structure). In some embodiments, transistor T is an n-type transistor. For example, transistor T may include a silicon channel (e.g., channel layer 120' may be a silicon layer) and a silicon epitaxial source / drain (e.g., doped semiconductor layer 156 may be an n-doped silicon structure). Gate stack 180 is disposed between the corresponding source / drain (e.g., source / drain structure 150). Figure 3R The internal spacer 149 is disposed between the gate stack 180 and the respective source / drain. Furthermore, the gate stack 180 engages a respective channel (e.g., channel layer 120'), and the respective channel extends between the respective source / drain (e.g., source / drain structure 150). Figure 3R In the described embodiment, transistor T is a GAA transistor. Therefore, the gate stack 180 can surround its respective channel layer and along the gate longitudinal direction ( Figure 5CThe gate stack 180 may include a gate dielectric (e.g., gate dielectric 182) and a gate electrode (e.g., gate electrode 184) surrounding its respective channel. In some embodiments, the gate stack 180 may wrap around and / or partially surround its respective channel layer (i.e., be disposed on at least both sides thereof), such as in the case where the transistor T is a forked transistor.

[0093] Because device 100 and its transistors (e.g., transistor T) are fabricated using a hard mask 128 with an isolation structure having the convex dot surface described herein, device 100 and / or its transistors exhibit improved performance and / or improved reliability. For example, refer to Figure 11 Figure 200 provides the threshold voltage (C) for devices fabricated with different isolation structure hard mask profiles (e.g., X1, X2, X3, X4, X5, X6, X7, and X8). eff AC-V t The effective capacitance as a function of the surrounding AC voltage is expressed as a percentage (%) of experimental results. Devices X1-X8 have various active region widths and / or various gate pitches. In plot 200, lines 202A and 202B correspond to the effective capacitance observed when devices X1-X8 are fabricated to provide an isolation structure hard mask with a concave top surface (also known as a smile top profile), as shown in the reference above. Figure 9A , Figure 9B and Figure 10 As described herein, lines 204A and 204B correspond to the effective capacitance observed when devices X1-X8 are fabricated to provide a hard mask of an isolation structure with a convex top surface (also known as a crying top profile), as described herein. As demonstrated by experimental results, the effective capacitance of devices X1-X8 is reduced by providing a hard mask of their isolation structure with a convex top surface. In some instances, the effective capacitance of the devices can be reduced by up to 1% by configuring their hard masks of the isolation structure with convex top surfaces as described herein, thereby improving device performance (e.g., improving their speed). In some instances, the effective conductance (i.e., the effective resistance (R0) of the devices is also observed. eff The reciprocal of (1 / R) effThe performance of isolation structures can be improved by configuring their hard masks to have convex tops as described herein. In some embodiments, improved device performance (e.g., reduced effective capacitance) is a result of improved step height uniformity provided when the hard mask of the isolation structure is configured to have convex tops. Improved step height uniformity can also improve device reliability and / or increase the oxide residue window (e.g., the amount of oxide residue that can be formed at the corner of the substrate layer 105' without impeding the complete formation of the gate stack 180 (e.g., its gate electrode 184) between the substrate layer 105' and the bottommost semiconductor layer 120). In some embodiments, improved step height uniformity can increase the oxide residue window by up to 1 nm, thereby significantly increasing process flexibility. Step height generally refers to the distance between the top of the isolation structure and the top of the substrate layer 105' (e.g., the semiconductor substrate in the channel region, over which the channel layer is formed). Different embodiments may have different advantages, and no particular advantage is required for any embodiment.

[0094] Figure 12 Flowcharts of part or all of a method 300 for fabricating a multi-gate device according to various embodiments of the present disclosure are provided. Method 300 may be implemented to fabricate devices described herein, such as device 100, and method 300 is similar in many respects to method 10, except that method 300 implements a pseudo (and / or one-time) oxide interposer (DOI). In block 315, method 300 includes forming an active region comprising a multilayer stack disposed over a substrate (e.g., a portion of a substrate). The multilayer stack includes a first sacrificial layer (e.g., a sacrificial semiconductor layer, such as a silicon-germanium layer) and a semiconductor layer (e.g., a silicon layer). In block 320, an isolation structure is formed around the active region (e.g., around its substrate). In block 325, an isolation structure hard mask is formed over the isolation structure. The isolation structure hard mask is formed adjacent to the substrate and is formed with convex tops and contours that can improve device performance and / or device reliability, as described herein. In some embodiments, the isolation structure and the isolation structure hard mask are disposed below the top of the substrate of the active region (e.g., below the top of its protrusion in the channel region), and the isolation structure hard mask may not extend above the top of the substrate of the active region. In block 330, a gate structure may be formed over a multilayer stack in the channel region. The gate structure may include a dummy gate stack and a gate spacer. The gate structure may extend over and interface with the isolation structure hard mask. In block 335, source / drain etching is performed to form source / drain trenches in the multilayer stack in the source / drain region. The source / drain trenches may be formed by removing a portion of the semiconductor layer, the sacrificial layer, and the substrate in the source / drain region.

[0095] After source / drain etching, method 300 includes: in block 340, removing a first sacrificial layer from the multilayer stack in the channel region to form a first gap between the semiconductor layers of the multilayer stack in the channel region; and in block 345, forming a second sacrificial layer (e.g., a sacrificial oxide layer, which may be referred to as DOI) in the first gap. In some embodiments, method 300 may further include: in block 350, recessing the second sacrificial layer to form an internal spacer notch between the ends of the semiconductor layers of the multilayer stack in the channel region; and in block 355, forming an internal spacer in the internal spacer notch. In block 360, method 300 includes forming a source / drain structure in a source / drain trench. Method 300 may include: in block 365, forming a dielectric layer (e.g., an interlayer dielectric layer and / or a contact etch stop layer) over the isolation structure hard mask and the source / drain structure. Method 300 may further include: in block 370, removing a dummy gate stack to form a gate opening; in block 375, removing a second sacrificial layer (e.g., a sacrificial oxide layer) to form a second gap between semiconductor layers of the multilayer stack in the channel region; and in block 380, forming a gate stack in the gate opening and the second gap. Embodiments of this disclosure contemplate additional processing. Additional steps may be provided before, during, and after method 300, and for additional embodiments of method 300, some of the described steps may be moved, replaced, or eliminated.

[0096] This document discloses a method for manufacturing a multi-gate device with improved performance (e.g., a multi-gate device with improved profile by providing an isolation structure hard mask). In some embodiments, the method includes: forming an isolation structure between a first active region and a second active region; and forming an isolation structure hard mask over the isolation structure. The top of the isolation structure is disposed at a distance below the top of a first substrate of the first active region and the top of a second substrate of the second active region. The thickness of the isolation structure hard mask is less than this distance, and forming the isolation structure hard mask is configured to provide an isolation structure hard mask with a convex top. In some embodiments, forming the isolation structure hard mask is further configured to provide an isolation structure hard mask having a first stepped height at the ends and a second stepped height in the middle that is less than the first stepped height. In some embodiments, forming the isolation structure hard mask is further configured to provide an isolation structure hard mask having an intermediate portion disposed between the end portions, wherein the intermediate portion is thicker than the end portions. In some embodiments, the method further includes: forming a gate stack over a first portion of the isolation structure hard mask; and forming a dielectric structure over a second portion of the isolation structure hard mask. In some embodiments, the method further includes forming an isolation structure hard mask pad over the isolation structure before forming the isolation structure hard mask.

[0097] In some embodiments, forming an isolation structure hard mask includes performing a deposition process and an etching process. In some embodiments, forming an isolation structure hard mask includes performing a modification process and a nitriding process. The modification process is performed after the deposition process, and the nitriding process is performed after the modification process and before the etching process. In some embodiments, performing a deposition process forms an isolation structure hard mask material, and performing a modification process includes reducing the thickness of the isolation structure hard mask material. In some embodiments, performing a deposition process includes depositing an amorphous silicon layer, and performing a nitriding process includes converting the amorphous silicon layer into a silicon nitride layer. In some embodiments, performing a modification process includes performing a hydrogen plasma treatment. In some embodiments, performing a nitriding process includes performing a nitrogen plasma treatment.

[0098] In some embodiments, the method includes forming a first multilayer stack and a second multilayer stack. The first multilayer stack includes a first semiconductor protrusion, the second multilayer stack includes a second semiconductor protrusion, and each of the first and second multilayer stacks includes a respective sacrificial layer and a respective semiconductor layer disposed over the first and second semiconductor protrusions, respectively. The method further includes: forming a dielectric structure between the first semiconductor protrusion of the first multilayer stack and the second semiconductor protrusion of the second multilayer stack; and forming a hard mask structure over the dielectric structure and between the first semiconductor protrusion of the first multilayer stack and the second semiconductor protrusion of the second multilayer stack. The hard mask structure is configured to provide an end of the hard mask structure having a first stepped height and an intermediate portion of the hard mask structure having a second stepped height less than the first stepped height. The method further includes replacing the respective sacrificial layers of the first and second multilayer stacks with gate stacks, wherein the gate stacks are formed over the hard mask structure. In some embodiments, forming the dielectric structure includes forming a shallow trench isolation structure.

[0099] In some embodiments, forming a hard mask structure includes forming a hard mask layer in a trench between a first multilayer stack and a second multilayer stack. The hard mask layer is formed over the first multilayer stack, the second multilayer stack, and the dielectric structure. Forming a hard mask structure may further include forming a dummy layer in the trench between the first multilayer stack and the second multilayer stack. The dummy layer covers the portion of the hard mask layer located above the top of the dielectric structure and between a first semiconductor protrusion of the first multilayer stack and a second semiconductor protrusion of the second multilayer stack. Forming a hard mask structure may further include: removing the dummy layer after removing the hard mask layer from above the top of the first multilayer stack and the top of the second multilayer stack; and removing the hard mask layer from above the sidewalls of the first multilayer stack and the sidewalls of the second multilayer stack after removing the dummy layer.

[0100] In some embodiments, forming a hard mask layer includes forming a silicon nitride layer having a varying thickness. In some embodiments, forming a hard mask structure includes: depositing an amorphous silicon layer; performing a hydrogen plasma treatment on the amorphous silicon layer; and performing a nitrogen plasma treatment after performing the hydrogen plasma treatment to convert the amorphous silicon layer into a silicon nitride layer. In some embodiments, performing the hydrogen plasma treatment includes adjusting the duration of the hydrogen plasma treatment to increase the convexity of the top of the portion of the amorphous silicon layer located above the top of the dielectric structure. In some embodiments, performing the hydrogen plasma treatment includes adjusting the hydrogen plasma treatment parameters to reduce the overhang of the amorphous silicon layer at the top corner of the first multilayer stack and the overhang of the amorphous silicon layer at the top corner of the second multilayer stack. In some embodiments, depositing the amorphous silicon layer includes adjusting the deposition parameters to provide an amorphous silicon deposition rate above the top of the dielectric structure, the top of the first multilayer stack, and the top of the second multilayer stack that is greater than the amorphous silicon deposition rate above the sidewalls of the first multilayer stack and the sidewalls of the second multilayer stack.

[0101] In some embodiments, the device structure includes: a semiconductor protrusion; a semiconductor layer disposed above the semiconductor protrusion; an isolation structure disposed adjacent to the semiconductor protrusion; and an isolation structure hard mask disposed on the isolation structure. In some embodiments, the top of the isolation structure is disposed below the top of the semiconductor protrusion at a certain distance, and the thickness of the isolation structure hard mask is less than this distance. In some embodiments, the end of the isolation structure hard mask has a first stepped height, the middle of the isolation structure hard mask has a second stepped height, and the second stepped height is less than the first stepped height. The device structure may further include a gate stack disposed between the semiconductor protrusion and the semiconductor layer. The gate stack at least surrounds (e.g., encloses) the semiconductor layer, and the gate stack extends above the isolation structure hard mask. In some embodiments, the isolation structure hard mask has a convex top surface. In some embodiments, the isolation structure includes a silicon oxide block, and the isolation structure hard mask includes a silicon nitride mask.

[0102] Some embodiments of this application provide a method for manufacturing a device structure, comprising: forming an isolation structure between a first active region and a second active region, wherein the top of the isolation structure is disposed at a certain distance below the top of a first substrate of the first active region and the top of a second substrate of the second active region; and forming an isolation structure hard mask above the isolation structure, wherein the thickness of the isolation structure hard mask is less than the distance, and the formation of the isolation structure hard mask is configured to provide the isolation structure hard mask having a convex top.

[0103] In some embodiments, forming the isolation structure hard mask includes performing a deposition process and an etching process. In some embodiments, forming the isolation structure hard mask includes performing a modification process and a nitriding process, wherein the modification process is performed after the deposition process, and the nitriding process is performed after the modification process and before the etching process. In some embodiments, performing the deposition process forms an isolation structure hard mask material, and performing the modification process includes reducing the thickness of the isolation structure hard mask material. In some embodiments, performing the deposition process includes depositing an amorphous silicon layer, and performing the nitriding process includes converting the amorphous silicon layer into a silicon nitride layer. In some embodiments, performing the modification process includes performing a hydrogen plasma treatment, and performing the nitriding process includes performing a nitrogen plasma treatment. In some embodiments, forming the isolation structure hard mask is further configured to provide an isolation structure hard mask having an intermediate portion disposed between end portions, wherein the intermediate portion is thicker than the end portions. In some embodiments, the method further includes: forming a gate stack over a first portion of the isolation structure hard mask; and forming a dielectric structure over a second portion of the isolation structure hard mask. In some embodiments, the method further includes forming an isolation structure hard mask pad over the isolation structure before forming the isolation structure hard mask.

[0104] Other embodiments of this application provide a method for manufacturing a device structure, comprising: forming a first multilayer stack and a second multilayer stack, wherein the first multilayer stack includes a first semiconductor protrusion, the second multilayer stack includes a second semiconductor protrusion, and the first multilayer stack and the second multilayer stack include a corresponding sacrificial layer and a corresponding semiconductor layer respectively disposed above the first semiconductor protrusion and the second semiconductor protrusion; forming a dielectric structure between the first semiconductor protrusion of the first multilayer stack and the second semiconductor protrusion of the second multilayer stack, wherein the first multilayer stack includes a first active region, the second multilayer stack includes a second active region, and the dielectric structure has a curved top profile; forming a hard mask structure above the dielectric structure and between the first semiconductor protrusion of the first multilayer stack and the second semiconductor protrusion of the second multilayer stack, wherein the hard mask structure is configured to provide an end of the hard mask structure having a first stepped height and an intermediate portion of the hard mask structure having a second stepped height less than the first stepped height; and replacing the corresponding sacrificial layers of the first multilayer stack and the second multilayer stack with gate stacks, wherein the gate stacks are formed above the hard mask structure.

[0105] In some embodiments, forming the hard mask structure over the dielectric structure and between the first semiconductor protrusion of the first multilayer stack and the second semiconductor protrusion of the second multilayer stack includes: forming a hard mask layer in a trench between the first multilayer stack and the second multilayer stack, wherein the hard mask layer is formed over the first multilayer stack, the second multilayer stack, and the dielectric structure; forming a dummy layer in the trench between the first multilayer stack and the second multilayer stack, wherein the dummy layer covers the portion of the hard mask layer located above the top of the dielectric structure and between the first semiconductor protrusion of the first multilayer stack and the second semiconductor protrusion of the second multilayer stack; removing the dummy layer after removing the hard mask layer from above the top of the first multilayer stack and the top of the second multilayer stack; and removing the hard mask layer from above the sidewalls of the first multilayer stack and the sidewalls of the second multilayer stack after removing the dummy layer. In some embodiments, forming the hard mask layer includes forming a silicon nitride layer having a varying thickness. In some embodiments, forming the hard mask structure over the dielectric structure and between the first semiconductor protrusion of the first multilayer stack and the second semiconductor protrusion of the second multilayer stack includes: depositing an amorphous silicon layer; performing a hydrogen plasma treatment on the amorphous silicon layer; and performing a nitrogen plasma treatment after performing the hydrogen plasma treatment to convert the amorphous silicon layer into a silicon nitride layer. In some embodiments, performing the hydrogen plasma treatment includes adjusting the duration of the hydrogen plasma treatment to increase the convexity of the top of the portion of the amorphous silicon layer located above the top of the dielectric structure. In some embodiments, performing the hydrogen plasma treatment includes adjusting the hydrogen plasma treatment parameters to reduce the overhang of the amorphous silicon layer at the top corner of the first multilayer stack and the overhang of the amorphous silicon layer at the top corner of the second multilayer stack. In some embodiments, depositing the amorphous silicon layer includes adjusting the deposition parameters to provide an amorphous silicon deposition rate above the top of the dielectric structure, the top of the first multilayer stack, and the top of the second multilayer stack that is greater than the amorphous silicon deposition rate above the sidewalls of the first multilayer stack and the sidewalls of the second multilayer stack. In some embodiments, forming the dielectric structure includes forming a shallow trench isolation structure between the first semiconductor protrusion of the first multilayer stack and the second semiconductor protrusion of the second multilayer stack.

[0106] Some embodiments of this application provide a device structure including: a semiconductor protrusion; a semiconductor layer disposed above the semiconductor protrusion; an isolation structure disposed adjacent to the semiconductor protrusion, wherein the top of the isolation structure is disposed at a certain distance below the top of the semiconductor protrusion, and the top of the isolation structure is non-planar; an isolation structure hard mask disposed on the isolation structure, wherein the thickness of the isolation structure hard mask is less than the distance, the end of the isolation structure hard mask has a first step height, the middle of the isolation structure hard mask has a second step height, and the second step height is less than the first step height; and a gate stack disposed between the semiconductor protrusion and the semiconductor layer, wherein the gate stack at least covers the semiconductor layer, the gate stack extends above the isolation structure hard mask, and the gate stack includes a gate dielectric and a gate electrode.

[0107] In some embodiments, the isolation structure hard mask has a convex top surface. In some embodiments, the isolation structure comprises a silicon oxide block, and the isolation structure hard mask comprises a silicon nitride mask.

[0108] The foregoing outlines features of several embodiments to enable those skilled in the art to better understand various aspects of the embodiments of this disclosure. Those skilled in the art should understand that they can readily use the embodiments of this disclosure as a basis to design or modify other processes and structures for performing the same purposes and / or achieving the same advantages as the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of the embodiments of this disclosure, and that various changes, substitutions, and alterations can be made therein without departing from the spirit and scope of the embodiments of this disclosure.

Claims

1. A method for manufacturing a device structure, comprising: An isolation structure is formed between a first active region and a second active region, wherein the top of the isolation structure is disposed at a certain distance below the top of a first substrate of the first active region and the top of a second substrate of the second active region; and An isolation structure hard mask is formed above the isolation structure, wherein the thickness of the isolation structure hard mask is less than the distance, and the formation of the isolation structure hard mask is configured to provide the isolation structure hard mask having a convex top.

2. The method according to claim 1, wherein, Forming the isolation structure hard mask includes performing a deposition process and an etching process.

3. The method according to claim 2, wherein, Forming the isolation structure hard mask includes performing a modification process and a nitriding process, wherein the modification process is performed after the deposition process, and the nitriding process is performed after the modification process and before the etching process.

4. The method according to claim 3, wherein, The deposition process is performed to form an isolation structure hard mask material, and the modified process includes reducing the thickness of the isolation structure hard mask material.

5. The method according to claim 3, wherein, The deposition process includes depositing an amorphous silicon layer, and the nitriding process includes converting the amorphous silicon layer into a silicon nitride layer.

6. The method according to claim 3, wherein, Implementing the modified process includes performing hydrogen plasma treatment, and implementing the nitriding process includes performing nitrogen plasma treatment.

7. The method according to claim 1, wherein, The hard mask forming the isolation structure is further configured to provide a hard mask having an intermediate portion disposed between the end portions, wherein the intermediate portion is thicker than the end portions.

8. The method according to claim 1, further comprising: A gate stack is formed above the first portion of the hard mask of the isolation structure; as well as A dielectric structure is formed above the second part of the hard mask of the isolation structure.

9. A method for manufacturing a device structure, comprising: A first multilayer stack and a second multilayer stack are formed, wherein the first multilayer stack includes a first semiconductor protrusion, the second multilayer stack includes a second semiconductor protrusion, and the first multilayer stack and the second multilayer stack include a corresponding sacrificial layer and a corresponding semiconductor layer respectively disposed above the first semiconductor protrusion and the second semiconductor protrusion; A dielectric structure is formed between the first semiconductor protrusion of the first multilayer stack and the second semiconductor protrusion of the second multilayer stack, wherein the first multilayer stack includes a first active region, the second multilayer stack includes a second active region, and the dielectric structure has a curved top profile. A hard mask structure is formed above the dielectric structure and between the first semiconductor protrusion of the first multilayer stack and the second semiconductor protrusion of the second multilayer stack, wherein the hard mask structure is configured to provide an end of the hard mask structure having a first stepped height and a middle portion of the hard mask structure having a second stepped height less than the first stepped height; and The respective sacrificial layers of the first multi-stack and the second multi-stack are replaced with gate stacks, wherein the gate stacks are formed over the hard mask structure.

10. A device structure, comprising: Semiconductor protrusion; A semiconductor layer is disposed above the semiconductor protrusion; An isolation structure is disposed adjacent to the semiconductor protrusion, wherein the top of the isolation structure is disposed at a certain distance below the top of the semiconductor protrusion, and the top of the isolation structure is non-planar; An isolation structure hard mask is disposed on the isolation structure, wherein the thickness of the isolation structure hard mask is less than the distance, the ends of the isolation structure hard mask have a first stepped height, the middle of the isolation structure hard mask has a second stepped height, and the second stepped height is less than the first stepped height; and A gate stack is disposed between the semiconductor protrusion and the semiconductor layer, wherein the gate stack at least covers the semiconductor layer, the gate stack extends over the isolation structure hard mask, and the gate stack includes a gate dielectric and a gate electrode.

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