Semiconductor device and method of manufacturing a semiconductor device

Abstract

According to various embodiments, a method of fabricating a semiconductor device includes depositing a source / drain epitaxial feature including a dopant over a source / drain region of an active region of a semiconductor device structure formed on a front side of a substrate. According to various embodiments, the method further includes etching a backside opening in the substrate to expose a backside surface of the source / drain epitaxial feature, performing a pre-amorphization process on the backside surface of the source / drain epitaxial feature, performing an anneal operation to generate heat within the backside surface of the source / drain epitaxial feature, and depositing a silicide layer on the backside surface of the source / drain epitaxial feature. Embodiments of the present application also relate to semiconductor devices and methods of fabricating semiconductor devices.

Description

Technical Field

[0001] Embodiments of this application relate to semiconductor devices and methods of manufacturing semiconductor devices. Background Technology

[0002] The integrated circuit (IC) industry has experienced rapid growth, driven by continuous technological advancements in materials and circuit design. These advancements have enabled successive generations of ICs to have components with smaller and more complex circuitry than their predecessors. Over time, the functional density of ICs (i.e., the number of interconnect devices per unit chip area) has generally increased, while the minimum geometry (the smallest component or line that can be formed using a given manufacturing process) has decreased. This trend of device scaling has already provided significant benefits, including improved production efficiency and reduced manufacturing costs. However, continued scaling also introduces greater complexity into IC handling and manufacturing, requiring corresponding innovations in manufacturing technologies to fully realize the advantages of advanced IC designs. Summary of the Invention

[0003] Some embodiments of this application provide a method of manufacturing a semiconductor device, comprising: depositing a source / drain epitaxial component comprising a dopant over a source / drain region of an active region of a semiconductor device structure formed on a front side of a substrate, wherein the source / drain epitaxial component includes a first layer and a second layer, the first layer being adjacent to a channel region of the active region, and the second layer being spaced apart from the channel region of the active region by the first layer, wherein a first concentration of the dopant in the first layer varies relative to a second concentration of the dopant in the second layer; etching a back-side opening in the substrate to expose a back-side surface of the source / drain epitaxial component; performing a pre-amorphization process on the back-side surface of the source / drain epitaxial component; performing an annealing operation to generate heat within the back-side surface of the source / drain epitaxial component; and depositing a silicide layer on the back-side surface of the source / drain epitaxial component.

[0004] Other embodiments of this application provide a method for manufacturing a semiconductor device, comprising: performing processing operations to form a back-side interconnect structure of the semiconductor device, the semiconductor device including source / drain epitaxial components located in an active region formed on a front side of a substrate, an interlayer dielectric layer disposed on the front side of the substrate above the source / drain epitaxial components, and source / drain contacts extending through the interlayer dielectric layer and electrically coupled to the source / drain epitaxial components, wherein a first conductivity of the source / drain contacts is greater than a second conductivity of the source / drain epitaxial components, the processing operations including: depositing a refractory metal layer above a back-side surface of the source / drain epitaxial components, and forming a silicide layer by performing a microwave annealing operation by exposing the back-side surface of the source / drain epitaxial components to microwave radiation, the microwave radiation generating thermal and electrical repairs to the back-side surface of the source / drain epitaxial components.

[0005] Further embodiments of this application provide a semiconductor device comprising: a semiconductor substrate having a front side and a back side opposite to the front side; a first interconnect structure disposed on the front side of the semiconductor substrate and extending over an active region, the first interconnect structure including a plurality of dielectric layers interleaved with a plurality of etch stop layers, and a plurality of front-side metal lines disposed in the plurality of dielectric layers; a second interconnect structure disposed on the back side of the semiconductor substrate, including a back-side metal line; a conductive via extending through the semiconductor substrate and electrically connecting the back-side metal line to a source / drain component of the active region; and a metal silicide formed between the conductive via and the source / drain component, wherein the metal silicide and the source / drain component include a dopant having a dopant concentration having a maximum value within the metal silicide. Attached Figure Description

[0006] Various aspects of the embodiments of this disclosure will be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard industry practice, the various components are not drawn to scale. In fact, for clarity of discussion, the dimensions of the various components may be arbitrarily increased or decreased.

[0007] Figure 1 This is a layout diagram showing a plan view of a semiconductor device according to various embodiments.

[0008] Figure 2A This is a layout diagram showing a plan view of a semiconductor device according to various embodiments.

[0009] Figure 2B It is a vertical cross-sectional view of a semiconductor device structure including electrical contacts (electrical contacts including conductive contact vias and metal wires) according to various embodiments.

[0010] Figure 2C According to various embodiments Figure 2A and Figure 2B A vertical cross-sectional view of a portion of a semiconductor device.

[0011] Figure 3A This is a vertical cross-sectional view of a semiconductor device including a front-side interconnect structure and a back-side interconnect structure according to various embodiments.

[0012] Figure 3B According to various embodiments Figure 3A A vertical cross-sectional view of a portion of a semiconductor device.

[0013] Figure 4A , Figure 4B , Figure 4C and Figure 4D According to various embodiments, for Figure 3A and Figure 3B A vertical cross-sectional view of the semiconductor structure used in the fabrication of the semiconductor structure.

[0014] Figure 5A It is a graph showing the time-dependent temperature measurements of various points in a semiconductor device subjected to laser annealing pulses, according to various embodiments.

[0015] Figure 5B It is carried out according to the instructions of the various embodiments. Figure 5A A vertical cross-sectional view of a semiconductor device at a point where temperature is measured.

[0016] Figure 6 It is a graph showing the change of germanium concentration with depth within the semiconductor device according to various embodiments.

[0017] Figure 7 The table schematically illustrates the repair mechanisms triggered by the microwave annealing process according to various embodiments.

[0018] Figure 8A This is a vertical cross-sectional view of a test structure used to determine a non-thermal repair mechanism according to various embodiments.

[0019] Figure 8B yes Figure 8A The graph shows the sheet resistance of the test structure that has undergone different annealing conditions.

[0020] Figure 9 This is a flowchart of the operation of a method for manufacturing a semiconductor device according to various embodiments.

[0021] Figure 10 This is a flowchart of the operation of a method for manufacturing a semiconductor device according to various embodiments. Detailed Implementation

[0022] The following disclosure provides numerous different embodiments or instances for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below to simplify embodiments of this disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first component on or over a second component may include embodiments where the first and second components are in direct contact, and may also include embodiments where one or more additional components may be formed between the first and second components, such that the first and second components are not in direct contact. Furthermore, reference numerals and / or characters may be repeated in various instances of embodiments of this disclosure. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0023] Furthermore, for ease of description, this document may use spatial relative terms such as “below,” “under,” “lower,” “above,” and “upper” to describe the relationship between one element or component and another (or other) element or component as shown in the figures. In addition to the orientations depicted in the figures, spatial relative terms are intended to include different orientations of the device in use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein may be interpreted accordingly. Furthermore, the term “made of” may mean either “comprising” or “consisting of.” In embodiments of this disclosure, the phrase “one of A, B, and C” means “A, B, and / or C” (A, B, C, A and B, A and C, B and C, or A, B, and C) and does not mean an element from A, an element from B, and an element from C, unless otherwise described.

[0024] The disclosed embodiments advantageously provide a semiconductor device structure with back-side source / drain contacts that exhibit reduced contact resistance due to a processing operation involving annealing to generate heat within the back-side surface of the source / drain epitaxial components. The annealing operation is performed after a pre-amorphization process and dopant implantation, and is carried out using either a high-energy, short-duration laser annealing process or a low-temperature microwave annealing process. Laser annealing provides localized heating that enhances dopant activation and induces solid-phase epitaxial regrowth (SPER) of the amorphous regions on the back-side surface of the source / drain epitaxial layer, while maintaining relatively low heating in other parts of the semiconductor device structure. Microwave annealing provides delocalized heating of the semiconductor device structure at a relatively lower temperature than laser annealing. Microwave annealing results in both thermal and non-thermal repair of the amorphous regions on the back-side surface of the source / drain epitaxial layer and further facilitates dopant activation. The disclosed embodiments exhibit improved device performance and reduced RC time delay due to the reduced contact resistance of the back-side source / drain contacts.

[0025] Figure 1 This is a layout diagram 100 illustrating a plan view of a semiconductor device according to various embodiments. Layout diagram 100 includes layout patterns corresponding to an oxide diffusion (OD) layer (referred to as "OD" in the legend) and a gate layer (referred to as "GL" in the legend). In some embodiments, the layout pattern included in the OD layer (referred to as the "OD layout pattern") indicates the formation of various active regions of the semiconductor device, and the layout pattern included in the GL layer (referred to as the "GL layout pattern") indicates the formation of a corresponding gate structure. In a corresponding embodiment, the gate structure 215 (e.g., see...) Figure 2B This corresponds to a polysilicon gate structure or a metal gate structure formed using a polysilicon structure as a sacrificial placeholder.

[0026] Figure 1 Some of the OD layout patterns in the diagram correspond to patterns formed by subtracting the removed portions defined by the OD isolation pattern group from a repeating OD pattern group. Similarly, Figure 1 The GL layout pattern in the diagram corresponds to the resulting pattern formed by subtracting the removed portion defined by the gate isolation pattern group from the repeating GL pattern group (e.g., using photolithographic patterning and etching processes to remove portions of the OD and GL patterns).

[0027] exist Figure 1 In the diagram, layout 100 corresponds to a portion of a circuit block. The circuit block can be a memory cell array, which includes multiple circuit cells (e.g., memory cells based on exemplary SRAM cells). For example, cell regions 101 and 103 can represent two memory cells in the memory cell array. Figure 1The structure is not limited to SRAM. In this respect, the structure of layout diagram 100 can be configured as a logic device.

[0028] exist Figure 1 In the layout diagram 100, among other aspects, OD layout patterns 111, 112, 114, 115, 116, 117, 118, and 119 indicating the active regions of the resulting semiconductor device. In this embodiment, the semiconductor device includes active regions corresponding to OD layout patterns 111, 114, 115, and 118 for forming p-type transistors, and active regions corresponding to OD layout patterns 112, 116, 117, and 119 for forming n-type transistors. In some embodiments, the active regions extend along a first horizontal direction (e.g., the X direction) and are located on or at least partially embedded in the substrate 210 of the semiconductor device (e.g., see...). Figure 2B ).exist Figure 1 In the layout diagram 100, among other things, layout patterns 122, 126, 127, 128, and 129 are included to indicate the gate structure of the resulting semiconductor device. In some embodiments, the gate structure extends along a second horizontal direction (e.g., the Y direction) and is positioned above the corresponding active region.

[0029] For example, to form a memory cell corresponding to cell region 101, two pull-down transistors PD1 and PD2 are defined based on gate structures corresponding to GL layout patterns 126 and 127 that overlap with the active regions corresponding to OD layout pattern 112. Two pull-up transistors PU1 and PU2 are defined based on gate structures corresponding to GL layout patterns 126 and 127 that overlap with the active regions corresponding to OD layout pattern 114. Furthermore, two write transfer gate transistors WPG1 and WPG2 are defined based on gate structures corresponding to GL layout patterns 122 and 128 that overlap with the active regions corresponding to OD layout pattern 112, and a read transfer gate transistor RPG is defined based on a gate structure corresponding to GL layout pattern 129 that overlaps with the active regions corresponding to OD layout pattern 114.

[0030] Figure 2A This is a layout diagram showing a plan view of the semiconductor device 200, and Figure 2B According to the various embodiments along Figure 2A A vertical cross-sectional view of the semiconductor device along line B-B'. At this point, Figure 2A The layout diagram is Figure 1 A simplified version of the layout diagram 100, in which the indications of n-type transistors (WPG1, PD1, PD2, WPG2) and p-type transistors (PU1, PU2, RPG) are omitted. Figure 2B The vertical plane of the cross-sectional view (i.e., Figure 2BThe XZ plane in the middle) is composed of Figure 2A The section B-B' is indicated. This plane cuts through a segment of the OD layout pattern 112, which includes multiple transistor structures configured as gate-all-around (GAA) transistor devices. Figure 2B The embodiments (including GAA transistor devices) are provided by way of example only, and various other semiconductor devices (e.g., planar field-effect transistors (FETs), fin field-effect transistors (FinFETs), complementary field-effect transistors (CFETs), etc.) are possible in other embodiments.

[0031] Figure 2B and Figure 2C This is a vertical cross-sectional view of a portion of the semiconductor device 200 according to various embodiments (including the conductive contact via 202 connected to the metal line 204a). Figure 2C The vertical plane of the cross-sectional view (i.e., Figure 2C The YZ plane in the middle) is composed of Figure 2B The cross section C-C' is indicated. The semiconductor device 200 includes a first device portion 206a formed in a series of front-end process (FEOL) processes, a second device portion 206b formed in a series of middle-end process (MEOL) processes, and a third device portion 206c formed in a series of back-end process (BEOL) processes.

[0032] The first device portion 206a is configured as a gate-all-around (GAA) transistor and includes multiple semiconductor layers stacked along the thickness direction (i.e., the Z direction) and configured as a stacked channel region 208. Although in Figure 2B The embodiments shown depict three stacked channel regions 208, but the embodiments disclosed herein are not limited thereto, and in other embodiments, various numbers of channel regions ≥1 (e.g., one channel region 208, two channel regions 208, four channel regions 208, etc.) are possible.

[0033] The first device portion 206a also includes a gate structure 215 surrounding each of the stacked channel regions 208. The gate structure 215 includes a conductive material 211 separated from the stacked channel regions 208 by a gate dielectric layer 212. The first device portion 206a also includes doped source / drain components comprising a semiconductor epitaxial layer (214a, 214b) formed over source / drain regions at opposite ends of the stacked channel regions 208 along the width direction (i.e., the X direction) and a plurality of dielectric spacers 216 electrically separating the gate structure 215 from the source / drain semiconductor epitaxial layers (214a, 214b). According to various embodiments, the source / drain epitaxial components (214a, 214b) include a first layer 214a and a second layer 214b, the first layer 214a being adjacent to the channel region 208 and the second layer 214b being spaced apart from the channel region 208 by the first layer 214a. According to various embodiments, the first concentration of the dopant in the first layer 214a varies relative to the second concentration of the dopant in the second layer 214b.

[0034] A first interlayer dielectric (ILD) layer 218a is formed above the source / drain semiconductor epitaxial layers (214a, 214b), and a contact etch stop layer 220 is formed between the source / drain semiconductor epitaxial layers (214a, 214b) and the first ILD layer 218a. Source / drain contacts 222a are formed in the first ILD layer 218a. The source / drain contacts 222a penetrate the contact etch stop layer 220 and form conductive contacts with the source / drain semiconductor epitaxial layers (214a, 214b). A conductive contact via 202 forms conductive contacts with the source / drain contacts 222a and with the metal line 204a, as shown in the reference. Figure 2C More detailed description.

[0035] refer to Figure 2C Conductive contact vias 202 (VD) are formed within a second ILD layer 218b, which is formed above a first ILD layer 218a. A first etch stop layer 224a is formed between the first ILD layer 218a and the second ILD layer 218b. Metal lines 204a are formed in a third ILD layer 218c, which is formed above the second ILD layer 218b, and a second etch stop layer 224b is formed between the second ILD layer 218b and the third ILD layer 218c (e.g., see...). Figure 2B At least one of the conductive contact via 202 and the metal wire 204a includes a metallic filler material, such as at least one of Mo, W, Ru, Al, Au, Ag, Cu, Mn, Ni, Fe, Pt, Ta, Nb, Zr, Re, Ir, and alloys thereof. For example, in Figure 2CIn some embodiments, the conductive contact via 202 comprises W, Mo, or Ru, and the metal wire 204a comprises Cu. These conductive materials are provided by way of example only, and other conductive materials are possible in other embodiments. In some embodiments, the conductive contact via 202 does not include a barrier layer, and the metal wire 204a includes a barrier layer 226 that at least covers the sidewalls of the metal filler material.

[0036] In some embodiments, the first ILD layer 218a, the second ILD layer 218b, and the third ILD layer 218c are made of silicon oxide, silicon nitride, silicon oxynitride (SiON), SiOCN, SiCN, fluorine-doped silicate glass (FSG), or a low-k dielectric material, and are formed by low-pressure chemical vapor deposition (LP-CVD), plasma-enhanced CVD (PE-CVD), PVD, ALD, flowable CVD, or any suitable technique. In some embodiments, the etch stop layers (224a, 224b) and the ILD layers (218a, 218b, 218c) are made of different materials. In some embodiments, the etch stop layers (224a, 224b) are made of nitrides, such as silicon nitride, titanium nitride, or tantalum nitride. The etch stop layers (224a, 224b) can be formed by atomic layer deposition (ALD), physical vapor deposition (PVD), CVD, electron beam evaporation, or any other suitable technique. In some embodiments, the etch stop layer (224a, 224b) has a thickness ranging from about 5 nm to about 40 nm, and in other embodiments, a thickness ranging from about 10 nm to about 20 nm.

[0037] In some embodiments, a barrier layer 226 is formed between the Cu metal filler material of the metal line 204a and the third ILD layer 218c, and is a metal backing layer comprising one of Ti, Ta, TiN, TaN, WN, TiC, TaC, and WC. The barrier layer 226 can be deposited using various techniques, such as ALD or CVD. Deposition of the barrier layer 226 can be performed at elevated temperatures. For example, during ALD deposition of the barrier layer 226, according to some embodiments, the structure is heated at a temperature ranging from about 100°C to about 500°C, and in other embodiments, at a temperature ranging from about 150°C to about 350°C.

[0038] According to some embodiments, a first metal silicide layer 228a is formed at the interface between the source / drain contact 222a and the source / drain semiconductor epitaxial layers (214a, 214b). According to one embodiment, a transition metal such as nickel is deposited over an exposed silicon or silicon-germanium surface by PVD or CVD. A subsequent thermal annealing step initiates a solid-state reaction between the metal and the underlying semiconductor, resulting in the formation of the metal silicide. In some embodiments, for the n-type region formed from epitaxial silicon, the process produces nickel silicide (NiSi), which provides low resistivity and good thermal stability.

[0039] In some embodiments, for p-type regions formed from silicon and germanium, the silicide process requires additional adjustments to accommodate the influence of germanium content. In some embodiments, a nickel-platinum alloy is used to promote uniform silicide formation and suppress agglomeration or phase separation. The final silicide composition can vary depending on the local Ge concentration, and process conditions can be adjusted to ensure consistent electrical and morphological properties across different device regions. In some embodiments, the process uses selective wet etching to remove unreacted metal, leaving self-aligned silicide contacts suitable for further metallization.

[0040] Other embodiments utilize different transition metals to form silicides, such as titanium, molybdenum, or alloys including molybdenum-titanium. Titanium silicide (TiSi2) and molybdenum silicide (MoSi2) can be formed using similar deposition and annealing processes and offer different electrical and thermal properties. MoTiSi alloys can also be used to tailor chip resistance and thermal stability for specific device requirements. The choice between these materials depends on factors including process compatibility, junction depth, and desired contact resistance.

[0041] To address the increasing power density and wiring congestion in advanced integrated circuit (IC) designs, some approaches utilize back-side power delivery (BPD) architectures to power supply networks via wafer back-side wiring. By repositioning power interconnects to the back side, such architectures reduce overall power consumption and increase the available front-side area for signal routing and device integration. This separation between power and signal layers supports improved performance scaling and enables design flexibility. However, BPD integration presents several challenges. Back-side via contacts tend to exhibit higher resistance than front-side contacts, partly due to reduced contact area and geometric constraints. Furthermore, thermal conditions remain limited, as the presence of copper interconnects on the front side restricts the permissible back-side process temperature to below approximately 500°C. These limitations necessitate careful coordination of materials and processing steps to achieve robust and low-resistance power delivery through the wafer back side.

[0042] Figure 3A It is a vertical cross-sectional view of a semiconductor device 300a including a front-side interconnect structure and a back-side interconnect structure, and Figure 3B According to various embodiments Figure 3A A vertical cross-sectional view of a portion of a semiconductor device. (Reference) Figure 3A The semiconductor device 300a includes a front-side structure 302a and a back-side structure 302b. Structure 300a is temporarily mounted to a carrier substrate 304 to enable processing from the back side of the wafer. A bonding oxide layer 306 secures the front-side structure 302a to the carrier substrate 304 and provides mechanical stability during subsequent thinning and back-side processing operations.

[0043] According to various embodiments, the bonding oxide layer 306 is formed by thermally growing or depositing oxide layers on one or both bonding surfaces. In one example, the process forms a silicon oxide layer on the surface of the front-side structure 302a and a corresponding oxide layer on the surface of the carrier substrate 304. The oxide layers are then contacted and bonded by a combination of surface activation (such as plasma or chemical treatment) and thermal annealing to strengthen the oxide-to-oxide bonding. This bonding arrangement enables reliable support for the semiconductor device 300a during the thinning and processing of the back-side structure 302b.

[0044] refer to Figure 3A and Figure 3B Semiconductor device 300a includes: a plurality of front-side interconnect structures having first metal lines 204a formed as part of a first metallization layer M0; and a plurality of back-side interconnect structures having second metal lines 204b formed as part of a first back-side metallization layer BMO. The first metal lines 204a are connected to conductive contact vias 202, the conductive contact vias 202 are connected to front-side source / drain contacts 222a, and the second metal lines 204b are connected to back-side source / drain contacts 222b. (Reference) Figure 3B The first metal silicide layer 228a separates the front-side source / drain contact 222a from the semiconductor epitaxial layer 214 of the source / drain component, and the second metal silicide layer 228b separates the back-side source / drain contact 222b from the semiconductor epitaxial layer 214. For simplicity, Figure 3B The source / drain component is shown as having only a single semiconductor epitaxial layer 214, but embodiments of this disclosure are not limited thereto. In this respect, in other embodiments, the source / drain component includes a multilayer structure (e.g., see...). Figure 2B and Figure 2C Semiconductor epitaxial layers (214a, 214b) in the middle.

[0045] refer to Figure 3BAccording to some embodiments, the contact surface area between the semiconductor epitaxial layer 214 and the back-side source / drain contact 222b may be smaller than the corresponding contact surface area between the semiconductor epitaxial layer 214 and the front-side source / drain contact 222a. In the absence of further processing operations, the reduced contact area can be a source of increased contact resistance. Therefore, the disclosed method provides an annealing operation to generate heat within the back-side surface of the source / drain epitaxial component to increase dopant activation and to repair damage caused by the pre-amorphization process prior to the selective contact doping operation, as referenced below. Figures 4A to 4D More detailed description.

[0046] Figures 4A to 4D According to various embodiments, for Figure 3A and Figure 3B Vertical cross-sectional views of the semiconductor structures (300a, 300b) and (400a, 400b, 400c, 400d) used in the fabrication of semiconductor structures (400a, 400b, 400c, 400d). (Reference) Figure 4A Structure 400a includes a front side portion 302a and a back side portion 302b. After the front side fabrication is completed, the structure is inverted and bonded to a carrier substrate to enable access to the back side of the original substrate for further processing, as referenced above. Figure 3A As described.

[0047] The front portion 302a includes a semiconductor epitaxial layer 214 formed in the source / drain region. A first silicide layer 228a is formed on the semiconductor epitaxial layer 214 to provide a low-resistance interface. A first source / drain contact 222a electrically connected to the silicide layer 228a is formed over the silicide layer 228a. An interlayer dielectric (ILD) 218 ​​surrounds the epitaxial layer 214, the silicide layer 228a, and the source / drain contact 222a, providing electrical isolation from adjacent structures. A contact etch stop layer (CESL) 220 is formed over the first source / drain contact 222a and the surrounding ILD 218. A conductive contact via 202 connected to the first source / drain contact 222a is formed through the ILD 218 and CESL 220 to enable electrical access from the front side. At this point, the conductive contact via 202 is electrically connected to the first metal line 204a (e.g., a line formed in the front first metallization layer M0). The operation performed on the back side 302b is as follows.

[0048] A patterned hard mask 221 is formed on the back side of substrate 210 to define the location of the back-side contact opening 402. According to an embodiment, the hard mask 221 comprises silicon nitride. In other embodiments, the hard mask 221 may comprise other etch-resistant materials, such as silicon carbide, silicon oxynitride, or a multilayer dielectric stack. In some embodiments, the hard mask 221 is implemented as a multilayer structure, for example, comprising a layer of silicon nitride combined with a layer of silicon oxide. Such a multilayer configuration can be selected to optimize etch selectivity and pattern fidelity during the formation of the back-side contact opening.

[0049] According to an embodiment, the hard mask 221 is formed by depositing one or more of these materials on the back side of the substrate 210 and patterning the resulting film using photolithography and anisotropic etching. The patterned hard mask 221 is used as an etching mask, and then directional etching, such as reactive ion etching (RIE), is performed to selectively remove material from the back side of the substrate 210. According to an embodiment, etching continues until it exposes the back side surface of the semiconductor epitaxial layer 214, thereby forming a back side contact opening aligned with the front source / drain regions.

[0050] After forming the back-side contact opening 402, the semiconductor epitaxial layer 214 is selectively doped to reduce contact resistance and improve conductivity at the exposed back-side contact surface. According to an embodiment, a pre-amorphous implantation (PAI) process is first performed to generate… Figure 4B The shallow amorphous region 404 is an exposed surface of the epitaxial layer 214. The PAI process is selected based on the conductivity type and composition of the epitaxial layer.

[0051] In some embodiments, for the n-type source / drain region, where the epitaxial layer 214 comprises silicon, pre-amorphization is performed using implantation of germanium (Ge) or silicon (Si) ions. According to embodiments, germanium is used because of its ability to effectively disrupt the crystal structure of silicon at relatively low doses and energies, creating a shallow amorphous region that facilitates subsequent dopant activation. In some embodiments, after pre-amorphization, an n-type dopant material such as phosphorus (P) or arsenic (As) is implanted into the amorphous region to increase the active carrier concentration near the back surface. The implantation energy and dose are selected to place the dopant within the amorphous layer while avoiding excessive diffusion. As described in more detail below, a subsequent thermal activation process is performed to recrystallize the amorphous region and activate the implanted dopant. In some embodiments, the thermal activation process can be implemented using laser annealing, flash annealing, or other rapid thermal processing techniques. Therefore, thermal activation can provide a relatively shallow absorption depth, which reduces or prevents heat transfer to the front side of the structure.

[0052] In some embodiments, for the p-type source / drain region, where the epitaxial layer 214 comprises silicon germanium (SiGe), pre-amorphization is similarly implemented using germanium implantation. Germanium is particularly effective for pre-amorphized SiGe layers because it matches the lattice properties and minimizes the risk of defect formation at the interface. In some embodiments, a p-type dopant material such as boron (B) is implanted, which is known for its high activation efficiency in SiGe. In some embodiments, the boron dopant is introduced after the PAI step, and the dose and energy are adjusted to maintain a shallow, high concentration distribution near the contact surface. According to various embodiments, the doping implantation process uses materials ranging from 1 × 10⁻⁶. 14 cm -2 Up to 1×10 17 cm -2 The implantation dose and implantation energy range from 100 eV to 10 keV using at least one of phosphorus, arsenic, and antimony for n-type doping or boron, aluminum, gallium, and indium for p-type doping.

[0053] In other embodiments, the PAI process can use optional atomic materials to achieve amorphization of the epitaxial layer. Suitable materials include silicon, germanium, arsenic, tin, indium, antimony, xenon, krypton, argon, and phosphorus, each of which can be selected based on factors such as atomic mass, implantation depth, and compatibility with subsequent doping steps. For example, heavier materials, such as xenon or antimony, can be used when deeper or more complete amorphization is desired. The selection of materials, energy, and dosage can be tailored to the material composition and the thermal constraints of the entire process flow. According to various embodiments, the PAI process ranges from 1 × 10⁻⁶. 12 cm -2 Up to 1×10 16 cm -2 The injection dose and injection energy range from 0.5 keV to 15 keV are used for implementation.

[0054] In some embodiments, a subsequent thermal activation process is performed to recrystallize the amorphized region and activate the implanted dopants. In some embodiments, a thermal budget is selected to remain within the constraints imposed by the front-side metallization, typically below approximately 500°C, which can be achieved using laser annealing, flash annealing, or other rapid thermal processing techniques. For example, in some embodiments, microwave annealing processes generate temperatures ranging from 400°C to 450°C. Temperatures below 400°C may not be effective for thermal activation, and temperatures above 500°C may damage the front-side metallization structure. The combination of pre-amorphization and selective doping can improve the electrical performance of the back-side contacts by reducing the Schottky barrier height and enhancing tunneling across the contact interface. For example, according to some embodiments, the non-thermoelectric field effect generated by the microwave annealing process is used to repair damaged layers of the N / P source / drain epitaxial semiconductor material after the Ge pre-amorphization process, thereby promoting the activation of boron and phosphorus dopants.

[0055] Figure 4B This is a reference to the implementation of various embodiments. Figure 4A The described structure 400b is generated by pre-amorphization and selective doping operations. Structure 404b includes an amorphous region 404 located within an exposed portion of the semiconductor epitaxial layer 214. The amorphous region 404 is generated by lattice disruption caused by the implanted pre-amorphization material (such as germanium or silicon) and extends from the back surface of the epitaxial layer to a defined depth. According to an embodiment, the amorphous region 404 includes unactivated interstitial dopant atoms. These inactive dopant atoms occupy non-substituted sites within the disordered crystal matrix, thereby remaining electrically inactive until further thermal processing is performed.

[0056] The thickness of the amorphous region 404 depends on factors such as the implanted material and the implantation energy. In various embodiments, the amorphous region 404 has a thickness of several nanometers. In some embodiments, a subsequent annealing operation recrystallizes the amorphous region and activates dopant atoms, creating a conductive region suitable for forming a low-resistance back-side electrical contact.

[0057] According to various embodiments, further processing includes an annealing operation, which includes microwave annealing, laser annealing, or a combination of microwave and laser annealing. For example, according to an embodiment, the annealing operation includes exposing the back surface of the source / drain epitaxial component to laser radiation with wavelengths ranging from about 0.4 micrometers to about 1.1 micrometers for a dwell time of less than about 0.5 milliseconds. Depending on these parameters, the laser radiation heats the back surface of the source / drain epitaxial component at a temperature ranging from about 500°C to about 1000°C. In this respect, the laser annealing process provides back-side heating that can promote dopant activation and cause thermal repair (e.g., solid-state epitaxial regrowth (SPER)) of the amorphous region 404 on the back surface of the source / drain epitaxial layer 214, while maintaining relatively low heating of other portions of the structure 404b.

[0058] According to various embodiments, the microwave annealing operation includes exposing the back surface of the semiconductor epitaxial layer 214 to microwave radiation. According to various embodiments, the microwave radiation is applied with a power ranging from about 50 W to about 5000 W at a frequency ranging from about 300 MHz to about 10 GHz. Such microwave radiation provides heating ranging from about 250°C to about 500°C to the back surface of the source / drain epitaxial member. In some embodiments, microwave annealing causes the contact resistance of the mixed layer between the source / drain epitaxial member and the silicide layer (e.g., amorphous region 404) to decrease from an initial value ranging from about 119 Ohm / sq to about 125 Ohm / sq to a reduced value ranging from about 115 Ohm / sq to about 118.5 Ohm / sq.

[0059] Microwave radiation can generate both thermal and electrical repairs on the back surface of source / drain epitaxial components. In this respect, thermal repair is a repair mechanism based on heat generated within the semiconductor epitaxial layer 214. Alternatively, the time-varying electromagnetic field of microwave radiation may induce another repair mechanism. In this respect, the electric field of microwave radiation interacts with charged interstitial atoms within the amorphous region 404. This interaction exerts an electromagnetic force on the charged ions, which, in addition to thermal energy, may induce ion movement. According to some embodiments, such additional movement can allow charged ions to reposition within the lattice and find alternative sites where they can combine and become activated dopant atoms. In this way, microwave radiation selectively repairs defect regions exhibiting electric field inhomogeneities through the direct interaction between the electric field of microwave radiation and the charge associated with the charged defect. (See below for reference.) Figure 7 These repair mechanisms will be described in more detail.

[0060] Then, by forming a second metal silicide layer 228b above the top surface of the semiconductor epitaxial layer 214, Figure 4B Structure 400b formed Figure 4CStructure 400c. At this point, according to various embodiments, refractory or near-noble metals are deposited over the surface of the semiconductor wafer using PVD techniques such as sputtering. Other suitable refractory metal deposition techniques include chemical vapor deposition (CVD), atomic layer deposition (ALD), electron beam evaporation, and ion beam deposition. These alternative methods can also form a metal layer prior to annealing to produce the desired silicide. A thermal annealing process can then be applied, which initiates a solid-state reaction between the deposited metal and the underlying silicon or silicon-germanium, forming a low-resistivity metal silicide compound at the interface. After the formation of the second metal silicide layer 228b, selective wet or dry etching can remove unreacted metal, leaving only self-aligned silicides in the areas where the metal contacts the silicon or silicon-germanium.

[0061] Several types of metal silicides can be formed, depending on the choice of metal and annealing conditions. Examples of suitable silicides include nickel silicide (NiSi), cobalt silicide (CoSi2), titanium silicide (TiSi2), platinum silicide (PtSi), and molybdenum silicides, such as molybdenum disilicide (MoSi2) and molybdenum pentasilicide (MoSi5). Nickel silicide advantageously offers a low formation temperature, compatibility with advanced technology nodes, and low resistivity. Cobalt silicide and titanium silicide can be chosen due to their higher thermal stability or specific integration requirements. Molybdenum silicide provides high thermal and chemical stability, making them suitable for applications requiring elevated operating temperatures or enhanced reliability in corrosive processing environments.

[0062] When the underlying epitaxial layer comprises n-type silicon, silicide formation typically proceeds uniformly due to the high reactivity of silicon with transition metals. The resulting silicide layer, such as NiSi, CoSi2, or MoSi2, exhibits low sheet resistance and forms stable electrical contacts with the doped silicon. When germanium-based pre-amorphization implantation (PAI) is performed prior to metal deposition, the implanted Ge atoms can participate in interfacial reactions during subsequent annealing. Therefore, in addition to the conventional metal silicides described above, mixed metal-silicon-germanium compounds can be formed. For example, metal germanides or metal silicides, such as nickel germanide (NiSi), can be generated at the reaction front. 1-x Ge x ), cobalt germanium silicon (CoSi) 1-x Ge x Alternatively, a ternary molybdenum-silicon-germanium phase can be used, depending on the relative concentrations of Si and Ge within the amorphous region. These mixed compounds can modify the local phase composition, diffusion behavior, or electrical properties of the resulting contact stack, while remaining compatible with standard silicide formation annealing processes.

[0063] Conversely, when the underlying epitaxial layer comprises p-type silicon-germanium (SiGe), the silicide formation process may differ due to the presence of germanium, which may be separated at the silicide interface or incorporated into the silicide crystal structure. For example, nickel silicide formed over p-type SiGe may include nickel-germanium silicide (NiSi). 1-x Ge x The molybdenum phase can react with silicon and germanium to form molybdenum silicongeride (Mo(Si)) 1-x Ge x (2 or similar phases), depending on the processing conditions. Temperature, annealing duration, and ambient atmosphere can be controlled to manage germanium diffusion and to maintain the desired silicide or germanium silicide phase and morphology.

[0064] In some implementations, a two-step annealing process is employed. The first annealing initiates the formation of a low-resistivity silicide phase, and the second, higher-temperature annealing stabilizes the silicide and improves its grain structure and uniformity. Process parameters such as metal film thickness, substrate doping concentration, and initial surface preparation are selected to enhance silicide integrity and minimize problems such as junction leakage, agglomeration, or silicide erosion.

[0065] refer to Figure 4D Then, the second metal silicide layer 228b is formed by depositing a conductive material in the back-side contact opening 402 above the semiconductor epitaxial layer 214. The conductive material includes one or more layers selected to promote adhesion, provide diffusion barrier function, and ensure low contact resistance, such as metal pad materials and metal filler materials. In some embodiments, the metal pad material includes conductive metal nitrides or metal carbides, such as titanium nitride, tantalum nitride, tungsten nitride, titanium carbide, tantalum carbide, and / or tungsten carbide. The deposition of the pad material can be carried out using ALD, CVD, or PVD, depending on integration requirements and step coverage considerations.

[0066] Following the pad deposition, a metallic filler material is deposited to fill the back-side contact opening 402. Suitable filler materials include tungsten, copper, aluminum, cobalt, ruthenium, molybdenum, tantalum, titanium, alloys thereof, and / or combinations thereof. The filler material is deposited using CVD, PVD, electroplating, or a combination of these techniques. For example, CVD is used for tungsten filling after the nucleation step, while copper is deposited by electroplating over a previously deposited PVD or ALD seed layer.

[0067] After depositing the conductive material, excess conductive material is removed from the area above the horizontal plane defined by the upper surface of the hard mask layer 221 by performing a planarization process. In some embodiments, planarization is performed using a chemical mechanical polishing (CMP) process, a trench etching process, or a combination of both. Other suitable planarization techniques are also applicable based on the material stack and integration process. The remaining portion of the conductive material (which fills the back-side contact opening 402 and contacts the second silicide layer 228b) forms the second source / drain contact 222b. This structure provides a low-resistance electrical connection to the source / drain regions formed within the semiconductor epitaxial layer 214.

[0068] Figure 3B Structure 300b is formed by the formation of a second metal wire 204b. Figure 4D The structure 400d is formed, and the second metal line 204b is formed as part of the first back-side metallization layer (BMO) to provide wiring and interconnection to additional device structures or external terminals. The second metal line 204b is formed in the fourth inter-layer dielectric (ILD) layer 218d defined by the metallization trench (e.g., see...). Figure 3A Within the first layer, the fourth ILD layer 218d is formed over the previously planarized surface (including the exposed portion of the hard mask layer 221 and the second source / drain contact 222b).

[0069] In some embodiments, the formation of the second metal line 204b begins by depositing a metal pad material along the sidewalls and bottom of a trench formed in the fourth ILD layer 218d. The metal pad material may include one or more conductive metal nitrides or metal carbides, such as titanium nitride, tantalum nitride, tungsten nitride, titanium carbide, tantalum carbide, and / or tungsten carbide. These pad materials serve as diffusion barrier layers to inhibit the migration of the metal filler into the surrounding dielectric and to promote adhesion between the trench surface and the metal filler. The pad deposition may be performed using ALD, CVD, or PVD, depending on the desired conformality and process integration.

[0070] After the liner is formed, a metallic filler material is deposited to fill the trenches in the fourth ILD layer 218d. Examples of suitable filler materials include tungsten, copper, aluminum, cobalt, ruthenium, molybdenum, tantalum, titanium, alloys thereof, and / or combinations thereof. The choice of filler material depends on electrical, thermal, and reliability requirements. Deposition techniques used to form the metallic filler material include CVD, PVD, electroplating, or combinations thereof. For example, in some embodiments, copper is deposited by electroplating over a previously deposited PVD or ALD seed layer, while in other embodiments, tungsten is deposited using a CVD process after the nucleation layer.

[0071] In some embodiments, after depositing the conductive filler, excess material above the surface of the fourth ILD layer 218d is removed by a planarization process. In some embodiments, planarization is performed using CMP, trench etching, or a combination of both to produce a substantially flat surface and isolate adjacent metal components. The remaining portion of the conductive material within the trench defines a second metal line 204b. The second metal line 204b establishes an electrical connection to the second source / drain contact 222b and forms part of a conductive path within the first back-side metallization layer BMO. This structure supports high-density, low-resistance signal routing and serves as the basis for additional wiring layers in advanced packaging or 3D integration schemes.

[0072] Figure 5A It is a graph showing the time-dependent temperature measurements at various points in a semiconductor device 500b subjected to laser annealing pulses, and... Figure 5B It is carried out according to the instructions of the various embodiments. Figure 5A A vertical cross-sectional view of semiconductor device 500b at the point of temperature measurement. (Reference) Figure 5B A first temperature measurement is performed at the first interface 502 between the second source / drain contact 222b and the second metal silicide layer 228b; a second temperature measurement is performed at the second interface 504 between the semiconductor epitaxial layer 214 and the first metal silicide layer 228a; a third temperature measurement is performed at the third interface 506 between the conductive contact via 202 and the first metal line 204a; and a fourth temperature measurement is performed on the front side of the first metal line 204a.

[0073] Figure 5A Time-dependent temperature measurements are performed in response to short-duration laser pulses 501 transmitted to semiconductor device 500b. For example, in Figure 5A and Figure 5B In one embodiment, during intermediate production operations, a pulse of laser radiation having a wavelength ranging from about 0.4 micrometers to about 1.1 micrometers is applied to the surface of the semiconductor epitaxial layer 214 closest to the first interface 502 for a dwell time of less than 0.5 ms (e.g., see...). Figure 4B ). Figure 5A The curves indicate that a strong temperature gradient is induced in semiconductor device 500b, with the highest temperature occurring at the location closest to the first interface 502. Furthermore, curve 502 indicates that a maximum temperature of approximately 850°C occurs in semiconductor device 500b closest to the first interface 502 and decays as a function of time. Other points far from the first interface 502 do not reach the same peak temperature achieved at the first interface 502. For example, the temperature at the front side of the first metal line 204a remains below 500°C.

[0074] Figure 5A and Figure 5B The results indicate that short-duration laser pulses generate temperatures between 500°C and 1000°C within the back surface of the source / drain epitaxial layer 215 (e.g., near the first interface 502), while maintaining relatively low temperatures in other parts of the structure 500b. Therefore, the laser annealing process provides localized heating that promotes dopant activation and causes amorphous regions 404 (e.g., see...) on the back surface of the source / drain epitaxial layer 214. Figure 4B Thermal repair (e.g., solid-phase epitaxial regrowth (SPER)) is performed while maintaining sufficiently low temperatures throughout the other parts of the semiconductor device 500b to avoid damage to the front-side structure, as described above.

[0075] Figure 6 These are graphs showing the variation of germanium concentration (602, 604) within the semiconductor device according to various embodiments as a function of depth. The first curve 602 corresponds to a concentration measurement performed without an annealing process, while the second curve corresponds to a concentration measurement performed after a laser annealing process. Figure 6 The measurements were performed using energy-dispersive X-ray spectroscopy (EDS). In each curve, the maximum germanium concentration occurred near the first interface 502 (e.g., see...). Figure 5B This is due to germanium deposited during the pre-amorphization process described above.

[0076] Curves 602 and 604 each show the decrease in germanium concentration as a function of distance from the first interface 502. However, the second curve 604 shows a larger decrease in germanium concentration within the semiconductor epitaxial layer 214 after laser annealing compared to the decrease that would occur without annealing. For example, curve 602 has a minimum value within the semiconductor epitaxial layer 214 that is approximately 27% smaller than the maximum value near the first interface 502. Conversely, curve 502 has a minimum value that is approximately 43% smaller than the maximum concentration near the first interface 502. Figure 6 The measurement corresponds to a range from approximately 2 × 10⁻⁶ near the first interface 502. 21 cm -3 Approximately 4×10 21 cm -3 Semiconductor device 500b with dopant concentration and dopant activation ratio ranging from about 20% to about 40%, the dopant activation ratio corresponding to the temperature caused by the laser annealing process, which ranges from about 850°C to about 1000°C.

[0077] Figure 7 Table 700 schematically illustrates the repair mechanisms induced by the microwave annealing process according to various embodiments. Column 702 corresponds to the thermal repair mechanism, wherein the microwave radiation field provides sufficient energy to overcome the energy barrier E.a The thermal energy (i.e., heat) is used to move impurity atoms from interstitial sites (where inactive impurity atoms (e.g., unionized)) to substitutional sites (e.g., ...). Figure 7 (The empty space in column 702 is shown). The two curves labeled T1 and T2 indicate the corresponding energy barriers for the two corresponding molecular / crystal configurations.

[0078] Additional repair mechanisms are indicated by column 704 in Table 700. At this point, the time-dependent electric field of the microwave radiation interacts directly with the charged impurities and imposes vibrational motions on each charged impurity in addition to the thermal motions of the lattice of the host atoms. Therefore, this electric field-induced energy helps overcome the energy barrier E. a This process involves moving charged impurity atoms to charged vacancy sites. Thus, charged impurities can fill charged vacancies and neutralize the charge associated with the impurities and vacancies. For this reason, this type of repair mechanism can be called "electrorepair," where defect regions exhibiting electric field inhomogeneities are repaired, and the inhomogeneities are reduced or eliminated.

[0079] Figure 8A This is a vertical cross-sectional view of test structure 800a used to determine non-thermal repair mechanisms, and Figure 8B yes Figure 8A The graph shows the sheet resistance of a test structure that has undergone different annealing conditions. Test structure 800a includes: an ion-implanted epitaxial semiconductor layer 802; an amorphous layer 804 comprising material subjected to solid-state epitaxial regrowth (SPER) under certain conditions; and a top silicon layer 806. A first curve 808 indicates the sheet resistance produced by different annealing operations performed at different temperatures for the same duration (e.g., 10 minutes) under purely thermal annealing conditions (e.g., using a temperature source other than microwave radiation). Curve 810 indicates the sheet resistance produced by low-power microwave annealing operations performed under conditions similar to those indicated by curve 808. The difference 814 between curves 808 and 810 indicates an additional field-based repair mechanism provided by the effect of the electric field associated with microwave radiation on charged impurities and charged vacancies.

[0080] The measurement corresponding to curve 810 corresponds to a microwave annealing operation performed at a relatively low microwave power, and measurement 816 corresponds to a microwave annealing operation performed at a relatively high power. At this point, the disclosed microwave annealing operation is performed at a power ranging from about 50 W to about 5000 W. The additional decrease in the sheet resistance of measurement 816 corresponds to an increased contribution due to the electric field-mediated repair mechanism. At this point, increasing the power of the microwave radiation corresponds to increasing the amplitude of the radiated electric field. In other words, increasing the microwave power corresponds to a stronger electric field in the microwave radiation. Therefore, the difference 818 between the measurement performed at a relatively lower power (i.e., curve 810) and the measurement 816 performed at the same temperature of 400°C at high power corresponds to an increased contribution from the electric field repair mechanism.

[0081] Figure 9 This is a flowchart of the operation of method 900 for manufacturing semiconductor devices (900, 1000) according to various embodiments. In operation 902, method 900 includes depositing doped source / drain epitaxial components (214, 214a, 214b) over the source / drain regions of the active region 112 of the semiconductor device (900, 1000) structure formed on the front side 302a of substrate 210. According to various embodiments, the source / drain epitaxial components (214, 214a, 214b) include a first layer 214a and a second layer 214b, the first layer 214a being adjacent to the channel region of the active region 112, and the second layer 214b being spaced apart from the channel region of the active region 112 by the first layer 214a (e.g., see...). Figure 2B and Figure 2C ), wherein the first concentration of the dopant in the first layer 214a varies relative to the second concentration of the dopant in the second layer 214b.

[0082] In operation 904, method 900 includes etching a back-side opening 402 in the substrate 210 to expose the back-side surface 502 of the source / drain epitaxial components (214, 214a, 214b). Figure 4A In operation 906, method 900 includes performing a pre-amorphization process on the back surface 502 of the source / drain epitaxial components (214, 214a, 214b). Figure 4B In operation 908, method 900 includes performing an annealing operation to generate heat within the back surface 502 of the source / drain epitaxial components (214, 214a, 214b). Figure 4B In operation 910, method 900 includes depositing a silicide layer 228b on the back side surface 502 of the source / drain epitaxial components (214, 214a, 214b).

[0083] According to various embodiments, the annealing operation further includes exposing the back surface 502 of the source / drain epitaxial components (214, 214a, 214b) to laser radiation having a wavelength ranging from 0.4 micrometers to 1.1 micrometers for a dwell time of less than 0.5 milliseconds. According to various embodiments, the laser radiation generates a temperature between 500°C and 1000°C within the back surface 502 of the source / drain epitaxial components (214, 214a, 214b). According to various embodiments, the laser radiation generates a thermal repair 702 on the back surface 502 of the source / drain epitaxial components (214, 214a, 214b). According to various embodiments, the annealing operation further includes exposing the back surface 502 of the source / drain epitaxial components (214, 214a, 214b) to microwave radiation.

[0084] According to various embodiments, microwave radiation generates a temperature between 250°C and 500°C within the back surface 502 of the source / drain epitaxial components (214, 214a, 214b). According to various embodiments, microwave radiation generates thermal repair 702 and electrical repair 704 on the back surface 502 of the source / drain epitaxial components (214, 214a, 214b). According to various embodiments, microwave radiation selectively repairs defect regions exhibiting electric field inhomogeneities (e.g., Figure 7 (Section 704). According to various embodiments, performing the annealing operation also includes reducing the contact resistance of the amorphous layer 404 between the source / drain epitaxial components (214, 214a, 214b) and the silicide layer 228b from an initial value ranging between 119 Ohm / sq and 125 Ohm / sq. Figure 8B The curve 808 in the figure decreases to a decrease value ranging between 115 Ohm / sq and 118.5 Ohm / sq. Figure 8B (Curve 810 in the text).

[0085] According to various embodiments, the microwave radiation includes frequencies ranging from 300 MHz to 10 GHz. According to various embodiments, the microwave radiation includes power ranging from 50 W to 5000 W. According to various embodiments, implementing the pre-amorphization process also includes using a power ranging from 1 × 10⁻⁶ W. 12 cm -2 Up to 1×10 16 cm -2 The implantation dose and implantation energy range from 0.5 keV to 15 keV. Ion implantation processes are carried out using at least one of silicon, germanium, arsenic, tin, indium, antimony, xenon, krypton, argon and phosphorus as implanting materials.

[0086] Figure 10This is a flowchart of the operation of a method 1000 for manufacturing semiconductor devices (900, 1000) according to various embodiments. Method 1000 includes performing processing operations (1002, 1004, 1006) to form a backside 302b interconnect structure of the semiconductor devices (900, 1000). The backside 302b interconnect structure includes a source / drain component 214, an interlayer dielectric layer disposed above the source / drain component 214, and source / drain contacts extending through the interlayer dielectric layer to be electrically coupled to the source / drain component 214, wherein a first conductivity of the source / drain contacts is greater than a second conductivity of the source / drain component 214. The processing operations (1002, 1004, 1006) are as follows.

[0087] In operation 1002, method 1000 includes performing a pre-amorphization process on the back surface 502 of source / drain epitaxial components (214, 214a, 214b) formed in the active region 112 of a semiconductor device (900, 1000) structure formed on the front side 302a of substrate 210. In operation 1004, method 1000 includes performing a dopant ion implantation process to introduce dopant into the back surface 502 of the source / drain epitaxial components (214, 214a, 214b). In operation 1006, method 1000 includes performing a microwave annealing operation by exposing the back surface 502 of the source / drain epitaxial components (214, 214a, 214b) to microwave radiation, the microwave radiation generating thermal and electrical repairs to the back surface 502 of the source / drain epitaxial components (214, 214a, 214b).

[0088] According to various embodiments, implementing the dopant ion implantation process also includes using ions ranging from 1×10⁻⁶. 14 cm -2 Up to 1×10 17 cm -2 The implantation dose and implantation energy range from 100 eV to 10 keV, using at least one of phosphorus, arsenic, and antimony for n-type doping or boron, aluminum, gallium, and indium for p-type doping as the implanting material to perform the ion implantation process. According to various embodiments, performing the microwave annealing operation further includes: controlling the frequency of the microwave radiation to a frequency value ranging from 300 MHz to 10 GHz; controlling the power of the microwave radiation to a power value ranging from 50 W to 5000 W; and performing the microwave annealing operation in an inert gas at a pressure ranging from 0.1 Torr to 760 Torr for an annealing time ranging from 0.1 minutes to 100 minutes.

[0089] According to various embodiments, method 1000 further includes performing a laser annealing operation by exposing the back surface 502 of the source / drain epitaxial components (214, 214a, 214b) to laser radiation of wavelengths ranging from 0.4 micrometers to 1.1 micrometers for a dwell time of less than 0.5 milliseconds. According to various embodiments, method 1000 further includes: controlling a first parameter of the microwave annealing operation such that a first temperature range of the back surface 502 of the source / drain epitaxial components (214, 214a, 214b) is from 400°C to 500°C; and controlling a second parameter of the laser annealing operation such that a second temperature range of the back surface 502 of the source / drain epitaxial components (214, 214a, 214b) is from 850°C to 1000°C.

[0090] Referring to all the accompanying drawings and various embodiments of the present disclosure, semiconductor devices (900, 1000) are disclosed. The semiconductor devices (900, 1000) include: a semiconductor substrate 210 having a front side 302a and a back side 302b opposite to the front side 302a; a first interconnect structure (206b, 206c) disposed on the front side 302a of the semiconductor substrate 210 and extending over an active region 112, the first interconnect structure (206b, 206c) including a plurality of dielectric layers (218a, 218b, 218c) interleaved with a plurality of etch stop layers (220, 224a, 224b), and a plurality of front metal lines (204a, M0) disposed in the plurality of dielectric layers (218a, 218b, 218c); and a second interconnect structure disposed on the back side 302b of the semiconductor substrate 210, including the back metal lines (204b, BMO).

[0091] The semiconductor devices (900, 1000) further include: a conductive via 222b extending through the semiconductor substrate 210 and electrically connecting a back-side metal line (204b, BMO) to a source / drain component 214 of the active region 112; and a metal silicide 228b formed between the conductive via 222b and the back-side metal line (204b, BMO). According to various embodiments, the contact resistance associated with the metal silicide 228b ranges between 115 Ohm / sq and 118.5 Ohm / sq.

[0092] According to various embodiments, the source / drain component 214 includes germanium with a concentration of 604, the concentration of 604 varying from a maximum concentration near the back-side interface 502 between the source / drain component 214 and the conductive via 222b to a minimum concentration within the source / drain component 214, the minimum concentration being smaller than the maximum concentration by a range from 27% to 43%. Figure 6According to various embodiments, the source / drain component 214 includes a range from 2 × 10⁻⁶ near the back-side interface 502 between the source / drain component 214 and the conductive via 222b. 21 cm -3 Up to 4×10 21 cm -3 The dopant concentration and the dopant activation ratio, ranging from 20% to 40%.

[0093] The disclosed embodiments advantageously provide semiconductor device structures (300b, 500b) with back-side source / drain contacts 222b, which have reduced contact resistance due to a processing operation involving annealing to generate heat within the back-side surface 502 of the source / drain epitaxial portion 214. The annealing operation is performed after the pre-amorphization process and dopant implantation, and uses a high-energy, short-duration laser annealing process (e.g., see...). Figures 5A to 6 ) or low-temperature microwave annealing (e.g., see Figures 7 to 8B The laser annealing process provides localized heating that enhances dopant activation and induces solid-state epitaxial regrowth (SPER) of the amorphous region 404 on the back surface 502 of the source / drain epitaxial layer 214, while maintaining relatively low heating of other portions (504, 506, 508) of the semiconductor device structure (300b, 500b). The microwave annealing process provides delocalized heating of the semiconductor device structure (300b, 500b) at a relatively lower temperature than laser annealing. Microwave annealing results in thermal repair 702 and non-thermal repair 704 of the amorphous region 404 on the back surface 505 of the source / drain epitaxial layer 214, and further facilitates dopant activation. The disclosed embodiments exhibit improved device performance and reduced RC time delay due to the reduced contact resistance of the back-side source / drain contacts.

[0094] According to various embodiments, a method of manufacturing a semiconductor device includes: depositing a source / drain epitaxial component comprising a dopant over a source / drain region of an active region of a semiconductor device structure formed on the front side of a substrate, wherein the source / drain epitaxial component includes a first layer and a second layer, the first layer being adjacent to a channel region of the active region, and the second layer being spaced apart from the channel region of the active region by the first layer, wherein a first concentration of dopant in the first layer varies relative to a second concentration of dopant in the second layer.

[0095] According to various embodiments, the method further includes: etching a back-side opening in a substrate to expose the back-side surface of a source / drain epitaxial component; performing a pre-amorphization process on the back-side surface of the source / drain epitaxial component; performing an annealing operation to generate heat within the back-side surface of the source / drain epitaxial component; and depositing a silicide layer on the back-side surface of the source / drain epitaxial component. According to various embodiments, performing the annealing operation further includes: exposing the back-side surface of the source / drain epitaxial component to laser radiation of wavelengths ranging from 0.4 micrometers to 1.1 micrometers for a dwell time of less than 0.5 milliseconds. According to various embodiments, the laser radiation heats the back-side surface of the source / drain epitaxial component at a temperature ranging from 500°C to 1000°C.

[0096] According to various embodiments, laser radiation generates thermal repair on the back surface of the source / drain epitaxial component. According to various embodiments, the annealing operation further includes exposing the back surface of the source / drain epitaxial component to microwave radiation. According to various embodiments, microwave radiation heats the back surface of the source / drain epitaxial component at a temperature ranging from 250°C to 500°C. According to various embodiments, microwave radiation generates both thermal and electrical repair on the back surface of the source / drain epitaxial component. According to various embodiments, microwave radiation selectively repairs defect regions exhibiting electric field inhomogeneities.

[0097] According to various embodiments, the silicide layer includes germanium. According to various embodiments, the frequency range of the microwave radiation is from 300 MHz to 10 GHz. According to various embodiments, the power range of the microwave radiation is from 50 W to 5000 W. According to various embodiments, implementing the pre-amorphization process further includes: using a power range from 1 × 10⁻⁶ W... 12 cm -2 Up to 1×10 16 cm -2 The implantation dose and implantation energy range from 0.5 keV to 15 keV, and the ion implantation process is carried out using at least one implantation material selected from silicon, germanium, arsenic, tin, indium, antimony, xenon, krypton, argon and phosphorus.

[0098] According to various embodiments, a method of manufacturing a semiconductor device includes: performing processing operations to form a back-side interconnect structure of the semiconductor device, the semiconductor device including source / drain epitaxial components located in an active region formed on a front side of a substrate, an interlayer dielectric layer disposed above the source / drain epitaxial components on the front side of the substrate, and source / drain contacts extending through the interlayer dielectric layer and electrically coupled to the source / drain epitaxial components, wherein a first conductivity of the source / drain contacts is greater than a second conductivity of the source / drain epitaxial components. The processing operations are as follows.

[0099] According to various embodiments, the method includes: depositing a refractory metal layer above the back surface of a source / drain epitaxial component, and forming a silicide layer by performing a microwave annealing operation through exposing the back surface of the source / drain epitaxial component to microwave radiation, wherein the microwave radiation generates thermal and electrical repairs to the back surface of the source / drain epitaxial component.

[0100] According to various embodiments, the method further includes performing a dopant ion implantation process to introduce a dopant into the back surface of the source / drain epitaxial component by performing operations including the following steps: using ions ranging from 1×10⁻⁶... 14 cm -2 Up to 1×10 17 cm -2 The implantation dose and implantation energy range from 100 eV to 10 keV, and the ion implantation process is performed using at least one implantation material selected from phosphorus, arsenic, and antimony for n-type doping or boron, aluminum, gallium, and indium for p-type doping. According to various embodiments, performing the microwave annealing operation further includes: controlling the frequency of the microwave radiation to a frequency value ranging from 300 MHz to 10 GHz; controlling the power of the microwave radiation to a power value ranging from 50 W to 5000 W; and performing the microwave annealing operation in an inert gas at a pressure ranging from 0.1 Torr to 760 Torr for an annealing time ranging from 0.1 minutes to 100 minutes.

[0101] According to various embodiments, the method further includes performing a laser annealing operation by exposing the back surface of the source / drain epitaxial component to laser radiation of wavelengths ranging from 0.4 micrometers to 1.1 micrometers for a dwell time of less than 0.5 milliseconds. According to various embodiments, the method further includes controlling a first parameter of the microwave annealing operation to apply heat to the back surface of the source / drain epitaxial component at a first temperature ranging from 400°C to 500°C; and controlling a second parameter of the laser annealing operation to apply heat to the back surface of the source / drain epitaxial component at a second temperature ranging from 850°C to 1000°C.

[0102] According to various embodiments, the semiconductor device includes: a semiconductor substrate having a front side and a back side opposite to the front side; a first interconnect structure disposed on the front side of the semiconductor substrate and extending over an active region, the first interconnect structure including a plurality of dielectric layers interleaved with a plurality of etch stop layers, and a plurality of front-side metal lines disposed in the plurality of dielectric layers; a second interconnect structure disposed on the back side of the semiconductor substrate, including a back-side metal line; a conductive via extending through the semiconductor substrate and electrically connecting the back-side metal line to a source / drain component of the active region; and a metal silicide formed between the conductive via and the source / drain component.

[0103] According to various embodiments, the metal silicide and source / drain components include a dopant having a dopant concentration having a maximum value within the metal silicide. According to various embodiments, the dopant is germanium, and the source / drain components include a germanium concentration that varies from a maximum value to a minimum value within the source / drain components, ranging from 27% to 43% less than the maximum value. According to various embodiments, the source / drain components include a dopant concentration that ranges from 2 × 10⁻⁶ near the back-side interface between the source / drain components and the conductive via. 21 cm -3 Up to 4×10 21 cm -3 ; and dopant activation ratio, ranging from 20% to 40%.

[0104] Some embodiments of this application provide a method of manufacturing a semiconductor device, comprising: depositing a source / drain epitaxial component comprising a dopant over a source / drain region of an active region of a semiconductor device structure formed on a front side of a substrate, wherein the source / drain epitaxial component includes a first layer and a second layer, the first layer being adjacent to a channel region of the active region, and the second layer being spaced apart from the channel region of the active region by the first layer, wherein a first concentration of the dopant in the first layer varies relative to a second concentration of the dopant in the second layer; etching a back-side opening in the substrate to expose a back-side surface of the source / drain epitaxial component; performing a pre-amorphization process on the back-side surface of the source / drain epitaxial component; performing an annealing operation to generate heat within the back-side surface of the source / drain epitaxial component; and depositing a silicide layer on the back-side surface of the source / drain epitaxial component.

[0105] In some embodiments, performing the annealing operation further includes exposing the back surface of the source / drain epitaxial component to laser radiation of wavelengths ranging from 0.4 μm to 1.1 μm for a dwell time of less than 0.5 ms. In some embodiments, the laser radiation heats the back surface of the source / drain epitaxial component at a temperature ranging from 500°C to 1000°C. In some embodiments, the laser radiation generates a thermal repair on the back surface of the source / drain epitaxial component. In some embodiments, performing the annealing operation further includes exposing the back surface of the source / drain epitaxial component to microwave radiation. In some embodiments, the microwave radiation heats the back surface of the source / drain epitaxial component at a temperature ranging from 250°C to 500°C. In some embodiments, the microwave radiation generates both thermal and electrical repairs on the back surface of the source / drain epitaxial component. In some embodiments, the microwave radiation selectively repairs defect regions exhibiting electric field inhomogeneities. In some embodiments, the silicide layer comprises germanium. In some embodiments, the frequency range of the microwave radiation is from 300 MHz to 10 GHz. In some embodiments, the power range of the microwave radiation is from 50 W to 5000 W. In some embodiments, implementing the pre-amorphization process further includes: using a power range from 1 × 10⁻⁶ W. 12 cm -2 Up to 1×10 16 cm -2 The implantation dose and implantation energy range from 0.5 keV to 15 keV, and the ion implantation process is carried out using at least one implantation material selected from silicon, germanium, arsenic, tin, indium, antimony, xenon, krypton, argon and phosphorus.

[0106] Other embodiments of this application provide a method for manufacturing a semiconductor device, comprising: performing processing operations to form a back-side interconnect structure of the semiconductor device, the semiconductor device including source / drain epitaxial components located in an active region formed on a front side of a substrate, an interlayer dielectric layer disposed on the front side of the substrate above the source / drain epitaxial components, and source / drain contacts extending through the interlayer dielectric layer and electrically coupled to the source / drain epitaxial components, wherein a first conductivity of the source / drain contacts is greater than a second conductivity of the source / drain epitaxial components, the processing operations including: depositing a refractory metal layer above a back-side surface of the source / drain epitaxial components, and forming a silicide layer by performing a microwave annealing operation by exposing the back-side surface of the source / drain epitaxial components to microwave radiation, the microwave radiation generating thermal and electrical repairs to the back-side surface of the source / drain epitaxial components.

[0107] In some embodiments, the method further includes performing a dopant ion implantation process to introduce a dopant into the back surface of the source / drain epitaxial component by performing operations including the following steps: using ions ranging from 1 × 10⁻⁶ 14 cm -2 Up to 1×10 17 cm -2 The implantation dose and implantation energy range from 100 eV to 10 keV, using at least one implantation material selected from phosphorus, arsenic, and antimony for n-type doping or boron, aluminum, gallium, and indium for p-type doping, are used to perform the ion implantation process. In some embodiments, the silicide layer includes germanium, and performing the microwave annealing operation further includes: controlling the frequency of the microwave radiation to a frequency value ranging from 300 MHz to 10 GHz; controlling the power of the microwave radiation to a power value ranging from 50 W to 5000 W; and performing the microwave annealing operation in an inert gas at a pressure ranging from 0.1 Torr to 760 Torr for an annealing time ranging from 0.1 minutes to 100 minutes. In some embodiments, the method further includes performing a laser annealing operation by exposing the back surface of the source / drain epitaxial component to laser radiation with wavelengths ranging from 0.4 micrometers to 1.1 micrometers for a dwell time of less than 0.5 milliseconds. In some embodiments, the method further includes: controlling a first parameter of the microwave annealing operation to apply heat to the back surface of the source / drain epitaxial member at a first temperature ranging from 400°C to 500°C; and controlling a second parameter of the laser annealing operation to apply heat to the back surface of the source / drain epitaxial member at a second temperature ranging from 850°C to 1000°C.

[0108] Further embodiments of this application provide a semiconductor device comprising: a semiconductor substrate having a front side and a back side opposite to the front side; a first interconnect structure disposed on the front side of the semiconductor substrate and extending over an active region, the first interconnect structure including a plurality of dielectric layers interleaved with a plurality of etch stop layers, and a plurality of front-side metal lines disposed in the plurality of dielectric layers; a second interconnect structure disposed on the back side of the semiconductor substrate, including a back-side metal line; a conductive via extending through the semiconductor substrate and electrically connecting the back-side metal line to a source / drain component of the active region; and a metal silicide formed between the conductive via and the source / drain component, wherein the metal silicide and the source / drain component include a dopant having a dopant concentration having a maximum value within the metal silicide.

[0109] In some embodiments, the dopant is germanium, and the source / drain component includes a germanium concentration ranging from a maximum to a minimum concentration within the source / drain component, within a range of 27% to 43% less than the maximum value. In some embodiments, the source / drain component includes the dopant concentration, which ranges from 2 × 10⁻⁶ near the back-side interface between the source / drain component and the conductive via. 21 cm -3 Up to 4×10 21 cm -3 ; and the dopant activation ratio, which ranges from 20% to 40%.

[0110] The foregoing outlines features of several embodiments to enable those skilled in the art to better understand various aspects of the embodiments of this disclosure. Those skilled in the art should understand that they can readily use the embodiments of this disclosure as a basis to design or modify other processes and structures for performing the same purposes and / or achieving the same advantages as the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of the embodiments of this disclosure, and that various changes, substitutions, and alterations can be made herein without departing from the spirit and scope of the embodiments of this disclosure.

Claims

1. A method for manufacturing a semiconductor device, comprising: A source / drain epitaxial component comprising a dopant is deposited over the source / drain region of an active region of a semiconductor device structure formed on the front side of a substrate, wherein the source / drain epitaxial component comprises a first layer and a second layer, the first layer being adjacent to a channel region of the active region, and the second layer being spaced apart from the channel region of the active region by the first layer, wherein a first concentration of the dopant in the first layer varies relative to a second concentration of the dopant in the second layer; A back-side opening is etched in the substrate to expose the back-side surface of the source / drain epitaxial component; A pre-amorphization process is performed on the back surface of the source / drain epitaxial component; An annealing operation is performed to generate heat within the back surface of the source / drain epitaxial components; and A silicide layer is deposited on the back surface of the source / drain epitaxial component.

2. The method according to claim 1, wherein, Performing the annealing operation further includes: The back surface of the source / drain epitaxial component is exposed to laser radiation of wavelengths ranging from 0.4 micrometers to 1.1 micrometers for a dwell time of less than 0.5 milliseconds.

3. The method according to claim 2, wherein, The laser radiation heats the back surface of the source / drain epitaxial component at a temperature ranging from 500°C to 1000°C.

4. The method according to claim 2, wherein, The laser radiation generates thermal repair on the back surface of the source / drain epitaxial component.

5. The method according to claim 1, wherein, Performing the annealing operation further includes: The back surface of the source / drain epitaxial component is exposed to microwave radiation.

6. The method according to claim 5, wherein, The microwave radiation heats the back surface of the source / drain epitaxial component at a temperature ranging from 250°C to 500°C.

7. The method according to claim 5, wherein, The microwave radiation generates thermal and electrical repairs on the back surface of the source / drain epitaxial component.

8. The method according to claim 7, wherein, The microwave radiation selectively repairs defect areas exhibiting uneven electric fields.

9. A method for manufacturing a semiconductor device, comprising: A processing operation is performed to form a back-side interconnect structure of the semiconductor device, the semiconductor device including source / drain epitaxial components located in an active region formed on a front side of a substrate, an interlayer dielectric layer disposed on the front side of the substrate above the source / drain epitaxial components, and source / drain contacts extending through the interlayer dielectric layer and electrically coupled to the source / drain epitaxial components, wherein a first conductivity of the source / drain contacts is greater than a second conductivity of the source / drain epitaxial components, the processing operation including: A refractory metal layer is deposited above the back surface of the source / drain epitaxial component, and a silicide layer is formed by performing a microwave annealing operation by exposing the back surface of the source / drain epitaxial component to microwave radiation, wherein the microwave radiation generates thermal and electrical repairs on the back surface of the source / drain epitaxial component.

10. A semiconductor device, comprising: A semiconductor substrate having a front side and a back side opposite to the front side; A first interconnect structure is disposed on the front side of the semiconductor substrate and extends over the active region. The first interconnect structure includes a plurality of dielectric layers interleaved with a plurality of etch stop layers, and a plurality of front metal lines disposed in the plurality of dielectric layers. A second interconnect structure is disposed on the back side of the semiconductor substrate, including a back side metal line; Conductive vias extend through the semiconductor substrate and electrically connect the back-side metal lines to the source / drain components of the active region; as well as Metal silicide is formed between the conductive via and the source / drain components. The metal silicide and the source / drain components include a dopant having a dopant concentration that has a maximum value within the metal silicide.

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