Integrated circuit and method of forming the same

Abstract

An integrated circuit includes a local gate interconnect structure on a gate metal of a transistor. After forming the gate metal, a layer of local interconnect metal is deposited on a top surface of the gate metal and patterned to form a local gate interconnect structure on the gate metal. An interlayer dielectric layer is then deposited and patterned to expose the local gate interconnect structure at selected gate contact locations. A gate contact via is then formed in the opening, providing electrical contact to the gate metal through the local gate interconnect structure. Embodiments of the present disclosure also relate to methods of forming an integrated circuit.

Description

Technical Field

[0001] Embodiments of this disclosure relate to integrated circuits and methods of forming the same. Background Technology

[0002] The semiconductor integrated circuit industry has experienced exponential growth. Technological advancements in integrated circuit materials and design have resulted in multiple generations of integrated circuits, each featuring smaller and more complex circuits than the previous generation. In the evolution of integrated circuits, functional density (i.e., the number of interconnect devices per chip area) has typically increased, while geometry (i.e., the smallest component (or line) that can be created using manufacturing processes) has decreased. This scaling down process generally provides benefits by increasing production efficiency and reducing associated costs. However, this scaling down also increases the complexity of handling and manufacturing integrated circuits. Summary of the Invention

[0003] Embodiments of this disclosure provide a method for forming an integrated circuit, comprising: depositing an isolation structure between a first semiconductor fin at a first active region and a second semiconductor fin at a second active region, wherein the isolation structure is in contact with a first fin substrate region of the first semiconductor fin and a second fin substrate region of the second semiconductor fin; defining a plurality of stacked channels of a transistor at the first active region from a plurality of stacked semiconductor layers of the first semiconductor fin by forming a first source / drain trench and a second source / drain trench in the first semiconductor fin; depositing a first source / drain component of the transistor in the first source / drain trench; and depositing a second source / drain component in the first semiconductor fin. A second source / drain component of the transistor is deposited in a trench; an interface gate dielectric layer is deposited on the channel; a high-k gate dielectric layer is deposited on the interface gate dielectric layer; a gate metal is deposited on the high-k gate dielectric layer, and a gate spacer layer extends along the sidewall of the gate structure, wherein the dielectric constant of the high-k gate dielectric layer is greater than the dielectric constant of the gate spacer layer; source / drain contacts are deposited on the first source / drain component of the transistor; an interconnect structure is deposited on the gate metal above the channel; a first interlayer dielectric layer is deposited over the interconnect structure and the source / drain contacts; a first opening is formed in the first interlayer dielectric layer to expose the interconnect structure; a gate contact via is deposited in the first opening, the gate contact via falling on the interconnect structure and electrically coupled to the gate metal; a second opening is formed in the first interlayer dielectric layer to expose the source / drain contacts; and a source / drain via is deposited in the second opening, the source / drain via being electrically coupled to the source / drain contacts.

[0004] Another embodiment of this disclosure provides a method for forming an integrated circuit, comprising: forming a first active region extending in a first lateral direction; forming a second active region extending in the first lateral direction; depositing an isolation structure between the first active region and the second active region; and depositing a first source / drain component of a transistor in the first active region, the first source / drain component being suspended above the isolation structure; A second source / drain component of the transistor is deposited in the first active region, and a plurality of channels of the transistor extend in the first lateral direction between the first source / drain component and the second source / drain component; a gate structure is deposited that extends in the second lateral direction across the first active region, the second active region, and the isolation structure and encloses the channels; source / drain contacts are deposited that are electrically coupled to the source / drain components through a silicide layer, wherein the conductivity of the silicide layer is greater than the conductivity of the source / drain components; a first dielectric layer is deposited on the gate structure; a first opening is formed in the first dielectric layer; a metal layer is deposited in the first opening on the gate structure that extends in the second lateral direction over the channels and the isolation structure; and a first gate contact via is deposited on the metal layer that is electrically coupled to the gate metal through the metal layer.

[0005] Another embodiment of this disclosure provides an integrated circuit, including: an active region extending in a first lateral direction; a first source / drain component located in the active region; a second source / drain component located in the active region; a plurality of stacked channels located in the active region, the plurality of stacked channels extending between the first source / drain component and the second source / drain component in the first lateral direction; and a contact etch stop layer located above the first source / drain component. A first interlayer dielectric layer is located above the contact etch stop layer, wherein the dielectric constant of the contact etch stop layer is greater than the dielectric constant of the first interlayer dielectric layer; a silicide layer is located on the first source / drain component; a first source / drain contact is located on the silicide layer and disposed within the first interlayer dielectric layer, wherein the silicide layer has a curved profile; a gate metal surrounds the channel; a second source / drain contact is located on the second source / drain component; a second interlayer dielectric layer is located above the gate metal; an interconnect structure is located on the gate metal; a gate contact via extends through the second interlayer dielectric layer and falls on the interconnect structure, wherein the length of the interconnect structure in the second lateral direction is greater than the length of the gate contact via in the second lateral direction; and a source / drain via extends through the interlayer dielectric layer and is electrically coupled to the first source / drain contact. Attached Figure Description

[0006] When read in conjunction with the accompanying drawings, aspects of this disclosure are best understood from the following detailed description. It should be noted that, in accordance with standard industry practice, the various components are not drawn to scale. In fact, for clarity of discussion, the dimensions of the individual components may be arbitrarily increased or decreased.

[0007] Figures 1 to 27 These are cross-sectional views, perspective views, and top views of integrated circuits at various processing stages according to some embodiments.

[0008] Figure 28 This is a flowchart of a method for manufacturing an integrated circuit according to some embodiments.

[0009] Figure 29 This is a flowchart of a method for manufacturing an integrated circuit according to some embodiments. Detailed Implementation

[0010] The following disclosure provides numerous different embodiments or examples for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below to simplify this disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first component on or over a second component may include embodiments where the first and second components are formed in direct contact, and may also include embodiments where an additional component may be formed between the first and second components, such that the first and second components may not be in direct contact. Furthermore, reference numerals and / or letters may be repeated in various examples. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0011] Additionally, for ease of description, spatial relative terms such as “below,” “under,” “lower,” “above,” and “upper” may be used herein to describe the relationship between one element or component and another, as shown in the figures. Besides the orientations shown in the figures, spatial relative terms are intended to include different orientations of the device in use or operation. The device may be positioned in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein can be interpreted accordingly.

[0012] Terms indicating relative degree (such as “about”, “basically”, etc.) should be interpreted as terms that a person skilled in the art would understand in accordance with current technical specifications.

[0013] This disclosure generally relates to semiconductor devices, and more specifically to field-effect transistors (FETs), such as planar FETs, three-dimensional fin FETs (FinFETs), or nanostructured devices. Examples of nanostructured devices include gate-all-around (GAA) devices, nanosheet FETs (NSFETs), nanowire FETs (NWFETs), and the like. In advanced technology nodes, the active region spacing between nanostructured devices is typically uniform, the source / drain epitaxial structure is symmetrical, and a metal gate surrounds all four sides of the nanostructure (e.g., a nanosheet).

[0014] GAA transistor structures can be patterned using any suitable method. For example, the structure can be patterned using one or more photolithography processes, including dual-patterning or multi-patterning processes. Typically, dual-patterning or multi-patterning processes combine photolithography and self-alignment processes, allowing the creation of patterns with, for example, smaller pitches than that achievable using a single direct photolithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a photolithography process. Spacers are formed alongside the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers can then be used to pattern the GAA structure.

[0015] According to some embodiments, the active region is combined with a semiconductor fin extending in a first lateral direction (e.g., the X direction). An isolation structure (such as a trench isolation structure) extends beside and between adjacent semiconductor fins in the first lateral direction. A gate region extends across the semiconductor fin and the isolation structure in a second lateral direction (e.g., the Y direction). Source / drain components of a transistor are formed in the semiconductor fin, wherein a stacked channel of the transistor extends between adjacent source / drain components in the X direction. The stacked channel is formed by the semiconductor fin and is located where the gate region crosses the active region. At the layout level, source / drain contact metal extends in the second lateral direction.

[0016] Embodiments of this disclosure provide a local interconnect metal layer on the gate metal, which helps increase the layout possibilities for gate contact landing. After forming the gate metal, a local interconnect metal layer is deposited on the top surface of the gate metal and patterned to form a local gate interconnect structure on the gate metal. An interlayer dielectric layer is then deposited and patterned to expose the local gate interconnect structure at selected gate contact locations. Gate contact vias are then formed in the openings, providing electrical contacts to the gate metal through the local gate interconnect structure. The use of the local gate interconnect structure offers several benefits. The local gate interconnect structure can extend over the gate isolation structure or gate protection structure, providing a larger area for gate contact via landing. This allows for larger gate isolation structure widths without the risk of gate contact vias failing to land on the gate metal. Therefore, lithographic constraints are relaxed. Furthermore, gate contact resistance is significantly reduced, while distributed gate resistance performance is improved. Threshold voltage offset is prevented or significantly reduced. Embodiments of this disclosure also provide better-functioning integrated circuits and higher wafer yields.

[0017] While the accompanying figures and description primarily focus on examples of nanostructured transistors that are stacked components including channels, the principles of this disclosure extend to other types of transistors. These principles extend to MOS transistors, FinFET transistors, and other types of transistors.

[0018] Figures 1 to 13C These are cross-sectional views and layout top views of an integrated circuit 100 manufactured according to some embodiments of the present disclosure. As will be described in further detail below, the manufacturing process produces a plurality of transistors 101.

[0019] Figure 1 This is a cross-sectional view of integrated circuit 100 at an intermediate processing stage. Integrated circuit 100 includes a substrate 102. Substrate 102 can be a semiconductor substrate, such as a bulk semiconductor, which can be doped (e.g., with P-type or N-type dopants) or undoped. The semiconductor material of substrate 102 can include silicon; germanium; compound semiconductors, including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductors, including silicon germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium phosphide indium, and / or gallium arsenide phosphide indium; or combinations thereof. Other substrates, such as single-layer, multi-layer, or gradient substrates, can be used.

[0020] Integrated circuit 100 includes a semiconductor stack 103, which includes a plurality of alternating semiconductor layers 104 and sacrificial semiconductor layers 106. Figure 1In the example, stack 103 includes three semiconductor layers 104 and three sacrificial semiconductor layers 106. However, in practice, different numbers of semiconductor layers 104 and sacrificial semiconductor layers 106 may be used without departing from the scope of this disclosure.

[0021] As will be further elaborated below, the semiconductor layer 104 will be patterned to form a stacked channel for multiple transistors. As will be elaborated further below, the sacrificial semiconductor layer 106 will eventually be completely removed to enable the formation of gate metal and other structures around the semiconductor nanostructures.

[0022] In some embodiments, the semiconductor layer 104 may be formed of a first semiconductor material such as silicon, silicon carbide, etc., and the sacrificial semiconductor layer 106 may be formed of a second semiconductor material such as germanium silicon. Each layer of the multilayer stack 103 may be epitaxially grown using processes such as chemical vapor deposition (CVD), atomic layer deposition (ALD), vapor phase epitaxy (VPE), molecular beam epitaxy (MBE), etc.

[0023] As will be explained in more detail below, due to the high etch selectivity between the materials of semiconductor layer 104 and sacrificial semiconductor layer 106, the sacrificial semiconductor layer 106 of the second semiconductor material can be removed without significantly etching the semiconductor layer 104 of the first semiconductor material, thereby allowing semiconductor layer 104 to be released to form the stacked channel region of the transistor.

[0024] In one example, semiconductor layer 104 is silicon, and sacrificial semiconductor layer 106 is silicon-germanium. In some embodiments, sacrificial semiconductor layer 106 has a germanium concentration between 10% and 50%, but other concentrations may be used without departing from the scope of this disclosure. This allows sacrificial semiconductor layer 106 to be selectively etched relative to semiconductor layer 104. Other materials and concentrations may be used without departing from the scope of this disclosure.

[0025] Figure 2A This is a cross-sectional view of an integrated circuit 100 according to some embodiments. Figure 2B Based on some embodiments Figure 2A The top layout diagram of the integrated circuit 100 at the processing stage is shown. Figure 2A The cross-sectional view corresponds to Figure 2B The cut line 2A is shown in the layout diagram. These diagrams include various layout diagrams of integrated circuit 100. The layout typically only shows the location of selected components of integrated circuit 100, as will be explained in more detail below. For example, dielectric structures are typically not shown in the layout diagram.

[0026] exist Figure 2AIn this design, semiconductor fins 108a and 108b are formed from stacked components 103. In the following discussion, some reference numerals include the suffix "a" or "b". The suffix may be omitted when the reference is not to a specific single structure. For example, when the reference to each semiconductor fin is general, semiconductor fins 108a and 108b may be simply referred to as semiconductor fin 108.

[0027] Semiconductor fins 108 are defined by trenches 110 formed in the stack 103 and the substrate 102. Although Figure 1 Not shown, a hard mask layer is first formed and patterned on the stack 103. Trench 110 is formed by an anisotropic etching process that etches in the downward direction in the presence of the patterned hard mask. The etching process defines semiconductor fins 108 by forming trench 110 through the sacrificial semiconductor layer 106, semiconductor layer 104, and substrate 102. The semiconductor fins 108 extend in the X direction and are spaced apart from each other in the Y direction by the trench 110. In some embodiments, the substrate of each fin 108 is a mesa structure 109, corresponding to the material of the semiconductor substrate laterally adjacent to the trench 110.

[0028] Each semiconductor fin 108 corresponds to an active region or active area of ​​the integrated circuit 100. Each active region corresponds to the location of the source / drain and channel regions forming a transistor. Semiconductor fin 108a corresponds to a first active region A1. Semiconductor fin 108b corresponds to a second active region A2. In some embodiments, the substrate 102 of each semiconductor fin corresponds to a doped well region.

[0029] exist Figure 2A In this process, an isolation structure 112 has been formed by depositing dielectric material in the grooves 110 between the fins 108. Figure 2A An isolation structure 112 as a single-layer dielectric material is shown. However, in practice, multiple dielectric layers can be used to form the isolation structure 112. The dielectric layers can be deposited by chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), or other suitable deposition processes. In an exemplary embodiment, the dielectric material of the isolation structure 112 includes silicon oxide. However, the dielectric material may include SiN, SiCN, SiOC, SiOCN, or other dielectric materials without departing from the scope of this disclosure.

[0030] After depositing the dielectric material of the isolation structure 112, an etch-back process has been performed to recess the top of the isolation structure 112 below the bottommost sacrificial semiconductor layer 106. This results in the top surface of the isolation structure 112 being lower than the bottom surface of the bottommost sacrificial semiconductor layer 106 of each fin. Other processes may be used to form the isolation structure 112 without departing from the scope of this disclosure. Each isolation structure 112 extends in the X direction alongside and between two adjacent semiconductor fins 108. In some embodiments, the isolation structure 112 is a shallow trench isolation structure. Each isolation structure 112 extends in the X direction alongside and contacts the mesa 109 (fin substrate) of the adjacent semiconductor fin 108. In some embodiments, the top surface of the isolation structure 112 is lower than the top surface of the adjacent mesa 109.

[0031] In some embodiments, the isolation structure 112 comprises SiO2, an oxide formed of tetraethyl orthosilicate, or other suitable dielectric material. In some embodiments, the isolation structure 112 has a depth between 50 nm and 100 nm.

[0032] Figure 2A The layout diagram only shows the active regions A1 and A2 (corresponding to the locations of semiconductor fins 108a and 108b). Subsequent layout diagrams will reveal the locations of other structures as they are formed within the integrated circuit 100. Dielectric layers are typically not shown in the layout diagrams.

[0033] Figure 3A This is a cross-sectional view of an integrated circuit 100 according to some embodiments. Figure 3B yes Figure 3A A top view of the layout of integrated circuit 100 at the processing stage shown. Figure 3A The cross-sectional view corresponds to Figure 3B Cutting line 3A in the middle.

[0034] exist Figure 3A In this configuration, sacrificial gate structures 114 are formed above fin 108. Each sacrificial gate structure 114 extends across semiconductor fin 108 and isolation structure 112 in the Y direction. The layout of the sacrificial gate structures 114 corresponds to the layout of the gate metal or gate structure of the transistor. In particular, the sacrificial gate structures 114 will eventually be replaced by gate metal. As will be explained in more detail below, local gate interconnect structures will be used to form gate contacts with relaxed lithographic constraints and improved electrical characteristics. Each sacrificial gate structure 114 corresponds to a corresponding gate metal layout location G1-G4 ( Figure 3B The layout diagram shows G4, but Figure 3A (Not shown in the image), although the actual gate metal has not yet been deposited.

[0035] The sacrificial gate structure 114 includes a dielectric layer 116. In an exemplary embodiment, the dielectric layer 116 comprises silicon oxide. However, alternatively, the dielectric layer 116 may comprise SiN, SiCN, SiOC, SiOCN, or other dielectric materials without departing from the scope of this disclosure. In some embodiments, the dielectric layer 116 has a low-k dielectric material. The dielectric layer 116 may be deposited by CVD, ALD, or PVD.

[0036] The sacrificial gate structure includes a sacrificial gate layer 118 located on the dielectric layer 116. The sacrificial gate layer 118 may include a material with high etch selectivity relative to the isolation structure 112. In an exemplary embodiment, the sacrificial gate layer 118 includes polycrystalline silicon. However, the sacrificial gate layer 118 may be a conductive, semiconductor, or non-conductive material, and may be or include amorphous silicon, polycrystalline silicon germanium (polycrystalline SiGe), metal nitrides, metal silicides, metal oxides, and metals. The sacrificial gate layer 118 may be deposited by physical vapor deposition (PVD), CVD, sputtering deposition, or other techniques used for depositing the selected material.

[0037] In some embodiments, the sacrificial gate structure 114 includes a dielectric layer located on the sacrificial gate layer 118. In an exemplary embodiment, the dielectric layer includes SiN. However, alternatively, the dielectric layer may include SiO, SiCN, SiOC, SiOCN, or other dielectric materials without departing from the scope of this disclosure. The dielectric layer may be deposited by CVD, ALD, or PVD.

[0038] exist Figure 3A In this embodiment, a gate spacer layer 120 is formed on the sidewalls of the sacrificial gate structure 114. Specifically, the gate spacer layer 120 is formed on the sidewalls of the dielectric layer 116 and the sacrificial gate layer 118. The gate spacer layer 120 is also formed on the top surface of the sacrificial gate structure 114, the top semiconductor layer 104 of each semiconductor fin 108, and other exposed surfaces. The gate spacer layer 120 can be formed by PVD, CVD, ALD, or other suitable deposition processes. In the specific example shown herein, the gate spacer layer 120 comprises SiOCN. Alternatively, the gate spacer layer 120 may comprise one or more of SiO, SiN, SiON, SiCN, SiOC, or other suitable dielectric materials. In some embodiments, the gate spacer layer 120 has a width between 2 nm and 8 nm, but other thicknesses may be utilized without departing from the scope of this disclosure.

[0039] exist Figure 3AIn this process, an etching process has been performed to pattern the gate spacer layer 120. The etching process includes an anisotropic etching process that etches in the downward direction. The anisotropic etching process removes the gate spacer layer 120 from the horizontal surface of the gate spacer 120, which has a smaller vertical thickness. After the gate spacer layer is patterned, the thicker vertical portion of the gate spacer layer 120 remains on the sidewall of the sacrificial gate structure 114.

[0040] If possible Figure 8C As can be seen, after the patterned gate spacer layer 120, dielectric structures 121 remain as residues of the gate spacer layer 120 on the top surface of the isolation structure 112. As will be explained in more detail below, these dielectric structures 121 will restrict the lateral growth of the lower portion of the source / drain components.

[0041] Figure 3B The layout diagram shows the layout positions of gate positions G1-G4 extending across active regions A1 and A2 in the Y direction. As will be explained in more detail below, the positions of the gate positions across the active regions correspond to the positions of the corresponding stacks that will form the channels of the transistor. As will be explained in more detail below, the stacks of transistor channels are formed at each intersection position.

[0042] Figure 4 This is a cross-sectional view of an integrated circuit 100 according to some embodiments. Figure 4 In some embodiments, source / drain trenches 124 have been formed. After patterning the gate spacer layer 120, one or more etching processes are performed to form the source / drain trenches 124 in the fins 108. Forming the source / drain trenches 124 includes etching portions through each semiconductor layer 104, each sacrificial semiconductor layer 106, and the substrate 102. Therefore, removal operations may include suitable etching operations for removing material from the semiconductor layers 104, sacrificial semiconductor layers 106, and substrate 102. Etching processes may include reactive ion etching (RIE), neutral beam etching (NBE), atomic layer etching (ALE), etc.

[0043] The formation of the source / drain trench 124 results in the formation of a stack 126 of the channel 105. Specifically, after the formation of the source / drain trench 124, the remaining portion of the semiconductor layer 104 now corresponds to the stacked channel 105 of the transistor. Thus, the channel 105 is defined from the semiconductor layer 104 by forming the trench 124 in the semiconductor fin 108. The formation of the source / drain trench 124 results in the formation of a plurality of sacrificial semiconductor nanostructures 107 from the sacrificial semiconductor layer 106. The substrate 102 is exposed at the bottom of each source / drain trench 124. As will be explained in more detail below, each stack 126 of the channel 105 corresponds to the stacked channel of a single transistor.

[0044] Figure 5 This is a cross-sectional view of an integrated circuit 100 according to some embodiments. Figure 5 In this process, a selective etching process has been performed to recess the exposed end portions of the sacrificial semiconductor nanostructure 107 while substantially not etching the channel 105. More specifically, a groove 129 is formed in the end portions of the sacrificial semiconductor nanostructure 107 relative to the adjacent channel 105. The groove 129 can be formed by performing an etching process that selectively etches the material of the sacrificial semiconductor nanostructure 107 relative to the materials of the channel 105 and the substrate 102.

[0045] Figure 6 This is a cross-sectional view of an integrated circuit 100 according to some embodiments. Figure 6 In this process, an internal spacer 130 has been formed in a trench. The internal spacer 130 is formed by depositing a dielectric layer on the exposed surfaces of the channel 105, the gate spacer layer 120, the sacrificial semiconductor nanostructure 107, and the substrate 102 in a conformal deposition process. Most notably, the dielectric layer fills the trench 129. The dielectric layer may include SiC, LaO, AlO, AlON, SiN, Si, ZnO, ZrN, ZrAlO, TiO, TaO, SiOCN, SiOC, SiCN, SiO, HfO, and ZrO. x Or other suitable dielectric materials. The dielectric layer can be formed by suitable deposition methods, such as CVD, ALD, PVD or other deposition processes.

[0046] The internal spacer 130 is formed by performing an anisotropic etching process in the downward direction. During the anisotropic etching process, the gate spacer layer 120 and the sacrificial gate structure 114 serve as a mask. The dielectric layer is removed from all locations exposed by the mask. As a result, the dielectric layer is removed from the trench 124. The portion of the dielectric layer retained in the trench 129 corresponds to the internal spacer 130. The internal spacer 130 contacts the ends of the sacrificial semiconductor nanostructure 107 and the channel 105. As will be further explained in detail below, the internal spacer 130 separates the gate metal from the source / drain components.

[0047] Figure 7 This is a cross-sectional view of an integrated circuit 100 according to some embodiments.

[0048] exist Figure 7In this process, an interposer 131 has been formed at the bottom of each source / drain trench 124. The interposer 131 is formed on the semiconductor substrate 102 exposed at the bottom of each source / drain trench 124. In some embodiments, the interposer comprises an intrinsic (undoped) semiconductor material, such as undoped silicon, undoped silicon germanium, or other undoped semiconductor materials. In some embodiments, the interposer comprises a dielectric material, such as SiN, SiCN, SiOCN, SiOC, or other suitable dielectrics. In some embodiments, the interposer 131 comprises a combination of an intrinsic semiconductor layer and a dielectric layer on the intrinsic semiconductor.

[0049] exist Figure 7 In some embodiments, the interposer 131 includes a bottom semiconductor layer 132 and a bottom dielectric structure 134 located on the bottom semiconductor layer 132. The bottom semiconductor layer 132 includes an intrinsic (undoped) semiconductor material, such as undoped silicon, undoped silicon germanium, or other undoped semiconductor materials. The bottom dielectric structure 134 may include SiN, SiCN, SiOCN, SiOC, or other suitable dielectric materials. The bottom dielectric structure 134 can be formed by ALD, CVD, or PVD and subsequent selected patterning processes. The bottom dielectric structure 134 helps prevent leakage current from flowing between the source / drain components 136 and the bottom semiconductor layer 132. In some embodiments, the bottom dielectric structure 134 has a thickness between 2 nm and 8 nm.

[0050] Figures 8A to 8C This is a cross-sectional view of an integrated circuit 100 according to some embodiments. Figure 8D This is a top view of the layout of an integrated circuit 100 according to some embodiments. Figures 8A to 8C The view is along Figure 8D The cut lines 8A-8C are used to capture the layout in the top view.

[0051] exist Figures 8A to 8C In some embodiments, source / drain components 136 have been formed in source / drain trenches 124. Source / drain components 136 are epitaxially grown from channels 105. Source / drain components 136 grow on exposed portions of fins 108 and contact channels 105. For each stack 126 of channels 105, there are two source / drain components 136. Figure 8A As shown, some stacks 126 of the channel 105 may share source / drain components 136 with stacks 126 of the channel 105 adjacent to each other in the X direction.

[0052] The source / drain component 136 may comprise any acceptable semiconductor material, such as that suitable for N-type or P-type devices. In some embodiments, for the N-type region, the source / drain component 136 comprises a material to which tensile strain is applied in the channel region, such as silicon, SiC, SiCP, SiP, SiAs, etc. According to some embodiments, for the P-type transistor, the source / drain component 136 comprises a material to which compressive strain is applied in the channel region, such as SiGe, SiGeB, Ge, GeSn, etc. The source / drain component 136 may have a surface protruding from the corresponding surface of the fin and may have a facet. In some embodiments, adjacent source / drain components 136 may be merged to form a single source / drain component 136 over two adjacent fins 108.

[0053] In some embodiments, an in-situ doping process may be performed during the formation of the source / drain component 136 to implant the source / drain component 136 with an N-type dopant or a P-type dopant, depending on the conductivity type of the transistor or region formed. The N-type dopant may include phosphorus, arsenic, antimony, or other suitable N-type dopant materials. The P-type dopant may include boron, gallium, indium, or other suitable P-type dopant materials. The source / drain component 136 may be doped and subsequently annealed. The source / drain component 136 may have a conductivity of approximately 10... 19 cm -3 Peace Treaty 10 21 cm -3 The concentration of impurities between them.

[0054] although Figures 8A to 8C Each source / drain component 136 is shown as a single epitaxial layer, but in some embodiments, each source / drain component 136 includes multiple epitaxial layers. A first epitaxial layer of the source / drain component 136 is grown at the end of the channel 105. A second epitaxial layer of the source / drain component 136 is grown on the first epitaxial layer, covering the side surface of the internal spacer 130. A final epitaxial layer of the source / drain component 136 is grown on a third epitaxial layer and fills the source / drain trench 124. Each epitaxial layer of the source / drain component 136 may have a different material and doping profile.

[0055] exist Figures 8A to 8CIn some embodiments, a contact etch stop layer (CESL) 140 and an interlayer dielectric (ILD) 143 have been formed. In some embodiments, CESL 140 is a thin dielectric layer conformally deposited on the exposed surfaces of the source / drain components 136, the dielectric structure 121, the isolation structure 112, and the gate spacer layer 120. In some embodiments, CESL 140 is a CESL bilayer including dielectric layers 141 and 142. Dielectric layer 141 may include SiO, SiN, SiOC, SiOCN, SiON, or other suitable dielectric materials. Dielectric layer 141 can be deposited by ALD, CVD, PVD, or other suitable deposition processes. Dielectric layer 142 may include SiO, SiN, SiOC, SiOCN, SiON, or other suitable dielectric materials and has a different composition than dielectric layer 141. Dielectric layer 142 can be deposited by ALD, CVD, PVD, or other suitable deposition processes. In some embodiments, the CESL 140 has a thickness between 3 nm and 6 nm, but other thicknesses may be used without departing from the scope of this disclosure.

[0056] Interlayer dielectric layer 143 covers CESL 140. Interlayer dielectric layer 143 fills the remaining space between adjacent sacrificial gate structures 114. Interlayer dielectric layer 143 may correspond to the bottommost interlayer dielectric layer of integrated circuit 100. In some embodiments, interlayer dielectric layer 143 may be referred to as ILD0. Interlayer dielectric layer 143 may include SiO, SiON, SiN, SiC, SiOC, SiOCN, SiON, or other suitable dielectric materials. Interlayer dielectric layer 143 may be deposited by CVD, ALD, PVD, or other suitable deposition processes. In some embodiments, the dielectric constant of CESL 140 is greater than the dielectric constant of interlayer dielectric layer 143.

[0057] In some embodiments, a CMP process is performed after the deposition of the interlayer dielectric layer 143. The result of the CMP process is that the top surfaces of the interlayer dielectric layer 143, CESL 140, gate spacer layer 120, and sacrificial gate layer 118 are coplanar. The CMP process can also reduce the height of the sacrificial gate structure 114 and the gate spacer layer 120.

[0058] like Figure 8C As shown, the source / drain component 136 is horizontally suspended above the isolation structure 112. Figure 8C A laterally grown dielectric structure 121 constraining the lower portion of the source / drain component 136 is also shown. A CESL 140 is formed on the surface of the dielectric structure 121, the source / drain component 136, and the isolation structure 112.

[0059] exist Figures 8A to 8CIn some embodiments, the sacrificial gate layer 118 has been removed. The sacrificial gate layer 118 can be removed by an etching process that selectively etches the material of the sacrificial gate layer 118 relative to adjacent materials, such as dielectric layer 116 and gate spacer layer 120. Removing the sacrificial gate layer 118 creates gate trenches between the gate spacer layers 120.

[0060] exist Figures 8A to 8C In some embodiments, an etching process has been performed to remove the sacrificial semiconductor nanostructure 107. The sacrificial semiconductor nanostructure 107 can be removed by a selective etching process using an etchant selective to the material of the channel 105, such that the sacrificial semiconductor nanostructure 107 is removed without substantially etching the channel 105. Removal of the sacrificial semiconductor nanostructure 107 is referred to as “releasing” the channel 105. In some embodiments, the etching process is an isotropic etching process using an etching gas and optionally a carrier gas, wherein the etching gas includes F2 and HF, and the carrier gas can be an inert gas such as Ar, He, N2, combinations thereof, etc. In some embodiments, the etching process causes the side surfaces of the channel 105 to become rounded. The etching process also creates gaps between the channels 105.

[0061] exist Figures 8A to 8C In some embodiments, a gate dielectric has been formed. The gate dielectric includes an interface gate dielectric layer 144 and a high-k gate dielectric layer 146. In some embodiments, the interface gate dielectric layer 144 has been deposited on an exposed portion of the channel 105. The interface gate dielectric layer 144 is formed directly on the exposed portion of the channel 105. The high-k gate dielectric layer 146 is formed on the interface gate dielectric layer 144 and other exposed surfaces, such as the exposed sidewalls of the gate spacer layer 120 and the internal spacer layer 130.

[0062] The interface gate dielectric layer 144 surrounds the channel 105. The interface gate dielectric layer 144 may include a dielectric material, such as silicon oxide, silicon nitride, or other suitable dielectric materials. The interface gate dielectric layer 144 may include a relatively low-k dielectric relative to the high-k dielectric, such as hafnium oxide, or other high-k dielectric materials that can be used as gate dielectrics for transistors. The high-k dielectric may include a dielectric material with a dielectric constant higher than that of silicon oxide. The interface gate dielectric layer 144 may be formed by a thermal oxidation process, a chemical vapor deposition (CVD) process, or an atomic layer deposition (ALD) process. The interface gate dielectric layer 144 may have a thickness between 0.5 nm and 2 nm. Other materials, deposition processes, and thicknesses may be used for the interface gate dielectric layer 144 without departing from the scope of this disclosure. Figure 8A The interface gate dielectric layer 144 is shown. Although Figure 8CAlthough not shown, the interface gate dielectric layer 144 is also present on the surface of the channel 105 between the channel 105 and the high-K gate dielectric layer 146.

[0063] A high-k gate dielectric layer 146 is deposited in a conformal deposition process. The conformal deposition process deposits the high-k gate dielectric layer 146 on the interface gate dielectric layer 144, the substrate 102, and the gate spacer layer 120. The high-k gate dielectric layer 146 surrounds the channel 105. The high-k gate dielectric layer 146 has a thickness between 1 nm and 3 nm. The high-k dielectric layer comprises one or more dielectric materials, such as HfO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, zirconium oxide, alumina, titanium oxide, hafnium dioxide-alumina (HfO2-Al2O3) alloy, other suitable high-k dielectric materials, and / or combinations thereof. The high-k gate dielectric layer 146 can be formed by CVD, ALD, or any suitable method. Other thicknesses, deposition processes, and materials may be used for the high-k gate dielectric layer 146 without departing from the scope of this disclosure. The dielectric constant of the high-K gate dielectric layer is greater than that of the gate spacer layer 120.

[0064] exist Figures 8A to 8C In some embodiments, gate metal 148 has been deposited. Gate metal 148 is deposited in place of the sacrificial gate layer 118 and the sacrificial semiconductor nanostructure 107. Therefore, as in... Figure 8B As can be seen, the gate metal 148 is located in the gate trench between the gate spacer layers 120 above the channel, and is located above the isolation structure 112 between the active regions. Figure 8A and Figure 8B As shown, the gate metal 148 also surrounds the channel 105.

[0065] As in Figure 8B As can be seen, the gate metal 148 of the gate layout G2 is short-circuited together around all channels 105a in active region A1 and channels 105b in active region A2. Each stack of channels 105 represents a separate transistor 101. More specifically, each location of the gate metal 148 across the semiconductor fin 108 corresponds to the location of a separate transistor 101. Figures 8A to 8C At the processing stage shown, the gate electrodes of all transistors below gate layout region G2 are short-circuited together. The same applies to the other gate regions G1, G2, and G4. Although not described herein, depending on the circuit layout, a gate metal dicing process is used to electrically isolate the gate electrodes of adjacent transistors by removing gate metal at selected locations.

[0066] exist Figures 8A to 8CIn the diagram, a single gate metal 148 is shown as the gate electrode of transistor 101. However, in practice, gate metal 148 may include multiple gate metals. For example, gate metal 148 may include one or more liner layers, one or more power function layers, and gate fill material filling the remaining space between gate spacer layers 120. Gate metal 148 may include one or more of TaN, TiN, TiSiN, Mo, WCN, TiSiN, TiAl, TiAlC, TiAlSiC, or other suitable conductive materials. Gate metal 148 may be deposited by PVD, ALD, or CVD.

[0067] After the gate metal 148 is formed, a CMP process is performed to reduce the height of the gate metal 148 and flatten the top surface of the remaining structure.

[0068] According to some embodiments, the critical dimensions of the semiconductor fin 108 and the Y-direction are between 10 nm and 90 nm. Other dimensions may be used without departing from the scope of this disclosure.

[0069] Figure 8D This is a top view of the layout of an integrated circuit 100 according to some embodiments. Figure 8D Layout view and Figure 3B The layout view is basically similar, but cut lines 8A, 8B and 8C are shown.

[0070] Figure 9A This is a cross-sectional view of an integrated circuit 100 according to some embodiments. Figure 9B This is a top view of the layout of an integrated circuit 100 according to some embodiments. Figure 9A The cross-sectional view corresponds to Figure 9B Cutting line 9A.

[0071] exist Figure 9A In the process, an etching process has been performed to expose the source / drain component 136. The etching process etches through the interlayer dielectric layer 143 above the source / drain component 136. The etching process continues through CESL 140 to expose the top surface of the source / drain component 136. The etching process causes the top surface of the source / drain component 136 to be recessed.

[0072] exist Figure 9AIn this embodiment, liner layer 156 has been deposited on CESL 140 and on the exposed recessed portion of source / drain component 136. In some embodiments, liner layer 156 is patterned to further expose the top surface of source / drain component 136. In some embodiments, liner layer 156 is a dielectric layer. In some embodiments, liner layer 156 is a conductive layer. In some embodiments, liner layer 156 comprises one or more of TiSiN, SiC, LaO, AlO, AlON, ZrO, HfO, SiN, ZnO, ZrN, ZrAlO, TiO, TaO, Y2O3, TaCN, ZrSi, SiOCN, SiOC, SiCN, HfSi, SiO, or other suitable materials.

[0073] exist Figure 9A In this process, a silicide layer 152 has been formed to prepare for the formation of source / drain contacts. The formation of the silicide layer 152 may include depositing a thin metal layer and performing a thermal annealing process that results in the formation of the silicide layer 152 from the metal layer. The silicide layer 152 may include TiSi, ZrSi, SbSi, BiSi, NiSi, SnSi, MoSi, or other suitable silicides.

[0074] exist Figure 9A In some embodiments, source / drain contacts 154 are formed on a silicide layer 152 above the source / drain component 136. The source / drain contacts are formed by depositing a metal layer on the silicide layer 152. In some embodiments, the source / drain contacts 154 include W, Ru, Co, Cu, Mo, TaN, TiN, or other suitable materials. In some embodiments, the source / drain contacts are formed directly on the silicide layer 152. The source / drain contacts 154 can be deposited by PVD, ALD, CVD, or other suitable deposition processes. In some embodiments, the source / drain contacts 154 can be formed in a bottom-up manner. In some embodiments, the source / drain contacts 154 include tungsten formed in a bottom-up manner. In some embodiments, the silicide layer 152 has a curved profile.

[0075] Figure 9BThe top view shows the layout position of the source / drain contacts 154 relative to the active regions A1 / A2 and the gate metal layouts G1-G4. The source / drain contact layout regions are labeled SDC1-3. The source / drain contacts are initially arranged as strips extending in the Y direction and parallel to the gate layouts between them. In some embodiments, a source / drain contact dicing process is performed to form source / drain contact dicing regions SDCC. The source / drain contact dicing regions SDCC correspond to locations where the source / drain contact lines SDC are interrupted or broken to achieve electrical isolation of the individual source / drain contacts 154. In some embodiments, the SDCC regions are formed by performing an etching process after depositing source / drain contact metal, which patterns the source / drain contacts 154. In some embodiments, the SDCC regions are formed by depositing metal for the source / drain contacts 154 in trenches extending in the Y direction, these trenches being segmented by the presence of dielectric structures. A similar gate dicing process can be performed to electrically isolate separate portions of the gate metal 148. In some embodiments, the source / drain contact 154 has a width between 5 nm and 20 nm in the X direction, but other dimensions may be utilized without departing from the scope of this disclosure.

[0076] exist Figure 9A In this process, a dielectric layer 160 has been formed on the top surface of the integrated circuit 100. Specifically, the dielectric layer 160 is located on the top surface of the gate metal 148, the interlayer dielectric layer 143, the source / drain contact 154, and other exposed structures. In some embodiments, the dielectric layer 160 includes SiC, LaO, AlO, AlON, SiN, Si, ZnO, ZrN, ZrAlO, TiO, TaO, Y2O3, TaCN, ZrSi, SiOCN, SiOC, SiCN, HfSi, LaO, SiO, HfO, ZrO, and HfAl. x O y HfSi x O y Or other suitable materials.

[0077] exist Figure 9A In this process, dielectric layer 162 has been formed on dielectric layer 160. In some embodiments, dielectric layer 162 includes SiC, LaO, AlO, AlON, SiN, Si, ZnO, ZrN, ZrAlO, TiO, TaO, Y2O3, TaCN, ZrSi, SiOCN, SiOC, SiCN, HfSi, LaO, SiO, HfO, ZrO, and HfAl. x O y HfSi x O yOr other suitable materials. Other materials may be used without departing from the scope of this disclosure. The dielectric layer 162 may be deposited by ALD, CVD, PVD or other suitable deposition processes.

[0078] Figure 10 This is a cross-sectional view of an integrated circuit 100 according to some embodiments. A trench 164 has been formed through dielectric layers 160 and 162. The trench 164 is formed by combining photolithography and corresponding etching processes, which expose selected portions of the gate metal 148. In some embodiments, the etching process is an anisotropic etching process that selectively etches in the downward direction. After the etching process, selected portions of the gate metal 148 are exposed.

[0079] Figure 11A This is a cross-sectional view of an integrated circuit 100 according to some embodiments. Figure 11B This is a top view of the layout of an integrated circuit 100 according to some embodiments. Figure 11A The view corresponds to Figure 11B Cutting line 11A.

[0080] exist Figure 11A In this embodiment, a local gate interconnect structure 166 has been formed on the exposed portion of the gate metal 148. The local gate interconnect structure 166 is formed by depositing a metal layer on the integrated circuit 100. The metal layer fills the trench 164 and covers the top surface of the interlayer dielectric layer 162. A CMP process is then performed to remove the metal layer from the top surface of the interlayer dielectric layer 162 and reduce the thickness of both the metal layer and the interlayer dielectric layer 162. The result is the formation of a local gate interconnect structure on the exposed top surface of the gate metal 148. The local gate interconnect structure facilitates the formation of gate contacts (e.g., gate contact vias) with greater flexibility and reduced layout constraints. In some embodiments, the local gate interconnect structure 166 comprises W, Ru, Cu, Co, Mo, TaN, TiN, or other suitable conductive materials. The conductive material of the local gate interconnect structure 166 can be deposited using PVD, ALD, CVD, or other suitable deposition processes. Figure 11B As better illustrated, the local gate interconnect structure has a trench 164 layout.

[0081] In some embodiments, the local gate interconnect structure 166 has a height between 3 nm and 20 nm. Therefore, as will be described in further detail below, the local gate interconnect structure 166 is relatively thin compared to the thickness of the gate contact via. In some embodiments, the local gate interconnect structure 166 has a width between 5 nm and 30 nm in the X direction. In some embodiments, the width of the local gate interconnect structure 166 in the X direction is less than the width of the exposed top surface of the gate metal 148 in the X direction. In some embodiments, the local gate interconnect structure 166 has a length between 5 nm and 100 nm in the Y direction. In some embodiments, when the contact length corresponds to the length in the Y direction of the contact between the local gate interconnect structure and the gate metal 148, the local gate interconnect structure 166 has a contact length in the Y direction between half the width of the channel 105. The layout, material, and height, width, and length dimensions of the local gate interconnect structure 166 as described above enable a larger gate isolation structure width without the risk that the gate contact via 172 cannot fall on the gate metal 148. Therefore, photolithographic constraints are relaxed. Furthermore, the height, width, and length of the local gate interconnect structure significantly reduce gate contact resistance while improving distributed gate resistance performance. This prevents or significantly reduces threshold voltage shift. Other dimensions can be utilized without departing from the scope of this disclosure.

[0082] According to some embodiments, Figure 11B The layout diagram illustrates the location of the local gate interconnect structure 166. In some embodiments, the local gate interconnect structure extends beyond the edge of the gate metal 148 in the Y direction. In some embodiments, as will be described in more detail below, the local gate interconnect structure 166 extends beyond the edge of the gate metal 148 in the Y direction, beyond the edge of the dielectric that isolates portions of the gate metal 148 from each other. In some embodiments, the local gate interconnect structure 166 covers the entire width of the active region in the Y direction. In some embodiments, the local gate interconnect structure 166 partially overlaps with the active region. Various configurations of the local gate interconnect structure 166 may be utilized without departing from the scope of this disclosure.

[0083] Figure 12 This is a cross-sectional view of an integrated circuit 100 according to some embodiments. Figure 12In this process, an interlayer dielectric layer 170 has been deposited on the interlayer dielectric layer 162 and the local gate interconnect structure 166. In some embodiments, the interlayer dielectric layer 170 corresponds to the regrowth of the interlayer dielectric layer 162. In some embodiments, the interlayer dielectric layer 170 is made of the same material as the interlayer dielectric layer 162. In some embodiments, the interlayer dielectric layer 170 and the interlayer dielectric layer 162 are sublayers of the same interlayer dielectric layer. In some embodiments, the interlayer dielectric layer 170 includes SiC, LaO, AlO, AlON, SiN, Si, ZnO, ZrN, ZrAlO, TiO, TaO, Y2O3, TaCN, ZrSi, SiOCN, SiOC, SiCN, HfSi, LaO, SiO, HfO, ZrO, and HfAl. x O y HfSi x O y Or other suitable materials. Other materials may be used without departing from the scope of this disclosure. The dielectric layer 170 may be deposited by ALD, CVD, PVD or other suitable deposition processes.

[0084] exist Figure 12 In some embodiments, a trench 171 has been formed through the interlayer dielectric layer 170. The trench 171 is formed in conjunction with a photolithography process and a corresponding etching process, which expose selected portions of the local gate interconnect structure 166. In some embodiments, the etching process is an anisotropic etching process that selectively etches in the downward direction. After the etching process, selected portions of the local gate interconnect structure 166 are exposed. In some embodiments, as described in more detail below, the trench 171 corresponds to a gate contact trench in which a gate contact conductive via will be formed.

[0085] Figure 13A This is a cross-sectional view of an integrated circuit 100 according to some embodiments. Figure 13B This is a cross-sectional view of an integrated circuit 100 according to some embodiments. Figure 13C This is a top view of the layout of an integrated circuit 100 according to some embodiments. Figure 13A and Figure 13B The cross-sectional view corresponds to Figure 13C Cutting lines 13A and 13B.

[0086] exist Figure 13AIn this embodiment, a gate contact via 172 has been formed on the exposed portion of the local gate interconnect structure 166. The gate contact via 172 is formed by depositing a metal layer on the integrated circuit 100. The metal layer fills the trench 171 and covers the top surface of the interlayer dielectric layer 170. A CMP process is then performed to remove the metal layer from the top surface of the interlayer dielectric layer 170 and reduce the thickness of both the metal layer and the interlayer dielectric layer 170. The result is that the gate contact via 172 is formed on the exposed top surface of the local gate interconnect structure 166. In some embodiments, the gate contact via 172 comprises tungsten, ruthenium, copper, cobalt, molybdenum, tantalum nitride, titanium nitride, or other suitable conductive materials. The conductive material for the gate contact via 172 can be deposited using PVD, ALD, CVD, or other suitable deposition processes.

[0087] In some embodiments, the local gate interconnect structure 166 has a larger width and length than the gate contact via 172. The increased width in the X direction and increased length in the Y direction of the local gate interconnect structure 166 relative to the gate contact via 172 facilitate relaxed layout constraints on the gate contact via 172 (such as overlapping or placement beyond the edge of the gate metal 148). The increased length and width of the interconnect structure 166 also provide reduced resistance due to the large contact area between the gate metal 148 and the local gate interconnect structure 166. In some embodiments, the vertical thickness of the local gate interconnect structure 166 is less than the vertical thickness of the gate contact via 172. This overall thickness reduction of the local gate interconnect structure 166 is a portion of the relaxation of photolithographic constraints during the patterning of the dielectric layer 170 to form the layout of the gate contact via 172. In some embodiments, the edge or sidewall of the gate contact via 172 is not aligned with the edge or sidewall of the local gate interconnect structure 166. In some embodiments, an interface exists between the gate contact via 172 and the local gate interconnect structure 166. According to some embodiments, the interface is particularly noticeable when the material of the local gate interconnect structure 166 is different from the material of the gate contact via 172.

[0088] In some embodiments, the gate contact via 172 has a height between 3 nm and 20 nm. Therefore, as will be described in further detail below, the gate contact via 172 is relatively thin compared to its thickness. In some embodiments, the gate contact via 172 has a width between 5 nm and 40 nm in the X direction. In some embodiments, the gate contact via 172 has a height between 10 nm and 50 nm. Other dimensions may be utilized without departing from the scope of this disclosure. In some embodiments, the local gate interconnect structure 166, the source / drain contact 154, and the gate contact via 172 do not have completely vertical sidewalls. In some embodiments, the sidewalls of the ramp are at an angle between 85° and 90° relative to the horizontal plane. In some embodiments, the pitch of the transistor 101 (the distance in the X direction between the centers of the gate metal of adjacent transistors 101) is between 35 nm and 100 nm, but other dimensions may be utilized without departing from the scope of this disclosure.

[0089] The use of a local gate interconnect structure 166 in conjunction with a gate contact via offers several benefits. For example, the gate contact via landing is not limited to the gate metal 148. Instead, the local gate interconnect structure 166 can cover the gate cut structure outside the end of the gate metal 148 in the Y direction, allowing the gate contact via 172 to also land outside the gate metal 148, thereby relaxing layout constraints. This enables the implementation of larger gate isolation structure widths without the risk that the gate contact via cannot land on the gate metal. Thus, lithographic constraints are relaxed. Furthermore, the gate contact resistance is significantly reduced, while the performance of the distributed gate resistance is improved. In some embodiments, the contact resistance Rc of the gate contact via 172 is reduced by between 50Ω and 200Ω compared to a solution without utilizing the local gate interconnect structure 166. In some embodiments, the performance of the distributed gate resistance Ro is improved by between 0.5% and 2%. In some embodiments, the threshold voltage offset is reduced to near 0V compared to a solution without utilizing the local gate interconnect structure 166.

[0090] Figure 13B The locations of the break in the local gate interconnect structure 166 and gate contact via 172 relative to the gate metal 148 adjacent to the gate isolation structure 174 are shown according to some embodiments. The layout location of the gate isolation structure 174 is... Figure 13C The layout is further explained in the top view.

[0091] As previously described, in some embodiments, the gate cleaved regions (GC) are implemented to electrically isolate portions of the gate metal layout (e.g., G2) from each other. Formation of the gate cleaved regions may include a patterned mask that exposes openings in the gate metal 148 at the locations of the gate cleaved regions. An etching process is then performed to remove the gate metal at the exposed locations, thereby electrically isolating adjacent portions of the gate metal 148 from each other. Dielectric material is then deposited at these locations to form a gate isolation structure 174. Figure 13B and Figure 13C A single gate isolation structure 174 at the end of G2 is shown. However, in practice, multiple gate isolation structures 174 may be formed in each gate metal line G in a circuit layout. In some embodiments, the gate isolation structure 174 comprises one or more of SiO, SiN, SiON, SiOCN, SiOC, SiCN, or other suitable dielectric materials.

[0092] Figure 13B and Figure 13C The view shows that a local gate interconnect structure 166 extends in the Y direction along the edge of the gate metal 148, across the gate isolation structure 174 between adjacent portions of the gate metal 148. As previously described, this increases layout flexibility. Furthermore, a gate contact via 172 is also located above the edge of the gate metal 148 and extends partially above the gate isolation structure 174.

[0093] Figure 13C The location of a source / drain via 173 according to some embodiments is also shown. The source / drain via 173 rests on a source / drain contact 154. The source / drain via 173 provides electrical coupling between the source / drain contact 154 and a metal line subsequently formed over the source / drain via 173. In some embodiments, the source / drain via 173 has a width between 5 nm and 40 nm in the X direction. In some embodiments, the source / drain via 173 comprises W, Ru, Cu, Co, Mo, TaN, TiN, or other suitable conductive materials.

[0094] Figure 14 This is a cross-sectional view of an integrated circuit 100 according to some embodiments. Figure 14 Integrated circuits and Figure 13A The integrated circuits are basically similar, except that... Figure 14 The source / drain via 173 is shown. (Example) Figure 13CAs can be seen in the view, in practice, the source / drain via 173 can be offset in the Y direction, such that the cross-sectional view in the X direction may not actually pass through the channel 105, the gate contact via 172, and the source / drain contact via 173. However, for the purpose of illustrating some aspects of the integrated circuit 100, according to some embodiments, it is advantageous to show the source / drain via 173 in the same view as the gate contact via 172.

[0095] In some embodiments, the source / drain via 173 is formed in the same processing steps as the gate contact via 172. Specifically, this is achieved when photolithography and etching processes are performed to open... Figure 12 When trench 171 is shown, trench 171 is also formed to expose the source / drain contacts 154 and the contact locations for the source / drain via 173. The deposition process that forms the gate contact via 172 also forms the source / drain via 173. After the CMP process, the top surface of the source / drain via 173 is coplanar with the top surface of the gate contact via 172. Therefore, in some embodiments, the source / drain via 173 is made of the same material as the gate contact via 172. In some embodiments, the height of the source / drain via 173 in the Z direction (the vertical distance between the top of the source / drain contact 154 and the top of the source / gate via 173) is greater than the height of the gate contact via 172 in the Z direction. In some embodiments, the height of the source / drain via 173 is between 15 nm and 120 nm, but other heights may be used without departing from the scope of this disclosure.

[0096] Figure 15 This is a layout top view of an integrated circuit 100 according to some embodiments. The layout top view shows two cells of the integrated circuit 100 according to some embodiments. As previously described, these cells utilize a local gate interconnect structure 166. The layout of the cells is... Figure 13C The layout top view is basically the same, except that a local gate interconnect structure 166 extends across the boundary between cells to electrically connect the gate metal of cell 1 to the gate metal of cell 2. In some embodiments, the gate metal 148 of the cells is separated by a gate cleaved region GC including a gate isolation structure 174. Figure 15 In the view, a gate contact via 172 is present at each end of the local gate interconnect structure 166. In other words, according to some embodiments, a plurality of gate contact vias fall on each local gate interconnect structure 166. This can provide current dispersion and lower resistance. Figure 15 In the example, the local gate interconnect structure 166 is contacted by a first gate contact via 172 at cell 1 and a second gate contact via 172 at cell 2.

[0097] Figure 16This is a layout top view of an integrated circuit 100 according to some embodiments. The layout top view shows two cells of the integrated circuit 100 according to some embodiments. As previously mentioned, these cells utilize a local gate interconnect structure 166. The layout of the cells is... Figure 15 The top view of the layout is basically the same, except that a single gate contact via 172 falls on a local gate interconnect structure that electrically connects the gate metals of the two cells. As can be seen, regardless of any cross-contamination, the use of the local gate interconnect structure allows for greater flexibility in the placement of the gate contact via 172. Figure 16 The gate contact via 172 is now located between A1 and A2. Other locations of the gate contact via 172 may be utilized without departing from the scope of this disclosure.

[0098] Figure 17A This is a cross-sectional view of an integrated circuit 100 according to some embodiments. Figure 17B yes Figure 17A A top view of the layout of integrated circuit 100. Figure 17A The view corresponds to Figure 17B Cutting line 17A.

[0099] Figure 17A Integrated circuits and Figure 14 The integrated circuit is essentially similar, except that a local source / drain interconnect structure 167 is used to facilitate the layout flexibility of the source / drain via 173. More specifically, the process used to form the local gate interconnect structure 166 also forms the local source / drain interconnect structure 167 on the top surface of the source / drain contact 154. Therefore, the photolithography and etching processes that expose the gate metal 148 through the dielectric layers 160 and 162 also expose the source / drain contacts at the selected locations for the local source / drain interconnect structure 167. The deposition of the metal layer forming the local gate interconnect structure 166 also forms the local source / drain interconnect structure 167. In some embodiments, the local gate interconnect structure 166 and the local source / drain interconnect structure 167 may be referred to as local interconnect structures. The use of the local source / drain interconnect structure relaxes the layout constraints of the source / drain via 173. The source / drain via 173 falls on and contacts the local source / drain interconnect structure 167. In this configuration, the local source / drain interconnect structure 167 has the same height and width in the X direction as the local gate interconnect structure 166. The source / drain via 173 has the same height as the gate contact via 172.

[0100] Figure 18 This is a simplified perspective view of an integrated circuit 100 according to some embodiments. Figure 18 The simplified 3D diagram does not show the dielectric layer. Figure 18A gate metal 148 is shown that spans two active regions A1 and A2 in the Y direction. Active regions A1 and A2 extend in the X direction. Figure 18 A first transistor 101a (where gate metal 148 spans active region A1) and a second transistor 101b (where gate metal 148 spans active region A2) are shown. The channels of transistors 101a and 101b are in... Figure 18 They are not visible in the view because they are obscured by the source / drain components 136. However, in practice, transistor 101a includes a stacked channel extending in the X direction between the source / drain components 136a. Gate metal 148 surrounds the channel of transistor 101a. Transistor 101b also includes a stacked channel extending in the X direction between the source / drain components 136b. Figure 18 (Only a single source / drain component 136b is visible). Source / drain contact 154a is coupled to the left side (in the X direction) of source / drain component 136a of transistor 101a. Source / drain contact 154b is electrically coupled to the source / drain component 136b of transistor 101b. Although... Figure 18 Not shown, but a silicide layer exists between the source / drain component 136 and the corresponding source / drain contact 154. Source / drain contact via 173a contacts the left source / drain contact 154a. Source / drain contact via 173b contacts the right source / drain contact 154b.

[0101] Figure 18 A partial gate interconnect structure 166 on the top surface of the gate metal 148 is shown. (See diagram.) Figure 18 As can be seen, the local gate interconnect structure 166 extends beyond the edge of the gate metal 148 in the Y direction. The width of the gate metal 148 in the X direction is greater than the width of the local gate interconnect structure 166. The gate contact via 172 falls on the local gate interconnect structure 166 at a location that also overlaps with the edge of the gate metal 148. Other configurations may be used without departing from the scope of this disclosure.

[0102] Figures 19 to 26 This is a cross-sectional view and a layout top view illustrating the process of forming an integrated circuit 100 using a local gate interconnect structure according to some embodiments.

[0103] Figure 19 This is a cross-sectional view of an integrated circuit 100 according to some embodiments. Figure 19 The processing stages shown are similar to Figure 3A In the processing stage shown, in addition to an additional sacrificial semiconductor layer 106 on the highest semiconductor layer 104, a layer 177 is formed on the highest sacrificial semiconductor layer 106, and a gate protection layer 179 is formed on the layer 177.

[0104] In some embodiments, layer 177 is a semiconductor layer made of the same semiconductor material as semiconductor layer 104. In some embodiments, layer 177 is a dielectric layer. The dielectric material may include SiO, SiN, SiON, SiOCN, SiOC, SiCN, or other suitable dielectric materials.

[0105] In some embodiments, the gate protection layer 179 is a dielectric layer. The gate protection layer 179 may include SiOCN, SiOC, SiCN, SiON, or other suitable dielectric materials. The gate protection layer 179 has a thickness between 2 nm and 15 nm, but other thicknesses may be used without departing from the scope of this disclosure.

[0106] exist Figure 19 In, according to some embodiments, basically as regarding Figure 3A As described above, a sacrificial gate structure 114 has been formed. The sacrificial gate structure 114 is formed on the gate protection layer 179. The sacrificial gate structure includes a dielectric layer 116 of the gate protection layer 179, a sacrificial gate layer 118 on the dielectric layer 116, a dielectric layer 182 on the sacrificial gate layer 118, and a dielectric layer 184 on the dielectric layer 182. Figure 3A Dielectric layers 182 and 184 are not shown in the diagram; however, in practice, Figure 3A The sacrificial gate structure 114 may also include dielectric layers 182 and 184. In some embodiments, dielectric layer 182 comprises silicon nitride, and dielectric layer 184 comprises silicon oxide. Optionally, dielectric layer 182 may comprise SiO, SiON, SiOCN, SiCN, SiOC, or other suitable dielectric materials. Dielectric layer 184 may comprise SiN, SiON, SiOCN, SiCN, SiOC, or other suitable dielectric materials. Figure 19 In the middle, the gate spacer layer 120 has not yet been deposited.

[0107] exist Figure 20 In, according to some embodiments, basically as regarding Figure 4 As described above, a gate spacer layer 120 and a source / drain trench 124 have been formed. The formation of the source / drain trench 124 results in the formation of a gate protection structure 180 from the gate protection layer 179. The gate spacer layer 120 is located on the top surface of the gate protection structure 180. Although Figure 20 Not shown in the diagram, but the source / drain trench 124 can also extend into the substrate 102, such as... Figure 4 As shown. Optionally, a subsequent etching process can extend the source / drain trench 124 into the substrate 102.

[0108] In some embodiments, the gate protection structure 180 has the same width and length as the top channel 105 of each stack 126. This is because the gate protection structure 180 is patterned using the gate spacer layer 120 and the sacrificial gate structure 114 as a mask. Layer 177 also has these dimensions.

[0109] exist Figure 21 In, according to some embodiments, basically as follows: Figures 5 to 8A The bottom semiconductor layer 132, bottom dielectric structure 134, internal spacer 130, and source / drain components 136 have been formed. Figure 21 In this configuration, the highest internal spacer 130 is located between the top channel 105 and the gate protection structure 180. Furthermore, the source / drain component 136 has a top surface located in the middle of the highest internal spacer 130.

[0110] exist Figure 22 In, according to some embodiments, basically as regarding Figure 8A As described, CESL 140, interlayer dielectric layer 143, interface gate dielectric layer 144, high-k gate dielectric layer 146, and gate metal 148 have been formed. Figure 22 In this configuration, a dielectric layer 186 has been formed on top of the interlayer dielectric layer 143. The dielectric layer 186 may include SiN, SiOCN, SiCN, SiON, or other suitable dielectric materials.

[0111] Figure 23 This is a cross-sectional view of an integrated circuit 100 according to some embodiments. Figure 23 The processing stages shown are Figure 9A The processing stages shown are basically similar, except that, as previously mentioned, the gate protection structure 180 has been formed according to some embodiments, and the dielectric layers 160 and 162 have not yet been formed. Figure 23 In this process, a CMP process has been performed to remove a portion of the gate metal 148 and the gate spacer layer 120 from the top surface of the gate protection structure 180. Therefore, the top surface of the gate protection structure 180 is flush with the gate metal 148, since the gate metal 148 is located on either side of the gate protection structure 80 in the Y direction (in...). Figure 23 (Not obvious in the view).

[0112] Figure 24 This is a cross-sectional view of an integrated circuit 100 according to some embodiments. Figure 19 The processing stages shown are related to Figure 11A The processing stages shown are essentially similar, with a gate protection structure 180 present. Specifically, dielectric layers 160 and 162 have been deposited and patterned to expose the gate metal 148 and the gate protection structure 180 at selected locations. A local gate interconnect structure 166 is then formed by depositing metal layers and performing a CMP process, as described above. Figure 11A As stated. Although Figure 24 Not shown in the diagram, but the local gate interconnect structure 166 is also located on the gate metal 148 adjacent to the gate protection structure 180 in the Y direction. This is described below. Figure 25B It's more obvious in the view.

[0113] Figure 25A This is a cross-sectional view of an integrated circuit 100 according to some embodiments. Figure 25B This is a cross-sectional view of an integrated circuit 100 according to some embodiments. Figure 25C This is a top view of the layout of an integrated circuit 100 according to some embodiments. Figure 25A and Figure 25B The view corresponds to Figure 25C Cutting lines 20A and 20B are shown.

[0114] Figures 25A to 25C The integrated circuit 100 is in Figures 13A to 13C The same processing stage is shown, except for the presence of gate protection structure 180. Specifically, it is basically as described regarding Figures 13A to 13C As described above, a dielectric layer 170 has been deposited, and a gate contact via 172 has been formed on the local gate interconnect structure 166. (As can be...) Figures 25A to 25C As can be seen, the gate contact via 172 can be located directly above the gate protection structure 180 (and correspondingly above the active region). In solutions that do not utilize local gate interconnect structures, the gate contact via 172 cannot fall directly on the gate protection structure 180 because the gate protection structure 180 is non-conductive and does not provide electrical connection to the gate metal 148. However, when the gate protection structure 180 is utilized, the use of the local gate interconnect structure 166 provides greater flexibility in the potential layout location of the gate contact via 172. Figures 19 to 25C The materials and dimensions used in the various structures of the integrated circuit 100 can be related to... Figures 1 to 17B The same applies to those described herein. The combined gate protection structure 180 utilizes the local gate interconnect structure 166 to provide improved pseudo-contacts, reducing oxidation of the gate metal and relaxing the layout constraints of the gate contact via 172. Furthermore, compared to solutions without utilizing the local gate interconnect structure 166, the contact resistance of the gate structure on the gate protection structure 180 utilizing the local gate interconnect structure 166 is reduced by between 50 Ω and 1000 Ω. Additionally, in some embodiments, the threshold voltage offset of the transistor in the active region is reduced from 30 mV to 0. The gate resistance Rg is reduced by between 50 Ω / sq and 200 Ω / sq. According to some embodiments, the dispersion resistance performance of the gate structure is improved by between 0.5% and 2%.

[0115] Figure 25BThe view more clearly shows how the local gate interconnect structure 166 overlaps and directly contacts the gate protection hard mask structure 180, the high-k gate dielectric layer 146, and the gate metal 148. Furthermore, Figure 15 and Figure 16 The additional layout of the local gate interconnect structure shown can be utilized together with the gate protection structure. Furthermore, Figure 17A and Figure 17B The local source / drain interconnect structure 167 can also be used together with the gate protection structure 180.

[0116] Figure 26 This is a cross-sectional view of an integrated circuit 100 according to some embodiments. Figure 26 In this structure, the local gate interconnect structure 166 extends across the entire gate protection structure 180 in the Y direction. Therefore, the local gate interconnect structure contacts the gate metal 148 on either side of the gate protection structure 180 in the Y direction. This further reduces the overall resistance of the gate structure and provides greater flexibility in the placement of the gate contact via 172.

[0117] Figure 27 This is a perspective view of an integrated circuit 100 according to some embodiments. Figure 27 The integrated circuit 100 is in most respects with Figure 18 The integrated circuit 100 is basically similar, except that it has a local source / drain interconnect structure 167 but no local gate interconnect structure 166 and gate contact via 172. The metal lines 190 of the first metal layer of the integrated circuit 100 electrically couple the two source / drain vias 173.

[0118] Figure 28 This is a flowchart of a method 2800 for forming an integrated circuit according to some embodiments. Method 2800 can utilize... Figures 1 to 27 The related description includes structures, processes, and systems. At 2802, method 2800 includes depositing an isolation structure between a first semiconductor fin at a first active region and a second semiconductor fin at a second active region, wherein the isolation structure is in contact with a first fin substrate region of the first semiconductor fin and a second fin substrate region of the second semiconductor fin. An example of the first semiconductor fin and the second semiconductor fin is... Figure 2A Semiconductor fins 108a / 108b. Figure 2A An example of the first active region A1 and the second active region A2. An example of an isolation structure is... Figure 2A The isolation structure 112. An example of the fin base region is... Figure 2AThe fin substrate region 109 is shown. At 2804, method 2800 includes defining multiple stacked channels of a transistor at a first active region from multiple stacked semiconductor layers of the first semiconductor fin by forming a first source / drain trench and a second source / drain trench in the first semiconductor fin. An example of a stacked channel is... Figure 4 The channel 105. At 2806, method 2800 includes depositing a first source / drain component of the transistor in a first source / drain trench. At 2808, method 2800 includes depositing a second source / drain component of the transistor in a second source / drain trench in a first semiconductor fin. An example of the first source / drain trench and the second source / drain trench is... Figure 4 The source / drain trench 124. An example of the first source / drain component and the second source / drain component is... Figure 8A The first source / drain component and the second source / drain component 136. At 2810, method 2800 includes depositing an interface gate dielectric layer on the channel. An example of an interface gate dielectric layer is... Figure 8A The interface gate dielectric layer 144. At 2812, method 2800 includes depositing a high-k gate dielectric layer on the interface gate dielectric layer, and a gate spacer layer extending along the sidewalls of the gate structure, wherein the dielectric constant of the high-k gate dielectric layer is greater than the dielectric constant of the gate spacer layer. An example of a high-k gate dielectric layer is... Figure 8A A high-k gate dielectric layer 146. At 2814, method 2800 includes depositing gate metal on the high-k dielectric layer. An example of the gate metal is... Figure 8A The gate metal 148. At 2816, method 2800 includes depositing source / drain contacts on the first source / drain portion of the transistor. An example of a source / drain contact is... Figure 9A The source / drain contact 154. At 2818, method 2800 includes depositing an interconnect structure on the gate metal above the channel. An example of the interconnect structure is... Figure 11A Interconnect structure 166. At 2820, method 2800 includes depositing a first interlayer dielectric layer over the interconnect structure and source / drain contacts. An example of the first interlayer dielectric layer is... Figure 12 The interlayer dielectric layer 170. At 2822, method 2800 includes forming a first opening in the first interlayer dielectric layer to expose the interconnect structure. An example of the first opening is... Figure 12 The central trench 171. At 2824, method 2800 includes depositing a gate contact via in the first opening, the gate contact via falling on the interconnect structure and electrically coupled to the gate metal. An example of a gate contact via is... Figure 13AGate contact via 172. At 2826, method 2800 includes forming a second opening in the first interlayer dielectric layer to expose the source / drain contact. At 2828, method 2800 includes depositing a source / drain via in the second opening, the source / drain via being electrically coupled to the first source / drain contact. An example of a source / drain via is... Figure 14 The source / drain via is 173.

[0119] Figure 29 This is a flowchart of a method 2900 for forming an integrated circuit according to some embodiments. Method 2900 can utilize... Figures 1 to 27 Related structures, processes, and systems. At 2902, method 2900 includes forming a first active region extending in a first lateral direction. At 2904, method 2900 includes forming a second active region extending in the first lateral direction. At 2906, method 2900 includes depositing an isolation structure between the first and second active regions. An example of the first and second active regions is... Figure 2A The active regions are 108a / 108b. An example of an isolation structure is... Figure 2A The isolation structure 112. At 2908, method 2900 includes depositing a first source / drain component of a transistor in the first active region, and the first source / drain component is suspended above the isolation structure. At 2910, method 2900 includes depositing a second source / drain component of a transistor in the first active region, and a plurality of channels of the transistor extending in a first lateral direction between the first source / drain component and the second source / drain component. An example of the first source / drain component and the second source / drain component is... Figure 8A The source / drain component 136. At 2912, method 2900 includes depositing a gate structure that extends across a first active region, a second active region, and an isolation structure in a second lateral direction, and encloses a plurality of stacked channels of the transistor. An example of a stacked channel is... Figure 4 The channel 105. An example of the gate structure is... Figure 8A Gate metal 148. At 2914, method 2900 includes depositing a source / drain contact electrically coupled to the source / drain component through a silicide layer, wherein the conductivity of the silicide layer is greater than the conductivity of the source / drain component. An example of the source / drain contact is... Figure 9A The source / drain contact 154. At 2916, method 2900 includes depositing a first dielectric layer on the gate structure. An example of the first dielectric layer is... Figure 10 The dielectric layer 162. At 2918, method 2900 includes forming a first opening in the first dielectric layer. An example of the first opening is... Figure 10The opening is 164. At 2920, method 2900 includes depositing a metal layer in the first opening on the gate structure, the metal layer extending in a second lateral direction above the channel and isolation structure. An example of the metal layer is... Figure 11A Metal layer 166. At 2922, method 2900 includes depositing a first gate contact via on the metal layer, the first gate contact via being electrically coupled to a gate structure through the metal layer. An example of the first gate contact via is... Figure 13A Gate contact via 172.

[0120] The disclosed embodiments provide a local interconnect metal layer on the gate metal, which helps increase the layout possibilities for gate contact landing. After forming the gate metal, a local interconnect metal layer is deposited on the top surface of the gate metal and patterned to form a local gate interconnect structure on the gate metal. An interlayer dielectric layer is then deposited and patterned to expose the local gate interconnect structure at selected gate contact locations. Gate contact vias are then formed in the openings, providing electrical contact to the gate metal through the local gate interconnect structure. The use of the local gate interconnect structure offers several benefits. The local gate interconnect structure can extend over the gate isolation structure or gate protection structure, providing a larger area for gate contact via landing. This allows for larger gate isolation structure widths without the risk of gate contact vias failing to land on the gate metal. Therefore, lithographic constraints are relaxed. Furthermore, gate contact resistance is significantly reduced, while distributed gate resistance performance is improved. Threshold voltage offset is prevented or significantly reduced. Embodiments of this disclosure also provide better-functioning integrated circuits and higher wafer yields.

[0121] In some embodiments, a method includes depositing an isolation structure between a first semiconductor fin at a first active region and a second semiconductor fin at a second active region. The isolation structure is in contact with a first fin substrate region of the first semiconductor fin and a second fin substrate region of the second semiconductor fin. The method includes defining a plurality of stacked channels of a transistor from a plurality of stacked semiconductor layers of the first semiconductor fin at the first active region by forming a first source / drain trench and a second source / drain trench in the first semiconductor fin, depositing a first source / drain component of the transistor in the first source / drain trench, and depositing a second source / drain component of the transistor in the second source / drain trench in the first semiconductor fin. The method includes depositing an interface gate dielectric layer on the channel, depositing a high-k gate dielectric layer on the interface gate dielectric layer, and depositing a gate metal on the high-k gate dielectric layer, with a gate spacer layer extending along the sidewalls of the gate structure. The dielectric constant of the high-k gate dielectric layer is greater than the dielectric constant of the gate spacer layer. The method includes depositing source / drain contacts on a first source / drain component of a transistor, depositing an interconnect structure on gate metal above a channel, depositing a first interlayer dielectric layer over the interconnect structure and the source / drain contacts, and forming a first opening in the first interlayer dielectric layer to expose the interconnect structure. The method includes depositing a gate contact via in the first opening, the gate contact via falling on the interconnect structure and electrically coupled to the gate metal, forming a second opening in the first interlayer dielectric layer, the second opening exposing the source / drain contacts, and depositing a source / drain via in the second opening, the source / drain via being electrically coupled to the source / drain contacts. In some embodiments, the method further includes forming the first interlayer dielectric layer on a second interlayer dielectric layer, wherein the top surface of the second interlayer dielectric layer is aligned with the top surface of the interconnect structure. In some embodiments, the method further includes forming the source / drain via and the gate contact via using the same deposition process. In some embodiments, the top surfaces of the source / drain contacts and the gate metal are aligned, wherein the top surface of the source / drain via is aligned with the top surface of the gate contact via, and wherein the source / drain via has a greater height than the gate contact via. In some embodiments, the method further includes: forming a partial source / drain interconnect structure on the top surface of the source / drain contacts; and depositing the source / drain via on the partial source / drain interconnect structure. In some embodiments, the method includes depositing the partial source / drain interconnect structure and the interconnect structure in the same deposition process. In some embodiments, the method further includes electrically isolating the first segment of the gate metal from the second segment of the gate metal by removing a portion of the gate metal and forming a gate isolation structure between the first segment and the second segment of the gate metal, wherein the first segment encloses the channel, and wherein the interconnect structure overlaps the first segment and the gate isolation structure.In some embodiments, the gate contact via is at least partially located above the gate isolation structure. In some embodiments, the interconnect structure extends across the isolation structure. In some embodiments, the gate contact via is located above the isolation structure.

[0122] In some embodiments, a method includes forming a first active region extending in a first lateral direction, forming a second active region extending in the first lateral direction, depositing an isolation structure between the first and second active regions, and depositing a first source / drain component of a transistor in the first active region, the first source / drain component being suspended above the isolation structure. The method includes depositing a second source / drain component of a transistor in the first active region, a plurality of channels of the transistor extending in the first lateral direction between the first and second source / drain components, depositing a gate structure extending in a second lateral direction across the first active region, the second active region, and the isolation structure and enclosing the channels, and depositing source / drain contacts electrically coupled to the source / drain components through a silicide layer. The conductivity of the silicide layer is greater than the conductivity of the source / drain components. The method includes depositing a first dielectric layer on a gate structure, forming a first opening in the first dielectric layer, depositing a metal layer in the first opening on the gate structure, the metal layer extending in a second lateral direction over a channel and an isolation structure, and depositing a first gate contact via on the metal layer, the first gate contact via being electrically coupled to a gate metal through the metal layer. In some embodiments, the method further includes forming a gate protection structure of dielectric material over the channel, wherein the top surface of the gate structure is aligned with the top surface of the gate protection structure, and wherein the metal layer is located on the gate protection structure and the gate metal. In some embodiments, the metal layer is located on the gate structure on opposite sides of the gate protection structure along the second lateral direction. In some embodiments, the first gate contact via is located above the gate protection structure, wherein the gate protection structure has the same layout as the top channel of a stacked channel in both the first and second lateral directions. In some embodiments, the method further includes forming a second gate contact via falling on the metal layer and electrically coupled to the first gate contact via.

[0123] In some embodiments, the integrated circuit includes an active region extending in a first lateral direction, a first source / drain component located in the active region, a second source / drain component located in the active region, and a plurality of stacked channels extending in the active region between the first source / drain component and the second source / drain component in the first lateral direction. The integrated circuit includes a contact etch stop layer above the first source / drain component and a first interlayer dielectric layer above the contact etch stop layer. The dielectric constant of the contact etch stop layer is greater than the dielectric constant of the first interlayer dielectric layer. The integrated circuit includes a silicide layer on the first source / drain component and a first source / drain contact on the silicide layer and disposed in the first interlayer dielectric layer. The silicide layer has a curved profile. The integrated circuit includes a gate metal enclosing the channels, a second source / drain contact on the second source / drain component, a second interlayer dielectric layer above the gate metal, an interconnect structure on the gate metal, and a gate contact via extending through the second interlayer dielectric layer and falling on the interconnect structure. The interconnect structure has a length greater than the gate contact via in the second lateral direction. The integrated circuit includes a source / drain via extending through an interlayer dielectric layer and electrically coupled to a first source / drain contact. In some embodiments, the height of the source / drain via is equal to the sum of the heights of the interconnect structure and the gate contact via. In some embodiments, the integrated circuit further includes a partial source / drain interconnect structure located on the first source / drain contact, wherein the source / drain via falls on the partial source / drain interconnect structure. In some embodiments, the integrated circuit further includes a gate protection structure of dielectric material located above the channel, wherein the top surface of the gate metal is aligned with the top surface of the gate protection structure, and wherein the interconnect structure is electrically coupled between the gate protection structure and the gate metal. In some embodiments, the interconnect structure contacts the gate metal on opposite sides of the gate protection structure along the second lateral direction, wherein the gate contact via is located above the gate protection structure.

[0124] The foregoing outlines features of several embodiments to enable those skilled in the art to better understand aspects of this disclosure. Those skilled in the art should understand that they can readily use this disclosure as a basis to design or modify other processes and structures for implementing the same purposes and / or achieving the same advantages as the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and alterations can be made to them herein without departing from the spirit and scope of this disclosure.

Claims

1. A method for forming an integrated circuit, comprising: An isolation structure is deposited between a first semiconductor fin at a first active region and a second semiconductor fin at a second active region, wherein the isolation structure is in contact with a first fin base region of the first semiconductor fin and a second fin base region of the second semiconductor fin. By forming a first source / drain trench and a second source / drain trench in the first semiconductor fin, a plurality of stacked channels of transistors are defined at the first active region from a plurality of stacked semiconductor layers of the first semiconductor fin. Deposit the first source / drain components of the transistor in the first source / drain trench; The second source / drain component of the transistor is deposited in the second source / drain trench in the first semiconductor fin; An interface gate dielectric layer is deposited on the channel; A high-k gate dielectric layer is deposited on the interface gate dielectric layer; A gate metal is deposited on the high-k gate dielectric layer, and a gate spacer layer extends along the sidewall of the gate structure, wherein the dielectric constant of the high-k gate dielectric layer is greater than the dielectric constant of the gate spacer layer. Deposit source / drain contacts on the first source / drain component of the transistor; An interconnect structure is deposited on the gate metal above the channel; A first interlayer dielectric layer is deposited over the interconnect structure and the source / drain contacts; A first opening is formed in the first interlayer dielectric layer to expose the interconnect structure; A gate contact via is deposited in the first opening, the gate contact via falling on the interconnect structure and electrically coupled to the gate metal; A second opening is formed in the first interlayer dielectric layer to expose the source / drain contacts; and A source / drain via is deposited in the second opening, and the source / drain via is electrically coupled to the source / drain contact.

2. The method of claim 1, further comprising forming the first interlayer dielectric layer on the second interlayer dielectric layer, wherein, The top surface of the second interlayer dielectric layer is aligned with the top surface of the interconnect structure.

3. The method of claim 1, further comprising forming the source / drain via and the gate contact via using the same deposition process.

4. The method according to claim 3, wherein, The top surfaces of the source / drain contacts and the gate metal are aligned, wherein the top surface of the source / drain via is aligned with the top surface of the gate contact via, and wherein the source / drain via has a greater height than the gate contact via.

5. The method according to claim 3, further comprising: A local source / drain interconnect structure is formed on the top surface of the source / drain contact; as well as The source / drain vias are deposited on the local source / drain interconnect structure.

6. The method of claim 5, comprising depositing the local source / drain interconnect structure and the interconnect structure in the same deposition process.

7. The method of claim 1, further comprising electrically isolating the first segment of the gate metal from the second segment of the gate metal by removing a portion of the gate metal and forming a gate isolation structure between the first segment and the second segment of the gate metal in place of the removed portion of the gate metal, wherein, The first segment encloses the channel, wherein the interconnect structure overlaps with the first segment and the gate isolation structure.

8. The method according to claim 7, wherein, The gate contact via is located at least partially above the gate isolation structure.

9. A method for forming an integrated circuit, comprising: A first active region extending in the first lateral direction is formed; A second active region is formed extending in the first lateral direction; An isolation structure is deposited between the first active region and the second active region; A first source / drain component of a transistor is deposited in the first active region, the first source / drain component being suspended above the isolation structure; A second source / drain component of the transistor is deposited in the first active region, and a plurality of channels of the transistor extend in the first lateral direction between the first source / drain component and the second source / drain component; A gate structure is deposited that extends across the first active region, the second active region, and the isolation structure in the second lateral direction and encloses the channel. A source / drain contact is deposited, wherein the source / drain contact is electrically coupled to the source / drain component through a silicide layer, wherein the conductivity of the silicide layer is greater than the conductivity of the source / drain component; A first dielectric layer is deposited on the gate structure; A first opening is formed in the first dielectric layer; A metal layer is deposited in the first opening on the gate structure, the metal layer extending in the second lateral direction over the channel and the isolation structure; and A first gate contact via is deposited on the metal layer, and the first gate contact via is electrically coupled to the gate metal through the metal layer.

10. An integrated circuit, comprising: The active region extends in the first lateral direction; The first source / drain component is located in the active region; The second source / drain component is located in the active region; Multiple stacked channels are located in the active region, and the multiple stacked channels extend in the first lateral direction between the first source / drain component and the second source / drain component; A contact etch stop layer is located above the first source / drain component; A first interlayer dielectric layer is located above the contact etch stop layer, wherein the dielectric constant of the contact etch stop layer is greater than the dielectric constant of the first interlayer dielectric layer. A silicide layer is located on the first source / drain component; A first source / drain contact is located on the silicide layer, and the first source / drain contact is disposed in the first interlayer dielectric layer, wherein the silicide layer has a curved profile; Gate metal surrounds the channel; The second source / drain contact is located on the second source / drain component; The second interlayer dielectric layer is located above the gate metal; Interconnection structures are located on the gate metal; A gate contact via extends through the second interlayer dielectric layer and rests on the interconnect structure, wherein the length of the interconnect structure in the second lateral direction is greater than the length of the gate contact via in the second lateral direction; and The source / drain via extends through the interlayer dielectric layer and is electrically coupled to the first source / drain contact.

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