Semiconductor memory device, method of forming semiconductor device and memory device

Abstract

The method includes: depositing a multi-layer stack on a semiconductor substrate, the multi-layer stack including a plurality of channel layers alternating with a plurality of sacrificial layers; forming a first fin in a first region of the semiconductor substrate, wherein forming the first fin includes performing an etching process to define a first nanostructure from the plurality of sacrificial layers and a second nanostructure from the plurality of channel layers; forming source / drain regions above the semiconductor substrate and on opposite sides of the first nanostructure; replacing the first nanostructure with a gate structure; and forming a front-side interconnect structure above the gate structure, the front-side interconnect structure including: a first write bit line for a first bit cell and a second write bit line for a second bit cell in a first metallization layer; and a common conductor in a second metallization layer disposed above the first metallization layer. Embodiments of the application also relate to semiconductor memory devices, methods of forming semiconductor devices and memory devices.

Description

Technical Field

[0001] Embodiments of this application relate to semiconductor memory devices, methods of forming semiconductor devices, and memory devices. Background Technology

[0002] Semiconductor devices are used in a variety of electronic applications, such as personal computers, mobile phones, digital cameras, and other electronic devices. Semiconductor devices are typically manufactured by sequentially depositing an insulating or dielectric layer, a conductive layer, and a semiconductor material layer on a semiconductor substrate, and then using photolithography to pattern the individual material layers to form circuit components and elements thereon.

[0003] The semiconductor industry continuously improves the integration density of individual electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by constantly reducing the size of the smallest component, which allows more components to be integrated into a given area. However, as the size of the smallest component decreases, additional problems arise that need to be addressed. Summary of the Invention

[0004] Some embodiments of this application provide a method for forming a semiconductor device including a first bit cell and a second bit cell adjacent to the first bit cell, the method comprising: depositing a multilayer stack on a semiconductor substrate, the multilayer stack including a plurality of sacrificial layers alternating with a plurality of channel layers; forming a first fin in a first region of the semiconductor substrate, wherein forming the first fin includes performing an etching process to define a first nanostructure by the plurality of sacrificial layers and a second nanostructure by the plurality of channel layers; forming a source / drain region above the semiconductor substrate and on the opposite side of the first nanostructure; replacing the first nanostructure with a gate structure; forming an interlayer dielectric layer above the source / drain region; and forming an interlayer dielectric layer extending through the layer. An interlayer dielectric layer is electrically coupled to source / drain contacts in a first source / drain region of the source / drain region, wherein the conductivity of the source / drain contacts is greater than the conductivity of the first source / drain region; and a front-side interconnect structure is formed above the interlayer dielectric layer and the gate structure, the front-side interconnect structure including: a first write bit line for the first bit cell and a second write bit line for the second bit cell, located in the first metallization layer; and a common conductor located in a second metallization layer disposed above the first metallization layer, wherein the common conductor spans the first bit cell and the second bit cell, and wherein a first common conductor of the common conductor is electrically connected to the first write bit line and the second write bit line.

[0005] Other embodiments of this application provide a method for forming a memory device including a first bit cell and a second bit cell, the method comprising: depositing a first sacrificial layer over a semiconductor substrate; depositing a first channel layer over the first sacrificial layer; depositing a second sacrificial layer over the first channel layer; depositing a second channel layer over the second sacrificial layer; forming a first fin in a first region of the semiconductor substrate for the first bit cell, and forming a second fin in a second region of the semiconductor substrate for the second bit cell, wherein forming the first fin and the second fin includes performing an etching process to define a first nanostructure of the first fin and the second fin by the first sacrificial layer and the second sacrificial layer, and to define a second nanostructure of the first fin and the second fin by the first channel layer and the second channel layer; using a first A gate structure replaces the first nanostructure of the first fin, and a second gate structure replaces the first nanostructure of the second fin; a first source / drain region is formed in the first fin on the opposite side of the first gate structure; a second source / drain region is formed in the second fin on the opposite side of the second gate structure; a silicide region is formed above the top surface of the first one in the first source / drain region, wherein the silicide region has a higher conductivity than the first one in the first source / drain region; and a shared read bit line is formed on the back side of the semiconductor substrate, the shared read bit line being disposed at the boundary between the first bit cell and the second bit cell, wherein the shared read bit line is electrically coupled to the first one in the first source / drain region and the first one in the second source / drain region.

[0006] Some embodiments of this application provide a semiconductor memory device, including: a first gate structure located above a first region of a semiconductor substrate, the first region being used for a first bit cell; a second gate structure located above a second region of the semiconductor substrate, the second region being used for a second bit cell, wherein, when viewed in a top view, the first bit cell and the second bit cell are adjacent; a first source / drain region located above the semiconductor substrate and on the opposite side of the first gate structure; a second source / drain region located above the semiconductor substrate and on the opposite side of the second gate structure; and a first active channel region disposed between the first source / drain regions and above the semiconductor substrate. A second active channel region is disposed between the second source / drain regions and above the semiconductor substrate, wherein the second gate structure includes a gate dielectric layer located above the second active channel region and a gate electrode located above the gate dielectric layer; a gate spacer extends along the sidewall of the second gate structure, wherein the dielectric constant of the gate dielectric layer is greater than the dielectric constant of the gate spacer; and a shared read bit line is located on the back side of the semiconductor substrate, the shared read bit line being positioned at the boundary between the first bit cell and the second bit cell, wherein the shared read bit line is electrically coupled to the first bit in the first source / drain region and the first bit in the second source / drain region. Attached Figure Description

[0007] Various aspects of the embodiments of this disclosure will be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard industry practice, the various components are not drawn to scale. In fact, for clarity of discussion, the dimensions of the various components may be arbitrarily increased or decreased.

[0008] Figure 1 Examples of nanostructured field-effect transistors (nanoFETs) are shown in three-dimensional views according to some embodiments.

[0009] Figure 2 , Figure 3 , Figure 4 , Figure 5 , Figure 6A , Figure 6B , Figure 6C , Figure 7A , Figure 7B , Figure 7C , Figure 8A , Figure 8B , Figure 8C , Figure 9 , Figure 10 , Figure 11A , Figure 11B , Figure 11C , Figure 11D , Figure 12A , Figure 12B , Figure 13A , Figure 13B , Figure 14A , Figure 14B , Figure 15A , Figure 15B , Figure 16A , Figure 16B , Figure 17A , Figure 17B , Figure 18A , Figure 18B , Figure 19A , Figure 19B , Figure 20 , Figure 21 , Figure 22 , Figure 23 , Figure 24 and Figure 25A This is a cross-sectional view of an intermediate stage in the fabrication of a nanoFET according to some embodiments.

[0010] Figure 25B , Figure 25C , Figure 25D , Figure 25E and Figure 25F This is a top view of an intermediate stage in the fabrication of a nanoFET according to some embodiments.

[0011] Figure 25G A circuit diagram of a bit cell of a semiconductor memory device according to some embodiments is shown.

[0012] Figure 26A , Figure 26B , Figure 27 and Figure 28 This is a cross-sectional view of an intermediate stage in the fabrication of a nanoFET according to some embodiments. Detailed Implementation

[0013] The following disclosure provides numerous different embodiments or instances for implementing various features of the embodiments of this disclosure. Specific examples of components and arrangements are described below to simplify the embodiments of this disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first component on or over a second component may include embodiments where the first and second components are in direct contact, and may also include embodiments where an additional component may be formed between the first and second components, thereby allowing the first and second components to not be in direct contact. Furthermore, reference numerals and / or characters may be repeated in various instances of the embodiments of this disclosure. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0014] Furthermore, for ease of description, this document uses spatial relative terms such as “below,” “under,” “lower,” “above,” and “upper” to describe the relationship between one element or component and another (or other elements or components) as shown in the figures. In addition to the orientations depicted in the figures, spatial relative terms are intended to include different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein can be interpreted accordingly.

[0015] Various embodiments provide semiconductor memory devices with improved performance and methods for forming the same. The semiconductor memory device can be implemented as, for example, a 7-transistor static random access memory (7T SRAM) bit cell, wherein the transistors can be implemented as nanostructured field-effect transistors (nanoFETs, also known as nanosheet field-effect transistors (NSFETs), nanowire field-effect transistors (NWFETs), or gate-all-around field-effect transistors (GAAFETs)). Embodiments include methods suitable for forming read bit lines (RBLs) disposed on the back side of the semiconductor memory device, wherein the read bit line (RBL) is shared between two adjacent 7T SRAM bit cells. For example, the shared read bit line (RBL) is located at the boundary between a first bit cell and a second bit cell, wherein the first bit cell and the second bit cell are adjacent to each other. The shared read bit line (RBL) can be electrically connected to a front-side interconnect structure on the front side of the semiconductor memory device and electrically connected to the transistors within each of the first and second bit cells via a back-side contact (which may also be referred to as a back-side via) disposed through the semiconductor substrate of the semiconductor memory device. In embodiments, the read bit line (RBL) may have a thickness ranging from 300 nm to 500 nm. In various embodiments, write bit lines (WBL and WBLB) are formed in the front-side interconnect structure at the first metal layer, which is positioned closer to the transistors of the semiconductor memory device compared to conventional implementations using higher metal layers that are further away from the transistors in the semiconductor memory device. For each of the first and second bit cells, the write bit line may be an independent conductor. The second metal layer of the front-side interconnect structure (positioned above the first metal layer) may include a common conductor spanning the first and second bit cells and providing shared electrical wiring and power to adjacent first and second bit cells. The shared read bit line (RBL) and the common conductor together allow for a folded design between the first and second bit cells (where signal lines are shared between adjacent bit cells, rather than each bit cell having a dedicated independent signal line).

[0016] Advantageous features of one or more embodiments disclosed herein may include read bit lines (RBLs) formed on the back side of the semiconductor memory device, allowing the read bit lines (RBLs) to be formed with larger dimensions. For example, the read bit lines (RBLs) have a thickness in the range of 300 nm to 500 nm. This can allow the resistance of the read bit lines (RBLs) to be reduced by 70% to 80%. Therefore, the read operation speed of the semiconductor memory device can be improved by 10% to up to 15%. Furthermore, positioning the shared read bit lines (RBLs) at the boundary between adjacent first and second bit cells can reduce layout imbalance problems and provide improved electrical matching between adjacent first and second bit cells. In addition, forming write bit lines (WBLs and WBLBs) in the front-side interconnect structure at the first metal layer closer to the transistor positioning of the semiconductor memory device, combined with forming a common conductor in the second metal layer that provides shared electrical wiring and power to the independent write bit lines, reduces the resistance in the write signal path and improves wiring efficiency. As a result, area utilization is improved, and a more compact cell layout that supports longer bit line designs can be achieved. Therefore, scalability for larger memory arrays can be improved, and overall manufacturing complexity can be reduced.

[0017] Figure 1 Examples of nanoFETs (e.g., nanowire FETs, nanosheet FETs, etc.) in a three-dimensional view according to some embodiments are shown. The nanoFET includes a nanostructure 55 (e.g., nanosheet, nanowire, etc.) located above fins (or protrusions / substrate portions) 66 on a substrate 50 (e.g., a semiconductor substrate), wherein the nanostructure 55 serves as a channel region for the nanoFET. The nanostructure 55 may include p-type nanostructures, n-type nanostructures, or combinations thereof. Shallow trench isolation (STI) regions 68 are disposed between adjacent fins 66, and the fins 66 may protrude above and from between adjacent STI regions 68. Although the STI regions 68 are described / shown as separated from the substrate 50, as used herein, the term "substrate" may refer solely to a semiconductor substrate or a combination of a semiconductor substrate and an STI region. Furthermore, although the bottom portion of the fin 66 is shown as being a single, continuous material with the substrate 50, the bottom portion of the fin 66 and / or the substrate 50 may include a single material or multiple materials. In this context, fin 66 refers to the portion extending between adjacent STI regions 68. In an embodiment, the nanoFET may be part of a semiconductor memory device comprising two adjacent 7T SRAM bit cells, wherein each bit cell comprises 7 transistors.

[0018] The gate dielectric layer 120 is located above the top surface of the fin 66 and extends along the top, sidewalls, and bottom surface of the nanostructure 55. The gate electrode 102 is located above the gate dielectric layer 120. Epitaxial source / drain regions 92 are disposed on the fin 66 on opposite sides of the gate dielectric layer 120 and the gate electrode 102. A first spacer 81 may be disposed on the sidewall of the gate dielectric layer.

[0019] Figure 1 Reference cross sections used in later figures are also shown. Cross section A-A' is along the longitudinal axis of the gate electrode 102 and in a direction, for example, perpendicular to the direction of current between the epitaxial source / drain regions 92 of the nanoFET. Cross section B-B' is parallel to cross section A-A' and extends through the epitaxial source / drain regions 92 of the plurality of nanoFETs. Cross section C-C' is perpendicular to cross section A-A' and parallel to the longitudinal axis of the fin 66 of the nanoFET and in a direction, for example, the direction of current between the epitaxial source / drain regions 92 of the nanoFET. For clarity, subsequent figures refer to these reference cross sections. Some embodiments discussed herein are discussed in the context of nanoFETs formed using a post-gate process. In other embodiments, a pre-gate process may be used.

[0020] Figures 2 to 28 This includes cross-sectional and top views of intermediate stages in the fabrication of a semiconductor memory device 10 including a nanoFET, according to some embodiments. Figures 2 to 5 , Figure 6A , Figure 7A , Figure 8A , Figure 11A , Figure 12A , Figure 13A , Figure 14A , Figure 15A , Figure 16A , Figure 17A , Figure 18A and Figure 19A It shows Figure 1 The reference section A-A' shown in the figure. Figure 6B , Figure 7B , Figure 8B , Figure 11B , Figure 11C , Figure 26A and Figure 26B It shows Figure 1 The reference section B-B' is shown in the figure. Figure 6C , Figure 7C , Figure 8C , Figure 9 , Figure 10 , Figure 11D , Figure 12B , Figure 13B , Figure 14B , Figure 15B , Figure 16B , Figure 17B , Figure 18B , Figure 19B , Figure 20 , Figure 21 , Figure 22 , Figure 23 , Figure 24 and Figure 25A It shows Figure 1 The reference section C-C' shown in the figure.

[0021] exist Figure 2 A substrate 50 is provided. The substrate 50 can be a semiconductor substrate, such as a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, etc., which can be doped (e.g., having p-type or n-type dopants) or undoped. The substrate 50 can be a wafer, such as a silicon wafer. Typically, an SOI substrate is a layer of semiconductor material formed on an insulating layer. The insulating layer can be, for example, a buried oxide (BOX) layer, a silicon oxide layer, etc. The insulating layer is provided on a substrate that is typically a silicon or glass substrate. Other substrates, such as multilayer or gradient substrates, can also be used. In some embodiments, the semiconductor material of the substrate 50 may include: silicon; germanium; compound semiconductors, including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductors, including silicon germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide, and / or gallium arsenide phosphide; or combinations thereof.

[0022] Substrate 50 has an n-type region 50N and a p-type region 50P. The n-type region 50N can be used to form an n-type device, such as an NMOS transistor, for example, an n-type nanoFET, and the p-type region 50P can be used to form a p-type device, such as a PMOS transistor, for example, a p-type nanoFET. The n-type region 50N can be physically separated from the p-type region 50P (as shown by separator 20), and any number of device components (e.g., other active devices, doped regions, isolation structures, etc.) can be disposed between the n-type region 50N and the p-type region 50P. Although one n-type region 50N and one p-type region 50P are shown, any number of n-type regions 50N and p-type regions 50P can be provided.

[0023] In addition, Figure 2In this process, a multilayer stack 64 is formed above the substrate 50. The multilayer stack 64 includes alternating layers of first semiconductor layers 51A-51C (collectively referred to as first semiconductor layers 51) and second semiconductor layers 53A-53C (collectively referred to as second semiconductor layers 53). For illustrative purposes and as discussed in more detail below, the first semiconductor layers (which may also be referred to as sacrificial layers) 51A, 51B, and 51C will be removed, and the second semiconductor layers (which may also be referred to as channel layers) 53A, 53B, and 53C will be patterned to form channel regions for the nanoFET in the n-type region 50N and the p-type region 50P. However, in some embodiments, the first semiconductor layers 51A, 51B, and 51C can be removed, and the second semiconductor layers 53A, 53B, and 53C can be patterned to form the channel region of the nanoFET in the n-type region 50N. Similarly, the second semiconductor layers 53A, 53B, and 53C can be removed, and the first semiconductor layers 51A, 51B, and 51C can be patterned to form the channel region of the nanoFET in the p-type region 50P. In some embodiments, the second semiconductor layers 53A, 53B, and 53C can be removed, and the first semiconductor layers 51A, 51B, and 51C can be patterned to form the channel region of the nanoFET in the n-type region 50N. Similarly, the first semiconductor layers 51A, 51B, and 51C can be removed, and the second semiconductor layers 53A, 53B, and 53C can be patterned to form the channel region of the nanoFET in the p-type region 50P. In some embodiments, the second semiconductor layers 53A, 53B, and 53C may be removed, and the first semiconductor layers 51A, 51B, and 51C may be patterned to form the channel region of the nanoFET in the n-type region 50N and the p-type region 50P.

[0024] For illustrative purposes, the multilayer stack 64 is shown as comprising three layers including a first semiconductor layer 51 and three layers including a second semiconductor layer 53. In some embodiments, the multilayer stack 64 may include two or more of the first semiconductor layers 51 and two or more of the second semiconductor layers 53. Each layer of the multilayer stack 64 may be epitaxially grown using processes such as chemical vapor deposition (CVD), atomic layer deposition (ALD), vapor phase epitaxy (VPE), molecular beam epitaxy (MBE), etc. In various embodiments, the first semiconductor layer 51 may be formed of a first semiconductor material suitable for p-type nanoFETs, such as silicon germanium, and the second semiconductor layer 53 may be formed of a second semiconductor material suitable for n-type nanoFETs, such as silicon, silicon carbon, etc. For illustrative purposes, the multilayer stack 64 is shown as having a bottom semiconductor layer suitable for p-type nanoFETs. In some embodiments, the multilayer stack 64 may be formed such that the bottom layer is a semiconductor layer suitable for n-type nanoFETs.

[0025] The first semiconductor material and the second semiconductor material can be materials that have high etch selectivity towards each other. Therefore, the first semiconductor layer 51 of the first semiconductor material can be removed without significantly removing the second semiconductor layer 53 of the second semiconductor material, thereby allowing the second semiconductor layers 53A, 53B, and 53C to be patterned to form the channel region of the nanoFET. Similarly, in an embodiment where the second semiconductor layer 53 is removed and the first semiconductor layers 51A, 51B, and 51C are patterned to form the channel region, the second semiconductor layer 53 of the second semiconductor material can be removed without significantly removing the first semiconductor layer 51 of the first semiconductor material, thereby allowing the first semiconductor layers 51A, 51B, and 51C to be patterned to form the channel region of the nanoFET.

[0026] Now for reference Figure 3 According to some embodiments, fins 66 are formed in substrate 50, and nanostructures 55 are formed in multilayer stack 64. In some embodiments, nanostructures 55 and fins 66 can be formed in multilayer stack 64 and substrate 50 respectively by etching trenches in multilayer stack 64 and substrate 50. Etching can be any acceptable etching process, such as reactive ion etching (RIE), neutral beam etching (NBE), or combinations thereof. Etching can be anisotropic. The nanostructures 55 formed by etching multilayer stack 64 can be further defined by a first semiconductor layer 51 defining first nanostructures 52A-52C (collectively referred to as first nanostructures 52), and by a second semiconductor layer 53 defining second nanostructures 54A-54C (collectively referred to as second nanostructures 54). First nanostructures 52 and second nanostructures 54 can be collectively referred to as nanostructure 55.

[0027] The fin 66 and nanostructure 55 can be patterned using any suitable method. For example, the fin 66 and nanostructure 55 can be patterned using one or more photolithography processes, including dual-patterning or multi-patterning processes. Typically, dual-patterning or multi-patterning processes combine photolithography and self-alignment processes, thereby allowing the creation of patterns with a pitch, for example, smaller than that achievable using a single, direct photolithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a photolithography process. Spacers are formed alongside the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers can then be used to pattern the fin 66.

[0028] For the purpose of explanation, Figure 3The fins 66 in the n-type region 50N and the p-type region 50P are shown to have substantially equal widths. In some embodiments, the width of the fin 66 in the n-type region 50N may be greater than or thinner than the width of the fin 66 in the p-type region 50P. Furthermore, while each of the fins 66 and nanostructures 55 is shown to always have a consistent width, in other embodiments, the fins 66 and / or nanostructures 55 may have tapered sidewalls, such that the width of each of the fins 66 and / or nanostructures 55 increases continuously in the direction toward the substrate 50. In such embodiments, each of the nanostructures 55 may have a different width and be trapezoidal in shape.

[0029] exist Figure 4 In the substrate 50, adjacent fins 66 form shallow trench isolation (STI) regions 68. STI regions 68 can be formed by depositing an insulating material over the substrate 50, fins 66, and nanostructure 55, and between adjacent fins 66. The insulating material can be an oxide, such as silicon oxide, nitrides, or combinations thereof, and can be formed by high-density plasma CVD (HDP-CVD), flowable CVD (FCVD), or combinations thereof. Other insulating materials formed by any acceptable process can be used. In the illustrated embodiment, the insulating material is silicon oxide formed by an FCVD process. Once the insulating material is formed, an annealing process can be performed. In the embodiment, the insulating material is formed such that excess insulating material covers the nanostructure 55. Although the insulating material is shown as a single layer, some embodiments may utilize multiple layers. For example, in some embodiments, a pad (not shown separately) can be formed first along the surfaces of the substrate 50, fins 66, and nanostructure 55. A filler material, such as those discussed above, can then be formed over the pad.

[0030] A removal process is then applied to the insulating material to remove excess insulating material above the nanostructure 55. In some embodiments, planarization processes, such as chemical mechanical polishing (CMP), etch-back processes, or combinations thereof, can be used. The planarization process exposes the nanostructure 55, thereby making the top surface of the nanostructure 55 flush with the top surface of the insulating material after the planarization process is completed.

[0031] The insulating material is then recessed to form the STI region 68. The insulating material is recessed such that the upper portions of the fins 66 in the n-type region 50N and p-type region 50P protrude from between adjacent STI regions 68. Furthermore, the top surface of the STI region 68 can have a flat surface, a convex surface, a concave surface (such as a recess), or a combination thereof, as shown. The top surface of the STI region 68 can be formed as flat, convex, and / or concave by appropriate etching. The STI region 68 can be recessed using acceptable etching processes, such as etching processes selective for the material of the insulating material (e.g., etching the material of the insulating material at a faster rate than the material of the fins 66 and nanostructures 55). For example, oxide removal can be used, employing, for example, dilute hydrofluoric acid (dHF).

[0032] The above about Figures 2 to 4 The described process is merely one example of how the fins 66 and nanostructures 55 can be formed. In some embodiments, the fins 66 and / or nanostructures 55 can be formed using masking and epitaxial growth processes. For example, a dielectric layer can be formed over the top surface of the substrate 50, and trenches can be etched through the dielectric layer to expose the underlying substrate 50. Epitaxial structures can be epitaxially grown in the trenches, and the dielectric layer can be recessed, causing the epitaxial structure to protrude from the dielectric layer to form the fins 66 and / or nanostructures 55. The epitaxial structure can include alternating semiconductor materials discussed above, such as a first semiconductor material and a second semiconductor material. In some embodiments of epitaxial growth of the epitaxial structure, the material being epitaxially grown can be doped in situ during growth, which avoids prior and / or subsequent implantation, but in-situ doping and implantation doping can be used together.

[0033] Furthermore, for illustrative purposes only, the first semiconductor layer 51 (and the resulting first nanostructure 52) and the second semiconductor layer 53 (and the resulting second nanostructure 54) are shown and discussed herein as comprising the same material in the p-type region 50P and the n-type region 50N. Therefore, in some embodiments, one or both of the first semiconductor layer 51 and the second semiconductor layer 53 may be different materials, or may be formed in a different order in the p-type region 50P and the n-type region 50N.

[0034] In addition, Figure 4In this process, suitable wells (not shown separately) can be formed in fins 66, nanostructures 55, and / or STI regions 68. In embodiments with different well types, photoresist or other masks (not shown separately) can be used to implement different implantation steps for n-type regions 50N and p-type regions 50P. For example, photoresist can be formed over fins 66 and STI regions 68 in n-type regions 50N and p-type regions 50P. The photoresist is patterned to expose the p-type region 50P. The photoresist can be formed using a spin-coating technique and can be patterned using an acceptable photolithography technique. Once the photoresist is patterned, n-type impurity implantation is performed in the p-type region 50P, and the photoresist can be used as a mask to substantially prevent n-type impurity implantation into the n-type region 50N. The n-type impurity (also called a dopant) can be implanted in the region to form an impurity in the p-type region 50N. 13 atoms / cm 3 To about 10 14 atoms / cm 3 Phosphorus, arsenic, antimony, etc., within a certain concentration range. After implantation, the photoresist is removed, such as through an acceptable ashing process.

[0035] After or before implantation of the p-type region 50P, photoresist or other masks (not shown separately) are formed over the fins 66, nanostructures 55, and STI regions 68 in both the p-type region 50P and the n-type region 50N. The photoresist is patterned to expose the n-type region 50N. The photoresist can be formed using a spin-coating technique and can be patterned using an acceptable photolithography technique. Once the photoresist is patterned, p-type impurity implantation can be performed in the n-type region 50N, and the photoresist can be used as a mask to substantially prevent p-type impurity implantation into the p-type region 50P. P-type impurities (also known as dopants) can be implanted into the region to form a dopant layer from approximately 10... 13 atoms / cm 3 To about 10 14 atoms / cm 3 The concentrations of boron, boron fluoride, indium, etc., are within a certain range. After implantation, the photoresist can be removed, such as through an acceptable ashing process.

[0036] After implanting the n-type region 50N and the p-type region 50P, annealing can be performed to repair implantation damage and to activate the implanted p-type and / or n-type impurities. In some embodiments, the growth material of the epitaxial fins can be doped in situ during growth, which can avoid implantation, but in-situ doping and implantation doping can be used together.

[0037] exist Figure 5In this process, a dummy dielectric layer 70 is formed on the fin 66 and / or nanostructure 55. The dummy dielectric layer 70 can be, for example, silicon oxide, silicon nitride, combinations thereof, etc., and can be deposited or thermally grown according to acceptable techniques. A dummy gate layer 72 is formed above the dummy dielectric layer 70, and a mask layer 74 is formed above the dummy gate layer 72. The dummy gate layer 72 can be deposited above the dummy dielectric layer 70 and then planarized, for example, by CMP. The mask layer 74 can be deposited above the dummy gate layer 72. The dummy gate layer 72 can be a conductive or non-conductive material and can be selected from the group including amorphous silicon, polysilicon, poly-SiGe, metal nitrides, metal silicides, metal oxides, and metals. The dummy gate layer 72 can be deposited by physical vapor deposition (PVD), CVD, sputtering deposition, or other techniques for depositing the selected material. The dummy gate layer 72 can be made of other materials that have high etch selectivity relative to the etching of the isolation region. The mask layer 74 may include, for example, silicon nitride, silicon oxynitride, etc. In this example, a single dummy gate layer 72 and a single mask layer 74 are formed across the n-type region 50N and the p-type region 50P. It should be noted that, for illustrative purposes only, the dummy dielectric layer 70 is shown to cover only the fin 66 and the nanostructure 55. In some embodiments, the dummy dielectric layer 70 may be deposited such that it covers the STI region 68, thereby extending between the dummy gate layer 72 and the STI region 68.

[0038] Figures 6A to 25F and Figures 26A to 28 Various additional steps in the fabrication of the embodiment device are shown, wherein the components are shown in either the n-type region 50N or the p-type region 50P. Figures 6A to 25F and Figures 26A to 28 Components of the semiconductor memory device 10 located in the active region 12 (e.g., including fins 66 and nanostructures 55) of the subsequently formed first cell 16 and the active region 14 (e.g., including fins 66 and nanostructures 55) of the subsequently formed second cell 18 can also be shown. Figure 6C , Figure 7C , Figure 8C , Figure 9 , Figure 10 , Figure 11D , Figure 12B , Figure 13B , Figure 14B , Figure 15B , Figure 16B , Figure 17B , Figure 18B , Figure 19B , Figure 20 , Figure 21 , Figure 22 , Figure 23 , Figure 24 and Figure 25AThe semiconductor memory device 10 is shown along Figure 6B and Figure 6C The diagram shows a cross-sectional view of line X-X', which extends through the active region 14 of the semiconductor memory device 10. The first bit cell 16 and the second bit cell 18 may be adjacent to each other, and each of the first bit cell 16 and the second bit cell 18 may be an SRAM bit cell comprising 7 transistors (subsequently in...). Figures 25A to 25G (As described in the text). Figures 6A to 6C In the middle, mask layer 74 (see Figure 5 The mask 78 can be patterned using acceptable photolithography and etching techniques to form a mask 78. The pattern of the mask 78 can then be transferred to a dummy gate layer 72 and a dummy dielectric layer 70 to form dummy gates 76 and dummy gate dielectrics 71, respectively. The dummy gates 76 cover the corresponding channel regions 60 of the fins 66 and / or nanostructures 55. The pattern of the mask 78 can be used to physically separate each of the dummy gates 76 from its adjacent counterparts. The dummy gates 76 may also have a longitudinal orientation substantially perpendicular to the longitudinal direction of the corresponding fin 66.

[0039] exist Figures 7A to 7C In the process, a first spacer 81 and a second spacer 82 are formed on the sidewalls of the fin 66 and / or the nanostructure 55. The first spacer 81 and the second spacer 82 can be formed by... Figures 6A to 6C The structure shown is formed by sequentially forming a first spacer layer and a second spacer layer on top of it. The first and second spacer layers are then patterned to form a first spacer 81 and a second spacer 82, respectively, which are subsequently used to form self-aligned source / drain regions. The first spacer layer can be formed on the top surface of the STI region 68; the top surface and sidewalls of the fin 66, nanostructure 55, and mask 78; and the sidewalls of the dummy gate 76 and dummy gate dielectric 71. A second spacer layer is deposited on top of the first spacer layer. The first spacer layer can be formed from silicon oxide, silicon nitride, silicon oxynitride, etc., using techniques such as thermal oxidation, or deposited via CVD, ALD, etc. The second spacer layer can be formed from a material having a different etch rate than the material of the first spacer layer, such as silicon oxide, silicon nitride, silicon oxynitride, etc., and can be deposited via CVD, ALD, etc.

[0040] Implantation for the lightly doped source / drain (LDD) regions (not shown separately) can be performed after the formation of the first spacer layer and before the formation of the second spacer layer. In embodiments with different device types, similar to the above... Figure 4The implantation discussed earlier can involve forming a mask, such as photoresist, over the n-type region 50N while exposing the p-type region 50P. An impurity of an appropriate type (e.g., p-type) can be implanted into the exposed fins 66 and nanostructures 55 in the p-type region 50P. The mask can then be removed. The n-type impurity can be any of the n-type impurities discussed earlier, and the p-type impurity can be any of the p-type impurities discussed earlier. The lightly doped source / drain regions can have a doping density ranging from approximately 1 × 10⁻⁶. 15 atoms / cm 3 To approximately 1×10 19 atoms / cm 3 The impurity concentration is within a certain range. Annealing can be used to repair implantation damage and to reactivate the implanted impurities.

[0041] Further reference Figures 7A to 7C The first spacer layer and the second spacer layer are etched to form the first spacer 81 and the second spacer 82, respectively. As will be discussed in more detail below, the first spacer 81 and the second spacer 82 are used for self-alignment of the subsequently formed source / drain regions and for protecting the sidewalls of the fin 66 and / or nanostructure 55 during subsequent processing. Suitable etching processes can be used to etch the first spacer layer and the second spacer layer, such as isotropic etching processes (e.g., wet etching processes), anisotropic etching processes (e.g., dry etching processes), etc. In some embodiments, the material of the second spacer layer has a different etch rate than the material of the first spacer layer, such that when the second spacer layer is patterned, the first spacer layer can be used as an etch stop layer, and thus, when the first spacer layer is patterned, the second spacer layer can be used as a mask. For example, an anisotropic etching process can be used to etch the second spacer layer, wherein the first spacer layer serves as an etch stop layer, and wherein the remaining portion of the second spacer layer forms the second spacer 82, as... Figure 7B As shown in the diagram. Subsequently, the second spacer 82 serves as a mask while the exposed portions of the first spacer layer are etched, thereby forming the first spacer 81, as shown. Figure 7B and Figure 7C As shown in the image.

[0042] like Figure 7B As shown, the first spacer 81 and the second spacer 82 are disposed on the sidewalls of the fin 66 and / or the nanostructure 55. Figure 7CAs shown, in some embodiments, the second spacer layer can be removed from above the first spacer layer adjacent to the mask 78, dummy gate 76, and dummy gate dielectric 71, and the first spacer 81 is disposed on the sidewalls of the mask 78, dummy gate 76, and dummy gate dielectric 71. In other embodiments, a portion of the second spacer layer may remain above the first spacer layer adjacent to the mask 78, dummy gate 76, and dummy gate dielectric 71.

[0043] It should be noted that the above disclosure generally describes the process for forming spacers and LDD regions. Other processes and sequences can be used. For example, fewer or additional spacers can be used, different step sequences can be used (e.g., the first spacer 81 can be patterned before depositing the second spacer layer), additional spacers can be formed and removed, etc. Furthermore, n-type and p-type devices can be formed using different structures and steps.

[0044] exist Figures 8A to 8C In some embodiments, a first groove 86 is formed in the nanostructure 55 and the fin 66. Epitaxial material and epitaxial source / drain regions are then formed in the first groove 86. The first groove 86 may extend through the first nanostructure 52, the second nanostructure 54, and partially through the fin 66. In some embodiments, the nanostructure 55 and the fin 66 may be etched such that the bottom surface of the first groove 86 is positioned below the top surface of the STI region 68, as shown below. Figure 8B As shown in the figure. In other embodiments, the top surface of the STI region 68 may be flush with the bottom surface of the first groove 86, or it may be disposed above the bottom surface of the first groove 86.

[0045] The first groove 86 can be formed by etching the nanostructure 55 and the fin 66 using an anisotropic etching process (such as RIE, NBE, etc.). During the etching process used to form the first groove 86, a first spacer 81, a second spacer 82, and a mask 78 mask portions of the fin 66, the nanostructure 55, and the substrate 50. Each layer of the nanostructure 55 can be etched using a single etching process or multiple etching processes. After the first groove 86 reaches the desired depth, etching can be stopped using a timed etching process.

[0046] exist Figure 9 In the process, portions of the sidewalls of the layers of the multilayer stack 64 formed of a first semiconductor material (e.g., a first nanostructure 52) exposed by the first groove 86 are etched to form a sidewall groove 88. While the sidewalls of the first nanostructure 52 adjacent to the sidewall groove 88 are... Figure 9The sidewalls are shown as straight, but they can be concave or convex. Isotropic etching processes, such as wet etching, can be used to etch the sidewalls. In embodiments where the first nanostructure 52 comprises, for example, SiGe and the second nanostructure 54 comprises, for example, Si or SiC, the sidewalls of the first nanostructure 52 can be etched using a dry etching process with tetramethylammonium hydroxide (TMAH), ammonium hydroxide (NH4OH), etc.

[0047] exist Figure 10 In the middle, an internal spacer 90 is formed in the sidewall groove 88. The internal spacer 90 can be formed by... Figure 9 The structure shown is formed by depositing an internal spacer layer (not shown separately) over it. The internal spacer 90 serves as the subsequently formed source / drain region alongside the gate dielectric layer 120 and the gate electrode 102 (which are then deposited on top of the structure). Figure 16A and Figure 16B The isolation components between (shown in the figure) will be formed in the first groove 86 as will be discussed in more detail below. The epitaxial source / drain regions and epitaxial material will be formed in the first groove 86, while the first nanostructures 52A, 52B and 52C will be replaced by the gate dielectric layer 120 and the gate electrode 102.

[0048] The internal spacer layer can be deposited using conformal deposition processes such as CVD, ALD, etc. The internal spacer layer can include materials such as silicon carbonitride (SiCN) or silicon carbonitride oxynitride (SiOCN). In other embodiments, silicon nitride or silicon oxynitride can be used, or any suitable material, such as a low-k material having a k value less than about 3.5. The internal spacer layer can then be anisotropically etched to form the internal spacer 90. Although the outer wall of the internal spacer 90 is shown flush with the sidewall of the second nanostructure 54, the outer wall of the internal spacer 90 may extend beyond or be recessed from the sidewall of the second nanostructure 54. Furthermore, although the outer wall of the internal spacer 90 is... Figure 10 The diagram shows a straight line, but the outer wall of the internal spacer 90 can be concave or convex. The internal spacer layer can be etched using anisotropic etching processes, such as RIE, NBE, etc. The internal spacer 90 can be used to prevent subsequent etching processes from affecting the subsequently formed source / drain regions. Figures 11A to 11D Damage to the gate dielectric layer 120 and gate electrode 102 (as shown in the diagram) Figures 16A to 16B The etching process shown in the figure.

[0049] exist Figures 11A to 11D In this process, a first epitaxial material 93 is formed in the bottom portion of the first groove 86 to a desired height. In some embodiments, the first epitaxial material 93 in the first groove 86 may be a sacrificial material that can be subsequently removed to form a back-side contact (such as back-side contact 162, hereinafter referred to as...). Figure 24 (Discussion). The first epitaxial material 93 can be epitaxially grown using processes such as chemical vapor deposition (CVD), atomic layer deposition (ALD), vapor phase epitaxy (VPE), and molecular beam epitaxy (MBE). The first epitaxial material 93 can include any acceptable material, such as silicon germanium, undoped silicon germanium, etc.

[0050] The first epitaxial material 93 can be formed of a material with high etch selectivity to the substrate 50 and dielectric layers (such as STI region 68). Therefore, the first epitaxial material 93 in the first recess 86 can be removed and replaced with a back-side contact (which may also be referred to as a back-side via) without significantly removing the substrate 50 and dielectric layer. For example, the atomic concentration of germanium in the first epitaxial material 93 can be greater than the atomic concentration of germanium in the substrate 50. A material with a higher germanium concentration can be etched at a higher rate compared to a material with a lower germanium concentration. Forming a first epitaxial material 93 with a higher germanium concentration enables selective removal during subsequent etching processes used to form self-aligned back-side contacts. In various embodiments, the first epitaxial material 93 provides etch selectivity that allows for precise formation of back-side contact openings without affecting other device structures.

[0051] Further reference Figures 11A to 11D After forming the first epitaxial material 93, an isolation layer 91 is conformally formed in the first groove 86 and on the first epitaxial material 93. The isolation layer 91 can be any suitable dielectric material, such as silicon nitride, and can be formed using suitable formation methods, such as CVD, ALD, etc. Figures 11A to 11D In one example, the isolation layer 91 covers the upper surface of the first epitaxial material 93 and contacts the sidewall of the lowermost internal spacer 90 at a position between the upper and lower surfaces of the lowermost internal spacer 90.

[0052] After forming the first epitaxial material 93 and the isolation layer 91, an epitaxial source / drain region 92 is formed in the first groove 86. In some embodiments, the epitaxial source / drain region 92 can apply stress to the second nanostructures 54A, 54B, and 54C, thereby improving performance. Figure 11D As shown, epitaxial source / drain regions 92 are formed in the first recess 86, such that each dummy gate 76 is disposed between corresponding adjacent pairs of epitaxial source / drain regions 92. In some embodiments, a first spacer 81 is used to separate the epitaxial source / drain regions 92 from the dummy gates 76, and an inner spacer 90 is used to separate the epitaxial source / drain regions 92 from the first nanostructures 52A, 52B, and 52C by an appropriate lateral distance, such that the epitaxial source / drain regions 92 do not short-circuit with the subsequently formed gate of the resulting nanoFET.

[0053] The epitaxial source / drain region 92 in the n-type region 50N (e.g., an NMOS region) can be formed by masking the p-type region 50P (e.g., a PMOS region). The epitaxial source / drain region 92 is then epitaxially grown in a first groove 86 in the n-type region 50N. The epitaxial source / drain region 92 can comprise any acceptable material suitable for an n-type nanoFET. For example, if the second nanostructure 54 is silicon, the epitaxial source / drain region 92 can comprise a material on which tensile strain is applied to the second nanostructures 54A, 54B, and 54C, such as silicon, silicon carbide, phosphorus-doped silicon carbide, silicon phosphide, etc. The epitaxial source / drain region 92 can have a surface protruding from the corresponding upper surface of the nanostructure 55 and can have small facets.

[0054] The epitaxial source / drain region in the p-type region 50P (e.g., a PMOS region) can be formed by masking the n-type region 50N (e.g., an NMOS region). The epitaxial source / drain region 92 is then epitaxially grown in a first groove 86 in the p-type region 50P. The epitaxial source / drain region 92 can comprise any acceptable material suitable for a p-type nanoFET. For example, if the first nanostructure 52 is silicon-germanium, the epitaxial source / drain region 92 can comprise a material on which compressive strain is applied to the first nanostructures 52A, 52B, and 52C, such as silicon-germanium, boron-doped silicon-germanium, germanium, germanium-tin, etc. The epitaxial source / drain region 92 can also have a surface protruding from the corresponding surface of the nanostructure 55 and can have a facet.

[0055] The epitaxial source / drain region 92, the first nanostructure 52, the second nanostructure 54, and / or the substrate 50 can be implanted with dopants to form the source / drain region, similar to the previously discussed process for forming lightly doped source / drain regions, followed by annealing. The source / drain region can have a dopant density of approximately 1 × 10⁻⁶. 19 atoms / cm 3 1×10 21 atoms / cm 3 The impurity concentrations between these values. The n-type and / or p-type impurities used for the source / drain regions can be any of the impurities discussed previously. In some embodiments, the epitaxial source / drain regions 92 can be doped in situ during growth.

[0056] Due to the epitaxial process used to form the epitaxial source / drain regions 92 in the n-type region 50N and the p-type region 50P, the upper surface of the epitaxial source / drain regions 92 has small planes that extend laterally outward beyond the sidewalls of the nanostructure 55. In some embodiments, these small planes cause adjacent epitaxial source / drain regions 92 of the same nanoFET to merge, such as... Figure 11BAs shown. In other embodiments, after the epitaxial process is completed, adjacent epitaxial source / drain regions 92 remain separated, as shown. Figure 11C As shown. In Figure 11B and Figure 11C In the illustrated embodiment, the first spacer 81 may be formed to the top surface of the STI region 68, thereby blocking epitaxial growth. In some other embodiments, the first spacer 81 may cover a portion of the sidewall of the nanostructure 55, further blocking epitaxial growth. In some other embodiments, the spacer etching used to form the first spacer 81 may be adjusted to remove spacer material, allowing the epitaxial growth region to extend to the surface of the STI region 68.

[0057] The epitaxial source / drain region 92 may include one or more semiconductor material layers. For example, the epitaxial source / drain region 92 may include a first semiconductor material layer 92A, a second semiconductor material layer 92B, and a third semiconductor material layer 92C. Any number of semiconductor material layers can be used for the epitaxial source / drain region 92. Each of the first semiconductor material layer 92A, the second semiconductor material layer 92B, and the third semiconductor material layer 92C may be formed of a different semiconductor material and may be doped to different dopant concentrations. In some embodiments, the first semiconductor material layer 92A may have a dopant concentration less than that of the second semiconductor material layer 92B and greater than that of the third semiconductor material layer 92C. In embodiments where the epitaxial source / drain region 92 includes three semiconductor material layers, the first semiconductor material layer 92A may be deposited, the second semiconductor material layer 92B may be deposited over the first semiconductor material layer 92A, and the third semiconductor material layer 92C may be deposited over the second semiconductor material layer 92B.

[0058] exist Figure 12A and Figure 12B In Figures 11A to 11D A first interlayer dielectric (ILD) 96 is deposited over the structure shown. The first ILD 96 can be formed of a dielectric material and can be deposited by any suitable method, such as CVD, plasma-enhanced CVD (PECVD), or FCVD. The dielectric material may include phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), undoped silicate glass (USG), etc. Other insulating materials formed by any acceptable process may be used. In some embodiments, a contact etch stop layer (CESL) 94 is disposed between the first ILD 96 and the epitaxial source / drain region 92, mask 78, and first spacer 81. CESL 94 may include a dielectric material having an etch rate different from that of the first ILD 96 above, such as silicon nitride, silicon oxide, silicon oxynitride, etc.

[0059] exist Figure 13A and Figure 13B In this process, a planarization process, such as CMP, can be performed to make the top surface of the first ILD 96 flush with the top surface of the dummy gate 76 or the mask 78. The planarization process may also remove the mask 78 on the dummy gate 76, as well as a portion of the first spacer 81 along the sidewall of the mask 78. After the planarization process, the top surfaces of the dummy gate 76, the first spacer 81, and the first ILD 96 are flush. Therefore, the top surface of the dummy gate 76 is exposed through the first ILD 96. In some embodiments, the mask 78 may be retained, in which case the planarization process makes the top surface of the first ILD 96 flush with the top surfaces of the mask 78 and the first spacer 81.

[0060] exist Figure 14A and Figure 14B In the etching step, the dummy gate 76 and mask 78 (if present) are removed to form a recess 98. A portion of the dummy gate dielectric 71 located in the recess 98 may also be removed. In some embodiments, only the dummy gate 76 is removed, and the dummy gate dielectric 71 remains and is exposed by the recess 98. In some embodiments, the dummy gate dielectric 71 is removed from the recess 98 in a first region of the die (e.g., a core logic region) and remains in the recess 98 in a second region of the die (e.g., an input / output region). In some embodiments, the dummy gate 76 is removed by an anisotropic dry etching process. For example, the etching process may include a dry etching process using a reactive gas that selectively etches the dummy gate 76 without etching the first ILD 96 and the first spacer 81. Each recess 98 exposes and / or is located on top of a multilayer stack 64. A portion of the multilayer stack 64 is disposed between adjacent pairs of epitaxial source / drain regions 92. During removal, the dummy gate dielectric 71 can be used as an etch stop layer when the dummy gate 76 is etched. Then, after removing the dummy gate 76, the dummy gate dielectric 71 may optionally be removed.

[0061] exist Figure 15A and Figure 15BIn this process, the first nanostructures 52A, 52B, and 52C are removed from regions 50N and 50P. The first nanostructures 52A, 52B, and 52C can be removed using an isotropic etching process such as wet etching or dry etching. The etchant used to remove the first nanostructures 52A, 52B, and 52C can be selective for the materials of the second nanostructures 54A, 54B, and 54C. The second nanostructures 54A, 54B, and 54C can subsequently be referred to as channel layers 54A, 54B, and 54C, respectively. The second nanostructures 54A, 54B, and 54C between adjacent epitaxial source / drain regions 92 can additionally be referred to as channel region 60. In embodiments where the first nanostructures 52A, 52B, and 52C comprise a first semiconductor material (e.g., SiGe, etc.) and the second nanostructures 54A, 54B, and 54C comprise a second semiconductor material (e.g., Si, SiC, etc.), a fluorine-based etchant such as hydrogen fluoride (HF) can be used to remove layers of the multilayer stack 64 in regions 50N and 50P.

[0062] exist Figure 16A and Figure 16B In this embodiment, a gate dielectric layer 120 and a gate electrode 102 are formed to replace the gate. In this embodiment, the gate dielectric layer 120 is conformally deposited in a recess 98. The gate dielectric layer 120 may be formed on the top surface, sidewalls, and bottom surface of the second nanostructures 54A, 54B, and 54C. The gate dielectric layer 120 may also be deposited on the top surface of the first ILD 96, CESL 94, the first spacer 81, and the STI region 68, as well as on the sidewalls of the first spacer 81 and the inner spacer 90.

[0063] According to some embodiments, the gate dielectric layer 120 includes one or more dielectric layers, such as oxides, metal oxides, or combinations thereof. For example, in some embodiments, the gate dielectric may include a silicon oxide layer and a metal oxide layer above the silicon oxide layer. In some embodiments, the gate dielectric layer 120 includes a high-k dielectric material, and in these embodiments, the gate dielectric layer 120 may have a k value greater than about 7.0, and may include metal oxides or silicates of hafnium, aluminum, zirconium, lanthanum, manganese, barium, titanium, lead, and combinations thereof. The structure of the gate dielectric layer 120 may be the same or different in the n-type region 50N and the p-type region 50P. The method of forming the gate dielectric layer 120 may include molecular beam deposition (MBD), ALD, PECVD, etc. In embodiments, the dielectric constant of the gate dielectric layer 120 is greater than the dielectric constant of the first spacer 81.

[0064] Gate electrodes 102 are deposited over gate dielectric layer 120 and fill the remaining portion of trench 98. Gate electrodes 102 may include metallic materials such as titanium nitride, titanium oxide, tantalum nitride, tantalum carbide, cobalt, ruthenium, aluminum, tungsten, combinations thereof, or multilayers thereof. For example, although in Figure 16A and Figure 16B A single-layer gate electrode 102 is shown, but the gate electrode 102 may include any number of pad layers, any number of work function adjustment layers, and filler material. Any combination of layers constituting the gate electrode 102 may be deposited between adjacent second nanostructures 54. The gate electrode 102 may be formed by any suitable deposition process, such as plasma-enhanced CVD (PECVD), ALD, CVD, etc.

[0065] The formation of the gate dielectric layer 120 in the n-type region 50N and the p-type region 50P can occur simultaneously, such that the gate dielectric layer 120 in each region is formed of the same material, and the formation of the gate electrode 102 can occur simultaneously, such that the gate electrode 102 in each region is formed of the same material. In some embodiments, the gate dielectric layer 120 in each region can be formed by different processes, such that the gate dielectric layer 120 can be made of different materials and / or have different numbers of layers, and / or the gate electrode 102 in each region can be formed by different processes, such that the gate electrode 102 can be made of different materials and / or have different numbers of layers. When different processes are used, individual masking steps can be used to mask and expose appropriate regions.

[0066] After filling the recess 98, a planarization process, such as CMP, can be performed to remove excess material from the gate dielectric layer 120 and the gate electrode 102, which lies above the top surface of the first ILD 96. The remaining material of the gate electrode 102 and the gate dielectric layer 120 thus forms the replacement gate structure of the resulting nanoFET. The gate electrode 102 and the gate dielectric layer 120 can be collectively referred to as gate structure 103. The gate electrode 102 and the gate dielectric layer 120 can also be collectively referred to as a “gate stack”.

[0067] exist Figure 17A and Figure 17B In the middle, it can be in the previous Figure 16A and Figure 16BA dielectric layer 104, including silicon nitride, is formed over the structure shown (e.g., over the gate structure 103, the first ILD 96, CESL 94, and the first spacer 81). In other embodiments, an optional step (not shown) may be implemented in which the gate structure 103 (including the gate dielectric layer 120 and the corresponding gate electrode 102) is recessed, thereby forming a groove directly over the gate structure 103 and between the opposing portions of the first spacer 81. A gate mask (not shown) comprising one or more dielectric material layers (such as silicon nitride, silicon oxynitride, etc.) is filled into the groove, followed by a planarization process to remove excess portions of the dielectric material extending over the first ILD 96. Gate contacts (such as gate contact 114, hereinafter referred to) are then formed. Figure 19A and Figure 19B (Discussion) Penetrates the gate mask to contact the top surface of the recessed gate electrode 102.

[0068] like Figure 17A and Figure 17B As further shown, a second ILD 106 is deposited over the first ILD 96 and over the dielectric layer 104. In some embodiments, the second ILD 106 is a flowable film formed by FCVD. In some embodiments, the second ILD 106 is formed of a dielectric material such as PSG, BSG, BPSG, USG, etc., and can be deposited by any suitable method, such as CVD, PECVD, etc.

[0069] exist Figure 18A and Figure 18B In the middle, a gate contact 114 is formed through the second ILD 106 and the dielectric layer 104 (subsequently in... Figure 19A and Figure 19B (shown in the diagram) opening 108, and through the second ILD 106, CESL 94 and the first ILD 96 to form the source / drain contact 112 (which is subsequently...) Figure 19BOpening 109 (shown in the diagram). Openings 108 and 109 can be formed using acceptable photolithography and etching techniques. Opening 108 can expose the surface of gate structure 103, and opening 109 can expose the surface of epitaxial source / drain region 92. A metal (not shown separately) capable of reacting with the underlying semiconductor material (e.g., silicon, silicon-germanium, germanium) to form a silicide or germanide region is first deposited over the exposed portion of epitaxial source / drain region 92 (such as nickel, cobalt, titanium, tantalum, platinum, tungsten, other noble metals, other refractory metals, rare earth metals, or alloys thereof), and then a thermal annealing process is performed to form silicide region 110, forming silicide region 110 over epitaxial source / drain region 92. Unreacted portions of the deposited metal are then removed, for example, by an etching process. Silicate region 110 can have a higher conductivity than epitaxial source / drain region 92. Silicide region 110 in epitaxial source / drain region 92 and subsequently formed source / drain contact 112 ( Figure 19B A low-resistance interface is formed between the source / drain contact 112 and the epitaxial source / drain region 92, as shown in the diagram. Therefore, the contact resistance between the source / drain contact 112 and the epitaxial source / drain region 92 can be reduced.

[0070] exist Figure 19A and Figure 19B In the first embodiment, a pad (such as a diffusion barrier layer, adhesive layer, etc.) and conductive material can be formed in openings 108 and 109. In other embodiments, only the conductive material is formed in openings 108 and 109. The pad may include titanium, titanium nitride, tantalum, tantalum nitride, etc. The conductive material may be tungsten, ruthenium, cobalt, copper, molybdenum, iridium, titanium, tantalum nitride, titanium nitride, nickel aluminide, etc. A planarization process, such as CMP, can be implemented to remove excess material from the surface of the second ILD 106. The remaining pad and conductive material form a gate contact 114 in opening 108 and a source / drain contact 112 in opening 109. The gate contact 114 is physically and electrically coupled to the gate electrode 102, and the source / drain contact 112 is physically and electrically coupled to the epitaxial source / drain region 92. In this embodiment, the conductivity of the source / drain contact 112 is greater than the conductivity of the epitaxial source / drain region 92. In this embodiment, the conductivity of the silicide region 110 is between the conductivity of the epitaxial source / drain region 92 and the conductivity of the source / drain contact 112.

[0071] exist Figure 20 In this process, a dielectric layer 135 is formed over the second ILD 106. The dielectric layer 135 can be a suitable dielectric material layer formed by a suitable formation method (such as CVD, PECVD, ALD, etc.), such as silicon carbonitride (e.g., SiCN), silicon nitride (SiN), etc. As a non-limiting example, the dielectric layer 135 is... Figure 20The dielectric layer 135 is shown as a single layer. In some embodiments, the dielectric layer 135 has a multilayer structure comprising multiple sublayers of different dielectric materials.

[0072] Next, vias 133 and 134 are formed to extend through dielectric layer 135 and to be electrically coupled to gate contact 114 and source / drain contact 112, respectively. Vias 133 and 134 can be formed by forming via openings extending through dielectric layer 135 and then filling the via openings with a conductive material. As an example, the conductive material can be a low-resistance metal, such as tungsten or molybdenum. In some embodiments, vias 133 and 134 have an unobstructed structure and are formed by filling the via openings with a single metallic material without forming a barrier layer along the sidewalls of the via openings. An unobstructed structure can be advantageous for advanced semiconductor processing nodes due to the difficulty of filling small openings.

[0073] After forming vias 133 and 134, an interconnect structure 130 (also referred to as a front-side interconnect structure) is formed over dielectric layer 135 and vias 133 and 134. Interconnect structure 130 may include dielectric layer 137 and conductive components (e.g., wires and conductive vias) formed in dielectric layer 137. Interconnect structure 130 may be electrically connected to transistors in first bit cell 16 and second bit cell 18, and may include write lines and other signal lines for first bit cell 16 and second bit cell 18.

[0074] The dielectric layer 137 can be formed of any suitable dielectric material, such as silicon oxide, silicon nitride, low-k dielectric materials, etc. Suitable formation methods (such as CVD, PECVD, ALD, combinations thereof, etc.) can be used to form the dielectric layer 137. Conductive components (e.g., wires and conductive vias) in the dielectric layer 137 can be formed using, for example, damascene or dual damascene processes. The conductive components may include diffusion barriers and a metallic material (e.g., copper) above the diffusion barriers. The diffusion barriers (also referred to as pads) may be, for example, Ta, Ti, TaN, TiN, etc. The metallic material may be, for example, Cu, Co, Ru, Mo, etc. In some embodiments, the topmost conductive component (e.g., the conductive component in the topmost dielectric layer 137 away from the substrate 50) may include conductive components for bonding to another semiconductor device (e.g., bonding pads or metal patterns for bonding).

[0075] The dielectric layer 137A of the interconnect structure 130 that is closest (e.g., a physical contact) to the dielectric layer 135 can be referred to as the M0 layer. Other dielectric layers 137 of the interconnect structure 130 (e.g., dielectric layers 137B-137G) can be referred to as V0 layer, M1 layer, V1 layer, M2 layer, V2 layer, and M3 layer, and so on. The M layers (e.g., M0, M1, M2, M3) can be metallization layers containing horizontal conductors for signal routing and power distribution. The V layers (e.g., V0, V1, V2) can contain conductive vias for providing electrical connections between adjacent metallization layers. In an embodiment, the M2 layer is positioned above the M1 layer, and the M3 layer is positioned above the M2 layer, such that the M1 layer is closer to the dielectric layer 135 than the M2 layer, and the M2 layer is closer to the dielectric layer 135 than the M3 layer. Figure 20 The number of dielectric layers 137 in the interconnect structure 130 shown is merely a non-limiting example, and any other suitable number is possible. In various embodiments, the interconnect structure 130 may have additional dielectric layers besides those shown.

[0076] In various embodiments, the interconnect structure 130 may include specific conductive components that allow read and write signal lines to form SRAM bit cells. For example, a separate read word line (RWL) 138 for each of the first cell 16 and the second cell 18 may be formed in the MO layer (dielectric layer 137A) to provide read access control for the first cell 16 and the second cell 18. The read word line (RWL) 138 may control the read access transistors within the first cell 16 and the second cell 18, allowing stored data to be read from the memory node of each of the first cell 16 and the second cell 18 during a read operation. Separate write bit lines 168 and 170 for each of the first cell 16 and the second cell 18 (e.g., including write bit line (WBL) 170 and complementary write bit line (WBLB) 168) may also be formed in the MO layer (dielectric layer 137A) and may be positioned closer to the transistors of the semiconductor memory device 10 compared to conventional embodiments using higher metal layers. Write bit line (WBL) 170 and complementary write bit line (WBLB) 168 can carry complementary data signals during write operations, allowing new data to be written into each of the first bit cell 16 and the second bit cell 18 of the memory node. Write bit line (WBL) 170 and complementary write bit line (WBLB) 168 (subsequently in...) Figure 25D (As shown in the diagram) This positioning in the M0 layer reduces the resistance in the write signal path and improves the write operation speed.

[0077] Shared conductors 140A and 140B can be formed in layer M1 (dielectric layer 137C) spanning the first bit cell 16 and the second bit cell 18. Conductors 140A and 140B provide shared electrical wiring and power to the independent write bit lines (WBL) 170 and complementary write bit lines (WBLB) 168 of adjacent first bit cells 16 and 18. Shared conductors 140A and 140B allow for shared wiring for write operations and support folded design configurations between first bit cells 16 and second bit cells 18 (where signal lines are shared between adjacent bit cells, rather than each bit cell having a dedicated independent signal line).

[0078] Independent conductors 139 for each of the first bit cell 16 and the second bit cell 18 can be formed in the M2 layer (dielectric layer 137E). The independent conductors 139 are configured to provide intermediate wiring connections to the read word line (RWL) 138 in the M0 layer. The independent conductors 139 provide electrical connections that allow signals to be distributed from higher metal layers to the read word line (RWL) 138.

[0079] A common conductor 142 spanning the first bit cell 16 and the second bit cell 18 can be formed in a higher metallization layer (such as the M3 layer (dielectric layer 137G)). The common conductor 142 can be electrically connected to the read word line (RWL) 138 via intermediate wiring provided by individual conductors 139 and other conductive vias (such as conductive vias 141) of the interconnect structure 130. The conductive vias 141 can be formed to provide a vertical electrical connection between the common conductor 142 in the M3 layer and the individual read word line (RWL) 138 in the M0 layer, thereby allowing signal routing between different metallization levels.

[0080] Advantages can be achieved by forming independent write bit lines 168 and 170 (e.g., including write bit line (WBL) 170 and complementary write bit line (WBLB) 168) for each of the first unit 16 and the second unit 18 in the M0 layer (e.g., dielectric layer 137A) and forming common conductors 140A and 140B across the first unit 16 and the second unit 18 in the M1 layer (e.g., dielectric layer 137C), wherein conductors 140A and 140B provide shared electrical wiring and power to the independent write bit line (WBL) 170 and complementary write bit line (WBLB) 168 of the adjacent first unit 16 and second unit 18. These advantages include the positioning of write bit lines (WBL) 170 and complementary write bit lines (WBLB) 168 in the M0 layer, and the shared conductors 140A and 140B within the M1 layer, shared by the first cell 16 and the second cell 18, wherein the M0 layer is the first metallization layer of the interconnect structure 130, which is closest to the transistor arrangement of the semiconductor memory device 10, and wherein the M1 layer is the second metallization layer of the interconnect structure 130. This results in reduced resistance in the write signal path and improved wiring efficiency within the interconnect structure 130. This reduction in resistance can lead to faster write operations and enhanced electrical performance of the semiconductor memory device 10. Furthermore, the improved wiring efficiency further enhances area utilization within the interconnect structure 130 and allows for a more compact cell layout supporting longer bit line designs, resulting in improved scalability for larger memory arrays and reduced overall manufacturing complexity.

[0081] exist Figure 21 In this configuration, the semiconductor memory device 10 can be flipped so that the exposed surface of the substrate 50 faces upwards. Figure 22 Then, a dielectric layer 152 can be formed on the exposed surface of the substrate 50. In an embodiment, the dielectric layer 152 may include silicon nitride, which is deposited by techniques such as CVD, PECVD, ALD, etc. After forming the dielectric layer 152, a dielectric layer 154 may be formed over the dielectric layer 152. In an embodiment, the dielectric layer 154 may serve as a hard mask layer and may include a dielectric material, such as silicon oxide, silicon oxynitride, etc., deposited by techniques such as CVD, PECVD, ALD, etc. After forming the dielectric layer 154, a photomask 156 (e.g., photoresist) can be formed over the dielectric layer 154 using spin coating techniques, etc. The photomask 156 can be patterned using acceptable photolithography and etching techniques to form openings in the photomask 156.

[0082] exist Figure 23In this process, after forming and patterning the photomask 156, the patterned photomask 156 can then be used as an etching mask to perform a first etching process to transfer the pattern of the photomask 156 to the dielectric layer 154. After performing the first etching process, the photomask 156 can be removed, such as by an acceptable ashing process. After removing the photomask 156, the dielectric layer 154 can be used as an etching mask to perform a second etching process to form one or more openings 158 extending through the dielectric layer 152 and the substrate 50 to expose one or more corresponding first epitaxial materials 93. In an embodiment, the second etching process may include performing a dry etching process using, for example, CH4 as an etchant. After performing the second etching process, a third etching process is performed to selectively remove the first epitaxial materials 93 exposed at the bottom of the openings 158 and to expose the top surface of the isolation layer 91 in the openings 158. In an embodiment, the third etching process may include an isotropic etching process that selectively removes the first epitaxial materials 93 based on its higher germanium atom concentration. The third etching process may include a wet etching process, for example, using a fluorine-based or chlorine-based etchant, to selectively remove the first epitaxial material 93 without significantly removing the material of the epitaxial source / drain regions 92, the substrate 50, and the isolation layer 91. After the third etching process, a fourth etching process is performed to remove portions of the isolation layer 91 located in one or more openings 158, and to expose the top surfaces of the corresponding epitaxial source / drain regions 92 in the openings 158. Performing the fourth etching process may include a dry etching process using, for example, CH4 as an etchant.

[0083] After the fourth etching process, a silicide region 161 is formed at the bottom of one or more openings 158 on the exposed top surface of the corresponding epitaxial source / drain region 92. The method for forming the silicide region 161 can be the same as that for the silicide region 110 (previously in...). Figure 18A and Figure 18B The formation methods described herein are the same or similar, and therefore will not be repeated.

[0084] exist Figure 24In the opening 158, a back-side contact 162 is formed to provide electrical connection to the corresponding epitaxial source / drain region 92. To form the back-side contact 162, a pad 159, such as a diffusion barrier layer, adhesive layer, etc., may be formed on the sidewall within the opening 158, and a conductive material is subsequently formed over the pad 159 and within the opening 158. The pad 159 may include titanium, titanium nitride, tantalum, tantalum nitride, etc. The conductive material may include tungsten (W), ruthenium (Ru), cobalt (Co), copper (Cu), molybdenum (Mo), iridium (Ir), titanium (Ti), tantalum nitride (TaN), titanium nitride (TiN), nickel aluminum oxide (NiAl), or combinations thereof. A planarization process, such as CMP, may be performed to remove excess material from the dielectric layer 154 and the pad 159, as well as the conductive material, from the surface of the dielectric layer 152. The remaining pad 159 and conductive material form the back-side contact 162 in the opening 158. The back contact 162 is physically and electrically coupled to the corresponding epitaxial source / drain region 92 via the silicide region 161. In this embodiment, after planarization, the top surface of the back contact 162 may be substantially flush with the top surface of the dielectric layer 152.

[0085] Further reference Figure 24 A dielectric layer 188 (not shown) can be formed over the dielectric layer 152, the back contact 162, and the substrate 50. The dielectric layer 188 can be formed from a suitable dielectric material, such as silicon nitride (SiN), silicon oxide, etc., formed by a suitable formation method (such as CVD, ALD, etc.). After forming the dielectric layer 188, trenches can be formed in the dielectric layer 188 using acceptable photolithography and etching techniques. A conductive material can be formed in the trenches and over the dielectric layer 188. In some embodiments, the conductive material includes copper, aluminum, cobalt, tungsten, titanium, tantalum, ruthenium, etc. The conductive material can be formed using suitable deposition processes, such as PVD, plating, CVD, etc. Planarization processes, such as CMP, polishing, etc., can be performed to remove excess conductive material from the surface of the dielectric layer 188. The remaining conductive material forms read lines (RBLs) 160 in the trenches. In one embodiment, after planarization, the top surface of the read line (RBL) 160 may be substantially flush with the top surface of the dielectric layer 188. In another embodiment, the read line (RBL) 160 may have a thickness T1 ranging from 300 nm to 500 nm and a width W1 ranging from 50 nm to 150 nm. In yet another embodiment, the read line (RBL) 160 is positioned at the boundary between the first cell 16 and the second cell 18 and is physically and electrically coupled to one or more epitaxial source / drain regions 92 in each of the first cell 16 and the second cell 18 via a back-side contact 162.

[0086] Figures 25A to 25FVarious views of a semiconductor memory device 10 according to some embodiments are shown. Figure 25A The active region 14 of the semiconductor memory device 10 is shown along... Figures 25B to 25F The cross-sectional view of line D-D' shown. Figures 25B to 25F Various top views of different components of a semiconductor memory device 10 according to some embodiments are shown. Figure 25G A circuit diagram of bit cell 30 according to some embodiments is shown. The same reference numerals throughout this embodiment (and the embodiments discussed below) indicate… Figures 1 to 24 The same components are formed using the same process in the embodiments shown. Therefore, the process steps and applicable materials will not be repeated herein.

[0087] Figure 25A It can be shown that the previous state after the flip semiconductor memory device 10 is shown Figure 24 The semiconductor memory device 10 shown in the figure enables the interconnect structure 130 to be disposed on the substrate 50. Figure 25A The active region 14 of the semiconductor memory device 10 is shown along... Figures 25B to 25F The cross-sectional view of line D-D' shown.

[0088] Figure 25BThe semiconductor memory device 10 is shown, comprising a first bit cell 16 and a second bit cell 18 adjacent to the first bit cell 16, wherein each of the first bit cell 16 and the second bit cell 18 is an SRAM bit cell (also referred to as a 7T SRAM bit cell) comprising seven transistors. A read bit line (RBL) 160 is positioned on the back side of the semiconductor memory device 10 and shared between the first bit cell 16 and the second bit cell 18, wherein the read bit line (RBL) 160 is disposed at the boundary between two adjacent first bit cells 16 and second bit cells 18. The seven transistors in each of the first bit cell 16 and the second bit cell 18 include two p-type pull-up transistors (PUs) to maintain stored data by connecting the memory node to a power supply, two n-type pull-down transistors (PDs) to provide a discharge path to ground, two p-type write transfer gate transistors (WPGs) to control write access to the memory node during write operations, and one n-type read port gate transistor (RPG) to provide dedicated read access without interfering with the stored data. The semiconductor memory device 10 may include a plurality of active regions 166 defining regions for forming transistors, wherein a gate structure 103 is disposed over these active regions 166 to form individual transistors. The active regions 166 may include: an active region 12, which is part of a first cell 16 and formed in an n-type region 50N for forming an n-type transistor; and an active region 14, which is part of a second bit cell 18 and also formed in an n-type region 50N for forming an n-type transistor, wherein active regions 12 and 14 represent transistor formation regions within their respective bit cell structures. A back-side contact 162 may extend through the substrate 50 to provide an electrical connection between the epitaxial source / drain regions 92 of the read port gate transistors (RPGs) of the first cell 16 and the second bit cell 18 and a shared read bit line (RBL) 160. In addition, the back-side power supply line 163 can be positioned on the back side of the semiconductor memory device 10 to provide power to the pull-up transistors (PUs) of the first cell 16 and the second cell 18.

[0089] In one embodiment, the read bit line (RBL) 160 may have a width W1 ranging from 50 nm to 150 nm. In another embodiment, each power supply line 163 may have a width W2 ranging from 50 nm to 150 nm. In another embodiment, the spacing S1 between the first sidewall of the read bit line (RBL) 160 and the second sidewall of the adjacent power supply line 163 is ranging from 50 nm to 150 nm, wherein the first and second sidewalls are adjacent to each other. In another embodiment, the ratio of the width W1 of the read bit line (RBL) 160 to the width W2 of each power supply line 163 is less than or equal to 5. In another embodiment, the ratio of the width W1 of the read bit line (RBL) 160 to the spacing S1 is less than or equal to 2. In an embodiment, the cell height C1 of each of the first cell 16 and the second cell 18 is equal to half the sum of the intervals S1, the width W1 of the read line (RBL) 160, and the width W2 of each power supply line 163, wherein the cell height C1 represents the dimension of each of the first cell 16 and the second cell 18 in a direction perpendicular to the length of the read line (RBL) 160 and the power supply line 163.

[0090] Advantages are achieved by forming a read bit line (RBL) 160 on the back side of the semiconductor memory device 10. The read bit line (RBL) 160 is shared between the first cell 16 and the second cell 18, wherein the read bit line (RBL) 160 is located at the boundary between the first cell 16 and the second cell 18. The read bit line (RBL) 160 is physically and electrically coupled to one or more epitaxial source / drain regions 92 in each of the first cell 16 and the second cell 18 via a back-side contact 162. These advantages include the ability to form a read bit line (RBL) 160 with a larger dimension. For example, the read bit line (RBL) 160 has a thickness T1 ranging from 300 nm to 500 nm and a width W1 ranging from 50 nm to 150 nm. This allows the resistance of the read bit line (RBL) 160 to be reduced by 70% to 80%. Therefore, the read operation speed of the semiconductor memory device 10 is improved by 10% to up to 15%. Furthermore, the positioning of the shared read bit line (RBL) 160 at the boundary between adjacent first bit cells 16 and second bit cells 18 can lead to a reduction in layout imbalance problems and improved electrical matching between adjacent first bit cells 16 and second bit cells 18. Additionally, forming the read bit line (RBL) 160 on the back side of the semiconductor memory device 10 provides additional spacing within the interconnect structure 130, allowing for the formation of write bit lines (WBL) 170 and complementary write bit lines (WBLB) 168 closer to the transistor positioning of the semiconductor memory device 10 in the M0 layer, and the formation of shared conductors 140A and 140B in the M1 layer. Therefore, wiring congestion in the interconnect structure 130 is reduced, and more efficient signal routing and power distribution are achieved within the semiconductor memory device 10.

[0091] Figure 25CThe semiconductor memory device 10 is shown to include a plurality of active regions 166, including: active region 12, which is part of a first bit cell 16; and active region 14, which is part of a second bit cell 18. Active regions 12 and 14 contain transistor elements for their respective bit cells. A gate structure 103 is disposed above the active regions 166 to form individual transistors. Source / drain contacts 112 provide electrical connections to epitaxial source / drain regions 92 of the transistors formed in the active regions 166, while gate contacts 114 provide electrical connections to the gate structure 103. The semiconductor memory device 10 may include: a conductive via 176 providing a power supply connection to a p-type pull-up transistor (PU) of the second bit cell 18; a conductive via 178 providing a ground connection to an n-type pull-down transistor (PD) of the first bit cell 16 and the second bit cell 18; and a conductive via 165 providing a power supply connection to the p-type pull-up transistor (PU) of the first bit cell 16. The semiconductor memory device 10 may also include a via 134 electrically coupled to a source / drain contact 112.

[0092] Figure 25DThe diagram illustrates the wiring formed in the MO layer of the interconnect structure 130 for the first cell 16 and the second cell 18. The wiring in the MO layer may include: a read word line (RWL) 138, which controls the corresponding n-type read port gate transistors (RPGs) of the first cell 16 and the second cell 18 to allow read access to the memory nodes of the first cell 16 and the second cell 18 during a read operation; a write bit line (WBL) 170, which carries the data signal to be written into the memory node during a write operation; a complementary write bit line (WBLB) 168, which carries a data signal complementary to the write bit line 170 during a write operation; a write word line (WWL) 172, which controls the p-type write transmission gate transistors (WPGs) of the first cell 16 and the second cell 18 to allow write access to the memory node; and a bit cell contact line (BCT) 174, which provides local wiring connections within each of the first cell 16 and the second cell 18. The conductors in the M0 layer of the interconnect structure 130 may further include: a power supply line 175 connected to a conductive via 176 to provide power to the p-type pull-up transistor (PU) of the second bit cell 18; and a ground supply line 177 connected to a conductive via 178 to provide a ground connection to the n-type pull-down transistors (PD) of the first bit cell 16 and the second bit cell 18. Compared to conventional implementations using a higher metallization layer, the positioning of the write bit line (WBL) 170 and complementary write bit line (WBLB) 168 in the M0 layer allows for reduced signal path resistance and improved electrical performance for read and write operations. The M0 layer is the metallization layer of the interconnect structure 130 closest to the transistors of the first bit cell 16 and the second bit cell 18.

[0093] Figure 25EThe diagram illustrates the conductors formed in the M1 layer of the interconnect structure 130 for the first unit 16 and the second unit 18. The conductors in the M1 layer include common conductors 140A and 140B that span the first unit 16 and the second unit 18 and provide shared electrical wiring and power to the individual write bit lines (e.g., write bit line (WBL) 170 and complementary write bit line (WBLB) 168) of the adjacent first unit 16 and second unit 18. A conductive via 184 connects the common conductor 140A to the write bit line (WBL) 170 in the underlying M0 layer of the first unit 16 and the second unit 18. In an embodiment, a first conductive via 184A connects the common conductor 140A to the first write bit line (WBL) 170A in the second unit 18. A conductive via 182 connects the common conductor 140B to the complementary write bit line (WBLB) 168 in the underlying M0 layer of the first unit 16 and the second unit 18. In one embodiment, a first conductive via 182A connects a common conductor 140B to a first complementary write bit line (WBLB) 168A in the first unit 16. The M1 layer may also include other common conductors, such as a common conductor 185 that, for example, spans the first unit 16 and the second unit 18 and provides shared wiring for write word lines (WWL) 172 in the first unit 16 and the second unit 18, wherein the common conductor 185 is connected to the write word lines (WWL) 172 in the M0 layer via a conductive via 186.

[0094] Figure 25FThe diagram illustrates the conductors formed in layers M2 and M3 of an interconnect structure 130 for a first cell 16 and a second cell 18 of a semiconductor memory device 10. In an embodiment, the semiconductor memory device 10 includes a separate conductor 139 for each of the first cell 16 and the second cell 18, the separate conductor 139 being formed in the M2 layer and configured to provide an intermediate wiring connection to a read word line (RWL) 138 in the M0 layer. The semiconductor memory device 10 also includes a common conductor 142 spanning and shared by the first cell 16 and the second cell 18, and formed in the M3 layer, wherein the common conductor 142 is electrically connected to the read word line (RWL) 138 in the M0 layer via the intermediate wiring provided by the separate conductors 139. A conductive via 141 provides a vertical electrical connection between the common conductor 142 in the M3 layer and the separate conductor 139 in the M2 layer. In one embodiment, the conductive via 141 includes a first conductive via 141A, which electrically connects a first common conductor 142A in layer M3 to a first independent conductor 139A in layer M2 of the second unit 18. In another embodiment, the conductive via 141 further includes a second conductive via 141B, which electrically connects a second common conductor 142B in layer M3 to a second independent conductor 139B in layer M2 of the first unit 16.

[0095] Figure 25G A circuit diagram of bit cells 30 of a semiconductor memory device 10 according to some embodiments is shown. In the embodiments, each of the first bit cell 16 and the second bit cell 18 (previously in...) Figures 1 to 25F The bit cell (described in the text) can be implemented as a bit cell 30. Bit cell 30 may include seven transistors and is hereinafter referred to as a 7T-SRAM bit cell. Bit cell 30 includes two cross-coupled inverters, forming a bistable memory element capable of storing one data bit. Bit cell 30 includes a first inverter formed by a p-type pull-up transistor PU0 and an n-type pull-down transistor PD0, and a second inverter formed by a p-type pull-up transistor PU1 and an n-type pull-down transistor PD1. The first and second inverters are cross-coupled such that the output of the first inverter (e.g., at memory node SN0) is connected to the input of the second inverter, and the output of the second inverter (e.g., at memory node SN1) is connected to the input of the first inverter, thereby forming a bistable latch capable of storing one data bit. Memory node SN1 stores the complementary bit of the bit stored at memory node SN0.

[0096] Further reference Figure 25GWrite access to memory nodes SN0 and SN1 is provided by p-type write transmission gate transistors WPG0 and WPG1, respectively. WPG0 is connected between memory node SN0 and write bit line WBL, while WPG1 is connected between memory node SN1 and complementary write bit line WBLB. Both WPG0 and WPG1 have gate terminals connected to write word line WWL, which controls access to bit cell 30 during write operations. Read access to memory node SN0 is provided by n-type read port gate transistor RPG, which is connected between memory node SN0 and read bit line RBL (e.g., a read bit line (RBL) 160 shared between adjacent bit cells, as previously described). Figures 1 to 25F (as described in the text). The gate terminal of the read port gate transistor RPG is connected to the read word line RWL, which controls read access to the bit cell 30 during a read operation.

[0097] During a write operation, the write word line WWL is asserted, and the read word line RWL is deasserted. This turns on p-type write transmission gate transistors WPG0 and WPG1, and turns off n-type read transmission gate transistor RPG, thereby allowing the differential voltage applied to the write bit line WBL and the complementary write bit line WBLB to rewrite the data stored in the cross-coupled inverter. During a read operation, the read word line RWL is asserted, and the write word line WWL is deasserted, and the stored data is sensed as the voltage on the read bit line RBL.

[0098] Figure 26A and Figure 26B A cross-sectional view of a semiconductor memory device 10 according to some embodiments is shown. Figure 26A A semiconductor memory device 10 according to some embodiments is shown. Figures 25B to 25E The cross-sectional view of line E-E' shown. Figure 26B A semiconductor memory device 10 according to some embodiments is shown. Figures 25B to 25E The cross-sectional view of line F-F' shown in the figure.

[0099] Figure 26AThe interconnect structure 130 is illustrated with M0 and M1 layers, and a silicide region 110 formed on the epitaxial source / drain region 92. Source / drain contacts 112 extend through insulating materials 190, 191, and 194 to electrically connect the silicide region 110 and the epitaxial source / drain region 92 to conductive components in the M0 layer. Insulating materials 190, 191, and 194 provide electrical isolation and may include silicon oxide, silicon nitride, low-k dielectric materials, or combinations thereof. A first epitaxial material 93 (e.g., comprising epitaxial materials 93A and 93B, distinct from each other) is positioned beneath one or more of the epitaxial source / drain regions 92. Conductive vias 176, 178, and 165 provide electrical connections within the M0 and M1 layers to power supply lines and signal wiring. A via 134 extends through dielectric layer 135 to provide a vertical electrical connection between source / drain contacts 112 and the interconnect structure 130 above. A first ILD 96 provides electrical isolation between adjacent epitaxial source / drain regions 92. A shared read bit line (RBL) 160 and a power supply line 163 are disposed on the back side of the semiconductor memory device 10, wherein the shared read bit line (RBL) 160 and the power supply line 163 are embedded in dielectric layer 188, and wherein the shared read bit line (RBL) 160 is positioned between the power supply lines 163. Back-side contacts 162 provide an electrical connection between the epitaxial source / drain regions 92 and the power supply lines 163, allowing power to be distributed to the transistors of the bit cells (e.g., first bit cell 16 and second bit cell 18) of the semiconductor memory device 10.

[0100] Figure 26B The M0 and M1 layers of the interconnect structure 130 are shown, along with a silicide region 110 formed on the epitaxial source / drain region 92. Source / drain contacts 112 extend through insulating materials 190, 191, and 194 to electrically connect the silicide region 110 and the epitaxial source / drain region 92 to conductive components in the M0 layer. A first epitaxial material 93 (e.g., comprising epitaxial materials 93A and 93B, distinct from each other) is positioned beneath one or more of the epitaxial source / drain regions 92. Conductive vias 176, 178, and 165 provide electrical connections within the M0 and M1 layers to power supply lines and signal wiring. The M1 layer includes a common conductor 140B that spans the first cell 16 and the second cell 18 of the semiconductor memory device 10 and provides shared electrical wiring and power to complementary write lines (WBLBs) 168 of the first cell 16 and the second cell 18, as previously described. Figure 25EAs described in [the text]. The first ILD 96 provides electrical isolation between adjacent epitaxial source / drain regions 92. A shared read bit line (RBL) 160 and a power supply line 163 are disposed on the back side of the semiconductor memory device 10, wherein the shared read bit line (RBL) 160 and the power supply line 163 are embedded in a dielectric layer 188, and wherein the shared read bit line (RBL) 160 is positioned between the power supply lines 163. A back-side contact 162 provides an electrical connection between the epitaxial source / drain regions 92 and the shared read bit line (RBL) 160, allowing read functionality for transistors in bit cells (e.g., first bit cell 16 and second bit cell 18) of the semiconductor memory device 10.

[0101] Figure 27 A semiconductor memory device 10 according to some other embodiments is shown. Unless otherwise stated, the same reference numerals in this embodiment (and the embodiments discussed below) denote... Figures 1 to 26B The same components are formed using the same process in the embodiments shown. Therefore, the process steps and applicable materials will not be repeated herein.

[0102] Figure 27 The diagram illustrates the conductors formed in the M1 layer of the interconnect structure 130 for the first cell 16 and the second cell 18. The conductors in the M1 layer include common conductors 140A and 140B that span the first cell 16 and the second cell 18 and provide shared electrical wiring and power to the individual write bit lines (e.g., write bit line (WBL) 170 and complementary write bit line (WBLB) 168) of the adjacent first cell 16 and second cell 18. A conductive via 184 connects the common conductor 140A to the write bit line (WBL) 170 in the underlying M0 layer of the first cell 16 and the second cell 18. In an embodiment, a first conductive via 184A also connects the common conductor 140A to the first complementary write bit line (WBLB) 168A in the first cell 16. A conductive via 182 connects the common conductor 140B to the complementary write bit line (WBLB) 168 in the underlying M0 layer of the first cell 16 and the second cell 18. In one embodiment, the first conductive via 182A also connects the common conductor 140B to the first write word line (WBL) 170A in the second bit cell 18. The M1 layer may also include other common conductors, such as a common conductor 185 that, for example, spans the first bit cell 16 and the second bit cell 18 and provides shared wiring for the write word line (WWL) 172 of the first bit cell 16 and the second bit cell 18, wherein the common conductor 185 is connected to the write word line (WWL) 172 in the M0 layer via a conductive via 186.

[0103] Figure 28A semiconductor memory device 10 according to some other embodiments is shown. Unless otherwise stated, the same reference numerals in this embodiment (and the embodiments discussed below) denote... Figures 1 to 27 The same components are formed using the same process in the embodiments shown. Therefore, the process steps and applicable materials will not be repeated herein.

[0104] Figure 28 The diagram illustrates the conductors formed in layers M2 and M3 of an interconnect structure 130 for a first cell 16 and a second cell 18 of a semiconductor memory device 10. In an embodiment, the semiconductor memory device 10 includes a separate conductor 139 for each of the first cell 16 and the second cell 18, the separate conductor 139 being formed in the M2 layer and configured to provide an intermediate wiring connection to a read word line (RWL) 138 in the M0 layer. The semiconductor memory device 10 also includes a common conductor 142 spanning and shared by the first cell 16 and the second cell 18, and formed in the M3 layer, wherein the common conductor 142 is electrically connected to the read word line (RWL) 138 in the M0 layer via the intermediate wiring provided by the separate conductors 139. A conductive via 141 provides a vertical electrical connection between the common conductor 142 in the M3 layer and the separate conductor 139 in the M2 layer. In one embodiment, the conductive via 141 includes a first conductive via 141A, which electrically connects a first common conductor 142A in layer M3 to a second independent conductor 139B in layer M2 of the first unit 16. In another embodiment, the conductive via 141 further includes a second conductive via 141B, which electrically connects a second common conductor 142B in layer M3 to the first independent conductor 139A in layer M2 of the second unit 18.

[0105] The embodiments of this disclosure have several advantageous features. The embodiments include a method suitable for forming read bit lines (RBLs) disposed on the back side of a semiconductor memory device, wherein the read bit lines (RBLs) are shared between two adjacent 7T SRAM bit cells. For example, the shared read bit line (RBL) is located at the boundary between a first cell and a second bit cell, wherein the first cell and the second bit cell are adjacent to each other. The shared read bit line (RBL) can be electrically connected to a front-side interconnect structure on the front side of the semiconductor memory device and electrically connected to a transistor within each of the first cell and the second bit cell via a back-side contact (which may also be referred to as a back-side via) disposed through the semiconductor substrate of the semiconductor memory device. In the embodiments, the read bit line (RBL) can have a thickness in the range of 300 nm to 500 nm. In various embodiments, write bit lines (WBL and WBLB) are formed in the front-side interconnect structure at a first metal layer, which is positioned closer to the transistors of the semiconductor memory device compared to conventional embodiments using a higher metal layer disposed further away from the transistors of the semiconductor memory device. For each of the first cell and the second bit cell, the write bit line can be an independent wire. The second metal layer of the front interconnect structure (positioned above the first metal layer) may include a common conductor across the first and second bit cells and providing shared electrical wiring and power to adjacent first and second bit cells. The shared read bit line (RBL) and the common conductor together allow for a folded design between the first and second bit cells (where signal lines are shared between adjacent bit cells, rather than each bit cell having a dedicated independent signal line).

[0106] These advantages include the read bit lines (RBLs) being formed on the back side of the semiconductor memory device, allowing for larger RBL dimensions. For example, the RBLs can have thicknesses ranging from 300 nm to 500 nm. This can allow for a 70% to 80% reduction in RBL resistance. Consequently, the read operation speed of the semiconductor memory device can be improved by 10% to up to 15%. Furthermore, positioning shared read bit lines (RBLs) at the boundary between adjacent first and second bit cells reduces layout imbalance and provides improved electrical matching between adjacent first and second bit cells. Additionally, forming write bit lines (WBLs and WBLBs) in the front-side interconnect structure at the first metal layer closer to the transistor positioning of the semiconductor memory device, combined with forming a common conductor within the second metal layer that provides shared electrical wiring and power to the individual write bit lines, reduces resistance in the write signal path and improves wiring efficiency. This improves area utilization and enables a more compact cell layout that supports longer bit line designs. Therefore, scalability for larger memory arrays can be improved, and overall manufacturing complexity can be reduced.

[0107] According to an embodiment, a method for forming a semiconductor device including a first cell and a second cell adjacent to the first cell includes: depositing a multilayer stack on a semiconductor substrate, the multilayer stack including a plurality of sacrificial layers alternating with a plurality of channel layers; forming a first fin in a first region of the semiconductor substrate, wherein forming the first fin includes performing an etching process to define a first nanostructure by the plurality of sacrificial layers and a second nanostructure by the plurality of channel layers; forming a source / drain region above the semiconductor substrate and on the opposite side of the first nanostructure; replacing the first nanostructure with a gate structure; forming an interlayer dielectric (ILD) layer above the source / drain region; and forming an extensional layer. A source / drain contact extending through the ILD layer to be electrically coupled to a first source / drain region of the source / drain region, wherein the conductivity of the source / drain contact is greater than the conductivity of the first source / drain region; and a front-side interconnect structure formed above the ILD layer and the gate structure, the front-side interconnect structure including: a first write bit line for a first bit cell and a second write bit line for a second bit cell, located in a first metallization layer; and a common conductor located in a second metallization layer disposed above the first metallization layer, wherein the common conductor spans the first bit cell and the second bit cell, wherein a first common conductor of the common conductor is electrically connected to the first write bit line and the second write bit line. In an embodiment, the first region is an n-type region. In an embodiment, each of the first bit cell and the second bit cell includes seven transistors. In an embodiment, the method further includes: forming a back-side contact extending through the semiconductor substrate, wherein the back-side contact is electrically coupled to a second source / drain region of the source / drain region. In one embodiment, the method further includes forming a read line (RBL) on the back side of a semiconductor substrate, wherein the read line is electrically coupled to a second source / drain region via a back-side contact. In another embodiment, the RBL is positioned at the boundary between the first and second bit cells. In yet another embodiment, the RBL has a thickness in the range of 300 nm to 500 nm.

[0108] According to an embodiment, a method for forming a memory device including a first bit cell and a second bit cell includes: depositing a first sacrificial layer over a semiconductor substrate; depositing a first channel layer over the first sacrificial layer; depositing a second sacrificial layer over the first channel layer; depositing a second channel layer over the second sacrificial layer; forming a first fin in a first region of the semiconductor substrate for the first bit cell and forming a second fin in a second region of the semiconductor substrate for the second bit cell, wherein forming the first fin and the second fin includes performing an etching process to define a first nanostructure of the first fin and the second fin by the first sacrificial layer and the second sacrificial layer, and defining a second nanostructure of the first fin and the second fin by the first channel layer and the second channel layer; replacing the first gate structure with a first gate structure. The method involves replacing the first nanostructure of the first fin with a second gate structure, and replacing the first nanostructure of the second fin with a second gate structure; forming a first source / drain region in the first fin on the opposite side of the first gate structure; forming a second source / drain region in the second fin on the opposite side of the second gate structure; forming a silicide region above the top surface of the first one in the first source / drain region, wherein the silicide region has a higher conductivity than the first one in the first source / drain region; and forming a shared read line (RBL) on the back side of the semiconductor substrate, the shared RBL being disposed at the boundary between the first bit cell and the second bit cell, wherein the shared RBL is electrically coupled to the first one in the first source / drain region and the first one in the second source / drain region. In an embodiment, the method further includes: forming a first back-side contact extending through the semiconductor substrate before forming the shared RBL, wherein the first back-side contact electrically couples the shared RBL to the first one in the first source / drain region. In an embodiment, the method further includes: forming a second back-side contact extending through the semiconductor substrate before forming the shared RBL, wherein the second back-side contact electrically couples the shared RBL to the first one in the second source / drain region. In an embodiment, the method further includes: forming a front-side interconnect structure over a first region and a second region of a semiconductor substrate, the front-side interconnect structure including: a first write bit line for a first bit cell and a second write bit line for a second bit cell, located in a first metallization layer; and a common conductor located in a second metallization layer disposed above the first metallization layer, wherein the common conductor spans the first bit cell and the second bit cell, and wherein a first common conductor of the common conductor is electrically connected to the first write bit line and the second write bit line. In an embodiment, each of the first region and the second region is an n-type region. In an embodiment, each of the first bit cell and the second bit cell includes seven transistors. In an embodiment, the shared RBL has a thickness in the range of 300 nm to 500 nm.

[0109] According to an embodiment, a semiconductor memory device includes: a first gate structure located above a first region of a semiconductor substrate, the first region being used for a first bit cell; a second gate structure located above a second region of the semiconductor substrate, the second region being used for a second bit cell, wherein, when viewed in a top view, the first bit cell and the second bit cell are adjacent; a first source / drain region located above the semiconductor substrate and on opposite sides of the first gate structure; a second source / drain region located above the semiconductor substrate and on opposite sides of the second gate structure; a first active channel region disposed between the first source / drain regions and above the semiconductor substrate; and a second active channel region. A source channel region is disposed between the second source / drain regions and above the semiconductor substrate. The second gate structure includes a gate dielectric layer above the second active channel region and a gate electrode above the gate dielectric layer. A gate spacer extends along the sidewall of the second gate structure, wherein the dielectric constant of the gate dielectric layer is greater than the dielectric constant of the gate spacer. A shared read line (RBL) is located on the back side of the semiconductor substrate, positioned at the boundary between the first and second bit cells, wherein the shared RBL is electrically coupled to the first bit in the first source / drain region and the first bit in the second source / drain region. In an embodiment, the semiconductor memory device further includes a first back-side contact extending through the semiconductor substrate, wherein the first back-side contact electrically couples the shared RBL to the first bit in the first source / drain region. In an embodiment, the semiconductor memory device further includes a second back-side contact extending through the semiconductor substrate, wherein the second back-side contact electrically couples the shared RBL to the first bit in the second source / drain region. In an embodiment, the shared RBL has a thickness in the range of 300 nm to 500 nm. In an embodiment, the semiconductor memory device further includes: a front interconnect structure located above the first region and the second region, the front interconnect structure including: a first write bit line for a first bit cell and a second write bit line for a second bit cell, located in a first metallization layer; and a common conductor located in a second metallization layer disposed above the first metallization layer, wherein the common conductor spans the first bit cell and the second bit cell, and wherein a first common conductor of the common conductor is electrically connected to the first write bit line and the second write bit line. In an embodiment, each of the first bit cell and the second bit cell includes seven transistors.

[0110] Some embodiments of this application provide a method for forming a semiconductor device including a first bit cell and a second bit cell adjacent to the first bit cell, the method comprising: depositing a multilayer stack on a semiconductor substrate, the multilayer stack including a plurality of sacrificial layers alternating with a plurality of channel layers; forming a first fin in a first region of the semiconductor substrate, wherein forming the first fin includes performing an etching process to define a first nanostructure by the plurality of sacrificial layers and a second nanostructure by the plurality of channel layers; forming a source / drain region above the semiconductor substrate and on the opposite side of the first nanostructure; replacing the first nanostructure with a gate structure; forming an interlayer dielectric layer above the source / drain region; and forming an interlayer dielectric layer extending through the layer. An interlayer dielectric layer is electrically coupled to source / drain contacts in a first source / drain region of the source / drain region, wherein the conductivity of the source / drain contacts is greater than the conductivity of the first source / drain region; and a front-side interconnect structure is formed above the interlayer dielectric layer and the gate structure, the front-side interconnect structure including: a first write bit line for the first bit cell and a second write bit line for the second bit cell, located in the first metallization layer; and a common conductor located in a second metallization layer disposed above the first metallization layer, wherein the common conductor spans the first bit cell and the second bit cell, and wherein a first common conductor of the common conductor is electrically connected to the first write bit line and the second write bit line.

[0111] In some embodiments, the first region is an n-type region. In some embodiments, each of the first bit cell and the second bit cell includes seven transistors. In some embodiments, the method further includes: forming a back-side contact extending through the semiconductor substrate, wherein the back-side contact is electrically coupled to a second source / drain region of the source / drain region. In some embodiments, the method further includes: forming a read bit line on the back side of the semiconductor substrate, wherein the read bit line is electrically coupled to the second source / drain region through the back-side contact. In some embodiments, the read bit line is positioned at the boundary between the first bit cell and the second bit cell. In some embodiments, the read bit line has a thickness in the range of 300 nm to 500 nm.

[0112] Other embodiments of this application provide a method for forming a memory device including a first bit cell and a second bit cell, the method comprising: depositing a first sacrificial layer over a semiconductor substrate; depositing a first channel layer over the first sacrificial layer; depositing a second sacrificial layer over the first channel layer; depositing a second channel layer over the second sacrificial layer; forming a first fin in a first region of the semiconductor substrate for the first bit cell, and forming a second fin in a second region of the semiconductor substrate for the second bit cell, wherein forming the first fin and the second fin includes performing an etching process to define a first nanostructure of the first fin and the second fin by the first sacrificial layer and the second sacrificial layer, and to define a second nanostructure of the first fin and the second fin by the first channel layer and the second channel layer; using a first A gate structure replaces the first nanostructure of the first fin, and a second gate structure replaces the first nanostructure of the second fin; a first source / drain region is formed in the first fin on the opposite side of the first gate structure; a second source / drain region is formed in the second fin on the opposite side of the second gate structure; a silicide region is formed above the top surface of the first one in the first source / drain region, wherein the silicide region has a higher conductivity than the first one in the first source / drain region; and a shared read bit line is formed on the back side of the semiconductor substrate, the shared read bit line being disposed at the boundary between the first bit cell and the second bit cell, wherein the shared read bit line is electrically coupled to the first one in the first source / drain region and the first one in the second source / drain region.

[0113] In some embodiments, the method further includes: forming a first back-side contact extending through the semiconductor substrate before forming the shared read bit line, wherein the first back-side contact electrically couples the shared read bit line to the first of the first source / drain regions. In some embodiments, the method further includes: forming a second back-side contact extending through the semiconductor substrate before forming the shared read bit line, wherein the second back-side contact electrically couples the shared read bit line to the first of the second source / drain regions. In some embodiments, the method further includes: forming a front-side interconnect structure over the first and second regions of the semiconductor substrate, the front-side interconnect structure including: a first write bit line for the first bit cell and a second write bit line for the second bit cell, located in a first metallization layer; and a common conductor located in a second metallization layer disposed above the first metallization layer, wherein the common conductor spans the first bit cell and the second bit cell, wherein a first common conductor of the common conductor is electrically connected to the first write bit line and the second write bit line. In some embodiments, each of the first and second regions is an n-type region. In some embodiments, each of the first and second bit cells includes seven transistors. In some embodiments, the shared read line has a thickness in the range of 300 nm to 500 nm.

[0114] Some embodiments of this application provide a semiconductor memory device, including: a first gate structure located above a first region of a semiconductor substrate, the first region being used for a first bit cell; a second gate structure located above a second region of the semiconductor substrate, the second region being used for a second bit cell, wherein, when viewed in a top view, the first bit cell and the second bit cell are adjacent; a first source / drain region located above the semiconductor substrate and on the opposite side of the first gate structure; a second source / drain region located above the semiconductor substrate and on the opposite side of the second gate structure; and a first active channel region disposed between the first source / drain regions and above the semiconductor substrate. A second active channel region is disposed between the second source / drain regions and above the semiconductor substrate, wherein the second gate structure includes a gate dielectric layer located above the second active channel region and a gate electrode located above the gate dielectric layer; a gate spacer extends along the sidewall of the second gate structure, wherein the dielectric constant of the gate dielectric layer is greater than the dielectric constant of the gate spacer; and a shared read bit line is located on the back side of the semiconductor substrate, the shared read bit line being positioned at the boundary between the first bit cell and the second bit cell, wherein the shared read bit line is electrically coupled to the first bit in the first source / drain region and the first bit in the second source / drain region.

[0115] In some embodiments, the semiconductor memory device further includes: a first back-side contact extending through the semiconductor substrate, wherein the first back-side contact electrically couples the shared read bit line to the first of the first source / drain regions. In some embodiments, the semiconductor memory device further includes: a second back-side contact extending through the semiconductor substrate, wherein the second back-side contact electrically couples the shared read bit line to the first of the second source / drain regions. In some embodiments, the shared read bit line has a thickness in the range of 300 nm to 500 nm. In some embodiments, the semiconductor memory device further includes: a front-side interconnect structure located above the first and second regions, the front-side interconnect structure including: a first write bit line for the first bit cell and a second write bit line for the second bit cell, located in a first metallization layer; and a common conductor located in a second metallization layer disposed above the first metallization layer, wherein the common conductor spans the first bit cell and the second bit cell, wherein a first common conductor of the common conductor is electrically connected to the first write bit line and the second write bit line. In some embodiments, each of the first and second bit cells includes seven transistors.

[0116] The foregoing outlines features of several embodiments to enable those skilled in the art to better understand various aspects of the embodiments of this disclosure. Those skilled in the art should understand that they can readily use the embodiments of this disclosure as a basis to design or modify other processes and structures for performing the same purposes and / or achieving the same advantages as the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of the embodiments of this disclosure, and that various changes, substitutions, and alterations can be made herein without departing from the spirit and scope of the embodiments of this disclosure.

Claims

1. A method for forming a semiconductor device including a first bit cell and a second bit cell adjacent to the first bit cell, the method comprising: A multilayer stack is deposited on a semiconductor substrate, the multilayer stack including a plurality of sacrificial layers alternating with a plurality of channel layers; A first fin is formed in a first region of the semiconductor substrate, wherein forming the first fin includes performing an etching process to define a first nanostructure by the plurality of sacrificial layers and a second nanostructure by the plurality of channel layers; A source / drain region is formed above the semiconductor substrate and on the opposite side of the first nanostructure; Replace the first nanostructure with a gate structure; An interlayer dielectric layer is formed above the source / drain region; Forming a source / drain contact extending through the interlayer dielectric layer to be electrically coupled to the first source / drain region of the source / drain region, wherein the conductivity of the source / drain contact is greater than the conductivity of the first source / drain region; and A front-side interconnect structure is formed above the interlayer dielectric layer and the gate structure. The front-side interconnect structure includes: a first write bit line for the first bit cell and a second write bit line for the second bit cell, located in the first metallization layer; and a common conductor located in a second metallization layer disposed above the first metallization layer, wherein the common conductor spans the first bit cell and the second bit cell, and wherein a first common conductor of the common conductor is electrically connected to the first write bit line and the second write bit line.

2. The method according to claim 1, wherein, The first region is an n-type region.

3. The method according to claim 1, wherein, Each of the first bit unit and the second bit unit includes seven transistors.

4. The method according to claim 1, further comprising: A back-side contact is formed extending through the semiconductor substrate, wherein the back-side contact is electrically coupled to a second source / drain region of the source / drain region.

5. The method according to claim 4, further comprising: A read bit line is formed on the back side of the semiconductor substrate, wherein the read bit line is electrically coupled to the second source / drain region through the back side contact.

6. The method according to claim 5, wherein, The read line is located at the boundary between the first bit unit and the second bit unit.

7. The method according to claim 5, wherein, The read lines have a thickness ranging from 300 nm to 500 nm.

8. A method for forming a memory device including a first bit cell and a second bit cell, the method comprising: A first sacrificial layer is deposited over a semiconductor substrate; A first channel layer is deposited above the first sacrificial layer; A second sacrificial layer is deposited above the first channel layer; A second channel layer is deposited above the second sacrificial layer; A first fin is formed in a first region of the semiconductor substrate for the first bit cell, and a second fin is formed in a second region of the semiconductor substrate for the second bit cell, wherein forming the first fin and the second fin includes performing an etching process to define a first nanostructure of the first fin and the second fin by the first sacrificial layer and the second sacrificial layer, and to define a second nanostructure of the first fin and the second fin by the first channel layer and the second channel layer; The first nanostructure of the first fin is replaced with a first gate structure, and the first nanostructure of the second fin is replaced with a second gate structure; A first source / drain region is formed in the first fin on the opposite side of the first gate structure; A second source / drain region is formed in the second fin on the opposite side of the second gate structure; A silicide region is formed above the top surface of the first one in the first source / drain region, wherein the silicide region has a higher conductivity than the first one in the first source / drain region; and A shared read bit line is formed on the back side of the semiconductor substrate. The shared read bit line is disposed at the boundary between the first bit cell and the second bit cell, wherein the shared read bit line is electrically coupled to the first bit cell in the first source / drain region and the first bit cell in the second source / drain region.

9. The method according to claim 8, further comprising: Prior to forming the shared read bit line, a first back-side contact is formed extending through the semiconductor substrate, wherein the first back-side contact electrically couples the shared read bit line to the first one in the first source / drain region.

10. A semiconductor memory device, comprising: A first gate structure is located above a first region of a semiconductor substrate, the first region being used for a first unit; A second gate structure is located above a second region of the semiconductor substrate, the second region being used for a second bit cell, wherein, when viewed in a top view, the first bit cell is adjacent to the second bit cell; The first source / drain region is located above the semiconductor substrate and on the opposite side of the first gate structure; The second source / drain region is located above the semiconductor substrate and on the opposite side of the second gate structure; The first active channel region is disposed between the first source / drain regions and above the semiconductor substrate; The second active channel region is disposed between the second source / drain region and above the semiconductor substrate, wherein the second gate structure includes a gate dielectric layer located above the second active channel region and a gate electrode located above the gate dielectric layer; A gate spacer extends along the sidewall of the second gate structure, wherein the dielectric constant of the gate dielectric layer is greater than the dielectric constant of the gate spacer; and A shared read bit line is located on the back side of the semiconductor substrate. The shared read bit line is positioned at the boundary between the first bit cell and the second bit cell, wherein the shared read bit line is electrically coupled to the first bit in the first source / drain region and the first bit in the second source / drain region.

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