Semiconductor device and method of manufacturing the same, power device

Abstract

The application provides a semiconductor device and a preparation method thereof and a power device. The method comprises the following steps: providing a substrate with a device region, the substrate having at least one groove extending along a second direction; forming a first mask layer on the substrate, the first mask layer comprising a plurality of first mask openings arranged at intervals along the second direction, the first mask openings extending along a first direction; the size of the plurality of first mask openings opposite to the device region in the second direction changes linearly; performing a doping process with the first mask layer as a mask layer to form initial body regions in the regions of the substrate exposed to each first mask opening; performing annealing and push-out processing on the plurality of initial body regions to diffuse and connect the plurality of initial body regions to form a body region; and the depth of the part of the body region opposite to the device region changes linearly. The application can simultaneously meet the requirements of high safety region and low on-resistance.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to a semiconductor device and its fabrication method, and a power device. Background Technology

[0002] Shielded Gate Trench FETs (SGT FETs) offer optimized high-voltage, high-speed, and low-loss performance for power MOSFETs and are widely used in high-efficiency, high-frequency power conversion applications. In these applications, power devices need to simultaneously possess high conduction performance and high reliability (wide safe operating area, SOA).

[0003] In related technologies, doped regions (boby) are usually formed in the substrate through doping processes (such as ion implantation). However, current doped regions cannot simultaneously meet the performance requirements of a high safe operating area (SOA) and low on-resistance. Summary of the Invention

[0004] In view of the above problems, embodiments of this application provide a semiconductor device and its fabrication method, as well as a power device, which can simultaneously meet the performance requirements of high safe operating area and low on-resistance.

[0005] To achieve the above objectives, the embodiments of this application provide the following technical solutions:

[0006] The first aspect of this application provides a method for fabricating a semiconductor device, comprising:

[0007] A substrate having a device region is provided, the substrate having at least one trench extending along a second direction, and the at least one trench having a trench structure;

[0008] A first mask layer is formed on the substrate, the first mask layer including a plurality of first mask openings spaced apart along a second direction, the first mask openings extending along a first direction; wherein, the size of the plurality of first mask openings opposite to the device region varies linearly in the second direction, and the first direction and the second direction intersect;

[0009] Using the first mask layer as a mask layer, a doping process is performed to form an initial body region in the area of ​​the substrate exposed in each of the first mask openings;

[0010] The initial body regions are annealed and pushed into a well, causing the initial body regions to diffuse and connect to form a body region; wherein the depth of the portion of the body region opposite to the device region changes linearly.

[0011] In one possible implementation, the linear change includes monotonic linear change and / or piecewise linear change.

[0012] In one possible implementation, the substrate further includes a terminal region adjacent to the device region.

[0013] In the direction from the terminal region to the device region, when the linear change is a monotonically linear change, the monotonically linear change includes linear increase or linear decrease; and in the direction from the terminal region to the device region, when the linear change is a piecewise linear change, the piecewise linear change is either linearly increase followed by linear decrease, or linearly decrease followed by linear increase.

[0014] In one possible implementation, the depth of the portion of the body region that is opposite to the terminal region is greater than the depth of the portion of the body region that is opposite to the device region.

[0015] In one possible implementation, the step of providing a substrate having device regions includes:

[0016] Provide a base;

[0017] The substrate is patterned to form at least one trench within the substrate, the at least one trench extending along a second direction;

[0018] A groove structure is formed within the groove.

[0019] In one possible implementation, the doping process includes at least one of ion implantation, thermal diffusion doping, and solid-state diffusion doping.

[0020] A second aspect of this application provides a semiconductor device comprising:

[0021] A substrate, the substrate including a device region, wherein at least one trench structure is disposed within the substrate, the at least one trench structure extending along a second direction;

[0022] A body region is disposed within the substrate and located on both sides of the corresponding trench structure in a first direction, wherein the depth of the portion of the body region opposite to the device region changes linearly, and the first direction and the second direction intersect.

[0023] In one possible implementation, the trench structure includes a shielding gate structure, an isolation layer, and a gate structure;

[0024] The shielding grid structure includes a shielding grid and a field oxide layer covering the bottom and sides of the shielding grid;

[0025] The isolation layer is disposed on the bottom surface of the shielding grid structure opposite to the substrate;

[0026] The gate structure is disposed on the isolation layer, and the gate structure includes a gate and a gate dielectric layer covering the side of the gate.

[0027] In one possible implementation, the thickness of the field oxide layer is greater than the thickness of the gate dielectric layer.

[0028] A third aspect of this application provides a power device that includes the semiconductor device provided in the second aspect described above.

[0029] In the semiconductor device and its fabrication method and power device provided in this application embodiment, the first mask layer is improved so that it includes a plurality of first mask openings spaced apart along a second direction, and the dimensions of these first mask openings opposite to the device region change linearly in the second direction. Subsequently, a doping process is performed using this first mask layer as a mask, causing the substrate to form multiple initial body regions in the exposed areas of each opening. These initial body regions are then annealed and pushed-in to diffuse and connect them to form body regions, and the depth of the portion of the body region opposite to the device region changes linearly. In this way, by orderly adjusting the size of the first mask openings and coordinating with subsequent pushing-in, a body region morphology with varying characteristics along the trench direction can be obtained within the same device region. This coordinates the relationship between conduction loss, operating boundary, and temperature stability, enabling the semiconductor device to have both a high-depth body region capable of achieving a high-safety region and a low-depth body region capable of achieving low on-resistance.

[0030] Furthermore, high-depth bulk regions can significantly optimize the electric field distribution of semiconductor devices, improve the avalanche withstand capability, reverse withstand voltage, and thermal load capacity of semiconductor devices, and widen the voltage and current boundaries of the safe operating area (SOA) of semiconductor devices. Low-depth bulk regions can also reduce the transport path of charge carriers in the bulk region, reduce the on-resistance of semiconductor devices, reduce energy loss during current conduction, and improve the power conversion efficiency of semiconductor devices, thus meeting the dual requirements of high safe operating area and low on-resistance of semiconductor devices.

[0031] In addition to the technical problems solved by the embodiments of this application, the technical features constituting the technical solutions, and the beneficial effects brought about by the technical features of these technical solutions described above, other technical problems that the semiconductor devices and their preparation methods and power devices provided by the embodiments of this application can solve, other technical features included in the technical solutions, and the beneficial effects brought about by these technical features will be further explained in detail in the specific embodiments. Attached Figure Description

[0032] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.

[0033] Figure 1 A process flow diagram of the method for fabricating a semiconductor device provided in the embodiments of this application;

[0034] Figure 2 A schematic diagram of a substrate provided in the method for fabricating a semiconductor device according to an embodiment of this application;

[0035] Figure 3 A top view of the semiconductor device fabrication method provided in this application after the formation of the second mask layer;

[0036] Figure 4 For along Figure 3 A cross-sectional view along the AA direction;

[0037] Figure 5 This is a schematic diagram illustrating the formation of a trench structure in a method for fabricating a semiconductor device according to an embodiment of this application.

[0038] Figure 6 A top view of the semiconductor device fabrication method provided in this application after the formation of the first mask layer;

[0039] Figure 7 For along Figure 6 Cross-sectional view along the BB direction;

[0040] Figure 8 This is a schematic diagram of the semiconductor device fabrication method provided in the embodiments of this application after the formation of the bulk region;

[0041] Figure 9 For along Figure 6 A cross-sectional view along the CC direction.

[0042] Figure label:

[0043] 100: Substrate; 110: Substrate; 120: Epitaxial layer; 130: Trench; 140: Initial body region; 150: Body region; 160: Termination region; 170: Device region;

[0044] 200: Trench structure; 210: Shielding gate structure; 211: Shielding gate; 212: Field oxide layer; 220: Isolation layer; 230: Gate structure; 231: Gate; 232: Gate dielectric layer;

[0045] 300: Second mask layer; 310: Second mask opening;

[0046] 400: First mask layer; 410: First mask opening.

[0047] The accompanying drawings illustrate specific embodiments of this application, which will be described in more detail below. These drawings and descriptions are not intended to limit the scope of the concept in any way, but rather to illustrate the concept of this application to those skilled in the art through reference to particular embodiments. Detailed Implementation

[0048] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this application as detailed in the appended claims.

[0049] As described in the background section, the doped regions in related technologies cannot simultaneously meet the performance requirements of a high safe operating area (SOA) and low on-resistance. The main reason for these problems is that in these technologies, the doped regions are mostly formed using a single ion implantation followed by annealing and push-in. This results in a relatively uniform doping concentration and depth in the formed doped regions. To enhance stability under high voltage and high current conditions, it is necessary to increase the implantation dose or the push-in depth. While this can improve the device's withstand capability to some extent, it also leads to enhanced channel control, restricted carrier transport, and increased conduction losses, ultimately increasing the on-resistance of the semiconductor device. Conversely, to reduce the on-resistance of the semiconductor device, shortening the channel may weaken the thermal stability and operating boundary of the semiconductor device under high temperature overload or transient stress, thus compressing the safe operating area. Therefore, the fabrication methods of these technologies struggle to simultaneously achieve both low on-resistance and a wide safe operating area within the same device.

[0050] To address the aforementioned technical problems, this application provides a semiconductor device and its fabrication method. The semiconductor device improves the first mask layer by including multiple first mask openings spaced apart along a second direction, with the dimensions of these openings relative to the device region linearly varying in the second direction. Subsequently, a doping process is performed using this first mask layer as a mask, forming multiple initial body regions in the exposed areas of each opening on the substrate. These initial body regions are then annealed and pushed-in to diffuse and connect, forming body regions with a linearly varying depth relative to the device region. In this way, by orderly adjusting the dimensions of the first mask openings and coordinating with subsequent pushing-in, a body region morphology with varying characteristics along the trench direction can be obtained within the same device region. This coordinates the relationship between conduction loss, operating boundary, and temperature stability, enabling the semiconductor device to achieve both high-depth body regions with high safety zones and low-depth body regions with low on-resistance.

[0051] Furthermore, high-depth bulk regions can significantly optimize the electric field distribution of semiconductor devices, improve the avalanche withstand capability, reverse withstand voltage, and thermal load capacity of semiconductor devices, and widen the voltage and current boundaries of the safe operating area (SOA) of semiconductor devices. Low-depth bulk regions can also reduce the transport path of charge carriers in the bulk region, reduce the on-resistance of semiconductor devices, reduce energy loss during current conduction, and improve the power conversion efficiency of semiconductor devices, thus meeting the dual requirements of high safe operating area and low on-resistance of semiconductor devices.

[0052] To make the above-mentioned objectives, features, and advantages of the embodiments of this application more apparent and understandable, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0053] This application provides a method for fabricating a semiconductor device, comprising the following steps:

[0054] Step S100: Provide a substrate having a device region, the substrate having at least one trench, the at least one trench extending along a second direction, and the at least one trench having a trench structure.

[0055] Please refer to Figure 1The substrate 100 serves as a support component for the semiconductor device, supporting other components disposed thereon. The substrate 100 can be made of a semiconductor material, which can be one or more of silicon, germanium, silicon-germanium compounds, and silicon-carbide compounds. It should be noted that the substrate 100 can be a single-layer structure or a multilayer structure. For example, the substrate 100 includes a substrate 110 and an epitaxial layer 120 disposed on the substrate 110. The conductivity type of the epitaxial layer 120 can be N-type or P-type. The following embodiments will be described in detail using an N-type conductivity type epitaxial layer as an example.

[0056] The substrate 100 has at least one trench 130 extending along a second direction, and the at least one trench 130 has a trench structure 200. The step of forming at least one trench 130 and at least one trench structure 200 within the substrate 100 includes the following steps:

[0057] Please refer to Figure 2 Provides a base of 100.

[0058] Please refer to Figure 3 and Figure 4 A patterned substrate 100 is formed, and at least one trench 130 is formed within the substrate, the at least one trench 130 extending along a second direction. Exemplarily, a second mask layer 300 and a photoresist layer (not shown) stacked on the substrate 100 can be formed, and the photoresist layer can be patterned using a photolithography process. Then, using the photoresist layer as a mask, the second mask layer 300 is patterned to form at least one second mask opening 310 in the second mask layer 300, the at least one second mask opening 310 extending along the second direction. It should be noted that when there are multiple second mask openings 310, the multiple second mask openings 310 are spaced apart along a first direction, and the first direction and the second direction intersect. For ease of detailed definition of the first direction and the second direction, as follows... Figure 3 As shown, the first direction is Figure 3 The X direction in the middle, the second direction is Figure 3 in the Y direction.

[0059] Continue to refer to Figure 4 Using the second mask layer 300 as a mask, an etching process is performed to remove a portion of the thickness of the substrate 100 exposed within the second mask opening 310, so as to form at least one trench 130 within the substrate 100.

[0060] Please refer to Figure 5After at least one trench 130 is formed, a trench structure 200 can be formed within the at least one trench 130. The trench structure 200 includes a shielding gate structure 210, an isolation layer 220, and a gate structure 230. The shielding gate structure 210 includes a shielding gate 211 and a field oxide layer 212 covering the bottom and side surfaces of the shielding gate 211. The isolation layer 220 is disposed on the side of the shielding gate structure 210 facing away from the bottom surface of the substrate 100. The gate structure 230 is disposed on the isolation layer 220, and the gate structure 230 includes a gate 231 and a gate dielectric layer 232 covering the side surfaces of the gate 231.

[0061] For example, a dielectric layer is formed at least on the inner wall of the trench. The dielectric layer may be made of silicon oxide. Thus, the dielectric layer can be formed at least on the inner wall of the trench by a deposition process or a thermal oxidation process.

[0062] Subsequently, a conductive layer can be formed within the area enclosed by the dielectric layer through a deposition process, and the conductive layer can be etched back through an etching process to remove a portion of the conductive layer, so that the remaining conductive layer constitutes the shielding gate 211. The dielectric layer covering the sides and bottom of the shielding gate 211 constitutes the field oxide layer 212.

[0063] Subsequently, an isolation layer 220 can be formed on the conductive layer using a deposition process, and the dielectric layer above the isolation layer 220 can be etched back. It should be noted that in this step, a portion of the dielectric layer thickness on the sidewalls of the trench can be removed, so that the remaining dielectric layer constitutes the gate dielectric layer 232. Alternatively, all the dielectric layers above the isolation layer can be etched back, allowing the gate dielectric layer 232 to be formed on the exposed inner wall of the trench using a deposition process. In this case, the material of the gate dielectric layer 232 can be different from the material of the dielectric layer. For example, the gate dielectric layer 232 can have a high dielectric constant. For instance, the material of the gate dielectric layer includes hafnium silicon oxide (HfSiO2), aluminum oxide (Al2O3), hafnium oxide (HfO2), hafnium oxynitride (HfON), zirconium oxide (ZrO2), tantalum oxide (Ta2O5), titanium oxide (TiO2), or strontium titanium oxide (SrTiO3). This effectively prevents electrons from directly tunneling through the gate dielectric layer and generating gate leakage current, which is beneficial for reducing the thickness of the gate dielectric layer, meeting the requirements for reducing process size, and providing a guarantee for the development of semiconductor devices towards integration.

[0064] To form the gate dielectric layer 232, a deposition process can be performed to form the gate 231 within the area enclosed by the gate dielectric layer 232 and the isolation layer 220. The gate 231 and the gate dielectric layer 232 constitute the gate structure 230. In this embodiment, the material of the gate 231 and the material of the shielding gate 211 can be the same. For example, the materials of the gate 231 and the shielding gate 211 are polysilicon.

[0065] Step S200: A first mask layer is formed on the substrate. The first mask layer includes a plurality of first mask openings spaced apart along a second direction and extending along a first direction. The dimensions of the plurality of first mask openings opposite to the device region change linearly in the second direction.

[0066] Please refer to Figure 6 For example, a first mask layer 400 can be formed on a substrate 100 by a deposition process, and the first mask layer 400 can be patterned to form a first mask opening 410 within the first mask layer 400. In some embodiments, a photoresist layer of a certain thickness can be coated on the first mask layer 400 by a coating process, and a photoresist pattern can be formed after exposure and development. Using the photoresist layer as a mask, the exposed first mask layer 400 is removed by an etching process, and after the photoresist is stripped off, the first mask layer 400 covered by the photoresist pattern is left, so as to form a plurality of first mask openings 410 within the first mask layer 400. The plurality of first mask openings 410 are arranged at intervals along a second direction, and each first mask opening 410 extends along a first direction, so that the first mask opening 410 is a strip structure. The first mask opening 410 can span a plurality of trench structures 200 and expose the corresponding areas of the plurality of trench structures 200.

[0067] The dimensions of the plurality of first mask openings 410 opposite to the device area vary linearly in the second direction, thereby allowing adjustment of the area size of the substrate 100 exposed by each first mask opening 410.

[0068] Step S300: Using the first mask layer as the mask layer, perform a doping process to form an initial bulk region in the area where the substrate is exposed at each opening of the first mask, as shown in the following structure. Figure 7 As shown.

[0069] The doping process can be any one of ion implantation, thermal diffusion doping, or solid-state diffusion doping, or a combination of two or more of them, to meet the requirements of different production lines for implantation accuracy, thermal budget, and lateral diffusion capability.

[0070] In one possible embodiment, if an ion implantation process is used, P-type dopant ions, such as boron ions, BF2 ions, or other acceptor ions capable of forming P-type body regions, can be selected. This, combined with a tilted implantation method, allows the dopant to form a more uniform lateral coverage in the region adjacent to the trench. If a thermal diffusion doping process is used, the dopant source can diffuse towards the substrate surface and near-surface layer at high temperatures, achieving the formation of a shallow initial body region. If a solid-state diffusion doping process is used, a solid-state doped film can be used to supply dopant atoms to the substrate during subsequent heat treatment, enhancing process compatibility.

[0071] It should be noted that when the doping process includes two of the above processes, the execution time of each doping process can be set freely.

[0072] Because the dimensions of the first mask openings differ in the second direction, the dopant flux and distribution boundary of the exposed substrate will vary accordingly. Therefore, the initial bulk regions formed by each opening exhibit differentiated doping concentrations and distribution boundaries. This difference results in different diffusion distances and connection timings for different initial bulk regions during subsequent annealing and push-in, thus providing preconditions for forming a continuous bulk region with linearly varying depth.

[0073] Step S400: Annealing and push-well processing is performed on multiple initial body regions to diffuse and connect them to form a body region; wherein the depth of the part of the body region opposite to the device region changes linearly.

[0074] Please refer to Figure 8 Annealing and push-pull processing can be carried out under controlled temperature and time conditions. Specifically, rapid thermal annealing, furnace tube annealing, or segmented heating annealing can be used to reduce lattice damage while promoting further diffusion of doped atoms into the substrate and laterally.

[0075] In this way, by controlling the annealing temperature, time, and heating / cooling rates, the spacing between the initial body regions can be gradually filled, eventually forming interconnected body regions 150 within the device region. Since each initial body region 150 already has a difference determined by the mask opening size during the formation stage, the body regions 150 after push-in exhibit corresponding linear depth variation characteristics in the portion opposite to the device region, thereby enabling a gradient configuration of the channel length at different locations near the trench.

[0076] This application embodiment, through the technical concept of orderly adjusting the mask opening size along the second direction and coordinating with subsequent push-well connection, can obtain a volume region with varying characteristics along the trench direction within the same device region, coordinating the relationship between conduction loss, operating boundary and temperature stability, so that the semiconductor device has a high-depth volume region that can achieve a high-safety area, and also a low-depth volume region that can achieve low on-resistance.

[0077] Furthermore, high-depth bulk regions can significantly optimize the electric field distribution of semiconductor devices, improve their avalanche withstand capability, reverse withstand voltage, and thermal carrying capacity, and widen the voltage and current boundaries of the safe operating area (SOA) of semiconductor devices. This prevents semiconductor devices from failing under high voltage and high current conditions, such as breakdown and thermal runaway, and ensures the reliability of semiconductor devices under extreme operating conditions. Alternatively, low-depth bulk regions can reduce the transport path of charge carriers in the bulk region, lower the on-resistance of semiconductor devices, reduce energy loss during current conduction, and improve the power conversion efficiency of semiconductor devices, thus meeting the dual requirements of high safe operating area and low on-resistance of semiconductor devices.

[0078] In one possible implementation, the linear change includes a monotonic linear change and / or a piecewise linear change. In some embodiments, the linear change includes a monotonic change. In other embodiments, the linear change includes a piecewise linear change. In still other embodiments, the linear change includes both a monotonic change and a piecewise linear change.

[0079] The term "monotonically linear change" refers to the continuous increase or decrease of the size of the second mask opening along the second direction or along the vertical direction at a fixed slope, thereby creating a stable gradient difference in the diffusion depth of the exposure window or volume region corresponding to adjacent second mask openings in the second direction. The term "piecewise linear change" refers to different segments along the second direction maintaining linear increases or decreases respectively, with the slope switching at the segment boundaries, ensuring that the size distribution or depth distribution maintains a controllable linear characteristic overall.

[0080] Thus, by optimizing the first mask layer, the size of the ion implantation opening can be controlled solely by adjusting the first mask opening of the first mask layer 400. This allows for the formation of a bulk region 150 with varying doping concentration and junction depth along the trench direction after annealing, resulting in a gradually changing channel length. A longer channel region can reduce the current gain and zero temperature coefficient point of the semiconductor device, while a shorter channel region ensures a lower on-resistance. This effectively expands the safe operating area, reduces the risk of thermal failure of the semiconductor device, and does not sacrifice the conductivity of the semiconductor device.

[0081] To facilitate a detailed description of the variations in the body region of the semiconductor device as defined in the embodiments of this application, a terminal region may be introduced for further definition.

[0082] In some embodiments, the substrate 100 further includes a terminal region 160 adjacent to the device region 170. Exemplarily, in a second direction, the terminal region 160 is located on one side of the device region 170. The terminal region 160 is an edge functional region disposed around the device region 170, used to cooperate with the device region 170 to define the electric field distribution and the bulk region extension boundary.

[0083] This allows us to use the direction from the terminal area 160 to the device area 170 as a reference. In the direction from the terminal area 160 to the device area 170, when the linear change is a monotonically linear change, the monotonically linear change includes either linear increase or linear decrease; and, in the direction from the terminal area 160 to the device area 170, when the linear change is a piecewise linear change, the piecewise linear change is either linearly increase followed by linear decrease, or linearly decrease followed by linear increase.

[0084] Along the direction from the termination region 160 to the device region 170, the depth of the body region 150 is designed to vary monotonically or piecewise linearly, ensuring that the depth of the body region 150 near the termination region 160 is greater than the depth of the body region 150 far from the termination region 160. This higher depth of the body region 150 near the termination region 160 significantly optimizes the edge electric field distribution of the semiconductor device, enhances the electric field mitigation effect at the interface between the termination region 160 and the device region 170, further improves the avalanche withstand capability, reverse withstand voltage, and thermal conductivity of the semiconductor device, effectively suppresses breakdown failure caused by the concentration of the edge electric field in the termination region 160, widens the voltage and current boundaries of the safe operating area (SOA) of the semiconductor device, and ensures the reliability of the semiconductor device under extreme high-voltage and high-current conditions.

[0085] In one possible implementation, the depth of the portion of the body region 150 opposite to the terminal region 160 is greater than the depth of the portion of the body region 150 opposite to the device region 170. This gives the body region 150 on the terminal region 160 side stronger electric field buffering and edge suppression capabilities, which can improve the stability of the semiconductor device under high voltage and high temperature conditions, thereby improving the performance of the semiconductor device.

[0086] Please combine Figure 6 , Figure 8 and Figure 9 This application provides a semiconductor device, which is prepared by the fabrication method described in any of the above embodiments. The semiconductor device includes:

[0087] A substrate 100 includes a device region 170. At least one trench structure 200 is disposed within the substrate 100, extending along a second direction. When there are multiple trench structures 200, they are arranged at intervals along a first direction. Each trench structure 200 includes a shielding gate structure 210, an isolation layer 220, and a gate structure 230. The shielding gate structure 210 includes a shielding gate 211 and a field oxide layer 212 covering the bottom and side surfaces of the shielding gate 211. The isolation layer 220 is disposed on the side of the shielding gate structure 210 facing away from the bottom surface of the substrate 100. The gate structure 230 is disposed on the isolation layer 220 and includes a gate 231 and a gate dielectric layer 232 covering the side surfaces of the gate 231. It should be noted that the specific material of the trench structure 200 can be referred to in the above embodiments, and will not be elaborated further in this embodiment.

[0088] A body region 150 is disposed within the base 100 and located on both sides of the corresponding trench structure 200 in the first direction, where the first and second directions intersect. It should be understood that when there are multiple trench structures 200, the body region 150 is shared between adjacent trench structures 200.

[0089] In this design, the depth of the portion of the body region 150 relative to the device region 170 varies linearly. This allows for a body region 150 with varying characteristics along the trench direction within the same device region 170, coordinating the relationship between conduction loss, operating boundary, and temperature stability. This enables the semiconductor device to possess both a high-depth body region capable of achieving a high safety zone and a low-depth body region capable of achieving low on-resistance. Furthermore, a high-depth body region can significantly optimize the device's electric field distribution, improving avalanche withstand capability, reverse withstand voltage, and thermal carrying capacity. It also widens the voltage and current boundaries of the device's safe operating area (SOA), preventing breakdown and thermal runaway failures under high voltage and high current conditions, thus ensuring the reliability of the semiconductor device under extreme operating conditions. Conversely, a low-depth body region can reduce the carrier transport path within the body region, lowering the device's on-resistance, reducing energy loss during current conduction, and improving the device's power conversion efficiency, thus balancing the dual requirements of a high safe operating area and low on-resistance in semiconductor devices.

[0090] In one possible implementation, the thickness of the field oxide layer 212 is greater than the thickness of the gate dielectric layer 232. This allows for a thinner gate dielectric layer 232, which enhances the gate 231's control over the channel, reduces the threshold voltage, and decreases the channel resistance, thereby improving the device's conduction characteristics. Conversely, a thicker field oxide layer 212 effectively alleviates electric field concentration at the gate corner, improving the breakdown voltage and long-term reliability of the semiconductor device.

[0091] This application also provides a power device, including the semiconductor device described in any of the above embodiments. The power device can be applied to discrete devices, AC-DC converters, or temperature sensors.

[0092] It should be noted that the beneficial effects of the power device provided in this application embodiment are the same as the beneficial effects of the semiconductor device provided in the above embodiment, and will not be elaborated further in this embodiment.

[0093] The various embodiments or implementation methods described in this specification are presented in a progressive manner. Each embodiment focuses on the differences from other embodiments, and the same or similar parts between the embodiments can be referred to each other.

[0094] It should be noted that the terms "one embodiment," "embodiment," "exemplary embodiment," "some embodiments," etc., mentioned in the specification indicate that the described embodiments may include specific features, structures, or characteristics, but not every embodiment necessarily includes that specific feature, structure, or characteristic. Furthermore, such phrases do not necessarily refer to the same embodiment. Moreover, when a specific feature, structure, or characteristic is described in connection with an embodiment, implementing such a feature, structure, or characteristic in conjunction with other embodiments, whether explicitly described or not, is within the knowledge scope of those skilled in the art.

[0095] Generally speaking, terms should be understood at least in part by their use in context. For example, the term "one or more" as used in the text can be used, at least in part, to describe any feature, structure, or characteristic of the meaning of the singular, or a combination of features, structures, or characteristics of the meaning of the plural. Similarly, at least in part, it depends on the context.

[0096] It should be readily understood that the terms “on,” “above,” and “on top of” in this application should be interpreted in the broadest possible sense, such that “on” means not only “directly on something” but also “on something” with an intermediate feature or layer therebetween, and that “above” or “on top of” means not only “on something” but also “on something” without an intermediate feature or layer therebetween (i.e., directly on something).

[0097] Furthermore, for ease of explanation, spatially relative terms such as "below," "below," "under," "above," and "above" may be used to describe the relationship of one element or feature relative to other elements or features as shown in the figures. Spatially relative terms are intended to encompass different orientations of the device in use or operation other than those shown in the figures. The device may have other orientations (rotated 90° or in other orientations), and the spatially relative descriptive terms used herein may be interpreted accordingly.

[0098] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. A method for fabricating a semiconductor device, characterized in that, include: A substrate having a device region is provided, the substrate having at least one trench extending along a second direction, and the at least one trench having a trench structure; A first mask layer is formed on the substrate, the first mask layer including a plurality of first mask openings spaced apart along a second direction, the first mask openings extending along a first direction; wherein, the size of the plurality of first mask openings opposite to the device region varies linearly in the second direction, and the first direction and the second direction intersect; Using the first mask layer as a mask layer, a doping process is performed to form an initial body region in the area of ​​the substrate exposed in each of the first mask openings; The initial body regions are annealed and pushed into a well, causing the initial body regions to diffuse and connect to form a body region; wherein the depth of the portion of the body region opposite to the device region changes linearly.

2. The method for fabricating a semiconductor device according to claim 1, characterized in that, The linear changes include monotonic linear changes and / or piecewise linear changes.

3. The method for fabricating a semiconductor device according to claim 2, characterized in that, The substrate also includes a terminal region adjacent to the device region. In the direction from the terminal region to the device region, when the linear change is a monotonically linear change, the monotonically linear change includes linear increase or linear decrease; and in the direction from the terminal region to the device region, when the linear change is a piecewise linear change, the piecewise linear change is either linearly increase followed by linear decrease, or linearly decrease followed by linear increase.

4. The method for fabricating a semiconductor device according to claim 3, characterized in that, The depth of the portion of the body region that is opposite to the terminal region is greater than the depth of the portion of the body region that is opposite to the device region.

5. The method for fabricating a semiconductor device according to any one of claims 1-4, characterized in that, The steps of providing a substrate with device regions include: Provide a base; The substrate is patterned to form at least one trench within the substrate, the at least one trench extending along a second direction; A groove structure is formed within the groove.

6. The method for fabricating a semiconductor device according to claim 5, characterized in that, The doping process includes at least one of ion implantation, thermal diffusion doping, and solid-state diffusion doping.

7. A semiconductor device, characterized in that, include: A substrate, the substrate including a device region, wherein at least one trench structure is disposed within the substrate, the at least one trench structure extending along a second direction; A body region is disposed within the substrate and located on both sides of the corresponding trench structure in a first direction, wherein the depth of the portion of the body region opposite to the device region changes linearly, and the first direction and the second direction intersect.

8. The semiconductor device according to claim 7, characterized in that, The trench structure includes a shielding gate structure, an isolation layer, and a gate structure; The shielding grid structure includes a shielding grid and a field oxide layer covering the bottom and sides of the shielding grid; The isolation layer is disposed on the bottom surface of the shielding grid structure opposite to the substrate; The gate structure is disposed on the isolation layer, and the gate structure includes a gate and a gate dielectric layer covering the side of the gate.

9. The semiconductor device according to claim 8, characterized in that, The thickness of the field oxide layer is greater than the thickness of the gate dielectric layer.

10. A power device, characterized in that, Includes the semiconductor device according to any one of claims 7-9.

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