Semiconductor structure and its preparation method

Abstract

This invention relates to a semiconductor structure and its fabrication method, comprising: a substrate having a first conductivity type; the thickness of the substrate being less than the minority carrier diffusion length of the substrate; a trigger electrode structure located on a first side of the substrate in a first direction; at least one source electrode structure located on a second side of the substrate in the first direction; and at least one drain electrode structure located on a second side of the substrate in the first direction, and spaced apart from the source electrode structure. The semiconductor structure of this application has good surge protection capability.

Description

Technical Field

[0001] This application relates to the field of integrated circuit technology, and in particular to a semiconductor structure and its fabrication method. Background Technology

[0002] Power devices in related technologies typically include three types: bipolar junction transistors (BJTs), silicon controlled rectifiers (SCRs), and metal-oxide-semiconductor field-effect transistors (MOSFETs).

[0003] However, the power devices in related technologies suffer from insufficient surge protection. Summary of the Invention

[0004] Therefore, it is necessary to provide a semiconductor structure with good surge resistance and its fabrication method.

[0005] In a first aspect, this application provides a semiconductor structure, comprising:

[0006] A substrate having a first conductivity type; the thickness of the substrate is less than the minority carrier diffusion length of the substrate;

[0007] A trigger electrode structure is located on a first side of the substrate in a first direction;

[0008] At least one source structure is located on the second side of the substrate in the first direction;

[0009] At least one drain structure is located on the second side of the substrate in the first direction and is spaced apart from the source structure.

[0010] In some embodiments, the trigger electrode structure includes:

[0011] A first doped region is located within a substrate and on a first side of the substrate in a first direction; the first doped region has a second conductivity type; the second conductivity type is opposite to the first conductivity type;

[0012] The first conductive layer is located on the side of the first doped region away from the substrate.

[0013] In some embodiments, the first doped region includes a plurality of first sub-doped regions spaced apart.

[0014] In some embodiments, the source structure includes:

[0015] The second doped region is located within the substrate and on a second side of the substrate in a first direction; the second doped region has a second conductivity type.

[0016] The second conductive layer is located on the side of the second doped region away from the substrate and is electrically connected to the second doped region;

[0017] In this embodiment, at least one of the second conductive layers of the source structure is in direct contact with the substrate.

[0018] In some embodiments, the drain structure includes:

[0019] A third doped region is located within the substrate and on a second side of the substrate in a first direction; the third doped region has a second conductivity type.

[0020] The third conductive layer is located on the side of the third doped region away from the substrate and is electrically connected to the third doped region; the orthographic projection of the third conductive layer on the second side surface of the substrate is located within the orthographic projection of the third doped region on the second side surface of the substrate.

[0021] In some embodiments, the spacing between the adjacent second doped region and the third doped region in the second direction is 1 μm to 10 μm; the second direction is perpendicular to the first direction.

[0022] In some embodiments, the semiconductor structure further includes:

[0023] A passivation layer is located on the second side of the substrate. The passivation layer has a first opening and a second opening. The first opening exposes the second doped region, and the second opening exposes the third doped region. The second conductive layer is located within the first opening, and the third conductive layer is located within the second opening.

[0024] Secondly, this application provides a method for fabricating a semiconductor structure, the method comprising:

[0025] A substrate is provided having a first conductivity type, and the thickness of the substrate is less than the minority carrier diffusion length of the substrate;

[0026] A trigger electrode structure is formed on a first side of the substrate in a first direction;

[0027] At least one source structure and at least one drain structure are formed on the second side of the substrate in the first direction; the drain structure is spaced apart from the source structure.

[0028] In some embodiments, forming a trigger electrode structure on a first side of the substrate in a first direction includes:

[0029] A first doped region is formed on a first side in a first direction within the substrate; wherein the first doped region has a second conductivity type, the second conductivity type being different from the first conductivity type;

[0030] A first conductive layer is formed on the side of the first doped region away from the substrate.

[0031] In some embodiments, forming at least one source structure and at least one drain structure on the second side of the substrate in the first direction includes:

[0032] A second doped region and a third doped region are formed on a second side in a first direction within the substrate; both the second doped region and the third doped region have a second conductivity type, and the second doped region and the third doped region are spaced apart in a second direction; the second direction is perpendicular to the first direction;

[0033] A second conductive layer and a third conductive layer are formed on a second side in a first direction within the substrate;

[0034] Wherein, the second conductive layer is electrically connected to the second doped region, and the third conductive layer is electrically connected to the third doped region; at least one of the second conductive layers of the source structure is in direct contact with the substrate; the orthographic projection of the third conductive layer on the second side surface of the substrate is located within the orthographic projection of the third doped region on the second side surface of the substrate.

[0035] The above-described semiconductor structure and its fabrication method have at least / may have the following beneficial effects:

[0036] The semiconductor structure of this application includes a substrate, a trigger structure, a source structure, and a drain structure. The substrate has a first conductivity type, while the trigger, source, and drain structures all have a second conductivity type. When no trigger voltage is applied to the trigger structure, no minority carriers are injected into the substrate. The source and drain structures are isolated by the high-resistivity substrate, and no current flows, thus the semiconductor structure is off. When a trigger voltage is applied to the trigger structure, it can inject a large number of minority carriers into the substrate. Because the substrate thickness is less than the minority carrier diffusion length, the injected minority carriers can pass through the substrate perpendicularly with almost no recombination, reaching the second side surface of the substrate. These minority carriers then accumulate in large quantities at the interface between the source and drain structures on the second side surface of the substrate, forming a high-concentration electron accumulation layer (conductive channel), connecting the source and drain structures, thereby turning on the semiconductor structure. As can be seen, in the semiconductor structure of this application, the trigger electrode structure-substrate-source drain structure constitutes a complete bipolar TVS (Transient Voltage Suppressor) structure. When a surge overvoltage occurs at the source drain or trigger electrode, the TVS structure will undergo avalanche breakdown in advance, rapidly dissipating the surge energy in the form of current. Therefore, the semiconductor structure of this application has good surge resistance. Attached Figure Description

[0037] To more clearly illustrate the technical solutions in the embodiments of this application or the conventional technology, the drawings used in the description of the embodiments or the conventional technology will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0038] Figure 1 This is a flowchart of a method for fabricating a semiconductor structure provided in one embodiment;

[0039] Figure 2 This is a schematic cross-sectional view of the structure obtained in step S101 of the semiconductor structure fabrication method provided in one embodiment;

[0040] Figure 3 This is a schematic cross-sectional view of the structure obtained in step S102 of the semiconductor structure fabrication method provided in one embodiment;

[0041] Figure 4 This is a schematic cross-sectional view of the structure obtained in step S103 of the semiconductor structure fabrication method provided in one embodiment.

[0042] Figure 5 This is a flowchart of step S102 provided in one embodiment;

[0043] Figure 6 This is a flowchart of step S103 provided in one embodiment;

[0044] Figure 7 This is a schematic cross-sectional view of a semiconductor structure in one embodiment;

[0045] Figure 8 This is a schematic diagram of the cross-sectional structure of the semiconductor structure in another embodiment;

[0046] Figure 9 This is a schematic cross-sectional view of the semiconductor structure in another embodiment;

[0047] Figure 10 This is a schematic diagram of the equivalent topology of a semiconductor structure in one embodiment.

[0048] Explanation of reference numerals in the attached figures: 10-substrate, 20-trigger electrode structure, 21-first doped region, 211-first sub-doped region, 22-first conductive layer, 30-protective layer, 40-source structure, 41-second doped region, 42-second conductive layer, 50-drain structure, 51-third doped region, 52-third conductive layer, 60-passivation layer, 70-fourth doped region. Detailed Implementation

[0049] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings, which illustrate embodiments of the present application. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that the disclosure of this application will be more thorough and complete.

[0050] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the specification of this application is for the purpose of describing particular embodiments only and is not intended to be limiting of this application.

[0051] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, parts, regions, layers, doping types, and / or portions, these elements, parts, regions, layers, doping types, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, part, region, layer, doping type, or portion from another element, part, region, layer, doping type, or portion. Therefore, without departing from the teachings of this invention, the first element, component, region, layer, doping type, or portion discussed below may be represented as a second element, component, region, layer, or portion; for example, the first doping type may be referred to as the second doping type, and similarly, the second doping type may be referred to as the first doping type; the first doping type and the second doping type are different doping types, for example, the first doping type may be P-type and the second doping type may be N-type, or the first doping type may be N-type and the second doping type may be P-type.

[0052] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, the element or feature described as “below,” “under,” or “below” will be oriented “above” the other element or feature. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. Furthermore, the device may also include other orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptive terms used herein will be interpreted accordingly.

[0053] When used herein, the singular forms of “a,” “an,” and “the” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising / including” or “having,” etc., specify the presence of the stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not preclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. Meanwhile, in this specification, the term “and / or” includes any and all combinations of the associated listed items.

[0054] Embodiments of the invention are described herein with reference to cross-sectional views illustrating ideal embodiments (and intermediate structures) of the invention, thus allowing for variations in the illustrated shape due to, for example, manufacturing techniques and / or tolerances. Therefore, embodiments of the invention should not be limited to the specific shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing techniques. For instance, implantation regions shown as rectangular typically have rounded or curved features at their edges and / or implantation concentration gradients, rather than a binary change from implantation regions to non-implantation regions. Similarly, the buried regions formed by implantation can result in some implantation in the region between the buried region and the surface traversed during implantation. Therefore, the regions shown in the figures are substantially schematic, and their shapes do not represent the actual shapes of regions of the device and do not limit the scope of the invention.

[0055] Power devices in related technologies typically include three types: bipolar junction transistors (BJTs), silicon controlled rectifiers (SCRs), and metal-oxide-semiconductor field-effect transistors (MOSFETs).

[0056] A transistor, also known as a bipolar junction transistor (BJT), is a three-terminal semiconductor device consisting of an emitter region, a base region, and a collector region forming two PN junctions. Based on the arrangement of these PN junctions, it is classified into two types: NPN and PNP. The core principle of this device is to achieve amplification by controlling a larger change in the collector current through a small change in the base current. The internal doping concentration of the device varies significantly: the emitter region is highly doped, the base region is the thinnest and least doped, and the collector region has the largest area and is moderately doped.

[0057] A thyristor (SCR) is a high-power electrical component. It boasts advantages such as small size, high efficiency, and long lifespan. In automatic control systems, it serves as a high-power driver, enabling the control of high-power equipment with low-power controls. It is widely used in AC / DC motor speed control systems, power regulation systems, and servo systems. Thyristors are classified into unidirectional and bidirectional types. A bidirectional thyristor, also called a three-terminal bidirectional thyristor or TRIAC, is structurally equivalent to two unidirectional thyristors connected in reverse. This type of thyristor has bidirectional conduction capability. Its on / off state is determined by the control electrode. Applying a positive (or negative) pulse to the control electrode will turn it on in the forward (or reverse) direction. The advantage of this device is its simple control circuit and the absence of reverse withstand voltage issues, making it particularly suitable for use as an AC contactless switch.

[0058] Metal-oxide-semiconductor (MOSFET) field-effect transistors are field-effect transistors manufactured using planar technology and are widely used in large-scale and very-large-scale integrated circuits. As one of the core technologies in the semiconductor device field, MOSFETs are mainly used as logic circuits for binary calculations, playing a crucial role in digital electronic devices. Based on their operating mechanisms, MOSFETs can be divided into enhancement-mode and depletion-mode types to meet different circuit design requirements.

[0059] As can be seen, transistors, silicon controlled rectifiers (SCRs), and MOSFETs are commonly used semiconductor switching devices. The key parameter of these devices is the on-state voltage drop (resistance). Lower on-state resistance results in lower losses.

[0060] Power devices exhibit various short-circuit modes, with bridge arm short circuits being one of the more severe. During a bridge arm short circuit, the current rises sharply, and the power device must withstand the bus voltage, posing a significant challenge to its performance and reliability.

[0061] In many power electronics applications, such as motor drives, short circuits sometimes occur. This requires power devices to have a certain short-circuit withstand capability, meaning they can withstand short-circuit current for a certain period without damage. Inrush current refers to a large current generated in a circuit due to a sudden power-on or the sudden connection of a large capacitor, causing the capacitor to experience a large dv / dt; or a large current generated by lightning strikes or charge induction between the circuit and lightning clouds, leading to device performance degradation or even damage. Inrush current is very common in power electronic circuits. The maximum inrush current value or energy that a device can withstand is defined as its inrush current withstand capability. Inrush withstand capability includes the inrush capability at the trigger electrode and the inrush capability between the source and drain.

[0062] Power devices (MOSFETs, BJTs, SCRs) in related technologies often suffer from problems such as high conduction losses, weak short-circuit robustness, and insufficient surge protection.

[0063] In some exemplary embodiments, please refer to Figure 1 This application provides a method for preparing a semiconductor structure, the method comprising steps S101 to S103.

[0064] S101: Provide a substrate having a first conductivity type, and the thickness of the substrate being less than the minority carrier diffusion length of the substrate.

[0065] Please see Figure 2In the embodiments of this application, the material of the substrate 10 can be any suitable substrate material known in the art, such as at least one of the following materials: silicon (Si), germanium (Ge), red phosphorus, silicon germanium (SiGe), silicon carbide (SiC), silicon carbide (SiGeC), indium arsenide (InAs), gallium arsenide (GaAs), indium phosphide (InP), or other III / V compound semiconductors, including multilayer structures composed of these semiconductors, or silicon on insulator (SOI), silicon on insulator stacked (SSOI), silicon on insulator stacked (S-SiGeOI), silicon on insulator (SiGeOI), and germanium on insulator (GeOI), or it can also be a double-side polished wafer (DSP), or a ceramic substrate such as alumina, quartz, or glass substrate, etc. The embodiments of this application are not limited here.

[0066] S102: A trigger electrode structure is formed on the first side of the substrate in the first direction.

[0067] Please see Figure 3 The trigger electrode structure 20 can be located on a first side of the substrate 10 in a first direction. In this embodiment, the first direction can be the X-axis direction shown in the figure, and the second direction can be the Y-axis direction shown in the figure. The trigger electrode structure 20 of this application can have a second conductivity type, which is different from the first conductivity type. In one example, if the first conductivity type is N-type, then the second conductivity type is P-type; or, if the first conductivity type is P-type, then the second conductivity type is N-type.

[0068] S103: At least one source structure and at least one drain structure are formed on the second side of the substrate in the first direction; the drain structure and the source structure are spaced apart.

[0069] Please see Figure 4 The source structure 40 and drain structure 50 can both be located on the second side of the substrate 10 in the first direction. The source structure 40 and drain structure 50 are spaced apart in the second direction. When there are multiple source structures 40, each source structure 40 is electrically connected to the others; when there are multiple drain structures 50, each drain structure 50 is electrically connected to the others. The source structure 40 and drain structure 50 of this application can both have a second conductivity type.

[0070] The above-mentioned method for fabricating semiconductor structures has at least the following beneficial effects:

[0071] The semiconductor structure fabrication method of this application produces a semiconductor structure comprising a substrate, a trigger structure, a source structure, and a drain structure. The substrate has a first conductivity type, while the trigger, source, and drain structures all have a second conductivity type. When no trigger voltage is applied to the trigger structure, no minority carriers are injected into the substrate, and the source and drain structures are isolated by the high-resistivity substrate, resulting in no current flow and the semiconductor structure being off. When a trigger voltage is applied to the trigger structure, it can inject a large number of minority carriers into the substrate. Because the substrate thickness is less than the minority carrier diffusion length, the injected minority carriers can pass through the substrate perpendicularly with almost no recombination, reaching the second side surface of the substrate. These minority carriers then accumulate in large quantities at the interface between the source and drain structures on the second side surface of the substrate, forming a high-concentration electron accumulation layer (conductive channel), connecting the source and drain structures, thus turning on the semiconductor structure. As can be seen, in the semiconductor structure of this application, the trigger electrode structure-substrate-source drain structure constitutes a complete bipolar TVS (Transient Voltage Suppressor) structure. When a surge overvoltage occurs at the source drain or trigger electrode, the TVS structure will undergo avalanche breakdown in advance, rapidly dissipating the surge energy in the form of current. Therefore, the semiconductor structure of this application has good surge resistance.

[0072] In some exemplary embodiments, please refer to Figure 5 Step S102, forming a trigger electrode structure on the first side of the substrate in the first direction, includes steps S501 to S502.

[0073] S501: A first doped region is formed on the first side in the first direction within the substrate.

[0074] Please continue reading. Figure 3 The trigger electrode structure 20 of this application includes a first doped region 21 and a first conductive layer 22. The first doped region 21 is located inside the substrate 10 and has a second conductivity type. The formation process of the first doped region 21 may include, but is not limited to, ion implantation (IMP) process.

[0075] S502: A first conductive layer is formed on the side of the first doped region away from the substrate.

[0076] Please continue reading. Figure 3 The first conductive layer 22 is located on the side of the first doped region 21 away from the substrate 10, and the first conductive layer 22 at least covers the first doped region 21.

[0077] In some exemplary embodiments, please refer to Figure 6Step S103 involves forming at least one source structure and at least one drain structure on the second side of the substrate in the first direction, including steps S601 and S602.

[0078] S601: A second doped region and a third doped region are formed on the second side of the substrate in the first direction, respectively.

[0079] Please continue reading. Figure 4 In this embodiment, the source structure 40 may include a second doped region 41 and a second conductive layer 42, and the drain structure 50 may include a third doped region 51 and a third conductive layer 52. Both the second doped region 41 and the third doped region 52 have a second conductivity type. As can be seen from the figure, both the second doped region 41 and the third doped region 52 are located inside the substrate 10, and are spaced apart in a second direction.

[0080] S602: A second conductive layer and a third conductive layer are formed on the second side of the substrate in the first direction.

[0081] The second conductive layer 42 is electrically connected to the second doped region 41, and the third conductive layer 52 is electrically connected to the third doped region 51; the second conductive layer 42 of at least one source structure 40 is in direct contact with the substrate 10; the orthographic projection of the third conductive layer 52 on the second side surface of the substrate 10 is located within the orthographic projection of the third doped region 51 on the second side surface of the substrate 10.

[0082] It should be understood that, although Figure 1 , Figure 5 and Figure 6 The steps in the flowchart are shown sequentially as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified herein, there is no strict order in which these steps are executed, and they can be performed in other orders. Figure 1 , Figure 5 and Figure 6 At least some of the steps in the process may include multiple steps or multiple stages. These steps or stages are not necessarily completed at the same time, but may be executed at different times. The execution order of these steps or stages is not necessarily sequential, but may be executed in turn or alternately with other steps or at least some of the steps or stages in other steps.

[0083] Please continue reading. Figure 4 The present invention also provides a semiconductor structure comprising:

[0084] Substrate 10 has a first conductivity type; the thickness of the substrate is less than the minority carrier diffusion length of the substrate;

[0085] The trigger electrode structure 20 is located on the first side of the substrate 10 in the first direction;

[0086] At least one source structure 40 is located on the second side of the substrate 10 in the first direction;

[0087] At least one drain structure 50 is located on the second side of the substrate 10 in the first direction and is spaced apart from the source structure 40.

[0088] In the embodiments of this application, the material of the substrate 10 can be any suitable substrate material known in the art, such as at least one of the following materials: silicon (Si), germanium (Ge), red phosphorus, silicon germanium (SiGe), silicon carbide (SiC), silicon carbide (SiGeC), indium arsenide (InAs), gallium arsenide (GaAs), indium phosphide (InP), or other III / V compound semiconductors, including multilayer structures composed of these semiconductors, or silicon on insulator (SOI), silicon on insulator stacked (SSOI), silicon on insulator stacked (S-SiGeOI), silicon on insulator (SiGeOI), and germanium on insulator (GeOI), or it can also be a double-side polished wafer (DSP), or a ceramic substrate such as alumina, quartz, or glass substrate, etc. The embodiments of this application are not limited here.

[0089] The trigger electrode structure 20 can be located on a first side of the substrate 10 in a first direction. In this embodiment, the first direction can be the X-axis direction shown in the figure, and the second direction can be the Y-axis direction shown in the figure. The trigger electrode structure 20 of this application can have a second conductivity type, which is different from the first conductivity type. In one example, if the first conductivity type is N-type, then the second conductivity type is P-type; or, if the first conductivity type is P-type, then the second conductivity type is N-type.

[0090] Please see Figure 4 The source structure 40 and drain structure 50 can both be located on the second side of the substrate 10 in the first direction. The source structure 40 and drain structure 50 are spaced apart in the second direction. When there are multiple source structures 40, each source structure 40 is electrically connected to the others; when there are multiple drain structures 50, each drain structure 50 is electrically connected to the others. The source structure 40 and drain structure 50 of this application can both have a second conductivity type.

[0091] In one example, the semiconductor structure of this application can have multiple source structures 40 and drain structures 50. Please refer to [link / reference]. Figure 4As can be seen, the source structure 40 and the drain structure 50 are arranged alternately in the second direction, and the source structure 40 and the drain structure 50 are spaced apart from each other.

[0092] In some exemplary embodiments, the trigger structure includes:

[0093] The first doped region 21 is located within the substrate 10 and on a first side of the substrate 10 in a first direction; the first doped region 21 has a second conductivity type; the second conductivity type is opposite to the first conductivity type.

[0094] The first conductive layer 22 is located on the side of the first doped region 21 away from the substrate 10.

[0095] The trigger structure 20 of this application includes a first doped region 21 and a first conductive layer 22. The first doped region 21 is located inside the substrate 10 and has a second conductivity type. The formation process of the first doped region 21 may include, but is not limited to, ion implantation (IMP) process.

[0096] The first conductive layer 22 is located on the side of the first doped region 21 away from the substrate 10, and the first conductive layer 22 at least covers the first doped region 21.

[0097] In some examples, the first doped region 21 can be a single unit, or, see [link to relevant documentation] Figure 7 The first doped region 21 includes a plurality of first sub-doped regions 211 spaced apart in a second direction. When the first doped region 21 includes a plurality of first sub-doped regions 211, the spacing between adjacent first sub-doped regions 211 in the second direction can be less than 10 μm. The spacing between adjacent first sub-doped regions 211 in the second direction can be 1 μm, 2 μm, 3 μm, 4 μm, 5 μm, 6 μm, 7 μm, 8 μm, 9 μm, or 10 μm, etc.

[0098] In some exemplary embodiments, the source structure 40 includes:

[0099] The second doped region 41 is located within the substrate 10 and on the second side of the substrate 10 in the first direction; the second doped region 41 has a second conductivity type.

[0100] The second conductive layer 42 is located on the side of the second doped region 41 away from the substrate 10 and is electrically connected to the second doped region 41.

[0101] In this embodiment, at least one source structure 40 has a second conductive layer 42 that is in direct contact with the substrate 10.

[0102] In the embodiments of this application, when there is only one source structure 40, the second conductive layer 42 is in direct contact with the substrate 10; when there are multiple source structures 40, at least a portion of the second conductive layer 42 is in direct contact with the substrate 10, and each second conductive layer 41 is spaced apart in the second direction and each second conductive layer 42 is electrically connected to each other.

[0103] In some examples, please refer to Figure 4 The semiconductor structure of this application includes three source structures 40, and a drain structure 50 is disposed between adjacent source structures 40. Each source structure 40 includes a second doped region 41 and a second conductive layer 42 (the second doped regions 41 of the three source structures 40 are respectively referred to as second doped region 41-1, second doped region 41-2 and second doped region 41-3; the three second conductive layers 42 are respectively referred to as second conductive layer 42-1, second conductive layer 42-2 and second conductive layer 42-3; the second doped region 41-1 and the second conductive layer 42-1 form one source structure 40; the second doped region 41-2 and the second conductive layer 42-2 form another source structure 40; the second doped region 41-3 and the second conductive layer 42-3 form yet another source structure 40). Figure 4 As can be seen, the second conductive layer 42-1 is in direct contact with the substrate 10. That is, the orthographic projection of the second conductive layer 42-1 onto the second side surface of the substrate 10 does not completely fall within the orthographic projection of the second doped region 41-1 onto the second side surface of the substrate. Specifically, the orthographic projection of the second conductive layer 42-1 onto the second side surface of the substrate 10 partially overlaps with the orthographic projection of the second doped region 41-1 onto the second side surface of the substrate. Part of the orthographic projection of the second conductive layer 42-1 onto the second side surface of the substrate 10 lies within the orthographic projection of the second doped region 41-1 onto the second side surface of the substrate, while a portion lies on the second side surface of the substrate. The second conductive layers 42-2 and 42-3 are not in direct contact with the substrate 10. That is, the orthographic projection of the second conductive layer 42-2 onto the second side surface of the substrate 10 falls within the orthographic projection of the second doped region 41-2 onto the second side surface of the substrate, and the orthographic projection of the second conductive layer 42-3 onto the second side surface of the substrate 10 falls within the orthographic projection of the second doped region 41-3 onto the second side surface of the substrate.

[0104] In other examples, please refer to Figure 8 The semiconductor structure of this application includes three source structures 40, each source structure 40 including a second doped region 41 and a second conductive layer 42 (the second doped region 41-1 and the second conductive layer 42-1 form one source structure 40; the second doped region 41-2 and the second conductive layer 42-2 form another source structure 40; the second doped region 41-3 and the second conductive layer 42-3 form yet another source structure 40). Figure 8As can be seen, the second conductive layer 42-1, the second conductive layer 42-2, and the second conductive layer 42-3 are all in direct contact with the substrate 10.

[0105] In some exemplary embodiments, the drain structure 50 includes:

[0106] The third doped region 51 is located within the substrate 10 and on the second side of the substrate 10 in the first direction; the third doped region 51 has a second conductivity type.

[0107] The third conductive layer 52 is located on the side of the third doped region 51 away from the substrate 10 and is electrically connected to the third doped region 51; the orthographic projection of the third conductive layer 52 on the second side surface of the substrate 10 is located within the orthographic projection of the third doped region 51 on the second side surface of the substrate 10.

[0108] Please see Figure 4 , Figure 7 or Figure 8 In this embodiment, the third conductive layer 52 is not in direct contact with the substrate 10; that is, the orthographic projection of the third conductive layer 52 onto the second side surface of the substrate 10 lies within the orthographic projection of the third doped region 51 onto the second side surface of the substrate 10. In some examples, the semiconductor structure of this application includes three drain structures 50. Each drain structure 50 includes a third doped region 51 and a third conductive layer 52 (the third doped regions 51 of the three drain structures 50 are respectively referred to as third doped region 51-1, third doped region 51-2, and third doped region 51-3; the three third conductive layers 52 are respectively referred to as third conductive layer 52-1, third conductive layer 52-2, and third conductive layer 52-3; the third doped region 51-1 and the third conductive layer 52-1 form one drain structure 50; the third doped region 51-2 and the third conductive layer 52-2 form another drain structure 50; and the third doped region 51-3 and the third conductive layer 52-3 form yet another drain structure 50). Figure 4 , Figure 7 , Figure 8 or Figure 9 As can be seen from the above, the orthographic projection of each third conductive layer 52 on the second side surface of the substrate 10 is located within the orthographic projection of the corresponding third doped region 51 on the second side surface of the substrate 10. That is, the orthographic projection of the third conductive layer 52-1 on the second side surface of the substrate 10 is located within the orthographic projection of the corresponding third doped region 51-1 on the second side surface of the substrate 10, the orthographic projection of the third conductive layer 52-2 on the second side surface of the substrate 10 is located within the orthographic projection of the corresponding third doped region 51-2 on the second side surface of the substrate 10, and the orthographic projection of the third conductive layer 52-3 on the second side surface of the substrate 10 is located within the orthographic projection of the corresponding third doped region 51-3 on the second side surface of the substrate 10.

[0109] When there are multiple drain structures 50, each third conductive layer 52 is electrically connected to the others.

[0110] In some examples, the spacing between adjacent second doped regions 41 and third doped regions 51 in the second direction can be less than 10 μm, for example, it can be between 1 μm and 10 μm. For example, the spacing between adjacent second doped regions 41 and third doped regions 51 in the second direction can be 1 μm, 2 μm, 3 μm, 4 μm, 5 μm, 6 μm, 7 μm, 8 μm, 9 μm or 10 μm, etc.

[0111] In some exemplary embodiments, the semiconductor structure further includes:

[0112] A passivation layer 60 is located on the second side of the substrate 10. The passivation layer 60 has a first opening and a second opening. The first opening exposes a second doped region 41, and the second opening exposes a third doped region 51. A second conductive layer 42 is located in the first opening, and a third conductive layer 52 is located in the second opening.

[0113] A protective layer 30 is located on the first side of the substrate 10. The protective layer 30 has a third opening that exposes the first doped region 21. The first conductive layer 22 is located inside the third opening.

[0114] In some exemplary embodiments, in the semiconductor structure of this application, there may be an ohmic contact layer between the first conductive layer 22 and the first doped region 21, and / or there may be an ohmic contact layer between the second conductive layer 42 and the second doped region 41, and / or there may be an ohmic contact layer between the third conductive layer 52 and the third doped region 51.

[0115] In some exemplary embodiments, please refer to Figure 9 The semiconductor structure further includes a fourth doped region 70, which has a first conductivity type and is located between adjacent second doped regions 41 and third doped regions 51. The doping concentration of the fourth doped region 70 is different from the doping concentration of the substrate 10. For example, the doping concentration of the fourth doped region 70 may be less than the doping concentration of the substrate 10, or the doping concentration of the fourth doped region 70 may be greater than the doping concentration of the substrate 10.

[0116] In a detailed embodiment, an example is given where the first conductivity type is P-type and the second conductivity type is N-type. When fabricating the semiconductor device, a P-type substrate 10 is first provided. Then, a first oxide layer with a thickness of 2000 angstroms is grown on a first side surface in a first direction of the substrate 10. Photolithography is then performed to form a first doped region 21 within the substrate 10, where phosphorus is doped using a diffusion method. The first doped region 21 and the substrate 10 can form a PN junction with a withstand voltage of 15V. Next, a second oxide layer with a thickness of 1000 angstroms can be grown on the first side surface in the first direction of the substrate 10. Then, contact holes are created on the oxide layer on the first side surface in the first direction of the substrate 10 using a dry etching process. A metal layer (the material of the metal layer can include at least a portion of TI, NI, and AG) is then grown. After dry etching of the metal layer, metal pads (i.e., the first conductive layer 22) are formed. The remaining oxide layer forms the protective layer 30.

[0117] Subsequently, a third oxide layer is grown on the second side surface of the substrate 10 in the first direction. The thickness of the third oxide layer can be 2000 angstroms. After photolithography and etching, phosphorus is implanted into the substrate 10 to form a second doped region 41. Similarly, a fourth oxide layer is grown again, followed by photolithography and etching, and phosphorus is implanted to form a third doped region 51.

[0118] After forming the second doped region 41 and the third doped region 51, all the oxide layer on the second side surface of the substrate 10 in the first direction can be etched away using hydrofluoric acid. Next, a passivation layer 60 can be grown on the second side surface of the substrate 10 in the first direction. In one example, the passivation layer 60 can be a composite film of an 8000 Å oxide layer + a 1000 Å phosphate glass layer + a 1000 Å silicon nitride layer. Then, a first opening and a second opening are formed on the passivation layer 60 by photolithography. The first opening exposes the second doped region 41, and the second opening exposes the third doped region 51. Next, Al metal can be grown on the second side surface of the substrate 10 in the first direction. After dry etching, separate pads (i.e., the second conductive layer 42 and the third conductive layer 52) are formed, wherein the second conductive layers 42 are electrically connected to each other, and the third conductive layers 52 are electrically connected to each other. In some examples, the source voltage and drain voltage of the semiconductor structure of this application can both be 300V, and the trigger voltage can be -10V.

[0119] A schematic diagram of the semiconductor structure prepared by the above-described semiconductor preparation method of this application can be seen as follows: Figure 4 , Figure 7 , Figure 8 or Figure 9 As shown, please refer to the following: Figure 10 , Figure 10 This application Figure 4 , Figure 7 , Figure 8 , Figure 9 The semiconductor structure corresponds to the device topology diagram. Among them, Figure 10 In this diagram, M1 refers to the first conductive layer 22, M2 refers to the second conductive layer 42, and M3 refers to the third conductive layer 52. It can be seen that the semiconductor structure of this application can be equivalent to a composite device of a transistor and a MOSFET. The second conductive layer 42 serves as both the base of the transistor and the source of the MOSFET, the first conductive layer 22 serves as the emitter of the transistor, the collector of the transistor is connected to the gate of the MOSFET, and the third conductive layer 52 serves as the drain of the MOSFET. When the first conductive layer 22 receives a trigger voltage, electrons from the N-type first doped region 21 diffuse into the P-type substrate 10, becoming minority carriers in the substrate 10. These electrons move towards the interface between the passivation layer 60 and the substrate 10, eventually accumulating at the interface. Consequently, the N-type second doped region 41, the electrons accumulated at the interface between the passivation layer 60 and the substrate 10, and the N-type third doped region 51 become conductive, i.e., the second conductive layer 42 and the third conductive layer 52 become conductive.

[0120] In the semiconductor structure of this application, the thickness of the substrate 10 in the first direction is less than the minority carrier diffusion length of the substrate 10. Therefore, when the first conductive layer 22 is triggered, the first doped region 21 injects a large number of minority carriers into the substrate 10. Since the thickness of the substrate 10 is less than the minority carrier diffusion length, most of the minority carriers can pass through the entire substrate 10 vertically with almost no recombination and reach the contact interface between the passivation layer 60 and the substrate 10. The minority carriers can be distributed between each of the second doped regions 41 and the third doped region 51, thereby avoiding local current concentration. In addition, in this application, each of the second conductive layers 41 can be configured to directly contact the substrate 10, thereby further improving the current uniformity. At the same time, the injected minority carriers can make the substrate 10 change from a high-resistivity semiconductor to a good conductor that is close to a metal, thereby reducing the on-resistance.

[0121] Meanwhile, the channel thickness is comparable to the substrate thickness, and the channel area covers the region between the second doped region 41 and the third doped region 51 on the second side surface of the substrate 10, which can further reduce the on-resistance. In addition, in this application, the second conductive layer 42 directly contacts the substrate 10, so that the current can flow out not only through the second doped region 41, but also directly through the substrate 10, thereby reducing parasitic resistance.

[0122] In this application, when the semiconductor structure is short-circuited, the current will increase sharply, which will further enhance the efficiency of minority carrier injection, further reduce the resistivity of the substrate 10, and the reduction of the on-resistance will suppress the spike of the short-circuit current and avoid the current from growing exponentially.

[0123] Furthermore, the trigger electrode structure-substrate-source structure of this application naturally forms a complete NPN or PNP transistor. Taking the trigger electrode structure-substrate-source structure forming an NPN transistor as an example, when a surge overvoltage occurs between the source (second conductive layer 42) and the drain (third conductive layer 52), the reverse-biased PN junction of the third doped region-substrate first undergoes avalanche breakdown, generating a large number of electron-hole pairs. Holes are injected into the substrate 10, causing the base potential to rise rapidly. When the base potential is higher than the trigger electrode (first conductive layer 22) potential, the PN junction of the first doped region 21 and the substrate 10 is forward biased, and the NPN transistor enters the saturation conduction state. The surge current is rapidly discharged through the path of "third doped region-substrate-second doped region-second conductive layer".

[0124] When a surge overvoltage occurs between the trigger electrode (first conductive layer 22) and the source electrode (second conductive layer 42), if the trigger electrode potential is higher than the source electrode, the PN junction of the first doped region 21 and the substrate 10 is reverse biased, resulting in avalanche breakdown, and the surge current is discharged through the path of "trigger electrode—first doped region—substrate—source". If the trigger electrode potential is lower than the source electrode, the PN junction of the first doped region 21 and the substrate 10 is forward biased, and the surge current is discharged through the path of "source—substrate—first doped region—trigger electrode".

[0125] In the description of this specification, references to terms such as "some embodiments," "other embodiments," and "ideal embodiments" indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the invention. In this specification, the illustrative descriptions of the above terms do not necessarily refer to the same embodiments or examples.

[0126] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features of the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0127] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. A semiconductor structure, characterized in that, include: A substrate having a first conductivity type; the thickness of the substrate is less than the minority carrier diffusion length of the substrate; A trigger electrode structure is located on a first side of the substrate in a first direction; At least one source structure is located on the second side of the substrate in the first direction; At least one drain structure is located on the second side of the substrate in the first direction and is spaced apart from the source structure.

2. The semiconductor structure according to claim 1, characterized in that, The trigger electrode structure includes: A first doped region is located within a substrate and on a first side of the substrate in a first direction; the first doped region has a second conductivity type; the second conductivity type is opposite to the first conductivity type; The first conductive layer is located on the side of the first doped region away from the substrate.

3. The semiconductor structure according to claim 2, characterized in that, The first doped region includes a plurality of first sub-doped regions spaced apart.

4. The semiconductor structure according to claim 1, characterized in that, The source structure includes: The second doped region is located within the substrate and on a second side of the substrate in a first direction; the second doped region has a second conductivity type. The second conductive layer is located on the side of the second doped region away from the substrate and is electrically connected to the second doped region; In this embodiment, at least one of the second conductive layers of the source structure is in direct contact with the substrate.

5. The semiconductor structure according to claim 4, characterized in that, The drain structure includes: A third doped region is located within the substrate and on a second side of the substrate in a first direction; the third doped region has a second conductivity type. The third conductive layer is located on the side of the third doped region away from the substrate and is electrically connected to the third doped region; the orthographic projection of the third conductive layer on the second side surface of the substrate is located within the orthographic projection of the third doped region on the second side surface of the substrate.

6. The semiconductor structure according to claim 5, characterized in that, The spacing between the adjacent second doped region and the third doped region in the second direction is 1 μm to 10 μm; the second direction is perpendicular to the first direction.

7. The semiconductor structure according to claim 5, characterized in that, The semiconductor structure also includes: A passivation layer is located on the second side of the substrate. The passivation layer has a first opening and a second opening. The first opening exposes the second doped region, and the second opening exposes the third doped region. The second conductive layer is located within the first opening, and the third conductive layer is located within the second opening.

8. A method for fabricating a semiconductor structure, characterized in that, The method includes: A substrate is provided having a first conductivity type, and the thickness of the substrate is less than the minority carrier diffusion length of the substrate; A trigger electrode structure is formed on a first side of the substrate in a first direction; At least one source structure and at least one drain structure are formed on the second side of the substrate in the first direction; the drain structure is spaced apart from the source structure.

9. The method for preparing a semiconductor structure according to claim 8, characterized in that, The formation of a trigger electrode structure on a first side of the substrate in a first direction includes: A first doped region is formed on a first side in a first direction within the substrate; wherein the first doped region has a second conductivity type, the second conductivity type being different from the first conductivity type; A first conductive layer is formed on the side of the first doped region away from the substrate.

10. The method for preparing a semiconductor structure according to claim 8, characterized in that, The formation of at least one source structure and at least one drain structure on the second side of the substrate in the first direction includes: A second doped region and a third doped region are formed on a second side in a first direction within the substrate; both the second doped region and the third doped region have a second conductivity type, and the second doped region and the third doped region are spaced apart in a second direction; the second direction is perpendicular to the first direction; A second conductive layer and a third conductive layer are formed on a second side in a first direction within the substrate; Wherein, the second conductive layer is electrically connected to the second doped region, and the third conductive layer is electrically connected to the third doped region; at least one of the second conductive layers of the source structure is in direct contact with the substrate; the orthographic projection of the third conductive layer on the second side surface of the substrate is located within the orthographic projection of the third doped region on the second side surface of the substrate.

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