IGBT bidirectional switching device structure and manufacturing method thereof

Abstract

The application discloses an IGBT bidirectional switch device structure and a manufacturing method thereof, and relates to the technical field of semiconductor power devices.The application comprises a silicon-based semiconductor substrate, wherein the silicon-based semiconductor substrate has a front surface and a back surface arranged oppositely.The application forms a deep groove isolation structure in an N-type epitaxial layer of the silicon-based semiconductor substrate, separates the N-type epitaxial layer into a first active region and a second active region, forms a first switch unit and a second switch unit in the two active regions respectively, forms a back surface common collector structure composed of an N-type buffer layer, a P-type collector region, an N-type cathode region and a back surface metal layer on the back surface, and makes a first emitter end, a second emitter end and a common collector end form a three-power-end bidirectional switch structure, so that the bidirectional switch integration of two IGBT switch units in the same chip is realized, the number of discrete device connections is reduced, and the device volume, parasitic parameters and packaging interconnection complexity are reduced.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor power device technology, and in particular relates to an IGBT bidirectional switching device structure and its fabrication method. Background Technology

[0002] In existing power conversion systems, bidirectional switching devices are mainly used to control the conduction and cutoff of electrical energy in both directions, and are commonly found in on-board chargers, energy storage converters, microgrids, uninterruptible power supplies (UPS), and photovoltaic inverter systems. With the rapid development of electric vehicles, distributed energy resources, and energy storage systems, the mode of power transmission is gradually shifting from unidirectional power supply to bidirectional flow. Power switching devices not only need to perform ordinary on / off control, but also need to adapt to charging, discharging, grid-connected, and off-grid operating states. In existing technologies, bidirectional switching functionality is often achieved by connecting two unidirectional power devices back-to-back, such as two MOSFETs or two IGBTs in reverse series, so that the forward and reverse current paths are controlled by the corresponding power devices. The back-to-back connection scheme can utilize mature silicon-based power devices and existing packaging processes, with an intuitive circuit structure and flexible device selection, and is already widely used in engineering applications. Another technical solution uses wide-bandgap semiconductor materials such as silicon carbide and gallium nitride to build a bidirectional control structure on a single chip. Leveraging the high breakdown field strength, high thermal conductivity, and high-frequency switching characteristics of wide-bandgap materials, it is suitable for bidirectional energy control in high-voltage and high-frequency scenarios.

[0003] The core drawback of existing bidirectional switching technology lies in its high conduction loss. Back-to-back discrete device solutions require two unidirectional power chips to form a bidirectional current path. When current is conducting in either direction, it must pass through the series-connected power device structure, increasing the on-state voltage drop and device heat generation. Although wide-bandgap semiconductor monolithic bidirectional switches employ a single-chip structure, conduction loss control in engineering applications remains constrained by limitations in device structure, driving methods, and process maturity. Summary of the Invention

[0004] To address the shortcomings of existing technologies, this invention provides an IGBT bidirectional switching device structure and its fabrication method. The technical problem this invention aims to solve is: how to integrate deep-trench isolated dual IGBT switching units, diode cell regions, and back common collector electrode structures within the same silicon substrate to address the issues of high on-state voltage drop, large conduction losses, and increased heat generation in existing bidirectional switching devices.

[0005] To achieve the above objectives, the present invention provides the following technical solution: an IGBT bidirectional switching device structure, comprising:

[0006] A silicon-based semiconductor substrate having a front side and a back side disposed opposite to each other, the silicon-based semiconductor substrate including an N-type epitaxial layer as a drift region;

[0007] A deep trench isolation structure is formed within the N-type epitaxial layer, dividing the N-type epitaxial layer into a first active region and a second active region;

[0008] The first switching unit is disposed in the first active region. The first switching unit includes a first IGBT cell region and a first diode cell region. The first IGBT cell region includes a first trench gate structure, a first P-well region, a first N-type emitter region, a first gate metal layer, and a first emitter metal layer. The first diode cell region includes a first P-type anode region. The first emitter metal layer forms a first emitter terminal.

[0009] The second switching unit is disposed in the second active region. The second switching unit includes a second IGBT cell region and a second diode cell region. The second IGBT cell region includes a second trench gate structure, a second P-well region, a second N-type emitter region, a second gate metal layer and a second emitter metal layer. The second diode cell region includes a second P-type anode region. The second emitter metal layer forms a second emitter terminal.

[0010] A back-side common collector structure is disposed on the back side of the silicon-based semiconductor substrate. The back-side common collector structure includes an N-type buffer layer, a P-type collector region, an N-type cathode region, and a back-side metal layer. The P-type collector region corresponds to the first IGBT cell region and the second IGBT cell region, and the N-type cathode region corresponds to the first diode cell region and the second diode cell region. The back-side metal layer forms a common collector terminal.

[0011] The first switching unit and the second switching unit are separated by the deep trench isolation structure and share the back common collector structure; the first transmitting end and the second transmitting end serve as two power connection terminals of the bidirectional energy conversion circuit, and the first transmitting end, the second transmitting end and the common collector end constitute a three-power-terminal bidirectional switching structure.

[0012] The present invention is further configured such that the deep trench isolation structure is filled with silicon dioxide, the isolation depth of the deep trench isolation structure is greater than the trench depth of the first trench gate structure and the second trench gate structure, and the deep trench isolation structure does not penetrate the silicon-based semiconductor substrate.

[0013] The present invention is further configured such that the first IGBT cell region further includes a first carrier storage layer, and the second IGBT cell region further includes a second carrier storage layer; neither the first diode cell region nor the second diode cell region has an N-type emitter region.

[0014] The present invention is further configured such that the P-type collector region includes a first P-type collector region and a second P-type collector region, and the N-type cathode region includes a first N-type cathode region and a second N-type cathode region; the first P-type collector region corresponds to the first IGBT cell region, the second P-type collector region corresponds to the second IGBT cell region, the first N-type cathode region corresponds to the first diode cell region, the second N-type cathode region corresponds to the second diode cell region, and the back metal layer is located on the back side of the first P-type collector region, the second P-type collector region, the first N-type cathode region, and the second N-type cathode region.

[0015] A method for fabricating an IGBT bidirectional switching device structure includes:

[0016] S1. A silicon-based semiconductor substrate is provided, the silicon-based semiconductor substrate having a front side and a back side disposed opposite to each other, the silicon-based semiconductor substrate including an N-type epitaxial layer, the N-type epitaxial layer serving as a drift region; a deep trench is etched to form a deep trench on the front side of the silicon-based semiconductor substrate, and a dielectric material is filled in the deep trench to form a deep trench isolation structure, the deep trench isolation structure dividing the N-type epitaxial layer into a first active region and a second active region;

[0017] S2. A front-side cell structure of a first switching unit is formed in the first active region, and a front-side cell structure of a second switching unit is formed in the second active region; wherein, the first switching unit includes a first IGBT cell region and a first diode cell region, and the second switching unit includes a second IGBT cell region and a second diode cell region; the first IGBT cell region is formed with a first trench gate structure, a first P-well region and a first N-type emitter region, the second IGBT cell region is formed with a second trench gate structure, a second P-well region and a second N-type emitter region, the first diode cell region is formed with a first P-type anode region, and the second diode cell region is formed with a second P-type anode region;

[0018] S3. A metal layer is formed on the front side of the silicon-based semiconductor substrate, and the metal layer is patterned to form a first gate metal layer, a first emitter metal layer, a second gate metal layer, and a second emitter metal layer.

[0019] S4. The back side of the silicon-based semiconductor substrate is doped to form an N-type buffer layer on the side of the N-type epitaxial layer near the back side, and a P-type collector region and an N-type cathode region are formed on the side of the N-type buffer layer near the back side; the P-type collector region is disposed corresponding to the first IGBT cell region and the second IGBT cell region, and the N-type cathode region is disposed corresponding to the first diode cell region and the second diode cell region;

[0020] S5. A back metal layer is deposited on the back side of the silicon-based semiconductor substrate to form a back common collector electrode structure and a common collector terminal.

[0021] The present invention is further configured such that the dielectric material is silicon dioxide; when forming the deep trench isolation structure, an isolation trench pattern is first formed on the front side of the silicon-based semiconductor substrate, and then the N-type epitaxial layer is dry etched along the isolation trench pattern, and silicon dioxide is deposited in the deep trench obtained by etching and planarized; the bottom of the deep trench isolation structure is lower than the bottom of the first trench gate structure and the second trench gate structure, and the deep trench isolation structure does not penetrate to the back side of the silicon-based semiconductor substrate.

[0022] The present invention is further configured such that both the first trench gate structure and the second trench gate structure are formed by trench etching, gate dielectric layer formation, and polysilicon filling; before forming the first P-well region and the second P-well region, a first carrier storage layer and a second carrier storage layer are formed in the first IGBT cell region and the second IGBT cell region, respectively; the first P-well region and the first P-type anode region are formed by the same P-type doping step, and the second P-well region and the second P-type anode region are formed by the same P-type doping step; the first N-type emitter region is formed only in the first IGBT cell region, and the second N-type emitter region is formed only in the second IGBT cell region.

[0023] The present invention is further configured such that the doping process includes: firstly performing N-type doping on the back side of the silicon-based semiconductor substrate to form the N-type buffer layer, and then performing P-type doping and N-type doping respectively using a back-side photolithography pattern to form the P-type collector region and the N-type cathode region; the P-type collector region includes a first P-type collector region corresponding to the first IGBT cell region and a second P-type collector region corresponding to the second IGBT cell region, and the N-type cathode region includes a first N-type cathode region corresponding to the first diode cell region and a second N-type cathode region corresponding to the second diode cell region; when forming the back-side common collector structure, the back-side metal layer is formed on the back side of the first P-type collector region, the second P-type collector region, the first N-type cathode region, and the second N-type cathode region.

[0024] The beneficial effects of this invention are as follows: This invention forms a deep trench isolation structure within the N-type epitaxial layer of a silicon-based semiconductor substrate, dividing the N-type epitaxial layer into a first active region and a second active region. A first switching unit and a second switching unit are formed in the two active regions respectively. At the same time, a back common collector electrode structure consisting of an N-type buffer layer, a P-type collector region, an N-type cathode region, and a back metal layer is formed on the back side. This enables the first emitter terminal, the second emitter terminal, and the common collector terminal to form a three-power-terminal bidirectional switching structure, thereby realizing the bidirectional switching integration of two IGBT switching units within the same chip. This reduces the number of discrete device connections and helps to reduce device size, parasitic parameters, and packaging interconnection complexity.

[0025] This invention employs a deep trench isolation structure to electrically isolate the first and second switching units, and uses a back-side common collector structure to achieve a shared back-side connection between the two switching units. This not only suppresses lateral leakage and mutual interference between the two active regions, improving device reliability, but also allows the first and second diode cell regions to form a freewheeling path in conjunction with the corresponding N-type cathode region, improving current conduction capability and reverse recovery characteristics during bidirectional energy conversion. Simultaneously, the inclusion of a carrier storage layer within the IGBT cell region enhances the carrier storage effect, reduces on-state voltage drop, and improves device conduction performance and energy conversion efficiency. Attached Figure Description

[0026] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below.

[0027] Figure 1 This is a schematic diagram of the core structure of the device of the present invention.

[0028] Figure 2 This is a flowchart illustrating the core manufacturing process of the present invention.

[0029] Figure 3 This is a schematic diagram illustrating the forward and reverse conduction principle of the present invention.

[0030] Figure 4 This is a schematic diagram of the complete device structure of the present invention. Detailed Implementation

[0031] The technical solutions of the present invention will be described below with reference to the accompanying drawings. The described embodiments are only some embodiments of the present invention, and not all embodiments.

[0032] Example 1

[0033] Please see Figures 1-4 This invention relates to an IGBT bidirectional switching device structure, comprising:

[0034] A silicon-based semiconductor substrate having a front side and a back side disposed opposite to each other, the silicon-based semiconductor substrate including an N-type epitaxial layer as a drift region.

[0035] A deep trench isolation structure is formed within an N-type epitaxial layer, dividing the N-type epitaxial layer into a first active region and a second active region. The deep trench isolation structure is filled with silicon dioxide, and the isolation depth of the deep trench isolation structure is greater than the trench depth of the first trench gate structure and the second trench gate structure, and the deep trench isolation structure does not penetrate the silicon-based semiconductor substrate.

[0036] The first switching unit is disposed in the first active region. The first switching unit includes a first IGBT cell region and a first diode cell region. The first IGBT cell region includes a first trench gate structure, a first P-well region, a first N-type emitter region, a first gate metal layer and a first emitter metal layer. The first diode cell region includes a first P-type anode region and the first emitter metal layer forms a first emitter terminal.

[0037] The second switching unit is located in the second active region. The second switching unit includes a second IGBT cell region and a second diode cell region. The second IGBT cell region includes a second trench gate structure, a second P-well region, a second N-type emitter region, a second gate metal layer, and a second emitter metal layer. The second diode cell region includes a second P-type anode region, and the second emitter metal layer forms a second emitter terminal. The first IGBT cell region also includes a first carrier storage layer, and the second IGBT cell region also includes a second carrier storage layer. Neither the first nor the second diode cell region has an N-type emitter region.

[0038] A back-side common-collector structure is disposed on the back side of a silicon-based semiconductor substrate. The back-side common-collector structure includes an N-type buffer layer, a P-type collector region, an N-type cathode region, and a back-side metal layer. The P-type collector region corresponds to the first IGBT cell region and the second IGBT cell region, and the N-type cathode region corresponds to the first diode cell region and the second diode cell region. The back-side metal layer forms a common collector terminal. The P-type collector region includes a first P-type collector region and a second P-type collector region, and the N-type cathode region includes a first N-type cathode region and a second N-type cathode region. The first P-type collector region corresponds to the first IGBT cell region, the second P-type collector region corresponds to the second IGBT cell region, the first N-type cathode region corresponds to the first diode cell region, and the second N-type cathode region corresponds to the second diode cell region. The back-side metal layer is located on the back side of the first P-type collector region, the second P-type collector region, the first N-type cathode region, and the second N-type cathode region.

[0039] The first and second switching units are separated by a deep trench isolation structure and share a common collector structure on the back side. The first and second transmitting terminals serve as two power connection terminals of the bidirectional energy conversion circuit, and the first transmitting terminal, the second transmitting terminal, and the common collector terminal constitute a three-power-terminal bidirectional switching structure.

[0040] A method for fabricating an IGBT bidirectional switching device structure includes:

[0041] S1. A silicon-based semiconductor substrate is provided, having a front side and a back side disposed opposite to each other. The silicon-based semiconductor substrate includes an N-type epitaxial layer, which serves as a drift region. A deep trench is etched on the front side of the silicon-based semiconductor substrate to form a deep trench isolation structure, and a dielectric material is filled within the deep trench to form a deep trench isolation structure. The deep trench isolation structure divides the N-type epitaxial layer into a first active region and a second active region. The dielectric material is silicon dioxide. When forming the deep trench isolation structure, an isolation trench pattern is first formed on the front side of the silicon-based semiconductor substrate, and then the N-type epitaxial layer is dry-etched along the isolation trench pattern. Silicon dioxide is deposited within the etched deep trench and planarized. The bottom of the deep trench isolation structure is lower than the bottom of the first trench gate structure and the second trench gate structure, and the deep trench isolation structure does not penetrate to the back side of the silicon-based semiconductor substrate.

[0042] S2. A front-side cell structure of a first switching unit is formed in a first active region, and a front-side cell structure of a second switching unit is formed in a second active region. The first switching unit includes a first IGBT cell region and a first diode cell region, and the second switching unit includes a second IGBT cell region and a second diode cell region. The first IGBT cell region has a first trench gate structure, a first P-well region, and a first N-type emitter region; the second IGBT cell region has a second trench gate structure, a second P-well region, and a second N-type emitter region; the first diode cell region has a first P-type anode region, and the second diode cell region has a second P-type anode region. Both the first trench gate structure and the second trench gate structure are formed by trench etching, gate dielectric layer formation, and polysilicon filling. Before forming the first P-well region and the second P-well region, a first carrier storage layer and a second carrier storage layer are formed in the first IGBT cell region and the second IGBT cell region, respectively. The first P-well region and the first P-type anode region are formed by the same P-type doping step, and the second P-well region and the second P-type anode region are formed by the same P-type doping step. The first N-type emitter region is formed only within the first IGBT cell region, and the second N-type emitter region is formed only within the second IGBT cell region.

[0043] S3. A metal layer is formed on the front side of a silicon-based semiconductor substrate, and the metal layer is patterned to form a first gate metal layer, a first emitter metal layer, a second gate metal layer, and a second emitter metal layer.

[0044] S4. The back side of the silicon-based semiconductor substrate is doped to form an N-type buffer layer on the side of the N-type epitaxial layer near the back side, and a P-type collector region and an N-type cathode region are formed on the side of the N-type buffer layer near the back side. The P-type collector region corresponds to the first IGBT cell region and the second IGBT cell region, and the N-type cathode region corresponds to the first diode cell region and the second diode cell region. The doping process includes: firstly, N-type doping is performed on the back side of the silicon-based semiconductor substrate to form an N-type buffer layer, and then P-type doping and N-type doping are performed using the back-side photolithography pattern to form the P-type collector region and the N-type cathode region. The P-type collector region includes a first P-type collector region corresponding to the first IGBT cell region and a second P-type collector region corresponding to the second IGBT cell region, and the N-type cathode region includes a first N-type cathode region corresponding to the first diode cell region and a second N-type cathode region corresponding to the second diode cell region. When forming the back common collector structure, the back metal layer is formed on the back side of the first P-type collector region, the second P-type collector region, the first N-type cathode region, and the second N-type cathode region.

[0045] S5. A back metal layer is deposited on the back side of the silicon-based semiconductor substrate to form a back common collector structure and a common collector terminal.

[0046] This structure divides the same silicon semiconductor substrate into a first active region and a second active region, and uses a deep trench isolation structure to separate the two active regions, allowing the first and second switching units to participate in power control processes in different directions. The deep trench isolation structure restricts the lateral electric field distribution and carrier lateral transport between the two active regions, allowing the two switching units to maintain their respective front-side gate control characteristics while sharing a common-collector back electrode structure. The common-collector back electrode structure, in conjunction with the first and second emitter terminals on the front side, forms a three-power terminal connection suitable for bidirectional power transfer, thereby achieving chip-level integration of bidirectional switching functionality at the device structure level.

[0047] Meanwhile, the IGBT cell region and the diode cell region are partitioned within the same switching unit, so that the controlled conduction path and the freewheeling path correspond to different front-side doped regions and back-side doped regions, respectively. The carrier storage layer is used to adjust the carrier distribution in the drift region when the IGBT is on, reducing the on-state voltage drop. The diode cell region does not have an N-type emitter region, so that the diode cell region mainly undertakes the freewheeling function and reduces the possibility of the diode cell region forming an additional emitter injection channel.

[0048] Example 2

[0049] Please see Figure 1 Based on Example 1, this example illustrates an IGBT bidirectional switching device structure that integrates a first switching unit, a second switching unit, a deep trench isolation structure, and a back common collector electrode structure within the same silicon-based semiconductor substrate.

[0050] 1. Silicon-based semiconductor substrate and isolation structure

[0051] The IGBT bidirectional switching device in this embodiment uses a silicon-based semiconductor substrate, which has a front side and a back side. The silicon-based semiconductor substrate includes an N-type epitaxial layer, which serves as a drift region.

[0052] The N-type epitaxial layer has a thickness of 60 μm and a resistivity of 38 Ω·cm, making it suitable for power devices with a voltage rating of 650V. A deep trench isolation structure is incorporated within the N-type epitaxial layer. This deep trench isolation structure is located between the first and second active regions, laterally dividing the N-type epitaxial layer into the first and second active regions.

[0053] The deep trench isolation structure is filled with silicon dioxide. The trench width of the deep trench isolation structure is 4 μm, and the isolation depth is 20 μm. The deep trench isolation structure does not penetrate the silicon-based semiconductor substrate. The trench depth of both the first and second trench gate structures is 5 μm. The isolation depth of the deep trench isolation structure is greater than the trench depth of the trench gate structure. The lateral spacing between the deep trench isolation structure and the adjacent trench gate structure is 3 μm.

[0054] 2. First switching unit

[0055] The first switching unit is located in the first active region. The first switching unit includes a first IGBT cell region and a first diode cell region.

[0056] The first IGBT cell region includes a first trench gate structure, a first P-well region, a first N-type emitter region, a first carrier storage layer, a first gate metal layer, and a first emitter metal layer.

[0057] The first trench gate structure has a trench width of 1.1 μm and a trench depth of 5 μm, with a center-to-center spacing of 4.2 μm between adjacent trench gate structures. A gate dielectric layer, which is a silicon oxide layer with a thickness of 85 nm, is disposed on the inner wall of the trench. The trench is filled with a polysilicon gate.

[0058] The junction depth of the first P-well region is 2.6 μm. The first N-type emitter region is located within the first P-well region, with a junction depth of 0.35 μm and a surface doping concentration of [missing information]. The first carrier storage layer is located between the first P-well region and the N-type epitaxial layer, with a thickness of 1.2 μm and a peak doping concentration of [missing value]. .

[0059] The first diode cell region includes a first P-type anode region. The junction depth of the first P-type anode region is 2.6 μm, and the surface doping concentration is [missing information]. The first diode cell region does not have an N-type emitter region. The first emitter metal layer forms the first emitter terminal.

[0060] 3. Second switching unit

[0061] The second switching unit is located in the second active region. The second switching unit includes a second IGBT cell region and a second diode cell region.

[0062] The second IGBT cell region includes a second trench gate structure, a second P-well region, a second N-type emitter region, a second carrier storage layer, a second gate metal layer, and a second emitter metal layer. The trench width of the second trench gate structure is 1.1 μm, and the trench depth is 5 μm. The junction depth of the second P-well region is 2.6 μm. The junction depth of the second N-type emitter region is 0.35 μm. The peak doping concentration of the second carrier storage layer is... .

[0063] The second diode cell region includes a second P-type anode region. The junction depth of the second P-type anode region is 2.6 μm. No N-type emitter region is provided in the second diode cell region. A second emitter metal layer forms the second emitter terminal.

[0064] The trench dimensions, junction depth, carrier storage layer thickness, and surface doping concentration of each doped region in the second IGBT cell region and the second diode cell region are the same as those in the corresponding regions of the first switching unit. The area ratio of the first IGBT cell region to the first diode cell region is 7:3. The area ratio of the second IGBT cell region to the second diode cell region is 7:3. The effective cell area of ​​the first active region is... The effective cell area of ​​the second active region is

[0065] 4. Backside common collector structure

[0066] A back common collector structure is disposed on the back side of the silicon-based semiconductor substrate. The back common collector structure includes an N-type buffer layer, a P-type collector region, an N-type cathode region, and a back metal layer.

[0067] The N-type buffer layer is located on the side of the N-type epitaxial layer near the back surface, with a thickness of 3 μm and a peak doping concentration of [missing value]. .

[0068] The P-type collector region includes a first P-type collector region and a second P-type collector region. The first P-type collector region corresponds to the first IGBT cell region, and the second P-type collector region corresponds to the second IGBT cell region. The junction depth of both the first and second P-type collector regions is 1.0 μm, and the surface doping concentration is [missing information]. .

[0069] The N-type cathode region includes a first N-type cathode region and a second N-type cathode region. The first N-type cathode region corresponds to the first diode cell region, and the second N-type cathode region corresponds to the second diode cell region. The junction depth of both the first and second N-type cathode regions is 0.8 μm, and the surface doping concentration is [missing information]. .

[0070] The back metal layer uses The composite metal layers have thicknesses of 0.1 μm, 0.5 μm, and 2.0 μm, respectively.

[0071] 5. Terminal structure and test results

[0072] The first emitter terminal, the second emitter terminal, and the common collector terminal constitute a three-power-terminal bidirectional switch structure. The first gate metal layer forms the first gate control region, and the second gate metal layer forms the second gate control region. The first switch unit and the second switch unit are separated by a deep trench isolation structure and share a common-collector structure on the back side.

[0073] Under the device simulation conditions, the ambient temperature was 25℃, the rated test current was 40A, and the reverse recovery simulation conditions were a forward current of 40A, a reverse voltage of 400V, and a di / dt of 200A / μs. Device simulations performed under these structural parameters yielded on-state voltage drops of approximately 1.66V and 1.69V, and reverse recovery times ranging from 95ns to 115ns.

[0074] During simulation, the drive voltages for both the first and second gate control regions were 15V. The forward and reverse blocking voltages of the device were both 650V.

[0075] In summary, the first and second switching units are formed within the same silicon-based semiconductor substrate. The deep trench isolation structure provides lateral isolation between the two active regions. The back-side common-collector structure forms a shared back-side power structure, which, within a single silicon-based semiconductor substrate, forms bidirectional switching units, reducing the inter-chip interconnect paths required for back-to-back connections of two discrete power chips.

[0076] Example 3

[0077] Please see Figure 2 Based on Examples 1 and 2, the purpose of this example is to illustrate a specific process for fabricating a monolithic IGBT bidirectional switching device structure based on silicon-based RC-IGBT technology.

[0078] 1. Formation of silicon-based semiconductor substrate and deep trench isolation structure

[0079] An N-type silicon epitaxial wafer was selected as the silicon-based semiconductor substrate. The N-type silicon epitaxial wafer includes an N-type epitaxial layer, which serves as the drift region. The N-type epitaxial layer has a thickness of 80 μm and a resistivity of 40 Ω·cm. After back-side thinning of the silicon-based semiconductor substrate, the back-side doped region is formed on the side of the N-type epitaxial layer near the back side.

[0080] Photoresist is coated on the front side of a silicon-based semiconductor substrate to form an isolation trench pattern. An N-type epitaxial layer is then dry-etched along the isolation trench pattern to form a deep trench. The deep trench has a width of 3 μm and a depth of 25 μm. The deep trench does not penetrate the silicon-based semiconductor substrate.

[0081] After removing the photoresist, silicon dioxide is deposited within the deep trench. The silicon dioxide deposition thickness is 3.5 μm. Following deposition, chemical mechanical planarization is performed to remove excess silicon dioxide from the front side, leaving the silicon dioxide within the deep trench to form a deep trench isolation structure. This deep trench isolation structure divides the N-type epitaxial layer into a first active region and a second active region on the front side of the silicon-based semiconductor substrate.

[0082] The first and second active regions are located on opposite sides of the deep trench isolation structure and are arranged in a parallel stripe pattern within the chip plane. Within a repeating cell region, the lateral width of both the first and second active regions is 200 μm, and the deep trench isolation structure is located between the first and second active regions.

[0083] 2. Formation of front trench gate structure and front doped region

[0084] A gate trench pattern is formed on the front side of the first and second active regions. Dry etching is performed along the gate trench pattern to form a first trench and a second trench, respectively. Both the first and second trenches have a width of 1.2 μm and a depth of 5 μm. The isolation depth of the deep trench isolation structure is greater than the depth of the first and second trenches.

[0085] The inner walls of the first and second trenches are thermally oxidized to form a gate dielectric layer. The gate dielectric layer has a thickness of 80 nm. Subsequently, doped polysilicon is deposited, and the polysilicon is etched back to retain the doped polysilicon within the first and second trenches, forming the first trench gate structure and the second trench gate structure.

[0086] Phosphorus ion implantation was performed in the first and second IGBT cell regions to form the first and second carrier storage layers. The phosphorus ion implantation energy was 300 keV, and the implantation dose was [missing information]. After injection, hot annealing is performed at a temperature of 1050℃ for 60 minutes.

[0087] Boron ion implantation was then performed to form a first P-well region, a second P-well region, a first P-type anode region, and a second P-type anode region. The boron ion implantation energy was 120 keV, and the implantation dose was [missing information]. After injection, a driving process is performed at a driving temperature of 1100℃ for 90 minutes.

[0088] After the drive-in process, the junction depth of the first P-well region and the second P-well region is 3.0 μm to 4.0 μm, and the junction depth of the first P-type anode region and the second P-type anode region is 3.0 μm to 4.0 μm.

[0089] Then, photoresist is used to mask the first and second diode cell regions, and arsenic ion implantation is performed only in the first and second IGBT cell regions to form the first and second N-type emitter regions. The arsenic ion implantation energy is 80 keV, and the implantation dose is... The first diode cell region and the second diode cell region do not have an N-type emitter region.

[0090] Arsenic ion implantation was followed by activation annealing at 950℃ for 30 seconds. After annealing, the junction depth of the first N-type emitter region and the second N-type emitter region was 0.3 μm to 0.5 μm.

[0091] 3. Formation of the front metal layer

[0092] An interlayer dielectric layer is deposited on the front side of a silicon-based semiconductor substrate. The interlayer dielectric layer is silicon dioxide with a thickness of 800 nm. Contact holes are etched into the interlayer dielectric layer to expose the lead-out regions of the first trench gate structure, the lead-out regions of the second trench gate structure, the first N-type emitter region, the second N-type emitter region, the first P-type anode region, and the second P-type anode region.

[0093] An aluminum-silicon-copper metal layer is sputtered on the front side. The thickness of the aluminum-silicon-copper metal layer is 3 μm. The aluminum-silicon-copper metal layer is patterned to form a first gate metal layer, a first emitter metal layer, a second gate metal layer, and a second emitter metal layer. The first emitter metal layer corresponds to a first switching unit, and the second emitter metal layer corresponds to a second switching unit.

[0094] 4. Formation of the back-side doped region

[0095] The back side of the silicon-based semiconductor substrate was thinned to a thickness of 130 μm. After back-side cleaning, phosphorus ion implantation was performed to form an N-type buffer layer. The phosphorus ion implantation energy was 500 keV, and the implantation dose was [missing information]. After injection, rapid hot annealing is performed at a temperature of 950℃ for 30 seconds.

[0096] Subsequently, back-side photolithography is performed. The back-side photolithography pattern uses the layout position corresponding to the aforementioned deep trench isolation structure as a partitioning reference, so that the back-side P-type collector region and N-type cathode region correspond to the front-side IGBT cell region and diode cell region, respectively. In this embodiment, the alignment deviation between the back-side photolithography pattern and the front-side cell region layout is no greater than 2μm.

[0097] Boron ions are heavily doped at the positions corresponding to the first and second IGBT cell regions to form the first and second P-type collector regions. The boron ion implantation energy is 80 keV, and the implantation dose is... .

[0098] Phosphorus ions are heavily doped at positions corresponding to the first and second diode cell regions to form the first and second N-type cathode regions. The phosphorus ion implantation energy is 100 keV, and the implantation dose is... After back-side partitioning is completed, activation annealing is performed at a temperature of 900℃ for 60 seconds. After activation annealing, the effective thickness of the N-type buffer layer is 3μm to 5μm, the junction depth of the first P-type collector region and the second P-type collector region is 0.5μm to 0.8μm, and the junction depth of the first N-type cathode region and the second N-type cathode region is 0.4μm to 0.7μm.

[0099] 5. Formation of the back common collector structure

[0100] A back metal layer is deposited on the back side of a silicon-based semiconductor substrate. The back metal layer employs... The composite metal layer has a thickness of 100 nm for the Ti layer, 300 nm for the Ni layer, and 1.5 μm for the Ag layer.

[0101] The back metal layer is located on the back side of the first P-type collector region, the second P-type collector region, the first N-type cathode region, and the second N-type cathode region, forming a back common collector electrode structure and a common collector terminal.

[0102] Through the above implementation steps, a first active region and a second active region separated by a deep trench isolation structure can be formed within the same silicon-based semiconductor substrate. Switching units containing IGBT cell regions and diode cell regions are formed within the two active regions, respectively. Simultaneously, a P-type collector region corresponding to the IGBT cell region, an N-type cathode region corresponding to the diode cell region, and a back metal layer are formed on the back side of the silicon-based semiconductor substrate, allowing the two switching units to share a common back collector structure. Thus, a three-power-terminal bidirectional switching device for bidirectional power conversion circuits is formed within a single silicon-based semiconductor substrate, avoiding the need for back-to-back packaging of two discrete power chips to form a bidirectional switch.

[0103] The foregoing has only described certain exemplary embodiments of the present invention by way of illustration. Undoubtedly, those skilled in the art can modify the described embodiments in various ways without departing from the spirit and scope of the present invention. Therefore, the foregoing drawings and descriptions are illustrative in nature and should not be construed as limiting the scope of protection of the claims of the present invention.

Claims

1. A structure for an IGBT bidirectional switching device, characterized in that, include: A silicon-based semiconductor substrate having a front side and a back side disposed opposite to each other, the silicon-based semiconductor substrate including an N-type epitaxial layer as a drift region; A deep trench isolation structure is formed within the N-type epitaxial layer, dividing the N-type epitaxial layer into a first active region and a second active region; The first switching unit is disposed in the first active region. The first switching unit includes a first IGBT cell region and a first diode cell region. The first IGBT cell region includes a first trench gate structure, a first P-well region, a first N-type emitter region, a first gate metal layer, and a first emitter metal layer. The first diode cell region includes a first P-type anode region. The first emitter metal layer forms a first emitter terminal. The second switching unit is disposed in the second active region. The second switching unit includes a second IGBT cell region and a second diode cell region. The second IGBT cell region includes a second trench gate structure, a second P-well region, a second N-type emitter region, a second gate metal layer and a second emitter metal layer. The second diode cell region includes a second P-type anode region. The second emitter metal layer forms a second emitter terminal. A back-side common collector structure is disposed on the back side of the silicon-based semiconductor substrate. The back-side common collector structure includes an N-type buffer layer, a P-type collector region, an N-type cathode region, and a back-side metal layer. The P-type collector region corresponds to the first IGBT cell region and the second IGBT cell region, and the N-type cathode region corresponds to the first diode cell region and the second diode cell region. The back-side metal layer forms a common collector terminal. The first switching unit and the second switching unit are separated by the deep trench isolation structure and share the back common collector structure; the first transmitting end and the second transmitting end serve as two power connection terminals of the bidirectional energy conversion circuit, and the first transmitting end, the second transmitting end and the common collector end constitute a three-power-terminal bidirectional switching structure.

2. The IGBT bidirectional switching device structure according to claim 1, characterized in that: The deep trench isolation structure is filled with silicon dioxide, and the isolation depth of the deep trench isolation structure is greater than the trench depth of the first trench gate structure and the second trench gate structure, and the deep trench isolation structure does not penetrate the silicon-based semiconductor substrate.

3. The IGBT bidirectional switching device structure according to claim 1, characterized in that: The first IGBT cell region further includes a first carrier storage layer, and the second IGBT cell region further includes a second carrier storage layer; neither the first diode cell region nor the second diode cell region has an N-type emitter region.

4. The IGBT bidirectional switching device structure according to claim 1, characterized in that: The P-type collector region includes a first P-type collector region and a second P-type collector region, and the N-type cathode region includes a first N-type cathode region and a second N-type cathode region; the first P-type collector region corresponds to the first IGBT cell region, the second P-type collector region corresponds to the second IGBT cell region, the first N-type cathode region corresponds to the first diode cell region, and the second N-type cathode region corresponds to the second diode cell region; the back metal layer is located on the back side of the first P-type collector region, the second P-type collector region, the first N-type cathode region, and the second N-type cathode region.

5. A method for fabricating an IGBT bidirectional switching device structure, characterized in that, include: S1. A silicon-based semiconductor substrate is provided, the silicon-based semiconductor substrate having a front side and a back side disposed opposite to each other, the silicon-based semiconductor substrate including an N-type epitaxial layer, the N-type epitaxial layer serving as a drift region; A deep trench is etched on the front side of the silicon-based semiconductor substrate, and a dielectric material is filled in the deep trench to form a deep trench isolation structure. The deep trench isolation structure divides the N-type epitaxial layer into a first active region and a second active region. S2. A front-side cell structure of a first switching unit is formed in the first active region, and a front-side cell structure of a second switching unit is formed in the second active region; wherein, the first switching unit includes a first IGBT cell region and a first diode cell region, and the second switching unit includes a second IGBT cell region and a second diode cell region; the first IGBT cell region is formed with a first trench gate structure, a first P-well region and a first N-type emitter region, the second IGBT cell region is formed with a second trench gate structure, a second P-well region and a second N-type emitter region, the first diode cell region is formed with a first P-type anode region, and the second diode cell region is formed with a second P-type anode region; S3. A metal layer is formed on the front side of the silicon-based semiconductor substrate, and the metal layer is patterned to form a first gate metal layer, a first emitter metal layer, a second gate metal layer, and a second emitter metal layer. S4. The back side of the silicon-based semiconductor substrate is doped to form an N-type buffer layer on the side of the N-type epitaxial layer near the back side, and a P-type collector region and an N-type cathode region are formed on the side of the N-type buffer layer near the back side; the P-type collector region is disposed corresponding to the first IGBT cell region and the second IGBT cell region, and the N-type cathode region is disposed corresponding to the first diode cell region and the second diode cell region; S5. A back metal layer is deposited on the back side of the silicon-based semiconductor substrate to form a back common collector structure and a common collector terminal.

6. The method for fabricating an IGBT bidirectional switching device structure according to claim 5, characterized in that: The dielectric material is silicon dioxide. When forming the deep trench isolation structure, an isolation trench pattern is first formed on the front side of the silicon-based semiconductor substrate, and then the N-type epitaxial layer is dry etched along the isolation trench pattern. Silicon dioxide is deposited in the deep trench obtained by etching and planarized. The bottom of the deep trench isolation structure is lower than the bottom of the first trench gate structure and the second trench gate structure, and the deep trench isolation structure does not penetrate to the back side of the silicon-based semiconductor substrate.

7. The method for fabricating an IGBT bidirectional switching device structure according to claim 5, characterized in that: Both the first trench gate structure and the second trench gate structure are formed by trench etching, gate dielectric layer formation, and polysilicon filling. Before forming the first P-well region and the second P-well region, a first carrier storage layer and a second carrier storage layer are formed in the first IGBT cell region and the second IGBT cell region, respectively. The first P-well region and the first P-type anode region are formed by the same P-type doping step, and the second P-well region and the second P-type anode region are formed by the same P-type doping step. The first N-type emitter region is formed only in the first IGBT cell region, and the second N-type emitter region is formed only in the second IGBT cell region.

8. The method for fabricating an IGBT bidirectional switching device structure according to claim 5, characterized in that: The doping process includes: firstly, performing N-type doping on the back side of the silicon-based semiconductor substrate to form the N-type buffer layer, and then performing P-type doping and N-type doping respectively using a back-side photolithography pattern to form the P-type collector region and the N-type cathode region; the P-type collector region includes a first P-type collector region corresponding to the first IGBT cell region and a second P-type collector region corresponding to the second IGBT cell region, and the N-type cathode region includes a first N-type cathode region corresponding to the first diode cell region and a second N-type cathode region corresponding to the second diode cell region; when forming the back-side common collector structure, the back-side metal layer is formed on the back side of the first P-type collector region, the second P-type collector region, the first N-type cathode region, and the second N-type cathode region.

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