Diamond and gan monolithic hetero-integrated logic power drive circuit and preparation method

Abstract

The application discloses a diamond and GaN monolithic hetero-integrated logic power drive circuit and a preparation method, belongs to the technical field of semiconductor devices, and comprises a substrate, an AlN / GaN buffer layer, a plurality of i-GaN channel layers, an AlGaN barrier layer, a SiN passivation layer, two types of transistors, a gate dielectric layer and a metal interconnection structure. The buffer layer is arranged on the substrate, the channel layers are arranged on the buffer layer in a spaced manner, and an isolation groove extending to the buffer layer is arranged between adjacent channel layers. The barrier layer and the passivation layer are sequentially arranged on the channel layers, the p-type diamond transistor and the n-type GaN transistor are separately arranged, the gate dielectric layer covers the whole region, the metal interconnection is connected with the electrode through a through hole, the two transistors are paired to form a unit multi-stage cascade, the last stage is connected with an output transistor, and the sources of the same type of transistors are commonly connected.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor device technology, specifically relating to diamond and GaN monolithic heterogeneous integrated logic power drive circuits and their fabrication methods. Background Technology

[0002] Gallium nitride (GaN) is a wide bandgap semiconductor that, compared to traditional silicon-based materials, has a wider bandgap, higher electron mobility, faster saturation electron velocity, and better dielectric properties, making it particularly suitable for high-frequency and high-voltage power electronics applications.

[0003] Compared to systems using discrete GaN devices, GaN monolithic integration technology not only offers cost advantages but also effectively suppresses parasitic capacitance and inductance, thereby improving system efficiency and reliability. Currently, mature enhancement-mode products of n-channel GaN high electron mobility transistors (HEMTs) are available.

[0004] However, complementary logic circuits require performance matching between p-channel and n-channel devices. Existing p-channel GaN devices suffer from extremely low hole mobility, difficulty in ohmic contact, low on-state current, high off-state leakage current, and high dynamic losses, resulting in poor high-temperature stability and weak anti-interference capability of the drive circuit. In addition, parasitic effects introduced by packaging interconnects in traditional solutions further deteriorate circuit performance. These problems severely restrict the performance and reliability of complementary logic circuits based on wide-bandgap semiconductors. Summary of the Invention

[0005] The purpose of this invention is to overcome the poor performance and reliability of complementary logic circuits based on wide bandgap semiconductors, and to propose a diamond and GaN monolithic heterogeneous integrated logic power drive circuit and its fabrication method.

[0006] To achieve the above objectives, the present invention adopts the following technical solution: In a first aspect, the present invention provides a diamond / GaN monolithic heterogeneous integrated logic power drive circuit, comprising a substrate, an AlN / GaN buffer layer, multiple i-GaN channel layers, an AlGaN barrier layer, a SiN passivation layer, multiple p-type diamond FETs, multiple n-type GaN HEMTs, a gate dielectric layer, and a metal interconnect structure; the AlN / GaN buffer layer is disposed on the substrate; multiple i-GaN channel layers are spaced apart on the AlN / GaN buffer layer, and an isolation trench extending into the AlN / GaN buffer layer is provided between adjacent i-GaN channel layers; the AlGaN barrier layer covers each i-GaN channel layer, and the SiN passivation layer covers the AlGaN barrier layer; a p-type diamond FET or an n-type GaN HEMT is respectively disposed above each i-GaN channel layer; each p-type diamond FET includes, from bottom to top, a diamond layer and a hydrogen termination layer, the diamond layer being disposed on the SiN passivation layer; the gate dielectric layer covers each hydrogen termination layer, the isolation trench, and each n-type GaN HEMT. HEMT; The gate dielectric layer contains the source, drain, and gate electrodes of each p-type diamond FET. The source and drain electrodes of each p-type diamond FET pass through the gate dielectric layer and contact the hydrogen termination layer. The source, drain, and gate electrodes of each n-type GaN HEMT pass through the SiN passivation layer and contact the AlGaN barrier layer. A metal interconnect structure connects to each electrode: the gate electrode of one p-type diamond FET is electrically connected to the gate electrode of one n-type GaN HEMT, and the drain electrode of one p-type diamond FET is electrically connected to the drain electrode of one n-type GaN HEMT, forming a transistor unit. Multiple transistor units are arranged sequentially, with the drain electrode of the first unit in adjacent groups electrically connected to the gate electrode of the second unit. The drain electrode of the last transistor unit is electrically connected to the gate electrode of an output n-type GaN HEMT. The source electrodes of each p-type diamond FET are electrically connected to each other. The source electrodes of each n-type GaN HEMT are electrically connected to each other.

[0007] Furthermore, the diamond layer of each p-type diamond FET is bonded to the SiN passivation layer; the gate electrode of each p-type diamond FET is disposed on the upper surface of the gate dielectric layer. Each n-type GaN HEMT has vias in the gate dielectric layer above the source electrode, drain electrode, and gate electrode, and the metal interconnect structure passes through the vias to connect to each electrode.

[0008] Furthermore, the gate dielectric layer is made of aluminum oxide; the gate electrode of each p-type diamond FET is made of aluminum; the source and drain electrodes of each p-type diamond FET are made of gold, and both the source and drain electrodes form ohmic contacts with the hydrogen termination layer.

[0009] Furthermore, the source and drain electrodes of each n-type GaN HEMT each include a titanium layer, an aluminum layer, a nickel layer, and a gold layer stacked sequentially from bottom to top, and both the source and drain electrodes form an ohmic contact with the AlGaN barrier layer; the gate electrode of each n-type GaN HEMT each includes a nickel layer and a gold layer stacked sequentially from bottom to top.

[0010] Furthermore, the circuit edge is provided with a stepped structure, which extends downward from the upper surface of the circuit into the interior of the AlN / GaN buffer layer; the inner wall and bottom of the isolation trench are covered with a gate dielectric layer.

[0011] Furthermore, the substrate material is silicon, sapphire, or silicon carbide; the AlN / GaN buffer layer is an AlN buffer layer or a GaN buffer layer.

[0012] Secondly, the present invention provides a method for fabricating a diamond and GaN monolithic heterogeneous integrated logic power drive circuit, comprising the following steps: An AlN / GaN buffer layer, an i-GaN channel layer, and an AlGaN barrier layer are sequentially formed on a substrate to obtain a GaN-based epitaxial wafer. A SiN passivation layer is deposited on a GaN-based epitaxial wafer; A diamond layer is transferred to form a portion of the SiN passivation layer; Etching the GaN-based epitaxial wafer into the AlN / GaN buffer layer forms isolation trenches, resulting in multiple device islands; A hydrogen termination layer is formed on the surface of the diamond layer; Etching removes part of the SiN passivation layer on the device island without the diamond layer, exposing the AlGaN barrier layer, and fabricating the source electrode, drain electrode, and gate electrode of the n-type GaN HEMT. A gate dielectric layer is deposited on the surface of each device island. The gate dielectric layer covers a hydrogen termination layer, an isolation trench, a SiN passivation layer for each n-type GaNHEMT, and each electrode. Etching removes part of the gate dielectric layer above the hydrogen termination layer, forming source / drain vias to expose the hydrogen termination layer; The source and drain electrodes of a p-type diamond FET are fabricated within the source-drain via, and the source and drain electrodes are in contact with a hydrogen termination layer. The gate electrode of a p-type diamond FET is fabricated on a gate dielectric layer above the diamond layer; Etching removes part of the gate dielectric layer above the electrodes of each n-type GaN HEMT to form interconnect vias; Metal interconnect structures are fabricated on the gate dielectric layer, and the metal interconnect structures connect the electrodes through interconnect vias.

[0013] Furthermore, the diamond layer is transferred and patterned through a bonding process; While etching to form isolation trenches, a stepped structure is etched at the edge of the GaN-based epitaxial wafer, and the stepped structure extends downward into the AlN / GaN buffer layer. The surface of the diamond layer is treated with hydrogen plasma to form a hydrogen termination layer.

[0014] Furthermore, after fabricating the source and drain electrodes of the n-type GaN HEMT, an annealing process is performed to form ohmic contacts; both the source and drain electrodes include a titanium layer, an aluminum layer, a nickel layer, and a gold layer stacked sequentially; the gate electrode includes a nickel layer and a gold layer stacked sequentially.

[0015] Furthermore, the source and drain electrodes of the p-type diamond FET are fabricated using gold layers, forming ohmic contacts with the hydrogen termination layer; The gate dielectric layer is formed by deposition of aluminum oxide material; The gate electrode of the p-type diamond FET is made of aluminum. The substrate is made of silicon, sapphire, or silicon carbide. The AlN / GaN buffer layer is formed using AlN or GaN materials.

[0016] Compared with the prior art, the present invention has the following beneficial technical effects: This invention proposes a monolithic heterogeneous integrated logic power drive circuit using diamond and GaN. Diamond possesses extremely high hole mobility and ultra-high thermal conductivity, effectively compensating for the insufficient hole transport capacity and poor heat dissipation performance of p-channel GaN devices. GaN, with its high electron mobility, high critical breakdown field strength, and high-frequency response characteristics, ensures the excellent performance of n-channel devices. Through monolithic heterogeneous integration, this method not only significantly improves the complementary logic circuit in terms of on-state current, switching speed, and power efficiency, but also fundamentally suppresses the self-heating effect under high-power operation by utilizing the efficient heat dissipation channels of diamond. The on-chip integrated logic-power unit can achieve step-by-step amplification from low-voltage logic signals to high-voltage, high-current output, eliminating the need for external driver chips and significantly reducing system latency and parasitic parameters. This invention provides an innovative implementation path for next-generation high-power-density, high-reliability intelligent power integrated circuits. Attached Figure Description

[0017] The accompanying drawings are provided to further understand the invention and constitute a part of this invention. The illustrative embodiments of the invention and their descriptions are used to explain the invention and do not constitute an improper limitation of the invention.

[0018] Figure 1 This is a circuit diagram of the diamond and GaN monolithic heterogeneous integrated logic power drive circuit of the present invention. Figure 2 This is a schematic diagram of the cross-sectional structure of the diamond and GaN monolithic heterogeneous integrated logic power drive circuit of the present invention; Figure 3 yes Figure 2 Top view; Figure 4 This is a schematic diagram of the fabrication process of the diamond and GaN monolithic heterogeneous integrated logic power drive circuit of the present invention.

[0019] Wherein, 1 is the substrate; 2 is the AlN / GaN buffer layer; 3 is the first i-GaN channel layer; 4 is the second i-GaN channel layer; 5 is the third i-GaN channel layer; 6 is the fourth i-GaN channel layer; 7 is the fifth i-GaN channel layer; 8 is the isolation trench; 9 is the first AlGaN barrier layer; 10 is the first SiN passivation layer; 11 is the first Diamond layer; 12 is the first H-terminated layer; 13 is the gate dielectric layer; 14 is the first source electrode; 15 is the first drain electrode; 16 is the first gate electrode; 17 is the second AlGaN barrier layer; 18 is the second SiN passivation layer; 19 is the second source electrode; 20 is the second drain electrode; 21 is the second gate electrode; and 22 is the third i-GaN channel layer. 23 is an AlGaN barrier layer, 24 is a third SiN passivation layer, 25 is a second Diamond layer, 26 is a second H-terminated layer, 27 is a third source electrode, 28 is a third gate electrode, 29 is a fourth AlGaN barrier layer, 30 is a fourth SiN passivation layer, 31 is a fourth source electrode, 32 is a fourth drain electrode, 33 is a fourth gate electrode, 34 is a fifth AlGaN barrier layer, 35 is a fifth SiN passivation layer, 36 is a fifth source electrode, 37 is a fifth drain electrode, 38 is a fifth gate electrode, 39 is a stepped structure, 40 is a first metal interconnect strip, 41 is a second metal interconnect strip, 42 is a third metal interconnect strip, 43 is a fourth metal interconnect strip, and 44 is a fifth metal interconnect strip. Detailed Implementation

[0020] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0021] It should be noted that when an element is referred to as being "set on" another element, it can be directly on the other element or there may be an intervening element. When an element is referred to as being "connected to" another element, it can be directly connected to the other element or there may be an intervening element. The terms "vertical," "horizontal," "left," "right," and similar expressions used herein are for illustrative purposes only and do not represent the only embodiments.

[0022] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. The terminology used herein in the description of the invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0023] It should be noted that the terms "first," "second," etc., in the specification and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0024] Example 1 The diamond and GaN monolithic heterogeneous integrated logic power drive circuit includes a substrate, an AlN / GaN buffer layer, multiple i-GaN channel layers, an AlGaN barrier layer, a SiN passivation layer, multiple p-type diamond field-effect transistors (i.e., p-type diamond FETs), multiple n-channel GaN high electron mobility transistors (i.e., n-type GaN HEMTs), a gate dielectric layer, and a metal interconnect structure. An AlN / GaN buffer layer is disposed on the substrate; multiple i-GaN channel layers are spaced apart on the AlN / GaN buffer layer, and isolation trenches extending into the AlN / GaN buffer layer are provided between adjacent i-GaN channel layers; an AlGaN barrier layer covers each i-GaN channel layer, and a SiN passivation layer covers the AlGaN barrier layer; a p-type diamond field-effect transistor or an n-channel GaN high electron mobility transistor is disposed above each i-GaN channel layer; each p-type diamond field-effect transistor includes a diamond layer and a hydrogen termination layer from bottom to top, with the diamond layer disposed on the SiN passivation layer; a gate dielectric layer covers each hydrogen termination layer, and the source electrode, drain electrode, and gate electrode of each p-type diamond field-effect transistor are disposed on the gate dielectric layer, with the source electrode and drain electrode contacting the hydrogen termination layer through the gate dielectric layer; the source electrode, drain electrode, and gate electrode of each n-channel GaN high electron mobility transistor contact the AlGaN barrier layer through the SiN passivation layer. The gate dielectric layer also covers the isolation trench and each n-channel GaN high electron mobility transistor. Through-holes are formed in the gate dielectric layer above the source, drain, and gate electrodes of each n-channel GaN high electron mobility transistor. Metal interconnect structures are disposed on the gate dielectric layer, passing through the through-holes and connecting to each electrode: the gate electrode of a p-type diamond field-effect transistor is electrically connected to the gate electrode of an n-channel GaN high electron mobility transistor; the drain electrode of the p-type diamond field-effect transistor is electrically connected to the drain electrode of the n-channel GaN high electron mobility transistor, forming a transistor unit. Multiple transistor units are arranged sequentially, with the drain electrode of the first unit in adjacent groups electrically connected to the gate electrode of the second unit; the drain electrode of the last transistor unit is electrically connected to the gate electrode of an output n-channel GaN high electron mobility transistor; the source electrodes of each p-type diamond field-effect transistor are electrically connected to each other; and the source electrodes of each n-channel GaN high electron mobility transistor are electrically connected to each other.

[0025] The diamond layer of each p-type diamond field-effect transistor is bonded to the SiN passivation layer; the gate electrode of each p-type diamond field-effect transistor is located on the upper surface of the gate dielectric layer.

[0026] The gate dielectric layer is made of aluminum oxide; the gate electrode of each p-type diamond field-effect transistor is made of aluminum; the source and drain electrodes of each p-type diamond field-effect transistor are made of gold, and both the source and drain electrodes form ohmic contacts with the hydrogen termination layer.

[0027] Each n-channel GaN high electron mobility transistor has a source electrode and a drain electrode consisting of a titanium layer, an aluminum layer, a nickel layer, and a gold layer stacked sequentially from bottom to top. Both the source electrode and the drain electrode form an ohmic contact with the AlGaN barrier layer. Each n-channel GaN high electron mobility transistor has a gate electrode consisting of a nickel layer and a gold layer stacked sequentially from bottom to top.

[0028] The circuit has a stepped structure at its edge, which extends downward from the upper surface of the circuit into the AlN / GaN buffer layer; the inner wall and bottom of the isolation trench are covered with a gate dielectric layer.

[0029] The substrate material is silicon, sapphire, or silicon carbide; the AlN / GaN buffer layer is an AlN buffer layer or a GaN buffer layer.

[0030] This invention relates to a monolithic heterogeneous integrated logic power drive circuit of diamond and GaN, based on the monolithic heterogeneous integration of a p-type diamond field-effect transistor (P-FET) and an n-channel GaN high electron mobility transistor (HEMT). This circuit features ultra-high thermal conductivity, high frequency, and low power consumption, and can be used as a core electronic component in GaN power device drive circuits. Its circuit schematic and device cross-sectional diagram are shown below. Figure 1 , Figure 2 As shown. This invention fully utilizes the extremely high hole mobility and ultra-high thermal conductivity of diamond, whose excellent heat dissipation capabilities can significantly reduce the self-heating effect of devices under high power density; at the same time, it leverages the high electron mobility, high voltage withstand capability, and high frequency characteristics of GaN, enabling it to achieve high efficiency and low loss in high-voltage, high-frequency operating environments. By complementing the advantages of the two materials and integrating them in a monolithic heterogeneous manner, this invention aims to overcome the performance bottlenecks of existing GaN-based complementary logic circuits, realizing high-performance, high-reliability amplifiers to meet the application requirements of next-generation high-frequency, high-power system architectures.

[0031] Example 2 A method for fabricating a diamond-GaN monolithic heterogeneous integrated logic power drive circuit includes the following steps: An AlN / GaN buffer layer, an i-GaN channel layer, and an AlGaN barrier layer are sequentially formed on a substrate to obtain a GaN-based epitaxial wafer. A SiN passivation layer is deposited on a GaN-based epitaxial wafer; A diamond layer is transferred to form a portion of the SiN passivation layer; Etching the GaN-based epitaxial wafer into the AlN / GaN buffer layer forms isolation trenches, resulting in multiple device islands; A hydrogen termination layer is formed on the surface of the diamond layer; Etching removes part of the SiN passivation layer on the device island without the diamond layer, exposing the AlGaN barrier layer, and fabricating the source electrode, drain electrode, and gate electrode of the n-channel GaN high electron mobility transistor. A gate dielectric layer is deposited on the surface of each device island. The gate dielectric layer covers a hydrogen termination layer, an isolation trench, a SiN passivation layer for each n-channel GaN high electron mobility transistor, and each electrode. Etching removes part of the gate dielectric layer above the hydrogen termination layer, forming source / drain vias to expose the hydrogen termination layer; The source and drain electrodes of a p-type diamond field-effect transistor are fabricated within a source-drain via, and the source and drain electrodes are in contact with a hydrogen termination layer. The gate electrode of a p-type diamond field-effect transistor is fabricated on a gate dielectric layer above the diamond layer; Etching removes part of the gate dielectric layer above the electrodes of each n-channel GaN high electron mobility transistor to form interconnect vias; Metal interconnect structures are fabricated on the gate dielectric layer, and the metal interconnect structures connect the electrodes through interconnect vias.

[0032] The diamond layer is transferred and patterned through a bonding process; While etching to form isolation trenches, a stepped structure is etched at the edge of the GaN-based epitaxial wafer, and the stepped structure extends downward into the AlN / GaN buffer layer. The surface of the diamond layer is treated with hydrogen plasma to form a hydrogen termination layer.

[0033] After fabricating the source and drain electrodes of the n-channel GaN high electron mobility transistor, an annealing process is performed to form ohmic contacts. Both the source and drain electrodes consist of a titanium layer, an aluminum layer, a nickel layer, and a gold layer stacked sequentially. The gate electrode consists of a nickel layer and a gold layer stacked sequentially.

[0034] The source and drain electrodes of the p-type diamond field-effect transistor are fabricated with gold layers and form ohmic contacts with the hydrogen termination layer. The gate dielectric layer is formed by deposition of aluminum oxide material; The gate electrode of the p-type diamond field-effect transistor is made of aluminum. The substrate is made of silicon, sapphire, or silicon carbide. The AlN / GaN buffer layer is formed using AlN or GaN materials.

[0035] Example 3 See Figure 1 , Figure 2 A diamond and GaN monolithic heterogeneous integrated logic power drive circuit includes a substrate 1, an AlN / GaN buffer layer 2 on the substrate 1, a first i-GaN channel layer 3, a second i-GaN channel layer 4, a third i-GaN channel layer 5, a fourth i-GaN channel layer 6, and a fifth i-GaN channel layer 7 on the AlN / GaN buffer layer 2.

[0036] An isolation trench 8 is provided between the first i-GaN channel layer 3 and the second i-GaN channel layer 4, and the isolation trench 8 extends into the AlN / GaN buffer layer 2. An isolation trench 8 is provided between the third i-GaN channel layer 3 and the second i-GaN channel layer 4, and the isolation trench 8 extends into the AlN / GaN buffer layer 2.

[0037] The first i-GaN channel layer 3 is provided with a first AlGaN barrier layer 9, a first SiN passivation layer 10, a first Diamond layer 11, and a first H-terminated layer 12 from bottom to top; the first H-terminated layer 12 is covered with a gate dielectric layer 13. A first source electrode 14, a first drain electrode 15, and a first gate electrode 16 are arranged horizontally on the gate dielectric layer 13. The first source electrode 14 extends through the gate dielectric layer 13 to the first H-terminated layer 12. The first drain electrode 15 extends through the gate dielectric layer 13 to the first H-terminated layer 12. The above structure located on the side of the first i-GaN channel layer 3 forms a first p-type diamond field-effect transistor.

[0038] The second i-GaN channel layer 4 is provided with a second AlGaN barrier layer 17 and a second SiN passivation layer 18 from bottom to top. The second SiN passivation layer 18 is provided with a second source electrode 19, a second drain electrode 20 and a second gate electrode 21 in a horizontal direction. The second source electrode 19 and the second drain electrode 20 extend through the second SiN passivation layer 18 to the second AlGaN barrier layer 17. The second gate electrode 21 extends through the second SiN passivation layer 18 to the second AlGaN barrier layer 17. The above structure located on this side of the second i-GaN channel layer 4 forms a first n-channel GaN high electron mobility transistor. The third i-GaN channel layer 5 is provided with a third AlGaN barrier layer 22, a third SiN passivation layer 23, a second Diamond layer 24, and a second H-terminated layer 25 from bottom to top; the second H-terminated layer 25 is covered with a gate dielectric layer 13. A third source electrode 26, a third drain electrode 27, and a third gate electrode 28 are arranged laterally on the gate dielectric layer 13. The third source electrode 26 extends through the gate dielectric layer 13 to the second H-terminated layer 25. The third drain electrode 27 extends through the gate dielectric layer 13 to the second H-terminated layer 25. The above structure located on the side of the third i-GaN channel layer 3 forms a p-type diamond field-effect transistor. A fourth AlGaN barrier layer 29 and a fourth SiN passivation layer 30 are sequentially arranged from bottom to top on the fourth i-GaN channel layer 6; a fourth source electrode 31, a fourth drain electrode 32 and a fourth gate electrode 33 are sequentially arranged laterally on the fourth SiN passivation layer 30; the fourth source electrode 31 and the fourth drain electrode 32 extend through the fourth SiN passivation layer 30 to the fourth AlGaN barrier layer 29; the fourth gate electrode 33 extends through the fourth SiN passivation layer 30 to the fourth AlGaN barrier layer 29; the above structure located on this side of the fourth i-GaN channel layer 6 forms a second n-channel GaN high electron mobility transistor; A fifth AlGaN barrier layer 34 and a fifth SiN passivation layer 35 are sequentially arranged from bottom to top on the fifth i-GaN channel layer 7; a fifth source electrode 36, a fifth drain electrode 37, and a fifth gate electrode 38 are sequentially arranged laterally on the fifth SiN passivation layer 35; the fifth source electrode 36 and the fifth drain electrode 37 extend through the fifth SiN passivation layer 35 to the fifth AlGaN barrier layer 34; the fifth gate electrode 38 extends through the fifth SiN passivation layer 35 to the fifth AlGaN barrier layer 34; the above structure located on this side of the fifth i-GaN channel layer 7 forms a third n-channel GaN high electron mobility transistor; The isolation trench 8 is covered with a gate dielectric layer 13; the second SiN passivation layer 15, the fourth SiN passivation layer 15, the fifth SiN passivation layer 15, the second source electrode 19, the second drain electrode 20, the second gate electrode 21, the fourth source electrode 31, the fourth drain electrode 32, the fourth gate electrode 33, the fifth source electrode 36, the fifth drain electrode 37, and the fifth gate electrode 38 are all covered with gate dielectric layers 13, and through holes are formed on the gate dielectric layers 13 on the second source electrode 19, the second drain electrode 20, the second gate electrode 21, the fourth source electrode 31, the fourth drain electrode 32, the fourth gate electrode 33, the fifth source electrode 36, the fifth drain electrode 37, and the fifth gate electrode 38; The first gate electrode 16 and the second gate electrode 21 are electrically connected through the first metal interconnect strip 40; the first drain electrode 15, the second drain electrode 20, the third gate electrode 28 and the fourth gate electrode 33 are electrically connected through the second metal interconnect strip 41; the third drain electrode 27, the fourth drain electrode 32 and the fifth gate electrode 38 are electrically connected through the third metal interconnect strip 42; the first source electrode 14 and the third source electrode 26 are electrically connected through the fourth metal interconnect strip 43; the second source electrode 19, the fourth source electrode 31 and the fifth source electrode 36 are electrically connected through the fifth metal interconnect strip 44; the edge of the monolithic heterogeneous integrated logic-power drive circuit has a stepped structure 39, which extends from the surface of the monolithic heterogeneous integrated logic-power drive circuit into the AlN / GaN buffer layer 2.

[0039] in, Figure 3 The first metal interconnect strip 40, the second metal interconnect strip 41, the third metal interconnect strip 42, the fourth metal interconnect strip 43, and the fifth metal interconnect strip 44 are only shown in the figure to illustrate the connection relationship; their specific positional relationships are not limited to these. Figure 3 The examples in the document can be set according to actual needs.

[0040] The first Diamond layer 11 is printed and bonded to the first SiN passivation layer 10, and the second Diamond layer 24 is printed and bonded to the third SiN passivation layer 23, forming a monolithic heterogeneous integration of a p-type diamond field-effect transistor and an n-channel GaN high electron mobility transistor.

[0041] The gate dielectric layer 13 is made of aluminum oxide; the first gate electrode 16 and the third gate electrode 28 are made of aluminum; the first source electrode 14, the first drain electrode 15, the third source electrode 26 and the third drain electrode 27 are all made of gold, and the first source electrode 14 and the first drain electrode 15 form ohmic contacts with the first H-terminated layer 12, and the third source electrode 26 and the third drain electrode 27 form ohmic contacts with the second H-terminated layer 25.

[0042] The thickness of the first Diamond layer 11 and the second Diamond layer 24 is 200 nm. 1μm or 300nm-1μm; the thickness of the first H-terminated layer 12 and the second H-terminated layer 25 is 0.5nm. 1nm or 1nm 2nm; the thickness of the first gate electrode 16 and the third gate electrode 28 is 100nm. 400nm or 100nm 200nm; the thicknesses of the first source electrode 14, the first drain electrode 15, the third source electrode 26, and the third drain electrode 27 are all 100nm. 400nm or 100nm 200nm; the thickness of gate dielectric layer 13 is 15nm. 30nm.

[0043] The materials of the second source electrode 19, the second drain electrode 20, the fourth source electrode 31, the fourth drain electrode 32, the fifth source electrode 36, and the fifth drain electrode 37 all include titanium, aluminum, nickel, and gold stacked from bottom to top. The second source electrode 19 and the second drain electrode 20 respectively form ohmic contacts with the second AlGaN barrier layer 17, the fourth source electrode 31 and the fourth drain electrode 32 respectively form ohmic contacts with the fourth AlGaN barrier layer 29, and the fifth source electrode 36 and the fifth drain electrode 37 respectively form ohmic contacts with the fifth AlGaN barrier layer 34. The materials of the second gate electrode 21, the fourth gate electrode 33, and the fifth gate electrode 38 include nickel and gold stacked from bottom to top.

[0044] The thicknesses of the second source electrode 19, the second drain electrode 20, the fourth source electrode 31, the fourth drain electrode 32, the fifth source electrode 36, and the fifth drain electrode 37 are all 100nm-300nm; the thicknesses of the second gate electrode 21, the fourth gate electrode 33, and the fifth gate electrode 38 are 100nm. 400nm or 120nm 250nm.

[0045] The substrate 1 is made of silicon, silicon carbide, or sapphire, with a thickness of 300μm-1000μm; the AlN buffer layer 2 has a thickness of 100nm-2000nm or the GaN buffer layer has a thickness of 1μm-5μm; the thicknesses of the first i-GaN channel layer 3, the second i-GaN channel layer 4, the third i-GaN channel layer 5, the fourth i-GaN channel layer 6, and the fifth i-GaN channel layer 7 are all 100nm-500nm; the thicknesses of the first AlGaN barrier layer 9, the second AlGaN barrier layer 17, the third AlGaN barrier layer 22, the fourth AlGaN barrier layer 29, and the fifth AlGaN barrier layer 34 are all 15nm-30nm; and the thicknesses of the first SiN passivation layer 10, the second SiN passivation layer 18, the third SiN passivation layer 23, the fourth SiN passivation layer 30, and the fifth SiN passivation layer 35 are all 20nm. 800nm; the thickness of the first metal interconnect strip 40, the second metal interconnect strip 41, the third metal interconnect strip 42, the fourth metal interconnect strip 43, and the fifth metal interconnect strip 44 is 100nm. 1μm.

[0046] Example 4 See Figure 4 The fabrication method of diamond and GaN monolithic heterogeneous integrated logic power drive circuit includes the following steps: Step 1: Prepare a SiN / AlGaN / GaN / AlN / GaN / Si / Sap / SiC substrate.

[0047] An AlN / GaN buffer layer 2, an i-GaN channel layer, an AlGaN barrier layer, and a SiN isolation layer are sequentially epitaxially grown on a Si / Sap / SiC substrate 1 using a metal-organic chemical vapor deposition process to obtain a SiN / AlGaN / GaN / AlN / GaN / Si / Sap / SiC substrate.

[0048] The thickness of the Si / Sap / SiC substrate 10 is 300μm-1000μm; the thickness of the AlN / GaN buffer layer 2 is 100nm-2000nm; the thickness of the i-GaN channel layer is 100nm-500nm; the thickness of the AlGaN barrier layer is 15nm-30nm; and the thickness of the SiN passivation layer is 15nm-20nm.

[0049] Step 2, Deposit SiN passivation layer A SiN layer is deposited on the SiN / AlGaN / GaN / AlN / GaN / Si / Sap / SiC substrate prepared in step 1 using a low-pressure chemical vapor deposition process. The SiN isolation layer prepared in step 1 is combined with this SiN layer and referred to as the SiN passivation layer. The thickness of the SiN passivation layer is 20nm-200nm.

[0050] Step 3: Prepare the diamond thin film product to be transferred on the SOI substrate. The specific preparation process is as follows: 3.1 A microwave plasma chemical vapor deposition process is used to form single-crystal diamond thin film islands on a Si substrate.

[0051] 3.2. Single-crystal diamond film islands are transferred to the SOI wafer by bonding, forming single-crystal diamond film islands on the SOI wafer.

[0052] 3.3 Using a wet etching process, the product obtained in 3.2 is placed in a 49% HF solution to etch away the buried oxide layer that is not covered by the islands of the single-crystal diamond film.

[0053] 3.4. Anchor points are created at the edge of the single-crystal diamond film using photolithography to prevent displacement and detachment of the single-crystal diamond film after the buried oxide layer is completely etched.

[0054] 3.5. Using a wet etching process, the product obtained in 3.4 is placed in a 49% HF solution to completely etch the buried oxide layer, causing the single-crystal diamond film to fall onto the SOI wafer substrate, thus obtaining the single-crystal diamond film product to be transferred.

[0055] Step 4: Transfer the diamond film product to be transferred onto the product prepared in step 3. Using micro-transfer technology, the diamond film of the diamond film product to be transferred is transferred onto the product prepared in step 3 to form a first diamond layer 11 and a second diamond layer 24, with the first diamond layer 11 and the second diamond layer 24 located on one side of the product prepared in step 3. The transfer process is as follows: 4.1 The product prepared in step 3 is placed in acetone, anhydrous ethanol and deionized water for ultrasonic cleaning in sequence, and then dried with a nitrogen gun.

[0056] 4.2. Solid polydimethylsiloxane (PDMS) is bonded to an SOI wafer with the buried oxide layer etched away, and then the two are separated at a speed of 10 cm / s to allow the single crystal diamond film to adhere to the PDMS.

[0057] 4.3. Solid polydimethylsiloxane (PDMS) with a single-crystal diamond film adhered to it is bonded to the product prepared in step 3. The two are then separated at a speed of 1 mm / s to allow the single-crystal diamond film to adhere to the product prepared in step 3, completing the transfer of the single-crystal diamond film. A Diamond layer 11 and a second Diamond layer 24 are formed on the product prepared in step 3. The thickness of the Diamond layer 11 and the second Diamond layer 24 is 300 nm. 1μm.

[0058] Step 5, Etching of isolation trenches An isolation trench 8 is etched to the AlN / GaN buffer layer 2 on one side of the first Diamond layer 11 and the second Diamond layer 24, with a depth of 600nm-700nm.

[0059] Step 6, Table etching Mesa etching is performed on the edge of the product prepared in step 5 to form a stepped structure 39 extending to the AlN buffer layer 2. First Diamond / SiN / AlGaN / GaN / AlN islands, second Diamond / SiN / AlGaN / GaN / AlN islands, first SiN / AlGaN / GaN / AlN islands, second SiN / AlGaN / GaN / AlN islands, and third SiN / AlGaN / GaN / AlN islands are formed on the stepped structure 39 and on both sides of the isolation trench 8, respectively. When multiple devices are used simultaneously, the stepped structure can provide isolation between devices, ensuring that damage to one device will not affect the normal operation of other devices. The mesa etching depth is 800 nm. 900nm.

[0060] The first Diamond / SiN / AlGaN / GaN / AlN island's i-GaN channel layer, AlGaN barrier layer, and SiN passivation layer are respectively the first i-GaN channel layer 3, the first AlGaN barrier layer 9, and the first SiN passivation layer 10; the second Diamond / SiN / AlGaN / GaN / AlN island's i-GaN channel layer, AlGaN barrier layer, and SiN passivation layer are respectively the third i-GaN channel layer 5, the third AlGaN barrier layer 22, and the third SiN passivation layer 23; the first Si .... The N-barrier layer and the SiN passivation layer are respectively the second i-GaN channel layer 4, the second AlGaN barrier layer 17, and the second SiN passivation layer 18; the i-GaN channel layer, AlGaN barrier layer, and SiN passivation layer of the second SiN / AlGaN / GaN / AlN island are respectively the fourth i-GaN channel layer 6, the fourth AlGaN barrier layer 29, and the fourth SiN passivation layer 30; the i-GaN channel layer, AlGaN barrier layer, and SiN passivation layer of the SiN / AlGaN / GaN / AlN island are respectively the fifth i-GaN channel layer 7, the fifth AlGaN barrier layer 34, and the fifth SiN passivation layer 35.

[0061] Step 7: Form an H-terminated layer above the Diamond layer of the first Diamond / SiN / AlGaN / GaN / AlN / GaN island and the second Diamond / SiN / AlGaN / GaN / AlN / GaN island.

[0062] Using plasma chemical vapor deposition (PCVDC), the Diomand layer 11 of the first Diamond / SiN / AlGaN / GaN / AlN / GaN island and the Diomand layer 24 of the second Diamond / SiN / AlGaN / GaN / AlN / GaN island are subjected to high-temperature hydrogen plasma treatment to form the first H-terminated layer 12 and the second H-terminated layer 25, respectively.

[0063] Step 8: Dielectric etching of the source and drain regions of the first, second, and third SiN / AlGaN / GaN / AlN islands. Using photolithography and reactive ion dry etching processes, the second SiN passivation layer 18 at corresponding positions on the source and drain regions of the first SiN / AlGaN / GaN / AlN island is etched away; the fourth SiN passivation layer 30 at corresponding positions on the source and drain regions of the second SiN / AlGaN / GaN / AlN island is etched away; and the fifth SiN passivation layer 35 at corresponding positions on the source and drain regions of the third SiN / AlGaN / GaN / AlN island is etched away.

[0064] Step 9: Fabricate the second, fourth, and fifth source / drain electrodes. The source and drain metal regions on the first, second, and third SiN / AlGaN / GaN / AlN islands were defined using photolithography. Electron beam evaporation was used to sequentially deposit 20 nm thick titanium, 140 nm thick aluminum, 55 nm thick nickel, and 45 nm thick gold metal to form the second source electrode 19, second drain electrode 20, fourth source electrode 31, fourth drain electrode 32, fifth source electrode 36, and fifth drain electrode 37, respectively. The electrodes were then annealed at 850°C in a nitrogen atmosphere for 30 seconds, resulting in ohmic contacts between the second source electrode 19 and the second drain electrode 20 and the second AlGaN barrier layer 17, ohmic contacts between the fourth source electrode 31 and the fourth drain electrode 32 and the second AlGaN barrier layer 29, and ohmic contacts between the fifth source electrode 36 and the fifth drain electrode 37 and the fifth AlGaN barrier layer 34.

[0065] Step 10: Dielectric etching of the gate regions of the first SiN / AlGaN / GaN / AlN island, the second SiN / AlGaN / GaN / AlN island, and the third SiN / AlGaN / GaN / AlN island. Using photolithography and reactive ion dry etching processes, the second SiN passivation layer 23 at the corresponding position on the gate region of the first SiN / AlGaN / GaN / AlN island is etched away, the fourth SiN passivation layer 30 at the corresponding position on the gate region of the second SiN / AlGaN / GaN / AlN island is etched away, and the fifth SiN passivation layer 35 at the corresponding position on the gate region of the third SiN / AlGaN / GaN / AlN island is etched away.

[0066] Step 11: Fabricate the second, fourth, and fifth gate electrodes. The gate metal regions on the first SiN / AlGaN / GaN / AlN island, the second SiN / AlGaN / GaN / AlN island, and the third SiN / AlGaN / GaN / AlN island are defined by photolithography. A 50 nm thick layer of nickel metal and a 200 nm thick layer of gold metal are deposited sequentially using electron beam evaporation to form the second gate electrode 21, the fourth gate electrode 33, and the fifth gate electrode 38.

[0067] Step 12: Fabricate the first source / drain electrode and the third source / drain electrode. The source and drain metal regions on the first H-terminated / Diomand / SiN / AlGaN / GaN / AlN island and the second H-terminated / Diomand / SiN / AlGaN / GaN / AlN island are defined by photolithography. A 100nm thick gold metal is deposited using electron beam evaporation to form the first source electrode 14, the first drain electrode 15, the third source electrode 28, and the third drain electrode 29, respectively. The first source electrode 14 and the first drain electrode 15 form ohmic contacts with the first H-terminated layer 12, and the third source electrode 26 and the third drain electrode 27 form ohmic contacts with the second H-terminated layer 25.

[0068] Step 13, gate dielectric layer growth Aluminum oxide (ANO) was deposited on the surface of the product prepared in step 13 using an atomic layer deposition process under a nitrogen atmosphere to form a gate dielectric layer 13. The thickness of the gate dielectric layer 13 is 20 nm.

[0069] Step 14: Fabricate the first gate electrode and the third gate electrode. The source and drain metal regions on the first H-terminated / Diomand / SiN / AlGaN / GaN / AlN island and the second H-terminated / Diomand / SiN / AlGaN / GaN / AlN island are defined by photolithography, and the first gate 16 and the third gate 28 are formed by depositing 100nm thick aluminum metal using electron beam evaporation.

[0070] Step 15: Etching and opening of the gate dielectric layer. Photolithography and inductively coupled plasma etching processes are used to etch away portions of the gate dielectric layer 13 covering the second gate electrode 21, the second source electrode 19, the second drain electrode 20, the fourth gate electrode 33, the fourth source electrode 31, the fourth drain electrode 32, the fifth gate electrode 38, the fifth source electrode 36, the fifth drain electrode 37, the first source electrode 14, the first drain electrode 15, the third source electrode 26, and the third drain electrode 27 to form vias, thereby exposing portions of the second gate electrode 21, the second source electrode 19, the second drain electrode 20, the fourth gate electrode 33, the fourth source electrode 31, the fourth drain electrode 32, the fifth gate electrode 38, the fifth source electrode 36, the fifth drain electrode 37, the first source electrode 14, the first drain electrode 15, the third source electrode 26, and the third drain electrode 27.

[0071] Step 16, Create Interconnected Metal Using photolithography and electron beam evaporation processes, a 50nm thick layer of nickel metal and a 200nm thick layer of gold metal are sequentially deposited on the gate dielectric layer 13 to form a first metal interconnect strip 40, a second metal interconnect strip 41, a third metal interconnect strip 42, a fourth metal interconnect strip 43, and a fifth metal interconnect strip 44. This forms a metal interconnect between the first gate electrode 16 and the second gate electrode 21, a metal interconnect between the first drain electrode 15, the second drain electrode 20, the third gate electrode 28, and the fourth gate electrode 33, a metal interconnect between the third drain electrode 27, the fourth drain electrode 32, and the fifth gate electrode 38, a metal interconnect between the second source electrode 19, the fourth source electrode 31, and the fifth source electrode 36, and a metal interconnect between the first source electrode 14 and the third source electrode 26. This results in a diamond and GaN monolithic heterogeneous integrated logic power drive circuit based on a p-type diamond field-effect transistor and an n-channel GaN high electron mobility transistor.

[0072] The above content provides a further detailed description of the present invention. It should not be construed that the specific embodiments of the present invention are limited to this. For those skilled in the art, several simple deductions or substitutions can be made without departing from the concept of the present invention, and all such deductions or substitutions should be considered as falling within the protection scope of the present invention as determined by the submitted content.

Claims

1. A diamond and GaN monolithic heterogeneous integrated logic power drive circuit, characterized in that, The system comprises a substrate, an AlN / GaN buffer layer, multiple i-GaN channel layers, an AlGaN barrier layer, a SiN passivation layer, multiple p-type diamond FETs, multiple n-type GaN HEMTs, a gate dielectric layer, and a metal interconnect structure. The AlN / GaN buffer layer is disposed on the substrate. Multiple i-GaN channel layers are spaced apart on the AlN / GaN buffer layer, with isolation trenches extending into the AlN / GaN buffer layer between adjacent i-GaN channel layers. The AlGaN barrier layer covers each i-GaN channel layer, and the SiN passivation layer covers the AlGaN barrier layer. A p-type diamond FET or an n-type GaN HEMT is disposed above each i-GaN channel layer. Each p-type diamond FET, from bottom to top, includes a diamond layer and a hydrogen termination layer, with the diamond layer disposed on the SiN passivation layer. The gate dielectric layer covers each hydrogen termination layer, the isolation trenches, and each n-type GaN HEMT. HEMT; The gate dielectric layer contains the source, drain, and gate electrodes of each p-type diamond FET. The source and drain electrodes of each p-type diamond FET pass through the gate dielectric layer and contact the hydrogen termination layer. The source, drain, and gate electrodes of each n-type GaN HEMT pass through the SiN passivation layer and contact the AlGaN barrier layer. A metal interconnect structure connects to each electrode: the gate electrode of one p-type diamond FET is electrically connected to the gate electrode of one n-type GaN HEMT, and the drain electrode of one p-type diamond FET is electrically connected to the drain electrode of one n-type GaN HEMT, forming a transistor unit. Multiple transistor units are arranged sequentially, with the drain electrode of the first unit in adjacent groups electrically connected to the gate electrode of the second unit. The drain electrode of the last transistor unit is electrically connected to the gate electrode of an output n-type GaN HEMT. The source electrodes of each p-type diamond FET are electrically connected to each other. The source electrodes of each n-type GaN HEMT are electrically connected to each other.

2. The diamond and GaN monolithic heterogeneous integrated logic power drive circuit according to claim 1, characterized in that, The diamond layer of each of the p-type diamond FETs is bonded to the SiN passivation layer; the gate electrode of each of the p-type diamond FETs is disposed on the upper surface of the gate dielectric layer; Each n-type GaN HEMT has vias in the gate dielectric layer above the source electrode, drain electrode, and gate electrode, and the metal interconnect structure passes through the vias to connect to each electrode.

3. The diamond and GaN monolithic heterogeneous integrated logic power drive circuit according to claim 2, characterized in that, The gate dielectric layer is made of aluminum oxide; the gate electrode of each p-type diamond FET is made of aluminum; the source electrode and drain electrode of each p-type diamond FET are made of gold, and the source electrode and the drain electrode form an ohmic contact with the hydrogen termination layer.

4. The diamond and GaN monolithic heterogeneous integrated logic power drive circuit according to claim 1, characterized in that, Each of the n-type GaN HEMTs comprises a titanium layer, an aluminum layer, a nickel layer, and a gold layer stacked sequentially from bottom to top as its source and drain electrodes, and both the source and drain electrodes form an ohmic contact with the AlGaN barrier layer; each of the n-type GaN HEMTs comprises a nickel layer and a gold layer stacked sequentially from bottom to top as its gate electrode.

5. The diamond and GaN monolithic heterogeneous integrated logic power drive circuit according to claim 1, characterized in that, The circuit has a stepped structure at its edge, which extends downward from the upper surface of the circuit into the interior of the AlN / GaN buffer layer; the inner wall and bottom of the isolation trench are covered with the gate dielectric layer.

6. The diamond and GaN monolithic heterogeneous integrated logic power drive circuit according to claim 1, characterized in that, The substrate is made of silicon, sapphire, or silicon carbide; the AlN / GaN buffer layer is an AlN buffer layer or a GaN buffer layer.

7. A method for fabricating a diamond and GaN monolithic heterogeneous integrated logic power drive circuit, characterized in that, Includes the following steps: An AlN / GaN buffer layer, an i-GaN channel layer, and an AlGaN barrier layer are sequentially formed on a substrate to obtain a GaN-based epitaxial wafer. A SiN passivation layer is deposited on the GaN-based epitaxial wafer; A diamond layer is transferred to form a portion of the SiN passivation layer; The GaN-based epitaxial wafer is etched into the AlN / GaN buffer layer to form isolation trenches, resulting in multiple device islands. A hydrogen termination layer is formed on the surface of the diamond layer; Etching removes part of the SiN passivation layer on the device island without the diamond layer, exposing the AlGaN barrier layer, and fabricating the source electrode, drain electrode, and gate electrode of the n-type GaN HEMT. A gate dielectric layer is deposited on the surface of each of the device islands, the gate dielectric layer covering the hydrogen termination layer, the isolation trench, the SiN passivation layer of each of the n-type GaN HEMTs and each electrode; Etching removes a portion of the gate dielectric layer above the hydrogen termination layer to form source / drain vias, exposing the hydrogen termination layer; A source electrode and a drain electrode of a p-type diamond FET are fabricated within the source-drain via, and the source electrode and the drain electrode are in contact with the hydrogen termination layer; A gate electrode for a p-type diamond FET is fabricated on the gate dielectric layer above the diamond layer; Etching removes a portion of the gate dielectric layer above the electrodes of each of the n-type GaN HEMTs to form interconnect vias; A metal interconnect structure is fabricated on the gate dielectric layer, and the metal interconnect structure connects each electrode through the interconnect via.

8. The method for fabricating a diamond and GaN monolithic heterogeneous integrated logic power drive circuit according to claim 7, characterized in that, The diamond layer is transferred and patterned through a bonding process; While etching to form the isolation trench, a stepped structure is etched to form the edge of the GaN-based epitaxial wafer, and the stepped structure extends downward into the AlN / GaN buffer layer. The surface of the diamond layer is treated with hydrogen plasma to form the hydrogen termination layer.

9. The method for fabricating a diamond and GaN monolithic heterogeneous integrated logic power drive circuit according to claim 7, characterized in that, After fabricating the source and drain electrodes of the n-type GaN HEMT, an annealing process is performed to form an ohmic contact. Both the source and drain electrodes comprise sequentially stacked titanium, aluminum, nickel, and gold layers. The gate electrode comprises sequentially stacked nickel and gold layers.

10. The method for fabricating a diamond and GaN monolithic heterogeneous integrated logic power drive circuit according to claim 7, characterized in that, The source and drain electrodes of the p-type diamond FET are fabricated with gold layers and form ohmic contacts with the hydrogen termination layer. The gate dielectric layer is formed by deposition of aluminum oxide material; The gate electrode of the p-type diamond FET is made of aluminum. The substrate is made of silicon, sapphire, or silicon carbide. The AlN / GaN buffer layer is formed using AlN or GaN materials.

Images