Semiconductor device and method of manufacturing the same

Abstract

The application provides a semiconductor device and a preparation method thereof. The semiconductor device comprises a first gate structure formed on an NMOS region, a second gate structure formed on a PMOS region, and an interlayer dielectric layer formed between the first gate structure and the second gate structure. The first gate structure comprises a first gate electrode layer, and the second gate structure comprises a second gate electrode layer. The first gate electrode layer and the second gate electrode layer are both inverted-trapezoidal in shape. The interlayer dielectric layer comprises a first contact hole and a second contact hole. The first contact hole is located in the interlayer dielectric layer on both sides of the first gate structure, and the second contact hole is located in the interlayer dielectric layer on both sides of the second gate structure. By adopting the inverted-trapezoidal first gate electrode layer and the inverted-trapezoidal second gate electrode layer, the capacitance value between the gate and the contact hole is stabilized, thereby improving the device performance.

Description

Technical Field

[0001] This application relates to the field of integrated circuit manufacturing technology, and in particular to a semiconductor device and its fabrication method. Background Technology

[0002] With the continuous development of semiconductor technology, the demand for integrated circuits is increasing, especially for MOS transistors in very large-scale integrated circuits. The size of MOS transistors is constantly shrinking, while the limitations and technical challenges in their fabrication are also increasing. Among these, power consumption and load capacitance become increasingly important as the gate size of MOS transistors shrinks. Research has found that the gate profile affects the capacitance between the gate and the contact hole, thus impacting device performance. Summary of the Invention

[0003] This application provides a semiconductor device and a method for fabricating the same, which at least helps to stabilize the capacitance value between the gate and the contact hole and improve device performance.

[0004] This application provides a semiconductor device, comprising:

[0005] A semiconductor substrate, wherein the semiconductor substrate includes an NMOS region and a PMOS region;

[0006] A first gate structure is formed on the semiconductor substrate of the NMOS region, and the first gate structure includes a first gate electrode layer;

[0007] A second gate structure is formed on the semiconductor substrate of the PMOS region, and the second gate structure includes a second gate electrode layer.

[0008] An interlayer dielectric layer is formed on the semiconductor substrate between the first gate structure and the second gate structure. The interlayer dielectric layer includes a first contact hole and a second contact hole. The first contact hole is located in the interlayer dielectric layer on both sides of the first gate structure, and the second contact hole is located in the interlayer dielectric layer on both sides of the second gate structure.

[0009] Both the first gate electrode layer and the second gate electrode layer have an inverted trapezoidal shape.

[0010] Furthermore, in semiconductor devices, the difference between the top width and the bottom width of the inverted trapezoidal shape is between 4 nanometers and 6 nanometers.

[0011] Another aspect of this application provides a method for fabricating a semiconductor device, comprising:

[0012] A semiconductor substrate is provided, the semiconductor substrate including an NMOS region and a PMOS region, and gate stacking layers are respectively formed on the semiconductor substrate of the NMOS region and the PMOS region. The gate stacking layers include, from bottom to top, a gate functional layer, a pseudo gate layer, a first hard mask layer and an isolation layer.

[0013] Using the isolation layer and the first hard mask layer as a mask, the dummy gate layer is selectively etched to give the dummy gate layer an inverted trapezoidal shape and to form a step between the dummy gate layer and the first gate functional layer.

[0014] Remove the isolation layer and the first hard mask layer;

[0015] A sidewall is formed, which covers the sidewall of the dummy gate layer and the gate functional layer;

[0016] A second hard mask layer and an interlayer dielectric layer are formed, wherein the second hard mask layer covers the semiconductor substrate, the sidewalls and the dummy gate layer, and the interlayer dielectric layer covers the second hard mask layer;

[0017] The first chemical mechanical polishing process is performed, and the polishing stops on the pseudo-gate layer;

[0018] Remove the dummy gate layer to form a gate recess;

[0019] A metal gate material layer is formed, which covers the interlayer dielectric layer and fills the gate recess;

[0020] A second chemical mechanical polishing process is performed, with polishing stopping on the interlayer dielectric layer to form a metal gate having an inverted trapezoidal morphology;

[0021] Contact holes are formed on the interlayer dielectric layer, and the contact holes are located on the semiconductor substrates on both sides of the metal gate.

[0022] Furthermore, in the semiconductor device fabrication method, an anisotropic dry etching process is employed during the selective etching of the dummy gate layer.

[0023] Furthermore, in the method for fabricating a semiconductor device, the step of forming gate stacked layers on the semiconductor substrates of the NMOS region and the PMOS region respectively includes:

[0024] The gate functional material layer, the dummy gate material layer, the first hard mask material layer, the isolation material layer, the APF material layer, the NFDARC material layer, the barrier material layer, and the first BARC material layer are formed sequentially.

[0025] A first photolithography process is performed to form patterned first photoresist layers on the NMOS region and the PMOS region, respectively.

[0026] Using the patterned first photoresist layer as a mask, the first BARC material layer, the barrier material layer, and the NFDARC material layer are etched to form the first BARC layer, the barrier layer, and the NFDARC layer.

[0027] Remove the patterned first photoresist layer, the first BARC layer, and the barrier layer;

[0028] Using the NFDARC layer as a mask, the APF material layer is etched to form the APF layer, and then the NFDARC layer is removed.

[0029] Using the APF layer as a mask, the isolation material layer and the first hard mask material layer are etched to form the isolation layer and the first hard mask layer, and then the APF layer is removed.

[0030] Furthermore, in the method for fabricating a semiconductor device, the step of forming gate stacked layers on the semiconductor substrates of the NMOS region and the PMOS region respectively further includes:

[0031] A SOC material layer and a second BARC material layer are sequentially spin-coated, wherein the SOC material layer covers the dummy gate material layer and the isolation layer, and the second BARC material layer covers the SOC material layer;

[0032] A second photolithography process is performed to form a patterned second photoresist layer, which is located above the isolation layer;

[0033] Using the patterned second photoresist layer as a mask, the second BARC material layer and the SOC material layer are etched to form the second BARC layer and the SOC layer.

[0034] Using the patterned second photoresist layer, BARC layer and SOC layer as a mask, the pseudo gate material layer and the gate functional material layer are etched to form the pseudo gate layer and the gate functional layer.

[0035] Remove the patterned second photoresist layer, second BARC layer, and SOC layer to form a gate stack layer.

[0036] Furthermore, in the method for fabricating a semiconductor device, the metal gate material layer comprises a first tantalum nitride, a titanium nitride, a second tantalum nitride, a titanium nitride-titanium composite layer, and aluminum, formed sequentially.

[0037] Furthermore, in the method for fabricating a semiconductor device, the gate functional material layer comprises a high-k dielectric layer material and a work function metal layer material formed sequentially.

[0038] Furthermore, in the semiconductor device fabrication method, both the first hard mask layer and the second hard mask layer are made of silicon nitride.

[0039] Furthermore, in the method for fabricating semiconductor devices, both the isolation material layer and the barrier material layer are silicon oxide.

[0040] The technical solution provided in this application includes a semiconductor device comprising a first gate structure formed on the semiconductor substrate in the NMOS region and a second gate structure formed on the semiconductor substrate in the PMOS region. The first gate structure includes a first gate electrode layer, and the second gate structure includes a second gate electrode layer. An interlayer dielectric layer is formed on the semiconductor substrate between the first gate structure and the second gate structure. The interlayer dielectric layer includes a first contact hole and a second contact hole. The first contact hole is located in the interlayer dielectric layers on both sides of the first gate structure, and the second contact hole is located in the interlayer dielectric layers on both sides of the second gate structure. Both the first gate electrode layer and the second gate electrode layer have an inverted trapezoidal shape. By employing an inverted trapezoidal shape for the first and second gate electrode layers, the capacitance value between the gate and the contact hole is stabilized, thereby improving device performance. Attached Figure Description

[0041] One or more embodiments are illustrated by way of example with corresponding pictures in the accompanying drawings. These illustrations do not constitute a limitation on the embodiments. Unless otherwise stated, the pictures in the accompanying drawings do not constitute a limitation on scale. In order to more clearly illustrate the technical solutions in the embodiments of this application or in the conventional technology, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0042] Figure 1 A cross-sectional schematic diagram of a semiconductor device provided in an embodiment of this application;

[0043] Figure 2 An electron microscope image of a gate structure provided in an embodiment of this application;

[0044] Figure 3 A schematic flowchart illustrating a method for fabricating a semiconductor device according to an embodiment of this application;

[0045] Figures 4A to 4G A cross-sectional schematic diagram of step S1 in the method for fabricating a semiconductor device provided in the embodiments of this application;

[0046] Figure 5A cross-sectional schematic diagram of step S2 in the method for fabricating a semiconductor device provided in the embodiments of this application;

[0047] Figure 6 This is a cross-sectional schematic diagram of steps S3 to S5 in the method for fabricating a semiconductor device provided in the embodiments of this application;

[0048] Figure 7 A cross-sectional schematic diagram of step S6 in the method for fabricating a semiconductor device provided in the embodiments of this application;

[0049] Figure 8 A cross-sectional schematic diagram of step S7 in the method for fabricating a semiconductor device provided in the embodiments of this application;

[0050] Figure 9 A cross-sectional schematic diagram of step S8 in the method for fabricating a semiconductor device provided in the embodiments of this application;

[0051] Figure 10 A cross-sectional schematic diagram of step S9 in the method for fabricating a semiconductor device provided in the embodiments of this application;

[0052] Figure 11 This is a cross-sectional schematic diagram of step S10 in the method for fabricating a semiconductor device provided in the embodiments of this application.

[0053] Explanation of icon numbers:

[0054] Figure 1 : 100-Semiconductor substrate, 101-NMOS region, 102-PMOS region, 200A-First gate structure, 201A-First gate electrode layer, 202A-First sidewall, 200B-Second gate structure, 201B-Second gate electrode layer, 202B-Second sidewall, 300-Interlayer dielectric layer, 301-First contact hole, 302-Second contact hole;

[0055] Figures 4A to 1010 - Semiconductor substrate, 01 - NMOS region, 02 - PMOS region, 11a - High-k dielectric layer material, 12a - Work function metal layer material, 13a - Pseudo-gate material layer, 14a - First hard mask material layer, 15a - Isolation material layer, 16a - APF material layer, 17a - NFDARC material layer, 18a - Barrier material layer, 19a - First BARC material layer, 20 - Patterned first photoresist layer, 11 - High-k dielectric layer, 12 13-Work function metal layer, 14-Dummy gate layer, 15-First hard mask layer, 16-Isolation layer, 17-APF layer, 18-NFDARC layer, 19-Block layer, 20-First BARC layer, 21-SOC layer, 22-Second BARC layer, 23-Patterned second photoresist layer, 24-Sidewall, 25-Second hard mask layer, 26-Interlayer dielectric layer, A-Gate trench, 27a-Metal gate material layer, 27-Metal gate, 28-Contact hole. Detailed Implementation

[0056] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0057] As the gate size of MOS transistors continues to shrink, the issue of dynamic power consumption becomes increasingly prominent. According to the dynamic power consumption formula: P = α·C·V²·f, where P represents dynamic power consumption, α represents the switching activity factor, C represents the load capacitance, V represents the supply voltage, and f represents the operating frequency. The main contributing factors to dynamic power consumption are switching power consumption, which is proportional to the frequency, the load capacitance, and the square of the voltage. Reducing the load capacitance C can effectively reduce the dynamic power consumption P. The contact-to-gate capacitance (CGC) is a key component of the load capacitance C; therefore, optimizing the gate structure affects the contact-to-gate capacitance (CGC) value, thus impacting device performance and dynamic power consumption.

[0058] Based on this, such as Figure 1 As shown, Figure 1This is a cross-sectional schematic diagram of a semiconductor device provided in an embodiment of this application. The semiconductor device provided in this embodiment includes at least: a semiconductor substrate 100, a first gate structure 200A, a second gate structure 200B, and an interlayer dielectric layer 300. The semiconductor substrate includes an NMOS region 101 and a PMOS region 102; the first gate structure 200A is formed on the semiconductor substrate 100 in the NMOS region 101, and the first gate structure 200A includes a first gate electrode layer 201A; the second gate structure 200B is formed on the semiconductor substrate 100 in the PMOS region 102, and the second gate structure 200B includes a second gate electrode layer 202B; wherein, both the first gate electrode layer 201A and the second gate electrode layer 201B have an inverted trapezoidal morphology. An interlayer dielectric layer 300 is formed on a semiconductor substrate 100 between a first gate structure 200A and a second gate structure 200NB. The interlayer dielectric layer 300 includes a first contact hole 301 and a second contact hole 302. The first contact hole 301 is located in the interlayer dielectric layers 300 on both sides of the first gate structure 200A, and the second contact hole 302 is located in the interlayer dielectric layers 300 on both sides of the second gate structure 200B.

[0059] The technical solution of this application improves device performance by using a first gate electrode layer 201A and a second gate electrode layer 201B with an inverted trapezoidal shape to stabilize the capacitance value between the gate and the contact hole.

[0060] As an example, the first gate structure 200A further includes a first sidewall 202A located on the sidewall of the first gate electrode layer 201A. The second gate structure 200B further includes a second sidewall 202B located on the sidewall of the second gate electrode layer 201B.

[0061] In this embodiment, the first gate electrode layer 201A and the second gate electrode layer 201B can both be pseudo gate layers or both be metal gates.

[0062] As an example, such as Figure 2 As shown, Figure 2 This is an electron microscope image of a gate structure provided in an embodiment of this application. The difference between the top width and the bottom width of the inverted trapezoidal morphology is between 4 nanometers and 6 nanometers. For example, the top width of the inverted trapezoidal morphology is 36.6 nanometers, and the bottom width is 30.6 nanometers.

[0063] Figure 3 This is a schematic flowchart illustrating a method for fabricating a semiconductor device according to an embodiment of this application. This method is used to fabricate the aforementioned semiconductor device. The method for fabricating a semiconductor device according to an embodiment of this application includes:

[0064] S1. A semiconductor substrate is provided, the semiconductor substrate including an NMOS region and a PMOS region, and gate stacking layers are formed on the semiconductor substrates of the NMOS region and the PMOS region, respectively. The gate stacking layers include, from bottom to top, a gate functional layer, a pseudo gate layer, a first hard mask layer and an isolation layer.

[0065] S2. Using the isolation layer and the first hard mask layer as a mask, selectively etch the dummy gate layer so that the dummy gate layer has an inverted trapezoidal morphology and forms a step between it and the gate functional layer.

[0066] S3. Remove the isolation layer and the first hard mask layer;

[0067] S4. Form sidewalls, which cover the sidewalls of the pseudo-gate layer and the gate functional layer;

[0068] S5. A second hard mask layer and an interlayer dielectric layer are formed sequentially. The second hard mask layer covers the semiconductor substrate, sidewalls, and dummy gate layer, and the interlayer dielectric layer covers the second hard mask layer.

[0069] S6. Perform the first chemical mechanical polishing process, and polishing stops on the dummy gate layer;

[0070] S7. Remove the dummy gate layer to form a gate groove;

[0071] S8. Form a metal gate material layer, which covers the interlayer dielectric layer and fills the gate trench;

[0072] S9. Perform the second chemical mechanical polishing process, and stop polishing on the interlayer dielectric layer to form a metal gate with an inverted trapezoidal morphology.

[0073] S10. A contact hole is formed on the interlayer dielectric layer, and the contact hole is located on the semiconductor substrate on both sides of the metal gate.

[0074] The embodiments of this application will be described in more detail below with reference to the accompanying drawings.

[0075] First, execute step S1, such as... Figure 4G As shown, a semiconductor substrate 10 is provided. The semiconductor substrate 10 includes an NMOS (N-type Field Effect Transistor) region 01 and a PMOS (P-type Field Effect Transistor) region 02. Gate stacked layers are formed on the semiconductor substrate 10 of the NMOS region 01 and the PMOS region 02, respectively. The gate stacked layers include, from bottom to top, a gate functional layer, a pseudo gate layer 13, a first hard mask layer 14 and an isolation layer 15.

[0076] NMOS device region 03 and PMOS device region 04 are also formed on the semiconductor substrate 10. Shallow trench (STI) isolation regions are formed between the NMOS and PMOS regions, between NMOS region 01 and NMOS device region 03, and between PMOS region 02 and PMOS device region 04. The semiconductor substrate can be monocrystalline silicon, polycrystalline silicon, or germanium-silicon compound, or other materials suitable as semiconductor substrates. In addition, the semiconductor substrate can include other structures depending on the device configuration.

[0077] In one embodiment, the step of forming gate stacked layers on the semiconductor substrates in the NMOS and PMOS regions respectively includes:

[0078] like Figure 4A As shown, a gate functional material layer, a pseudo gate material layer 13a, a first hard mask material layer 14a, an isolation material layer 15a, an APF (Advanced Patterning Film) material layer 16a, an NFDARC (Nitrogen Free Dielectric Anti-Reflective Coating) material layer 17a, a barrier material layer 18a, and a first BARC (Bottom Anti-Reflective Coating) material layer 19a are formed sequentially.

[0079] Further, the gate functional material layer includes a high-k dielectric layer material 11a and a work function metal layer material 12a formed sequentially. The high-k dielectric layer material 11a can be hafnium dioxide (HfO), and the work function metal layer material 12a can be titanium nitride (TiN). The isolation material layer 15a and the barrier material layer 18a are both silicon oxide (SiO2). Among them, the barrier material layer 18 is CAP OX. The first hard mask material layer is silicon nitride (SiN). The dummy gate material layer in this step is amorphous silicon (A-Si).

[0080] Continue to refer to the appendix Figure 4A The first photolithography process is performed to form patterned first photoresist layers 20 on NMOS region 01 and PMOS region 02, respectively.

[0081] like Figure 4B As shown, using the patterned first photoresist layer 20 as a mask, the first BARC material layer 19, the barrier material layer 18, and the NFDARC material layer 17 are etched to form the first BARC layer 19, the barrier layer 18, and the NFDARC layer 17.

[0082] The first BARC layer 19 is a graphical first BARC material layer 19a. The barrier layer 18 is a graphical barrier material layer 18a. The NFDARC layer 17 is a graphical NFDARC material layer 17a.

[0083] like Figure 4C As shown, the patterned first photoresist layer 20, first BARC layer 19, and barrier layer 18 are removed.

[0084] like Figure 4D As shown, using NFDARC layer 17 as a mask, APF material layer 16a is etched to form APF layer 16, and NFDARC layer 17 is removed.

[0085] like Figure 4E As shown, using the APF layer 16 as a mask, the isolation material layer 15a and the first hard mask material layer 14a are etched to form the isolation layer 15 and the first hard mask layer 14, and the APF layer 16 is removed.

[0086] In one embodiment, the step of forming gate stacked layers on the semiconductor substrates 10 in NMOS region 01 and PMOS region 02 respectively further includes:

[0087] like Figure 4F As shown, a SOC (Spin-On Carbon) material layer 21a and a second BARC material layer 22a are spin-coated sequentially. The SOC material layer 21a covers the dummy gate material layer 13a, the isolation layer 15 and the first hard mask layer 14, and the second BARC material layer 22a covers the SOC material layer 21a.

[0088] Continue to refer to Figure 4F A second photolithography process is performed to form a patterned second photoresist layer 23, which is located on the second BARC material layer 22a above the isolation layer 15.

[0089] like Figure 4G As shown, using the patterned second photoresist layer 23 as a mask, the second BARC material layer 22a and the SOC material layer 21a are etched to form the second BARC layer 22 and the SOC layer 21.

[0090] Continue to refer to Figure 4G Using the patterned second photoresist layer 23, second BARC layer 22 and SOC layer 21 as a mask, the dummy gate material layer 13a and gate functional material layer are etched to form the dummy gate layer 13 and the gate functional layer, and the patterned second photoresist layer 23, second BARC layer 22 and SOC layer 21 are removed to form a gate stack.

[0091] In this step, an ashing process can be used to remove the patterned second photoresist layer 23, first BARC layer 22, and SOC layer 21.

[0092] Next, proceed to step S2, such as... Figure 5 As shown, using the isolation layer 15 and the first hard mask layer 14 as a mask, the dummy gate layer 13 is selectively etched so that the dummy gate layer 13 has an inverted trapezoidal morphology and forms a step between it and the gate functional layer.

[0093] In step S2, an anisotropic dry etching process is used to selectively etch the dummy gate layer 13.

[0094] Next, proceed to step S3, such as... Figure 6 As shown, the isolation layer 15 and the first hard mask layer 14 are removed.

[0095] The isolation layer 15 is made of silicon oxide and can be removed using hydrofluoric acid. The first hard mask layer 14 is made of silicon nitride and can be removed using hot phosphoric acid.

[0096] Next, proceed to step S4 and continue referring to... Figure 6 Sidewall 24 is formed, which covers the sidewalls of the pseudo-gate layer 13 and the gate functional layer.

[0097] In this embodiment, the material of the sidewall 24 can be at least one of silicon nitride and silicon oxide.

[0098] Since the pseudo-gate layer 13 has an inverted trapezoidal shape and forms a step with the gate functional layer, the inner wall of the formed sidewall 24 is inclined inward along the depth direction and forms a step shape with the sidewall region of the gate functional layer sidewall.

[0099] After forming the sidewall 24, an annealing process is performed to form source / drain regions on the semiconductor substrate 10 on the side of the sidewall 24. After the annealing process, the amorphous silicon material of the dummy gate layer 13 is transformed into polycrystalline silicon.

[0100] Next, proceed to step S5 and continue referring to... Figure 6 A second hard mask layer 25 and an interlayer dielectric layer 26 are formed sequentially. The second hard mask layer 25 covers the semiconductor substrate 10, the sidewall 24 and the dummy gate layer 13, and the interlayer dielectric layer 26 covers the second hard mask layer 25.

[0101] In this embodiment, the second hard mask layer 25 is made of silicon nitride. The interlayer dielectric layer 26 is made of silicon oxide.

[0102] Next, proceed to step S6, such as... Figure 7 As shown, a first chemical mechanical polishing process is performed, and polishing stops on the dummy gate layer 13. Thus, after the first chemical mechanical polishing process, the top surface of the dummy gate layer 13 is exposed.

[0103] Next, proceed to step S7, such as... Figure 8 As shown, the dummy gate layer 13 is removed to form a gate recess A.

[0104] Optionally, a wet etching process is performed to remove the dummy gate layer 13. The etching solution used in the wet etching process is diluted TMAH (tetramethylammonium hydroxide) to remove the dummy gate layer 13. Optionally, a dry etching process is performed to remove the dummy gate layer 13. The dry etching gas is a mixture of HBr (hydrogen bromide) and a small amount of oxygen.

[0105] Next, proceed to step S8, such as... Figure 9 As shown, a metal gate material layer 27a is formed, which covers the interlayer dielectric layer 26 and fills the gate recess A.

[0106] Furthermore, the material of the metal gate material layer 27a may include a first tantalum nitride (TaN), a titanium nitride (TiN), a second tantalum nitride (TaN), a titanium nitride-titanium composite layer (TiAl / Al), and aluminum (Al) formed sequentially.

[0107] Next, proceed to step S9, such as... Figure 10 As shown, a second chemical mechanical polishing process is performed, and polishing stops on the interlayer dielectric layer 26 to form a metal gate 27, which has an inverted trapezoidal morphology.

[0108] Next, proceed to step S10, as follows: Figure 11 As shown, a contact hole 28 is formed on the interlayer dielectric layer 26, and the contact hole 28 is located on the semiconductor substrate 10 on both sides of the metal gate 27a.

[0109] Specifically, contact holes are formed on the source and drain regions of NMOS region 01 and PMOS region 02, respectively, and the contact holes are used to form plugs for the source and drain regions.

[0110] The resulting semiconductor device has an inverted trapezoidal metal gate, which stabilizes the capacitance between the gate and the contact hole and improves the device performance.

[0111] Those skilled in the art will understand that the above embodiments are specific examples of implementing this application, and in practical applications, various changes in form and detail can be made without departing from the spirit and scope of this application. Any person skilled in the art can make various alterations and modifications without departing from the spirit and scope of this application; therefore, the scope of protection of this application should be determined by the scope defined in the claims.

Claims

1. A semiconductor device, characterized in that, include: A semiconductor substrate, wherein the semiconductor substrate includes an NMOS region and a PMOS region; A first gate structure is formed on the semiconductor substrate of the NMOS region, and the first gate structure includes a first gate electrode layer; A second gate structure is formed on the semiconductor substrate of the PMOS region, and the second gate structure includes a second gate electrode layer. An interlayer dielectric layer is formed on the semiconductor substrate between the first gate structure and the second gate structure. The interlayer dielectric layer includes a first contact hole and a second contact hole. The first contact hole is located in the interlayer dielectric layer on both sides of the first gate structure, and the second contact hole is located in the interlayer dielectric layer on both sides of the second gate structure. Both the first gate electrode layer and the second gate electrode layer have an inverted trapezoidal shape.

2. The semiconductor device according to claim 1, characterized in that, The difference between the top width and the bottom width of the inverted trapezoidal shape is between 4 nanometers and 6 nanometers.

3. A method for fabricating a semiconductor device, used to form the semiconductor device according to any one of claims 1 to 2, characterized in that, include: A semiconductor substrate is provided, the semiconductor substrate including an NMOS region and a PMOS region, and gate stacking layers are respectively formed on the semiconductor substrate of the NMOS region and the PMOS region. The gate stacking layers include, from bottom to top, a gate functional layer, a pseudo gate layer, a first hard mask layer and an isolation layer. Using the isolation layer and the first hard mask layer as a mask, the dummy gate layer is selectively etched to give the dummy gate layer an inverted trapezoidal shape and to form a step between the dummy gate layer and the gate functional layer. Remove the isolation layer and the first hard mask layer; A sidewall is formed, which covers the sidewall of the dummy gate layer and the gate functional layer; A second hard mask layer and an interlayer dielectric layer are formed, wherein the second hard mask layer covers the semiconductor substrate, the sidewalls and the dummy gate layer, and the interlayer dielectric layer covers the second hard mask layer; The first chemical mechanical polishing process is performed, and the polishing stops on the pseudo-gate layer; Remove the dummy gate layer to form a gate recess; A metal gate material layer is formed, which covers the interlayer dielectric layer and fills the gate recess; A second chemical mechanical polishing process is performed, with polishing stopping on the interlayer dielectric layer to form a metal gate having an inverted trapezoidal morphology; Contact holes are formed on the interlayer dielectric layer, and the contact holes are located on the semiconductor substrates on both sides of the metal gate.

4. The method for fabricating a semiconductor device according to claim 3, characterized in that, During the selective etching of the dummy gate layer, an anisotropic dry etching process is employed.

5. The method for fabricating a semiconductor device according to claim 3, characterized in that, The step of forming gate stacked layers on the semiconductor substrates of the NMOS region and the PMOS region respectively includes: The gate functional material layer, the dummy gate material layer, the first hard mask material layer, the isolation material layer, the APF material layer, the NFDARC material layer, the barrier material layer, and the first BARC material layer are formed sequentially. A first photolithography process is performed to form patterned first photoresist layers on the NMOS region and the PMOS region, respectively. Using the patterned first photoresist layer as a mask, the first BARC material layer, the barrier material layer, and the NFDARC material layer are etched to form the first BARC layer, the barrier layer, and the NFDARC layer. Remove the patterned first photoresist layer, the first BARC layer, and the barrier layer; Using the NFDARC layer as a mask, the APF material layer is etched to form the APF layer, and then the NFDARC layer is removed. Using the APF layer as a mask, the isolation material layer and the first hard mask material layer are etched to form the isolation layer and the first hard mask layer, and then the APF layer is removed.

6. The method for fabricating a semiconductor device according to claim 5, characterized in that, The step of forming gate stacked layers on the semiconductor substrates of the NMOS region and the PMOS region respectively further includes: A SOC material layer and a second BARC material layer are sequentially spin-coated, wherein the SOC material layer covers the dummy gate material layer and the isolation layer, and the second BARC material layer covers the SOC material layer; A second photolithography process is performed to form a patterned second photoresist layer, which is located above the isolation layer; Using the patterned second photoresist layer as a mask, the second BARC material layer and the SOC material layer are etched to form the second BARC layer and the SOC layer. Using the patterned second photoresist layer, BARC layer and SOC layer as a mask, the pseudo gate material layer and the gate functional material layer are etched to form the pseudo gate layer and the gate functional layer. Remove the patterned second photoresist layer, second BARC layer, and SOC layer to form a gate stack layer.

7. The method for fabricating a semiconductor device according to claim 3, characterized in that, The metal gate material layer includes a first tantalum nitride, a titanium nitride, a second tantalum nitride, a titanium nitride-titanium composite layer, and aluminum, which are formed sequentially.

8. The method for fabricating a semiconductor device according to claim 3, characterized in that, The gate functional material layer comprises a high-k dielectric layer material and a work function metal layer material formed sequentially.

9. The method for fabricating a semiconductor device according to claim 3, characterized in that, Both the first hard mask layer and the second hard mask layer are made of silicon nitride.

10. The method for fabricating a semiconductor device according to claim 5, characterized in that, Both the insulating material layer and the barrier material layer are silicon oxide.

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