Semiconductor device

Abstract

A semiconductor device includes a plurality of lower sheet patterns spaced apart from each other in a first direction, and a plurality of upper sheet patterns spaced apart from each other in the first direction on the plurality of lower sheet patterns. The semiconductor device has a gate electrode structure surrounding each of the plurality of lower sheet patterns and each of the plurality of upper sheet patterns, and extending in a second direction intersecting the first direction. A lower gate contact is disposed below the gate electrode structure in the first direction and superposed with the plurality of lower sheet patterns. A first liner film is disposed on a side surface of the lower gate contact, wherein a width of the gate electrode structure in the second direction can decrease downward along the first direction.

Description

Technical Field

[0001] This disclosure relates to semiconductor devices. Background Technology

[0002] Semiconductor devices are core components for controlling or amplifying electrical signals in electronic devices, and various types of semiconductor devices can be manufactured. For example, memory devices are primarily used for storing and retrieving data, while non-memory devices can be used to control or amplify electrical signals. Semiconductor devices are core components of electronic devices and play a vital role in various fields, including computers, communication equipment, and consumer electronics.

[0003] With industrial development, the performance and functional requirements of electronic devices are constantly increasing. Therefore, high-performance characteristics of semiconductor devices are essential, and to meet these requirements, the integration density of semiconductor devices is increasing. Various methods are being researched for forming semiconductor devices with excellent performance and improved integration density. Summary of the Invention

[0004] The objective of this disclosure is to provide a semiconductor device with improved electrical characteristics and integration density.

[0005] Another objective of this disclosure is to provide a method for manufacturing semiconductor devices with improved electrical characteristics and integration density.

[0006] According to some embodiments of this disclosure, a semiconductor device may include: a plurality of lower wafer patterns spaced apart from each other in a first direction; a plurality of upper wafer patterns spaced apart from each other in the first direction on the plurality of lower wafer patterns; a gate electrode structure surrounding each of the plurality of lower wafer patterns and each of the plurality of upper wafer patterns, and the gate electrode structure extending in a second direction intersecting the first direction; a lower gate contact disposed below the gate electrode structure and superimposed on the plurality of lower wafer patterns in the first direction; and a first liner disposed on a side surface of the lower gate contact, wherein the width of the gate electrode structure in the second direction may decrease downward along the first direction.

[0007] According to some embodiments of this disclosure, a semiconductor device may include: a plurality of lower wafer patterns spaced apart from each other in a first direction; a plurality of upper wafer patterns spaced apart from each other in the first direction on the plurality of lower wafer patterns; a gate electrode structure surrounding each of the plurality of lower wafer patterns and each of the plurality of upper wafer patterns, and the gate electrode structure extending in a second direction intersecting the first direction; a gate insulating film disposed between the plurality of upper wafer patterns and the gate electrode structure, and between the plurality of lower wafer patterns and the gate electrode structure; a lower gate contact disposed below the gate electrode structure; a lower source / drain pattern disposed on one side of the plurality of lower wafer patterns; a lower source / drain contact connected to the lower source / drain pattern and extending to the lower surface of the lower source / drain pattern; and a first liner and a second liner disposed between the lower gate contact and the lower source / drain contact, wherein the lower gate contact and the lower source / drain contact may be stacked on top of each other in a third direction, the third direction intersecting each of the first direction and the second direction.

[0008] According to some embodiments of this disclosure, a semiconductor device may include: a plurality of lower wafer patterns spaced apart from each other in a first direction; a plurality of upper wafer patterns spaced apart from each other in the first direction above the plurality of lower wafer patterns; a gate electrode structure surrounding each of the plurality of lower wafer patterns and each of the plurality of upper wafer patterns, and the gate electrode structure extending in a second direction intersecting the first direction; a lower gate contact disposed below the gate electrode structure in the first direction and stacked with the plurality of lower wafer patterns; a first substrate disposed on a side surface of the lower gate contact; and a lower source / drain pattern disposed on one side of the plurality of lower wafer patterns. An upper source / drain pattern is disposed on one side of the plurality of upper patterns; a lower source / drain contact is connected to the lower source / drain pattern; a second liner is disposed between the lower source / drain contact and the first liner; a gate separator structure extends upward in a third direction and is disposed on the side surface of the gate electrode structure, the third direction intersecting each of the first and second directions; and a gate insulating film may be disposed between the plurality of lower patterns and the gate electrode structure, between the plurality of upper patterns and the gate electrode structure, and between the first liner and the gate electrode structure, wherein the lower source / drain contact may be stacked with the lower gate contact in a third-direction upward direction.

[0009] According to some embodiments of this disclosure, a method of manufacturing a semiconductor device includes: forming a plurality of lower wafer patterns and a plurality of upper wafer patterns on a lower pattern of a substrate, the plurality of lower wafer patterns being spaced apart from each other in a first direction, and the plurality of upper wafer patterns being spaced apart from the plurality of lower wafer patterns in the first direction; forming a preliminary semiconductor pattern disposed on the substrate and a lower source / drain pattern disposed on the preliminary semiconductor pattern; forming a gate insulating film on the plurality of lower wafer patterns and the plurality of upper wafer patterns; forming a gate electrode structure surrounding each of the plurality of lower wafer patterns and the plurality of upper wafer patterns and extending in a second direction intersecting the first direction; forming a first liner on the gate insulating film; forming a lower source / drain contact connected to the lower source / drain pattern; and forming a lower gate contact disposed on the first liner, stacked with the plurality of lower wafer patterns in the first direction, and connected to the gate electrode structure.

[0010] According to some embodiments, the step of forming the first liner may include: removing the lower pattern to expose the gate insulating film; and forming the first liner on the exposed gate insulating film.

[0011] According to some embodiments, the method of manufacturing a semiconductor device may further include: forming a first substrate on a gate insulating film, and then forming a sacrificial insulating pattern on the first substrate; forming a first trench by using the sacrificial insulating pattern as an etch mask to remove part of the gate electrode structure; and forming a gate separation structure on the first trench.

[0012] According to some embodiments, the step of forming a lower gate contact may include: forming a second trench by removing a portion of a first liner, a portion of a gate insulating film, and a portion of a gate electrode structure; and forming a lower gate contact on the second trench.

[0013] According to some implementations, the side surface of the second trench may include a first portion and a second portion with different slopes.

[0014] According to some embodiments, the step of forming a lower source / drain contact may include: removing a pre-formed semiconductor pattern to expose the lower source / drain pattern; forming a second substrate on the lower surface of the lower source / drain pattern and on a first substrate; removing a portion of the second substrate; and forming the lower source / drain contact on the second substrate and the lower source / drain pattern.

[0015] According to some embodiments, the first liner and the second liner may be disposed between the lower source / drain contact and the lower gate contact.

[0016] According to some implementations, the lower gate contact and the lower source / drain contact may be stacked on top of each other in a third direction, the third direction intersecting each of the first and second directions.

[0017] According to some embodiments, the first liner may be made of different materials than the plurality of lower sheet patterns.

[0018] According to some implementations, the first liner may surround the side surface of the lower gate contact.

[0019] According to some embodiments of this disclosure, the area of ​​the gate electrode structure can be reduced by providing a lower gate contact to be stacked with the plurality of wafer patterns. Therefore, the electrical characteristics and integration density of the semiconductor device can be improved. Attached Figure Description

[0020] The above and other embodiments and features of this disclosure will become clearer by referring to the accompanying drawings and describing the exemplary embodiments in detail.

[0021] Figure 1 This is an exemplary plan view illustrating a semiconductor device according to some embodiments of the present disclosure.

[0022] Figure 2 It shows along Figure 1 A cross-sectional view of the cut taken by line A-A'.

[0023] Figure 3 It shows along Figure 1 A cross-sectional view of the cut taken by line B-B'.

[0024] Figure 4 It is shown Figure 3 A magnified view of region Q1.

[0025] Figure 5 It is shown Figure 3 A magnified view of region Q1.

[0026] Figure 6 This is a view illustrating a semiconductor device according to some embodiments of the present disclosure.

[0027] Figure 7 This is a view illustrating a semiconductor device according to some embodiments of the present disclosure.

[0028] Figure 8 This is a view illustrating a semiconductor device according to some embodiments of the present disclosure.

[0029] Figure 9 This is a view illustrating a semiconductor device according to some embodiments of the present disclosure.

[0030] Figure 10 This is a view illustrating a semiconductor device according to some embodiments of the present disclosure.

[0031] Figure 11 and Figure 12 This is a view illustrating a semiconductor device according to some embodiments of the present disclosure.

[0032] Figures 13 to 32 This is a view illustrating a method of manufacturing a semiconductor device according to some embodiments of the present disclosure.

[0033] Figures 33 to 42 This is a view illustrating a method of manufacturing a semiconductor device according to some embodiments of the present disclosure. Detailed Implementation

[0034] In this disclosure, the terms "upper," "lower," "upper surface," and "lower surface" are provided for ease of interpretation and are not intended to limit the disclosure. The terms "upper," "lower," "upper surface," and "lower surface" are described based on the accompanying drawings, and the terms specifying vertical relationships may be changed when the drawings are inverted or rotated.

[0035] As used herein, the term “at least one of…” may mean and cover all possible combinations of one or more of the associated listed items. For example, “at least one of A, B or C” means that all of the following are possible: (i) at least one of A; (ii) at least one of B; (iii) at least one of C; (iv) at least one of A and at least one of B; (v) at least one of B and at least one of C; (vi) at least one of A and at least one of C; or (vii) at least one of A, at least one of B and at least one of C, wherein A, B and C may be singular or plural.

[0036] In the following, with reference to the accompanying drawings, a semiconductor device and a method of manufacturing a semiconductor device according to some embodiments of the present disclosure will be described in detail.

[0037] Figure 1 This is an exemplary plan view illustrating a semiconductor device according to some embodiments of the present disclosure. Figure 2 It shows along Figure 1 A cross-sectional view of the cut taken by line A-A'. Figure 3 It shows along Figure 1 A cross-sectional view of the cut taken by line B-B'. Figure 4 It is shown Figure 3 A magnified view of region Q1. Figure 5 It is shown Figure 3 A magnified view of region Q1. For reference, Figure 1 It is concentrated in the gate electrode structure GS, the lower gate contact 125 and the lower source / drain contact 160.

[0038] Reference Figures 1 to 5A semiconductor device according to some embodiments may include a plurality of lower wafer patterns NS1, a plurality of upper wafer patterns NS2, a gate electrode structure GS, a lower gate contact 125, a first liner film 292, a lower source / drain pattern 150, a lower source / drain contact 160, a second liner film 294, an intermediate interlayer insulating film 200, an intermediate insulating pattern 202, an upper source / drain pattern 250, an upper source / drain contact 260, a gate cover pattern 270, a gate spacer 275, and a gate separation structure 310.

[0039] Semiconductor devices according to some embodiments may include metal-oxide-semiconductor field-effect transistors (MOSFETs), and more specifically, may include three-dimensional multi-stacked semiconductor devices referred to as gate-all-around (GAA) transistors or multi-bridge channel field-effect transistors (MBCFETs).

[0040] The active region AP can be a region in which multiple lower wafer patterns NS1, lower source / drain patterns 150, multiple upper wafer patterns NS2, and upper source / drain patterns 250, as described below, are disposed. The active region AP may extend in a first direction D1. The first direction D1 may intersect with a second direction D2. For example, the first direction D1 may be perpendicular to the second direction D2. A third direction D3 may intersect with each of the first direction D1 and the second direction D2. For example, the third direction D3 may be perpendicular to each of the first direction D1 and the second direction D2.

[0041] Multiple substrate patterns NS1 may be disposed on the active region AP. Each of the multiple substrate patterns NS1 may be spaced apart from each other on a third-direction D3. Each of the multiple substrate patterns NS1 may have a nanosheet shape. Although two substrate patterns NS1 are shown, this disclosure is not limited thereto.

[0042] Each die pattern NS1 may include one of elemental semiconductors (e.g., silicon (Si)), IV-IV compound semiconductors (e.g., silicon-germanium (SiGe)), and / or III-V compound semiconductors. IV-IV compound semiconductors may be, for example, binary or ternary compounds comprising at least two of carbon (C), silicon (Si), germanium (Ge), and tin (Sn). III-V compound semiconductors may be, for example, binary, ternary, and / or quaternary compounds formed by combining at least one group III element (aluminum (Al), gallium (Ga), or indium (In)) with a group V element (phosphorus (P), arsenic (As), or antimony (Sb)).

[0043] Multiple bottom-mount patterns NS1 may include a first bottom-mount pattern NS1_1 and a second bottom-mount pattern NS1_2. The first bottom-mount pattern NS1_1 may be disposed on the second bottom-mount pattern NS1_2. The second bottom-mount pattern NS1_2 may be disposed on the lower gate contact 125, as will be described below.

[0044] The widths of the first lower cover pattern NS1_1 and the second lower cover pattern NS1_2 in the second direction D2 are not constant. For example, the widths of the first lower cover pattern NS1_1 and the second lower cover pattern NS1_2 in the second direction D2 may increase as they move further away from the gate cover pattern 270. In a cross-sectional view, each of the first lower cover pattern NS1_1 and the second lower cover pattern NS1_2 may have a tapered side surface.

[0045] Multiple upper pattern NS2 can be set on the active region AP. Multiple upper pattern NS2 can be spaced apart from multiple lower pattern NS1 on the third direction D3. Multiple upper pattern NS2 can be superimposed on multiple lower pattern NS1 on the third direction D3.

[0046] Each of the plurality of top sheet patterns NS2 may have a nanosheet shape. Each of the plurality of top sheet patterns NS2 may be spaced apart from each other on a third-direction D3. Although two top sheet patterns NS2 are shown, this disclosure is not limited thereto.

[0047] The material description of the upper pattern NS2 may be the same as that of the lower pattern NS1. In some embodiments, the material of the upper pattern NS2 may be the same as that of the lower pattern NS1. However, this disclosure is not limited thereto. For example, the material of the upper pattern NS2 may be different from that of the lower pattern NS1.

[0048] Multiple upper sheet patterns NS2 may include a first upper sheet pattern NS2_1 and a second upper sheet pattern NS2_2. The first upper sheet pattern NS2_1 may be disposed on the second upper sheet pattern NS2_2. The second upper sheet pattern NS2_2 may be disposed on the intermediate insulating pattern 202.

[0049] The widths of the first upper pattern NS2_1 and the second upper pattern NS2_2 in the second direction D2 are not constant. For example, the widths of the first upper pattern NS2_1 and the second upper pattern NS2_2 in the second direction D2 may increase as they move further away from the gate cover pattern 270. In terms of cross-section, each of the first upper pattern NS2_1 and the second upper pattern NS2_2 may have a tapered shape. The widths of the plurality of upper patterns NS2 in the second direction D2 may be smaller than the widths of the plurality of lower patterns NS1 in the second direction D2, but this disclosure is not limited thereto.

[0050] An intermediate insulating pattern 202 may be disposed between a plurality of upper wafer patterns NS2 and a plurality of lower wafer patterns NS1. The intermediate insulating pattern 202 may be stacked on a third-direction D3 with the plurality of upper wafer patterns NS2 and the plurality of lower wafer patterns NS1. The intermediate insulating pattern 202 may include an insulating material. For example, the intermediate insulating pattern 202 may include silicon nitride. However, this disclosure is not limited thereto.

[0051] In some embodiments, the intermediate insulation pattern 202 may be omitted. In the location where the intermediate insulation pattern 202 is omitted, an upper pattern NS2 or a lower pattern NS1 may be provided.

[0052] The gate electrode structure GS can be disposed on the intermediate insulating pattern 202, multiple lower wafer patterns NS1, and multiple upper wafer patterns NS2. The gate electrode structure GS can surround the intermediate insulating pattern 202, multiple lower wafer patterns NS1, and multiple upper wafer patterns NS2. The gate electrode structure GS can extend in the second direction D2. The gate electrode structure GS can intersect with the active region AP.

[0053] The width of the gate electrode structure GS in the second direction D2 is not constant. For example, the width of the gate electrode structure GS in the second direction D2 may decrease downward along the third direction D3. In other words, the width of the gate electrode structure GS in the second direction D2 may decrease as it moves further away from the gate cover pattern 270, as will be described below. In terms of cross-section, the gate electrode structure GS may have a tapered shape.

[0054] The gate electrode structure GS may include a first metal pattern 120, a second metal pattern 220 and a third metal pattern 230.

[0055] A first metal pattern 120 may be disposed on a plurality of lower pattern NS1. The first metal pattern 120 may surround the plurality of lower pattern NS1. The first metal pattern 120 may surround four surfaces of each lower pattern NS1. For example, the first metal pattern 120 may surround the upper surface, lower surface and two side surfaces of each lower pattern NS1. Here, the upper surface and lower surface of each lower pattern NS1 represent surfaces facing each other in a third direction D3, and the two side surfaces of each lower pattern NS1 represent surfaces facing each other in a second direction D2.

[0056] The first metal pattern 120 may be disposed between the second lower plate pattern NS1_2 and the lower gate contact 125. The first metal pattern 120 may also be disposed between the second lower plate pattern NS1_2 and the first lower plate pattern NS1_1. The first metal pattern 120 may also be disposed between the first lower plate pattern NS1_1 and the intermediate insulating pattern 202. The first metal pattern 120 may be disposed on the upper surface and side surface of the lower gate contact 125. For example, the first metal pattern 120 may be disposed between the side surface of the lower gate contact 125 and the gate separation structure 310.

[0057] A second metal pattern 220 may be disposed on the first metal pattern 120. In some embodiments, the second metal pattern 220 may contact the first metal pattern 120. For example, the lower surface of the second metal pattern 220 may contact the upper surface of the first metal pattern 120. However, this disclosure is not limited thereto. For example, the second metal pattern 220 may be spaced apart from the first metal pattern 120 in a third direction D3, and an insulating layer may be disposed between the second metal pattern 220 and the first metal pattern 120. In some embodiments, an intermediate insulating pattern 202 may be disposed between the first metal pattern 120 and the second metal pattern 220. The first metal pattern 120 and the second metal pattern 220 may surround the intermediate insulating pattern 202.

[0058] The second metal pattern 220 may surround a plurality of upper patterns NS2. The second metal pattern 220 may surround four surfaces of each upper pattern NS2. For example, the second metal pattern 220 may surround the upper surface, lower surface, and two side surfaces of each upper pattern NS2. Here, the upper and lower surfaces of each upper pattern NS2 represent surfaces facing each other in a third direction D3, and the two side surfaces of each upper pattern NS2 represent surfaces facing each other in a second direction D2.

[0059] The second metal pattern 220 can be disposed between the second upper pattern NS2_2 and the intermediate insulating pattern 202. The second metal pattern 220 can also be disposed between the second upper pattern NS2_2 and the first upper pattern NS2_1.

[0060] In some embodiments, each of the first metal pattern 120 and the second metal pattern 220 may be a work-function modulating film for regulating the threshold voltage of a transistor using a gate electrode structure GS as the gate electrode. The first metal pattern 120 may be a different conductive work-function modulating film than the second metal pattern 220. For example, the first metal pattern 120 may be a p-type work-function modulating film, and the second metal pattern 220 may be an n-type work-function modulating film. In another example, the first metal pattern 120 may be an n-type work-function modulating film, and the second metal pattern 220 may be a p-type work-function modulating film.

[0061] The first metal pattern 120 may include at least one of Mo, Pd, Ru, Pt, TiN, WN, TaN, Ir, TaC, RuN, and / or MoN. The second metal pattern 220 may include at least one of TiAlC, TiAlN, TiAlC-N, TiAl, TaAlC, TaAlN, TaAlC-N, and / or TaAl, but this disclosure is not limited thereto.

[0062] The third metal pattern 230 may be disposed on the second metal pattern 220. Although the third metal pattern 230 is shown not in contact with the first metal pattern 120, the present disclosure is not limited thereto. For example, the third metal pattern 230 may be disposed on the side surface of the first metal pattern 120.

[0063] The third metal pattern 230 may include at least one of the following: metal, metal alloy, conductive metal nitride, metal silicide, doped semiconductor material, conductive metal oxide, and / or conductive metal nitride. For example, the third metal pattern 230 may include titanium nitride (TiN), tantalum carbide (TaC), tantalum nitride (TaN), titanium silicon nitride (TiSiN), tantalum silicon nitride (TaSiN), titanium titanium nitride (TaTiN), titanium aluminum nitride (TiAlN), tantalum aluminum nitride (TaAlN), tungsten nitride (WN), ruthenium (Ru), titanium aluminum (TiAl), titanium aluminum carbonitride (TiAlC-N), titanium aluminum carbide (TiAlC), titanium carbide (TiC), tantalum carbonitride (TaCN), tungsten (W), and aluminum. The materials may include at least one of the following: Al, copper (Cu), cobalt (Co), titanium (Ti), tantalum (Ta), nickel (Ni), platinum (Pt), nickel-platinum (Ni-Pt), niobium (Nb), niobium nitride (NbN), niobium carbide (NbC), molybdenum (Mo), molybdenum nitride (MoN), molybdenum carbide (MoC), tungsten carbide (WC), rhodium (Rh), palladium (Pd), iridium (Ir), osmium (Os), silver (Ag), gold (Au), zinc (Zn), vanadium (V), and / or combinations thereof, but this disclosure is not limited thereto. Conductive metal oxides and conductive metal nitrides may include the oxidized forms of the above-described materials, but this disclosure is not limited thereto.

[0064] The gate insulating film 130 can be disposed between the gate electrode structure GS and multiple lower wafer patterns NS1, between the gate electrode structure GS and multiple upper wafer patterns NS2, and between the gate electrode structure GS and the intermediate insulating pattern 202. For example, the gate insulating film 130 can be disposed between the first metal pattern 120 and multiple lower wafer patterns NS1. The gate insulating film 130 can be disposed between the second metal pattern 220 and multiple upper wafer patterns NS2. The gate insulating film 130 can be disposed on the first substrate 292. The gate insulating film 130 can be disposed between the first metal pattern 120 and the lower source / drain pattern 150, and between the second metal pattern 220 and the upper source / drain pattern 250.

[0065] In some embodiments, the gate insulating film 130 may include multiple films. For example, the gate insulating film 130 may include an interface insulating film and a high-k insulating film. The interface insulating film may include, for example, silicon oxide. The high-k insulating film may include a high-k material having a dielectric constant greater than that of the interface insulating film. The high-k insulating film may include at least one of boron nitride, hafnium oxide, hafnium silicon oxide, hafnium aluminum oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanate, barium titanate, strontium titanate, yttrium oxide, aluminum oxide, lead scandium tantalate, and / or lead zinc niobate.

[0066] A lower gate contact 125 may be disposed on the gate electrode structure GS. For example, the lower gate contact 125 may be disposed below the gate electrode structure GS and may be connected to the gate electrode structure GS. For example, the lower gate contact 125 may be connected to the first metal pattern 120. In some embodiments, the lower gate contact 125 may extend through the lower surface of the first metal pattern 120. One end of the lower gate contact 125 may be disposed in the first metal pattern 120.

[0067] The lower gate contact 125 may be stacked on a third direction D3 with each of a plurality of lower die patterns NS1 and a plurality of upper die patterns NS2. The lower gate contact 125 may be aligned on a third direction D3 with the plurality of lower die patterns NS1 and a plurality of upper die patterns NS2. For example, the plurality of lower die patterns NS1 and the plurality of upper die patterns NS2 may be sequentially disposed on the lower gate contact 125.

[0068] The width of the lower gate contact 125 in the second direction D2 is not constant. For example, the width of the lower gate contact 125 in the second direction D2 may increase as it moves further away from the plurality of underlying patterns NS1. In another example, the width of the lower gate contact 125 in the second direction D2 may remain constant and then increase as it moves further away from the plurality of underlying patterns NS1. In other words, as... Figure 4As shown, the width of the upper portion of the lower gate contact 125 in the second direction D2 can remain constant, and the width of the lower portion of the lower gate contact 125 in the second direction D2 can increase as it moves further away from the plurality of lower die patterns NS1.

[0069] The lower gate contact 125 may include a first side surface 125_SS1, a second side surface 125_SS2, a third side surface 125_SS3, and a fourth side surface 125_SS4. The first side surface 125_SS1 of the lower gate contact 125 may face the second side surface 125_SS2 in the second direction D2. The third side surface 125_SS3 of the lower gate contact 125 may face the fourth side surface 125_SS4 in the first direction D1.

[0070] like Figure 4 As shown, the first side surface 125_SS1 and the second side surface 125_SS2 of the lower gate contact 125 may include a first portion P1 and a second portion P2. Since the description of the second side surface 125_SS2 of the lower gate contact 125 is the same as the description of the first side surface 125_SS1, the following description focuses on the first side surface 125_SS1. The first portion P1 of the first side surface 125_SS1 may have a first slope, and the second portion P2 of the first side surface 125_SS1 may have a second slope. The first slope may be different from the second slope. For example, the first slope may be greater than the second slope.

[0071] In some embodiments, each of the first side surface 125_SS1 and the second side surface 125_SS2 of the lower gate contact 125 may have a constant slope. For example... Figure 5 As shown, in terms of cross-section, each of the first side surface 125_SS1 and the second side surface 125_SS2 of the lower gate contact 125 may have a linear shape.

[0072] The lower gate contact 125 may include a gate contact barrier film 122 and a gate contact fill film 124. The gate contact barrier film 122 may define a side surface of the lower gate contact 125. The gate contact fill film 124 may be disposed in the gate contact barrier film 122.

[0073] The gate contact barrier film 122 may include, for example, one of tantalum (Ta), tantalum nitride (TaN), titanium (Ti), titanium nitride (TiN), ruthenium (Ru), cobalt (Co), nickel (Ni), nickel boride (NiB), tungsten (W), tungsten nitride (WN), tungsten carbonitride (WCN), zirconium (Zr), zirconium nitride (ZrN), vanadium (V), vanadium nitride (VN), niobium (Nb), niobium nitride (NbN), platinum (Pt), iridium (Ir), and rhodium (Rh). The gate contact filler film 124 may include, for example, one of aluminum (Al), tungsten (W), cobalt (Co), ruthenium (Ru), and molybdenum (Mo), but this disclosure is not limited thereto.

[0074] A first liner 292 may surround a side surface of the lower gate contact 125. The first liner 292 may be disposed on a side surface of the lower gate contact 125. For example, the first liner 292 may be disposed on a first side surface 125_SS1, a second side surface 125_SS2, a third side surface 125_SS3, and a fourth side surface 125_SS4 of the lower gate contact 125. The first liner 292 may be disposed on a portion of a first portion P1 and a second portion P2 of the first side surface 125_SS1. In some embodiments, the first liner 292 may contact the first side surface 125_SS1 to the fourth side surface 125_SS4 of the lower gate contact 125.

[0075] The upper surface 292_US of the first liner 292 may be disposed at a lower vertical height than the upper surface 125_US of the lower gate contact 125. In this disclosure, vertical height refers to the vertical height in a third direction D3. Vertical height may represent the distance from a reference height to the surface of a particular structure in the third direction D3. The reference height may correspond to the vertical height of the upper or lower surface of any structure having a flat surface. One end of the lower gate contact 125 may protrude from the upper surface 292_US of the first liner 292 in the third direction D3. The lower gate contact 125 may extend through the upper surface 292_US of the first liner 292. The lower gate contact 125 may extend through the gate insulating film 130 disposed on the upper surface 292_US of the first liner 292.

[0076] A gate insulating film 130 may be disposed between the first substrate 292 and the gate electrode structure GS. The gate insulating film 130 may be disposed on the first substrate 292. For example, the gate insulating film 130 may be disposed on the upper surface 292_US of the first substrate 292 and on two side surfaces in the second direction D2. The gate insulating film 130 disposed on the upper surface 292_US of the first substrate 292 may contact the lower gate contact 125.

[0077] The width of the first backing film 292 in the second direction D2 may increase as it moves further away from the plurality of lower sheet patterns NS1. The width of the first backing film 292 in the second direction D2 may be equal to or greater than the width of the plurality of lower sheet patterns NS1 in the second direction D2. For example, the width W1 of the upper surface 292_US of the first backing film 292 in the second direction D2 may be equal to or greater than the width W2 of the lower surface of the second lower sheet pattern NS1_2 in the second direction D2. In one example, the width of the first backing film 292 in the second direction D2 may be equal to or greater than the width of each of the plurality of lower sheet patterns NS1 in the second direction D2.

[0078] The first backing film 292 may be made of different materials with the plurality of underlying patterns NS1. The first backing film 292 may include an insulating material. For example, the first backing film 292 may include one of silicon nitride (SiN), silicon oxynitride (SiON), silicon carbonitride (SiCN), and silicon carbonitride oxynitride (SiOCN). However, this disclosure is not limited thereto.

[0079] The lower source / drain pattern 150 can be disposed on the active region AP. The lower source / drain pattern 150 can be disposed on the side surface of multiple lower die patterns NS1. The lower source / drain pattern 150 can be connected to the multiple lower die patterns NS1. A portion of the side surface of the lower source / drain pattern 150 can contact the lower die pattern NS1, and another portion can contact the gate insulating film 130. The lower source / drain pattern 150 can be disposed on one side of the gate electrode structure GS.

[0080] The lower source / drain pattern 150 can be an epitaxial pattern formed by a selective epitaxial growth process using multiple lower patterns NS1 as seeds. The lower source / drain pattern 150 can be used as the source or drain of a transistor that uses multiple lower patterns NS1 as the channel region.

[0081] An insulating capping layer 205 may be disposed on the lower source / drain pattern 150. The insulating capping layer 205 may cover the upper surface of the lower source / drain pattern 150. The material description of the insulating capping layer 205 may be the same as the material description of the etch stop film 285.

[0082] Intermediate interlayer insulating film 200 may be disposed on insulating capping layer 205. Intermediate interlayer insulating film 200 may be disposed between insulating capping layer 205 and upper source / drain pattern 250. Intermediate interlayer insulating film 200 may be disposed on the side surface of intermediate insulating pattern 202. In some embodiments, a portion of intermediate interlayer insulating film 200 may be superimposed on intermediate insulating pattern 202 in a first direction D1. Intermediate interlayer insulating film 200 may include insulating material. The description of the material of intermediate interlayer insulating film 200 may be the same as the description of the material of upper interlayer insulating film 280.

[0083] The upper source / drain pattern 250 can be disposed on the active region AP. The upper source / drain pattern 250 can be disposed on the intermediate interlayer insulating film 200. The upper source / drain pattern 250 can be disposed on the side surface of multiple upper patterns NS2. The upper source / drain pattern 250 can be connected to multiple upper patterns NS2. A portion of the side surface of the upper source / drain pattern 250 can contact the upper pattern NS2, and another portion can contact the gate insulating film 130. The upper source / drain pattern 250 can be disposed on one side of the gate electrode structure GS. The upper source / drain pattern 250 can be stacked with the lower source / drain pattern 150 on the third-direction D3.

[0084] The upper source / drain pattern 250 can be an epitaxial pattern formed by a selective epitaxial growth process using multiple upper pattern NS2 as seeds. The upper source / drain pattern 250 can be used as the source or drain of a transistor that uses multiple upper pattern NS2 as the channel region.

[0085] Each of the lower source / drain pattern 150 and the upper source / drain pattern 250 may include a semiconductor material. For example, each of the lower source / drain pattern 150 and the upper source / drain pattern 250 may include elemental semiconductor silicon (Si) or germanium (Ge). Each of the lower source / drain pattern 150 and the upper source / drain pattern 250 may also include a binary or ternary group IV compound or a group IV doped compound thereof comprising at least two of carbon (C), silicon (Si), germanium (Ge), and / or tin (Sn). For example, each of the lower source / drain pattern 150 and the upper source / drain pattern 250 may include silicon (Si), silicon-germanium (SiGe), germanium (Ge), or silicon carbide (SiC), but this disclosure is not limited thereto.

[0086] Each of the lower source / drain pattern 150 and the upper source / drain pattern 250 may include a dopant doped in a semiconductor material. The dopant may include at least one of boron (B), phosphorus (P), carbon (C), arsenic (As), antimony (Sb), bismuth (Bi), and / or oxygen (O), without limitation. In some embodiments, the lower source / drain pattern 150 and the upper source / drain pattern 250 may include dopants with different conductivity types.

[0087] For ease of description, each of the lower source / drain pattern 150 and the upper source / drain pattern 250 is shown as a single film, but this disclosure is not limited thereto. In some embodiments, each of the lower source / drain pattern 150 and the upper source / drain pattern 250 may comprise multiple films comprising different materials. In some embodiments, each of the lower source / drain pattern 150 and the upper source / drain pattern 250 may comprise multiple layers of the same material and constituent materials with different concentrations.

[0088] The lower source / drain contact 160 may be disposed on the lower source / drain pattern 150. The lower source / drain contact 160 may be disposed below the lower source / drain pattern 150. The lower source / drain contact 160 may extend through the lower surface of the lower source / drain pattern 150. One end of the lower source / drain contact 160 may be disposed within the lower source / drain pattern 150. For example, the upper surface of the lower source / drain contact 160 may be disposed within the lower source / drain pattern 150. The lower source / drain contact 160 may be electrically connected to the lower source / drain pattern 150.

[0089] The lower source / drain contact 160 may be aligned with the lower gate contact 125 in the first direction D1. The lower source / drain contact 160 may be stacked with the lower gate contact 125 in the first direction D1. The first substrate 292 and the second substrate 294 may be disposed between the lower source / drain contact 160 and the lower gate contact 125.

[0090] The lower source / drain contact 160 may include a lower source / drain contact barrier film 162 and a lower source / drain contact filler film 164. The lower source / drain contact barrier film 162 may define the side surface and the upper surface of the lower source / drain contact 160. The lower source / drain contact filler film 164 may be disposed in the lower source / drain contact barrier film 162.

[0091] The lower source / drain contact barrier film 162 may include, for example, one of tantalum (Ta), tantalum nitride (TaN), titanium (Ti), titanium nitride (TiN), ruthenium (Ru), cobalt (Co), nickel (Ni), nickel boride (NiB), tungsten (W), tungsten nitride (WN), tungsten carbonitride (WCN), zirconium (Zr), zirconium nitride (ZrN), vanadium (V), vanadium nitride (VN), niobium (Nb), niobium nitride (NbN), platinum (Pt), iridium (Ir), and rhodium (Rh). The lower source / drain contact filler film 164 may include, for example, one of aluminum (Al), tungsten (W), cobalt (Co), ruthenium (Ru), and molybdenum (Mo), but this disclosure is not limited thereto.

[0092] The second liner 294 may be disposed on the lower surface of the lower source / drain pattern 150. The second liner 294 may be disposed on the side surface of the lower source / drain contact 160. For example, the second liner 294 may surround the side surface of the lower source / drain contact 160. In some embodiments, the second liner 294 may contact the first liner 292, but this disclosure is not limited thereto.

[0093] The second liner 294 may include an insulating material. For example, the second liner 294 may include one of silicon nitride (SiN), silicon oxynitride (SiON), silicon carbonitride (SiCN), and silicon carbonitride oxynitride (SiOCN), but this disclosure is not limited thereto. In some embodiments, the first liner 292 and the second liner 294 may include the same material. In some embodiments, the first liner 292 and the second liner 294 may include different materials.

[0094] When the first liner 292 and the second liner 294 comprise the same material, the boundary between the first liner 292 and the second liner 294 may be indistinguishable. However, this disclosure is not limited thereto. For example, a silicon oxide film may be formed between the first liner 292 and the second liner 294, so the boundary between the first liner 292 and the second liner 294 may be identifiable.

[0095] Upper source / drain contact 260 may be disposed on upper source / drain pattern 250. Upper source / drain contact 260 may extend through upper interlayer insulating film 280, etch stop film 285, and upper surface of upper source / drain pattern 250. One end of upper source / drain contact 260 may be disposed in upper source / drain pattern 250. For example, upper source / drain contact 260 may be electrically connected to upper source / drain pattern 250.

[0096] The upper source / drain contact 260 may include an upper source / drain contact barrier film 262 and an upper source / drain contact filler film 264. The material descriptions of the upper source / drain contact barrier film 262 and the upper source / drain contact filler film 264 may be the same as the material descriptions of the lower source / drain contact barrier film 162 and the lower source / drain contact filler film 164, respectively.

[0097] Gate spacer 275 may be disposed on a side surface of gate electrode structure GS. For example, gate spacer 275 may be disposed on a side surface of second metal pattern 220. Gate spacer 275 may be disposed on both side surfaces of second metal pattern 220 disposed on first upper pattern NS2_1. Gate spacer 275 may extend along the side surface of gate electrode structure GS. Gate insulating film 130 may be disposed between gate spacer 275 and gate electrode structure GS. For example, gate insulating film 130 may extend along both side surfaces of gate spacer 275.

[0098] The gate spacer 275 may include at least one of, for example, silicon nitride (SiN), silicon oxynitride (SiON), silicon dioxide (SiO2), silicon carbonitride (SiOCN), silicon boron nitride (SiBN), silicon boron oxynitride (SiOBN), silicon carbonitride (SiOC), and / or combinations thereof. Although the gate spacer 275 is shown as a single film, this disclosure is not limited thereto.

[0099] A gate cover pattern 270 may be disposed on the upper surface of the gate electrode structure GS, the upper surface of the gate spacer 275, and the upper surface of the gate separator structure 310. The gate cover pattern 270 may cover the upper surface of the gate electrode structure GS and the upper surface of the gate separator structure 310. Although the gate cover pattern 270 is shown as contacting the upper surface of the gate spacer 275, this disclosure is not limited thereto. For example, the gate cover pattern 270 may be disposed between a pair of gate spacers 275 and may contact the side surfaces of the gate spacers 275.

[0100] The gate cover pattern 270 may include at least one of silicon nitride (SiN), silicon oxynitride (SiON), silicon carbonitride (SiCN), silicon carbonitride (SiOCN), and / or combinations thereof. The gate cover pattern 270 may include a material having etch selectivity relative to the upper interlayer insulating film 280.

[0101] An upper interlayer insulating film 280 may be disposed on the upper source / drain pattern 250. An etch stop film 285 may be disposed between the upper interlayer insulating film 280 and the upper source / drain pattern 250. The upper interlayer insulating film 280 may be disposed within the etch stop film 285.

[0102] The upper interlayer insulating film 280 may include at least one of silicon oxide (SiO), silicon nitride (SiN), silicon oxynitride (SiON), and / or a low-k material. Low-k materials may include, for example, tetraethyl orthosilicate (FTEOS), silsesquioxane (HSQ), bisbenzocyclobutene (BCB), tetramethyl orthosilicate (TMOS), octamethylcyclotetrasiloxane (OMCTS), hexamethyldisiloxane (HMDS), trimethylsilyl borate (TMSB), diacetoxyditert-butoxysiloxane (DADBS), trimethylsilyl phosphate (TMSP), polytetrafluoroethylene (PTFE), TOSZ (TonenSilazen), FSG (fluorinated silicate glass), polyimide nanofoam based on polypropylene oxide, carbon-doped silica (CDO), organosilicon glass (OSG), SiLK, amorphous fluorinated carbon, silica aerogel, silica degel, mesoporous silica, and / or combinations thereof, but this disclosure is not limited thereto.

[0103] An etch stop film 285 may be disposed between the upper interlayer insulating film 280 and the upper source / drain pattern 250. The etch stop film 285 may cover the upper surface of the upper source / drain pattern 250. The etch stop film 285 may include at least one of silicon nitride (SiN), silicon oxide (SiO), silicon oxynitride (SiON), silicon oxycarbonitrile (SiOCN), silicon boron nitride (SiBN), silicon boron oxynitride (SiOBN), silicon oxycarbonitrile (SiOC), and / or combinations thereof.

[0104] A gate separator structure 310 may be disposed on the lower surface of the gate cover pattern 270. The gate separator structure 310 may extend in a first direction D1 and a third direction D3. The gate separator structure 310 may be disposed on the side surface of the gate electrode structure GS. The gate separator structure 310 may separate the gate electrode structure GS. The width of the gate separator structure 310 in the second direction D2 may increase as it moves further away from the gate cover pattern 270.

[0105] A portion of the gate separator structure 310 may be disposed on a side surface of the first substrate 292. In some embodiments, a portion of the gate separator structure 310 may contact the first substrate 292. A gate electrode structure GS may be disposed between the gate separator structure 310 and the first substrate 292. For example, a first metal pattern 120 may be disposed between the gate separator structure 310 and the first substrate 292.

[0106] In a semiconductor device, the gate electrode structure GS needs to have a width not less than a predetermined size in order to form the gate contact 125. In a semiconductor device according to some embodiments of the present disclosure, the lower gate contact 125 may be stacked on a third direction D3 with a plurality of lower wafer patterns NS1 and a plurality of upper wafer patterns NS2. By providing the lower gate contact 125 to be stacked on the wafer patterns NS1 and NS2 on the third direction D3, the width of the gate electrode structure GS in the second direction D2 can be reduced. The area of ​​the gate electrode structure GS can thus be reduced, thereby increasing the integration density of the semiconductor device. Furthermore, due to the reduction in the area of ​​the gate electrode structure GS, parasitic capacitance can be reduced, and the electrical characteristics of the semiconductor device can be enhanced.

[0107] The gate separator structure 310 may include an insulating film 312 and an insulating filler film 314. The insulating film 312 may define the side surface and the top surface of the gate separator structure 310. The insulating filler film 314 may be disposed in the insulating film 312. The insulating film 312 may include, for example, one of silicon nitride (SiN), silicon oxynitride (SiON), silicon carbonitride (SiOCN), silicon boron nitride (SiBN), silicon boron oxynitride (SiOBN), and silicon carbonitride (SiCN). The insulating filler film 314 may include, for example, at least one of silicon dioxide (SiO2), silicon oxynitride (SiON), silicon carbonitride (SiOCN), silicon boron oxynitride (SiOBN), silicon carbonitride (SiOC), and / or combinations thereof.

[0108] Figure 6 This is a view illustrating a semiconductor device according to some embodiments of the present disclosure. For convenience, the description and references are primarily... Figures 1 to 5 The components described are different components.

[0109] Reference Figure 6 According to some embodiments, a semiconductor device may include a lower spacer 298.

[0110] A lower spacer 298 may be disposed between the first liner 292 and the gate separator 310. The gate separator 310 may be disposed on a first side surface of the lower spacer 298. The first liner 292 may be disposed on a second side surface of the lower spacer 298. The upper surface of the lower spacer 298 may contact the gate electrode structure GS and the gate insulating film 130. The lower spacer 298 may space the gate electrode structure GS and the first liner 292 apart.

[0111] Figure 7 This is a view illustrating a semiconductor device according to some embodiments of the present disclosure. For convenience, the description and references are primarily... Figures 1 to 5 The components described are different components.

[0112] Reference Figure 7 In a semiconductor device according to some embodiments, the upper surface 310_US of the gate separator structure 310 may include a convex curved surface. The upper surface 310_US of the gate separator structure 310 may be disposed at a higher vertical height than the upper surface of the gate electrode structure GS.

[0113] The gate cover pattern 270 may be disposed on the upper surface 310_US of the gate separator structure 310. The gate cover pattern 270 may have a concave shape corresponding to the upper surface 310_US of the gate separator structure 310.

[0114] Figure 8 This is a view illustrating a semiconductor device according to some embodiments of the present disclosure. For convenience, the description and references are primarily... Figures 1 to 5 The components described are different components.

[0115] Reference Figure 8 In a semiconductor device according to some embodiments, the distance between the first substrate 292 and the second underlay pattern NS1_2 may be different from the distance between the second underlay pattern NS1_2 and the first underlay pattern NS1_1. For example, the distance H1 from the upper surface 292_US of the first substrate 292 to the lower surface of the second underlay pattern NS1_2 may be greater than the distance H2 from the upper surface of the second underlay pattern NS1_2 to the lower surface of the first underlay pattern NS1_1.

[0116] The upper surface of the lower gate contact 125 may be disposed between the first substrate 292 and the second underlay pattern NS1_2. In a semiconductor device according to some embodiments, the process margin for forming the lower gate contact 125 can be improved by making the distance H1 from the upper surface 292_US of the first substrate 292 to the lower surface of the second underlay pattern NS1_2 larger.

[0117] Figure 9 This is a view illustrating a semiconductor device according to some embodiments of the present disclosure. For convenience, the description and references are primarily... Figures 1 to 5 The components described are different components.

[0118] Reference Figure 9 In a semiconductor device according to some embodiments, the widths of the first substrate 292, the plurality of lower wafer patterns NS1, and the plurality of upper wafer patterns NS2 in the second direction D2 may be constant. In some embodiments, the width of the first substrate 292 in the second direction D2 and the widths of the plurality of lower wafer patterns NS1 and the plurality of upper wafer patterns NS2 in the second direction D2 may be the same.

[0119] The width of the lower gate contact 125 in the second direction D2 can be constant. The width of the lower gate contact 125 in the second direction D2 can be smaller than the width of the plurality of lower die patterns NS1 in the second direction D2.

[0120] Figure 10 This is a view illustrating a semiconductor device according to some embodiments of the present disclosure. For convenience, the description and references are primarily... Figures 1 to 5 The components described are different components.

[0121] Reference Figure 10 In a semiconductor device according to some embodiments, the lower source / drain pattern 150 may include a lower source / drain liner 152 and a lower source / drain filler 151.

[0122] The lower source / drain pattern 150 may be disposed in the lower source / drain trench. The lower source / drain liner 152 may extend along the sidewall of the lower source / drain trench. The lower source / drain liner 152 may define the sidewall of the lower source / drain pattern 150. The lower source / drain liner 152 may extend along the side surfaces of a plurality of lower die patterns NS1. The lower source / drain liner 152 may contact the side surfaces of the plurality of lower die patterns NS1 and the side surface of the gate insulating film 130. The gate insulating film 130 may be disposed between the lower source / drain liner 152 and the first metal pattern 120.

[0123] The lower source / drain filling film 151 may be disposed in the lower source / drain liner 152. Although only a single layer of the lower source / drain filling film 151 is shown, the present disclosure is not limited thereto; the lower source / drain filling film 151 may include multiple layers.

[0124] In some embodiments, the lower source / drain liner 152 and the lower source / drain filler 151 may comprise the same material with different concentrations of constituent materials. However, this disclosure is not limited thereto. For example, the lower source / drain liner 152 and the lower source / drain filler 151 may comprise different materials.

[0125] Figure 11 and Figure 12 This is a view illustrating a semiconductor device according to some embodiments of the present disclosure. For reference, Figure 11 This is a plan view illustrating a semiconductor device according to some embodiments of the present disclosure. Figure 12 It shows along Figure 11 A cross-sectional view of the cut taken along line B-B'. Showing along... Figure 11 The cross-sectional view of the cut taken by line A-A' can be compared with... Figure 2 similar.

[0126] Reference Figure 11 and Figure 12 According to some embodiments, a semiconductor device may include a device isolation film 102.

[0127] The device isolation film 102 may be disposed below the gate electrode structure GS, and the gate insulating film 130 may be disposed on the upper surface of the device isolation film 102. The device isolation film 102 may be disposed on the side surface of the first substrate 292. The device isolation film 102 may have a shallow trench isolation (STI) structure with excellent device isolation characteristics.

[0128] The lower gate contact 125 may be disposed between adjacent device isolation films 102 in the second direction D2. In some embodiments, the lower surface of the lower gate contact 125 may be disposed on the same plane as the lower surface of the device isolation film 102.

[0129] The device isolation film 102 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film, but this disclosure is not limited thereto. Although the device isolation film 102 is shown as a single insulating film, this disclosure is not limited thereto.

[0130] The gate separator structure 320 separates the gate electrode structure GS. The gate separator structure 320 extends to the gate electrode structure GS and the device isolation film 102. The gate separator structure 320 is spaced apart from the active region AP in the second direction D2. The gate separator structure 320 is disposed on the lower surface of the gate cover pattern 270. The gate separator structure 320 extends in the first direction D1 and the third direction D3. The width of the gate separator structure 320 in the second direction D2 decreases as the gate separator structure 320 becomes further away from the gate cover pattern 270.

[0131] The gate separator structure 320 may include an insulating film 322 and an insulating filler film 324. The insulating film 322 may define a side surface of the gate separator structure 320. The insulating filler film 324 may be disposed in the insulating film 322. The insulating film 322 may include, for example, one of silicon nitride (SiN), silicon oxynitride (SiON), silicon carbonitride (SiOCN), silicon boron nitride (SiBN), silicon boron oxynitride (SiOBN), and silicon carbonitride (SiCN). The insulating filler film 324 may include at least one of silicon dioxide (SiO2), silicon oxynitride (SiON), silicon carbonitride (SiOCN), silicon boron oxynitride (SiOBN), silicon carbonitride (SiOC), and / or combinations thereof.

[0132] Figures 13 to 32 This is a view illustrating a method of manufacturing a semiconductor device according to some embodiments of the present disclosure. For reference, Figure 13 This is a plan view illustrating a semiconductor manufacturing method according to some embodiments. Figure 14 , Figure 16 , Figure 18 , Figure 20 , Figure 22 , Figure 25 , Figure 27 , Figure 29 and Figure 31 It shows along Figure 13 A cross-sectional view of the cut taken by line A-A'. Figure 15 , Figure 17 , Figure 19 , Figure 21 , Figure 23 , Figure 24 , Figure 26 , Figure 28 , Figure 30 and Figure 32 It shows along Figure 13A cross-sectional view of the cut taken by line B-B'. For convenience, refer to... Figures 1 to 5 Components that are identical to those described are either briefly described or omitted.

[0133] Reference Figures 13 to 15 Multiple lower wafer patterns NS1, multiple upper wafer patterns NS2, gate electrode structure GS, gate insulating film 130, intermediate insulating pattern 202, pre-semiconductor pattern 145, lower source / drain pattern 150, upper source / drain pattern 250, insulating capping layer 205, intermediate interlayer insulating film 200, upper source / drain contact 260, gate spacer 275, gate capping pattern 270, upper interlayer insulating film 280 and etch stop film 285 can be formed on substrate 100.

[0134] The substrate 100 may be bulk silicon or silicon-on-insulator (SOI). Optionally, the substrate 100 may include, but is not limited to, silicon germanium (SiGe), silicon germanium-on-insulator (SGOI), indium antimonide, lead telluride compound, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide.

[0135] The substrate 100 may include a lower pattern BP. The lower pattern BP may be stacked on a third direction D3 with a plurality of lower patterns NS1 and a plurality of upper patterns NS2. In some embodiments, the lower pattern BP may be formed by removing a portion of the substrate 100, but this disclosure is not limited thereto. A device isolation film 102 may be disposed between adjacent lower patterns BP in the second direction D2.

[0136] Multiple lower wafer patterns NS1 and multiple upper wafer patterns NS2 spaced apart from each other in a third direction D3 can be formed on the lower pattern BP of the substrate 100. Subsequently, a pre-semiconductor pattern 145, a lower source / drain pattern 150, and an upper source / drain pattern 250 can be formed on the substrate 100. The pre-semiconductor pattern 145 can be disposed on the substrate 100. The pre-semiconductor pattern 145 can be stacked with the substrate 100 in a first direction D1. The pre-semiconductor pattern 145 may include a semiconductor material. Then, a gate insulating film 130 can be formed, and a gate electrode structure GS can be formed.

[0137] Reference Figure 16 and Figure 17 The substrate 100 can be removed, thereby exposing the pre-formed semiconductor pattern 145, the device isolation film 102, and the gate insulating film 130. For example, the lower pattern BP of the substrate 100 can be removed, thereby exposing the side surface of the device isolation film 102 and the gate insulating film 130.

[0138] In some implementations, the semiconductor device can be flipped before removing the substrate 100. For example, it can be... Figure 14 and Figure 15The semiconductor device shown is rotated 180 degrees so that the substrate 100 is positioned on top. The substrate 100 can then be removed by an etching process.

[0139] In some embodiments, the step of removing substrate 100 may include a chemical mechanical polishing (CMP) process. For example, a portion of substrate 100 may be removed by a CMP process, and the remainder of substrate 100 may be removed by an etching process.

[0140] Reference Figure 18 and Figure 19 It can remove Figure 17 The device isolation film 102 shown is used, and a first substrate 292 can be formed thereon. For example, the device isolation film 102 can be removed to expose the gate insulating film 130. The first substrate 292 can then be formed on the prepared semiconductor pattern 145 and the gate insulating film 130. The first substrate 292 can be formed along the pattern BP (see below) Figure 15 The gate insulating film 130 and device isolation film 102 exposed by the removal of the semiconductor pattern 145 extend. The first liner 292 may extend along the lower and side surfaces of the prepared semiconductor pattern 145. In some embodiments, the first liner 292 may be formed conformally, but this disclosure is not limited thereto.

[0141] Reference Figure 20 and Figure 21 A sacrificial insulating pattern 300 may be formed on the first substrate 292. For example, an insulating material may be deposited on the first substrate 292 to cover the first substrate 292. Then, a portion of the insulating material may be removed to form the sacrificial insulating pattern 300. For example, a portion of the insulating material may be removed by a CMP process. The sacrificial insulating pattern 300 may not cover a portion of the gate insulating film 130. The sacrificial insulating pattern 300 may expose a portion of the gate insulating film 130.

[0142] Reference Figure 22 and Figure 23 The portion of the first liner 292 exposed by the sacrificial insulating pattern 300 can be removed. A portion of the first liner 292 can be removed to expose the prepared semiconductor pattern 145 and the gate insulating film 130. The first liner 292 can be formed on the sacrificial insulating pattern 300. The first liner 292 can surround the side surface of the sacrificial insulating pattern 300.

[0143] Reference Figure 24A portion of the gate electrode structure GS can be removed by an etching process to form the first trench T1. For example, the first substrate 292 and the sacrificial insulating pattern 300 can be used as etching masks to remove a portion of the gate electrode structure GS. The first trench T1 separates the gate electrode structure GS. The first trench T1 exposes the side surface of the gate electrode structure GS and the lower surface of the gate cover pattern 270. The width of the first trench T1 in the second direction D2 can increase as it moves further away from the gate cover pattern 270.

[0144] In some embodiments, the upper surface of the first trench T1 may include a convex surface, wherein the upper surface of the first trench T1 may represent the surface defined by the gate cover pattern 270. During etching of the first trench T1, a portion of the gate cover pattern 270 may be removed, thereby forming a convex surface on the upper surface of the first trench T1.

[0145] In a method of manufacturing a semiconductor device according to some embodiments of the present disclosure, the first trench T1 can be formed by using a first substrate 292 and a sacrificial insulating pattern 300 as an etching mask. Because no additional photolithography process is required to form the first trench T1 for forming a separate mask, manufacturing complexity is reduced and costs are saved.

[0146] Reference Figure 25 and Figure 26 , can Figure 24 A gate separator structure 310 is formed in the first trench T1 shown. Specifically, an insulating liner 312 may be formed along the side and top surfaces of the first trench T1. The insulating liner 312 may extend on the lower surface of the sacrificial insulating pattern 300 and the lower surface of the prepared semiconductor pattern 145. An insulating filler 314 may then be formed in the insulating liner 312. For example, the insulating filler 314 may fill the remaining portion of the first trench T1 after the insulating liner 312 is formed. In some embodiments, an insulating material may be deposited in the insulating liner 312, and a portion of the insulating material may be removed by a CMP process to form the insulating filler 314.

[0147] Although the upper surface of the gate separator 310 is shown as flat, this disclosure is not limited thereto. For example, when Figure 24 When the upper surface of the first trench T1 shown includes a convex curved surface, the upper surface of the gate separator structure 310 can be connected with... Figure 7 The upper surface shown is similar.

[0148] Reference Figure 27 and Figure 28 It can remove Figure 25 A portion of the insulating liner 312 shown is prepared with a semiconductor pattern 145, and a second liner 294 and lower source / drain contacts 160 may be formed therefrom.

[0149] Specifically, a portion of the insulating liner 312 may be removed to expose Figure 25 The prepared semiconductor pattern 145 is shown. The prepared semiconductor pattern 145 can then be removed to expose the lower surface of the lower source / drain pattern 150. Subsequently, a second substrate 294 can be formed in the location where the prepared semiconductor pattern 145 has been removed. The second substrate 294 can be formed on the side surface of the first substrate 292 and on the lower surface of the lower source / drain pattern 150.

[0150] Then, a portion of the second substrate 294 and a portion of the lower source / drain pattern 150 can be removed, and a lower source / drain contact 160 can be formed on the lower source / drain pattern 150. For example, a portion of the second substrate 294 disposed on the lower surface of the lower source / drain pattern 150 can be removed. A portion of the second substrate 294 and a portion of the lower source / drain pattern 150 can be removed by an etching process. For example, the etching process can be a dry etching process. Furthermore, a portion of the second substrate 294 can be removed by the etching process, thereby exposing the gate separator structure 310 and the sacrificial insulating pattern 300.

[0151] The lower source / drain contact 160 can be formed by sequentially forming a lower source / drain contact barrier film 162 and a lower source / drain contact filler film 164 on the second liner 294 and the lower source / drain pattern 150.

[0152] Reference Figure 29 and Figure 30 The sacrificial insulation pattern 300 can be removed to form a second trench T2. The side and top surfaces of the second trench T2 can be defined by a first liner 292.

[0153] Reference Figure 31 and Figure 32 The third trench T3 can be formed by removing a portion of the first substrate 292, a portion of the gate insulating film 130, and a portion of the gate electrode structure GS. For example, it can be formed by removing a portion of the first substrate 292, a portion of the gate insulating film 130, and a portion of the gate electrode structure GS. Figure 29 and Figure 30 The upper surface of the second trench T2 shown is etched to form the third trench T3.

[0154] The third trench T3 may expose the side surface of the first liner 292 and the lower portion of the gate electrode structure GS. For example, the third trench T3 may expose the lower portion of the first metal pattern 120. In some embodiments, the side surface of the third trench T3 may include a first portion and a second portion with different slopes, but this disclosure is not limited thereto. The side surface of the third trench T3 may have a constant slope.

[0155] Subsequently, referring to Figure 2 and Figure 3 , can Figure 31 and Figure 32 A lower gate contact 125 is formed on the third trench T3 shown. For example, a gate contact barrier film 122 and a gate contact fill film 124 may be formed sequentially on the third trench T3. When the side surface of the third trench T3 includes a first portion and a second portion with different slopes, the shape of the lower gate contact 125 may be as follows. Figure 4 As shown in the diagram. When the side surface of the third trench T3 has a constant slope, the shape of the lower gate contact 125 can be as follows. Figure 5 As shown in the image.

[0156] Figures 33 to 42 This is a view illustrating a method of manufacturing a semiconductor device according to some embodiments of the present disclosure. For reference, Figure 33 This is a plan view illustrating a method for manufacturing a semiconductor device according to some embodiments. Figure 34 , Figure 35 , Figure 36 , Figure 38 , Figure 40 and Figure 42 It shows along Figure 33 A cross-sectional view of the cut taken by line B-B'. Figure 37 , Figure 39 and Figure 41 It shows along Figure 33 A cross-sectional view of the cut taken by line A-A'. For convenience, refer to... Figures 1 to 5 as well as Figures 11 to 12 Components that are identical to those described are either briefly described or omitted.

[0157] Show along Figure 33 The cross-sectional view of the cut taken by line A-A' can be compared with... Figure 14 Same. (Refer to...) Figure 14 , Figure 33 and Figure 34 Multiple lower wafer patterns NS1, multiple upper wafer patterns NS2, gate electrode structure GS, gate insulating film 130, intermediate insulating pattern 202, pre-semiconductor pattern 145, lower source / drain pattern 150, upper source / drain pattern 250, insulating capping layer 205, intermediate interlayer insulating film 200, upper source / drain contact 260, gate spacer 275, gate capping pattern 270, upper interlayer insulating film 280, etch stop film 285 and gate separation structure 320 can be formed on substrate 100.

[0158] The lower surface of the gate separator structure 320 may be disposed on the substrate 100. The gate separator structure 320 may separate the gate electrode structure GS. The width of the gate separator structure 320 in the second direction D2 may decrease as the gate separator structure 320 moves further away from the gate cover pattern 270. The gate separator structure 320 may include an insulating liner 322 and an insulating filler 324.

[0159] Reference Figure 35 It can remove Figure 34 The substrate 100 shown is used to form the fourth trench T4. The fourth trench T4 may be formed by removing... Figure 34 The space of the lower pattern BP of the substrate 100 shown. The fourth trench T4 exposes the side surface of the device isolation film 102 and the gate insulating film 130.

[0160] Reference Figure 36 A first liner 292 may be formed on the fourth trench T4 and the device isolation film 102. For example, the first liner 292 may extend along the side and top surfaces of the fourth trench T4. The first liner 292 may extend along the lower surface of the device isolation film 102. In some embodiments, the first liner 292 may be formed conformally, but this disclosure is not limited thereto.

[0161] Reference Figure 37 and Figure 38 A portion of the first liner 292 and a portion of the gate electrode structure GS can be removed by an etching process.

[0162] A portion of the first substrate 292 can be removed to expose the prepared semiconductor pattern 145 and the device isolation film 102. During the etching process, the portion of the first substrate 292 that can be removed... Figure 36 A portion of the upper surface of the fourth trench T4 and a portion of the gate electrode structure GS are shown to form a fifth trench T5. The fifth trench T5 exposes the gate electrode structure GS.

[0163] Reference Figure 39 and Figure 40 , can Figure 38 A lower gate contact 125 is formed on the fifth trench T5 shown. For example, the lower gate contact 125 can be formed by sequentially forming a gate contact barrier film 122 and a gate contact fill film 124 on the fifth trench T5. A first liner 292 may surround the side surface of the lower gate contact 125.

[0164] Reference Figure 41 and Figure 42 The prepared semiconductor pattern 145 can be removed, and a second substrate 294 can be formed.

[0165] For example, the pre-formed semiconductor pattern 145 can be removed to expose the lower surface of the lower source / drain pattern 150 and the first substrate 292. Then, a second substrate 294 can be formed to extend along the side surface of the first substrate 292, the lower surface of the lower source / drain pattern 150, the lower surface of the lower gate contact 125, and the lower surface of the device isolation film 102.

[0166] Subsequently, referring to Figure 11 and Figure 12 A portion of the second liner 294 and a portion of the lower source / drain pattern 150 can be removed, and the lower source / drain contact 160 can be formed.

[0167] While this specification contains numerous specific details of implementation, these should not be construed as limiting the scope or claimable scope of any invention, but rather as descriptions of features specific to particular embodiments of a particular invention. Specific features described in the context of individual embodiments in this specification may also be implemented in combination in a single embodiment. Conversely, various features described in the context of a single embodiment may also be implemented individually or in any suitable sub-combination in multiple embodiments. Furthermore, although features may be described above as functioning in a specific combination, in some cases, one or more features from the combination may be removed from the combination, and the combination may refer to a sub-combination or a variation of the sub-combination.

[0168] Although specific embodiments of this disclosure have been described with reference to the accompanying drawings, those skilled in the art will understand that this disclosure can be implemented in other specific forms without altering the technical concept or essential characteristics of the disclosure. Therefore, it should be understood that the above embodiments are illustrative in all respects and not restrictive.

Claims

1. A semiconductor device, comprising: Multiple lower-piece patterns are spaced apart from each other in the first direction; Multiple upper patterns are spaced apart from each other in a first direction, wherein the multiple upper patterns are on the multiple lower patterns; A gate electrode structure surrounds each of the plurality of lower sheet patterns and each of the plurality of upper sheet patterns, wherein the gate electrode structure extends in a second direction intersecting the first direction; The lower gate contact is located below the gate electrode structure in a first direction and is stacked with the plurality of lower die patterns; and The first liner is on the side surface of the lower gate contact. In this configuration, the width of the gate electrode structure in the second direction decreases downward along the first direction.

2. The semiconductor device of claim 1, comprising: A gate insulating film is located between the plurality of lower wafer patterns and the gate electrode structure, between the plurality of upper wafer patterns and the gate electrode structure, and between the first liner and the gate electrode structure.

3. The semiconductor device as claimed in claim 1, wherein, The lower gate contact includes a first side surface and a second side surface opposite to the first side surface in a second direction, and The first side surface includes a first portion having a first slope and a second portion having a second slope, the second slope being different from the first slope.

4. The semiconductor device of claim 1, wherein, The first liner surrounds the side surface of the lower gate contact, and Wherein, the width of the first liner in the second direction is equal to or greater than the width of each of the plurality of lower sheet patterns in the second direction.

5. The semiconductor device of claim 1, further comprising: A gate separator structure extends upward in a third direction, intersecting each of the first and second directions, wherein the gate separator structure is on the side surface of the gate electrode structure, and A portion of the gate separator structure is located on the side surface of the first liner.

6. The semiconductor device of claim 5, further comprising: Gate overlay pattern on the upper surface of the gate electrode structure. In this case, the width of the gate separator structure in the second direction increases as it moves further away from the gate cover pattern.

7. The semiconductor device of claim 5, further comprising: The lower spacer is located between the gate separator structure and the first liner.

8. The semiconductor device of claim 1, wherein, The first liner and the plurality of lower sheet patterns comprise different materials.

9. The semiconductor device of claim 1, wherein, The lower gate contact includes a gate contact barrier film and a gate contact fill film, and The gate contact barrier film contacts the first liner film.

10. The semiconductor device of claim 1, wherein, The plurality of lower die patterns include a first lower die pattern and a second lower die pattern sequentially stacked on the lower gate contact, and The distance from the upper surface of the first liner to the lower surface of the first lower pattern is greater than the distance from the upper surface of the first lower pattern to the lower surface of the second lower pattern.

11. The semiconductor device according to any one of claims 1 to 10, further comprising: The lower source / drain pattern, on the first side of the plurality of lower patterns in the third direction, intersects with each of the first and second directions in the third direction; Lower source / drain contacts are connected to the lower source / drain pattern; as well as The second liner surrounds the side surface of the lower source / drain contact and is also on the side surface of the first liner.

12. A semiconductor device, comprising: Multiple lower-piece patterns are spaced apart from each other in the first direction; Multiple upper patterns are spaced apart from each other in a first direction, wherein the multiple upper patterns are on the multiple lower patterns; A gate electrode structure surrounds each of the plurality of lower sheet patterns and each of the plurality of upper sheet patterns, wherein the gate electrode structure extends in a second direction intersecting the first direction; A gate insulating film is located between the plurality of upper wafer patterns and the gate electrode structure, and between the plurality of lower wafer patterns and the gate electrode structure. The lower gate contact is located below the gate electrode structure; The lower source / drain pattern, on the first side of the plurality of lower patterns in the third direction, intersects with each of the first and second directions in the third direction; Lower source / drain contacts, connected to the lower source / drain pattern, and extending to the lower surface of the lower source / drain pattern; and The first and second films are located between the lower gate contact and the lower source / drain contact. The lower gate contact and the lower source / drain contact are stacked on top of each other in a third-order direction.

13. The semiconductor device of claim 12, wherein, The first liner is on the side surface of the lower gate contact. The second liner is located on the side surface of the lower source / drain contact, and The first liner is in contact with the second liner.

14. The semiconductor device of claim 12, wherein, The plurality of upper wafer patterns, the plurality of lower wafer patterns, and the lower gate contact are aligned in a first direction.

15. The semiconductor device of claim 12, wherein, The gate insulating film is on the upper and side surfaces of the first liner.

16. The semiconductor device of claim 12, wherein, The gate electrode structure includes: a first metal pattern surrounding the plurality of lower sheet patterns, a second metal pattern surrounding the plurality of upper sheet patterns, and a third metal pattern on the second metal pattern.

17. The semiconductor device according to any one of claims 12 to 16, further comprising: A gate separation structure extends upward on the third side and on the side surface of the gate electrode structure; as well as The device isolation film is located between the gate separator structure and the lower gate contact. The gate insulating film is located on the upper surface of the device isolation film.

18. The semiconductor device according to any one of claims 12 to 16, further comprising: An intermediate insulating pattern is located between the plurality of lower sheet patterns and the plurality of upper sheet patterns.

19. The semiconductor device according to any one of claims 12 to 16, further comprising: Upper source / drain pattern, on one side of the plurality of upper plate patterns; as well as Upper source / drain contacts, on the upper source / drain pattern.

20. A semiconductor device, comprising: Multiple lower-piece patterns are spaced apart from each other in the first direction; Multiple upper pattern pieces are spaced apart from each other in a first direction and are above the multiple lower pattern pieces; A gate electrode structure surrounds each of the plurality of lower sheet patterns and each of the plurality of upper sheet patterns, wherein the gate electrode structure extends in a second direction intersecting the first direction; The lower gate contact is located below the gate electrode structure in a first direction and is stacked with the plurality of lower die patterns; The first liner is on the side surface of the lower gate contact; Lower source / drain pattern, on the first side of the plurality of lower plate patterns; Lower source / drain contacts are connected to the lower source / drain pattern; The second liner is located between the lower source / drain contact and the first liner. And a gate insulating film, between each of the plurality of lower wafer patterns and the gate electrode structure, between each of the plurality of upper wafer patterns and the gate electrode structure, and between the first substrate and the gate electrode structure. The lower source / drain contact is stacked with the lower gate contact in the third direction, and the third direction intersects with each of the first and second directions.

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