Semiconductor device and method of manufacturing the same

Abstract

A semiconductor device includes gate lines adjacent to each other in a first horizontal direction and each extending in a second horizontal direction, source / drain regions adjacent to the gate lines in the first horizontal direction, respectively, backside via contacts connected to a pair of the source / drain regions facing each other in the second horizontal direction, backside insulating patterns aligned with the gate lines in a vertical direction and spaced apart from each other in the first horizontal direction, semiconductor blocks contacting sidewalls of the backside insulating patterns, and a device isolation layer covering sidewalls of the backside via contacts, wherein the backside via contacts include a pair of first portions facing the pair of the source / drain regions and a second portion between the pair of the first portions, and a first horizontal width of the pair of the first portions is smaller than a second horizontal width of the second portion.

Description

Cross-reference of related applications

[0001] This application claims priority and benefit to Korean Patent Application 10-2025-0054740, filed with the Korean Intellectual Property Office on April 25, 2025, the entire disclosure of which is incorporated herein by reference. Technical Field

[0002] The disclosed concept relates to a semiconductor device and a method of manufacturing the same, and more specifically, to a semiconductor device including a back-side contact and a method of manufacturing the semiconductor device. Background Technology

[0003] With the development of electronics, the miniaturization of semiconductor devices has been rapidly achieved. In these highly miniaturized semiconductor devices, not only high operating speeds but also high operating precision are required. Therefore, there is a need for a wiring structure that includes conductors with a stable and optimized arrangement within a relatively small area. Summary of the Invention

[0004] The disclosed concept provides a semiconductor device with improved functional reliability and a method for manufacturing the same.

[0005] According to various aspects of the disclosed concept, a semiconductor device is provided, comprising: a plurality of gate lines adjacent to each other in a first horizontal direction and each extending in a second horizontal direction substantially perpendicular to the first horizontal direction; a plurality of source / drain regions respectively arranged adjacent to the plurality of gate lines in the first horizontal direction; a back-side via contact connected to a pair of source / drain regions facing each other in the second horizontal direction; a plurality of back-side insulating patterns aligned vertically with the plurality of gate lines and spaced apart from each other in the first horizontal direction; a plurality of semiconductor blocks contacting sidewalls of the plurality of back-side insulating patterns in the first horizontal direction; and a device isolation layer covering the sidewalls of the back-side via contact in the second horizontal direction, wherein the back-side via contact includes a pair of first portions facing the pair of source / drain regions and a second portion disposed between the pair of first portions, and the first horizontal width of the pair of first portions in the first horizontal direction is smaller than the second horizontal width of the second portion in the first horizontal direction.

[0006] According to various aspects of the disclosed concept, a semiconductor device is provided, comprising: a plurality of gate lines adjacent to each other in a first horizontal direction and each extending in a second horizontal direction substantially perpendicular to the first horizontal direction; a plurality of source / drain regions respectively arranged adjacent to the plurality of gate lines in the first horizontal direction; a first back-side via contact connected to a first pair of source / drain regions facing each other in the second horizontal direction; and a second back-side via contact spaced apart from the first back-side via contact in the first horizontal direction and connected to a pair of source / drain regions facing each other in the second horizontal direction. The device comprises: a second pair of source / drain regions facing each other; a plurality of back-side insulating patterns aligned vertically with a plurality of gate lines; a plurality of semiconductor blocks contacting the sidewalls of the plurality of back-side insulating patterns in a first horizontal direction; and a device isolation layer covering the sidewalls of a first back-side via contact and a second back-side via contact in a second horizontal direction, wherein the first back-side via contact includes a pair of first portions facing the first pair of source / drain regions and a second portion disposed between the first pair of source / drain regions, and the first horizontal width of the pair of first portions in the first horizontal direction is smaller than the second horizontal width of the second portion in the first horizontal direction.

[0007] According to various aspects of the disclosed concept, a semiconductor device is provided, comprising: a plurality of gate lines adjacent to each other in a first horizontal direction and each extending in a second horizontal direction substantially perpendicular to the first horizontal direction; a plurality of source / drain regions respectively arranged adjacent to the plurality of gate lines in the first horizontal direction; a back-side via contact connected to any pair of source / drain regions facing each other in the second horizontal direction; a front-side contact connected to a source / drain region selected from the plurality of source / drain regions; a plurality of back-side insulating patterns aligned vertically with the plurality of gate lines and spaced apart from each other in the first horizontal direction; a plurality of semiconductor blocks contacting sidewalls of the plurality of back-side insulating patterns in the first horizontal direction; and a device isolation layer covering the sidewalls of the back-side via contact in the second horizontal direction, wherein the back-side via contact includes a pair of first portions facing the pair of source / drain regions and a second portion disposed between the pair of first portions, the first portion having a first horizontal width in the first horizontal direction being smaller than the second horizontal width of the second portion in the first horizontal direction.

[0008] According to various aspects of the disclosed concept, a method for manufacturing a semiconductor device is provided, the method comprising: forming a sacrificial layer on a substrate and forming a stacked structure on the sacrificial layer, wherein a plurality of sacrificial semiconductor layers and a plurality of nanosheet semiconductor layers are alternately stacked; forming a plurality of finned active regions defining trenches by etching a portion of each of the plurality of sacrificial semiconductor layers, the plurality of nanosheet semiconductor layers, the sacrificial layer and the substrate and replacing the sacrificial layer with an etch stop layer; forming a device isolation layer filling the trenches; dividing the plurality of nanosheet semiconductor layers into a plurality of nanosheet stacks and forming a plurality of recesses; forming a plurality of source / drain regions filling the plurality of recesses; forming a gate space by removing the plurality of sacrificial semiconductor layers and forming a gate dielectric layer and a gate line within the gate space; and removing from the back side of the substrate... The substrate exposes multiple finned active regions and a device isolation layer; multiple vertical holes are formed by etching a portion of each of the multiple finned active regions, and multiple back-side insulating patterns are formed to fill the multiple vertical holes; multiple semiconductor blocks formed by etching the multiple finned active regions divided by the multiple back-side insulating patterns are formed to create a first space and a second space, wherein the first space and the second space are interconnected and expose a selected pair of source / drain regions among a plurality of source / drain regions; and a back-gate via contact is formed to fill the first space and the second space, wherein the back-side via contact includes a pair of first portions filling the first space and a second portion filling the second space, and the first width of the pair of first portions in a first horizontal direction is smaller than the second width of the second portions in a first horizontal direction.

[0009] In one embodiment, a pair of first portions may contact a plurality of semiconductor blocks in a first horizontal direction, and a second portion may contact some of the device isolation layer and a plurality of back-side insulating patterns in the first horizontal direction.

[0010] In an embodiment, the second part may have a polygonal shape with rounded corners in a plan view.

[0011] In an embodiment, the second part may have a polygonal shape with angles in the plan view.

[0012] In an embodiment, the second portion may have a shape that protrudes outward toward the second portion as the second portion moves away from each of the pair of first portions in a second horizontal direction.

[0013] In one embodiment, the upper surface of the pair of first portions may be located at a vertical level higher than the upper surface of the second portion.

[0014] In an embodiment, the semiconductor device may further include a front contact connected to one of a plurality of source / drain regions, wherein a source / drain region connected to the front contact may not be included in a pair of source / drain regions connected to a back via contact.

[0015] In an embodiment, the method may further include: forming a front contact connected to some of the source / drain regions among a plurality of source / drain regions, wherein the front contact may be connected to at least one of a pair of source / drain regions connected to a back via contact.

[0016] In an embodiment, the method may further include: forming front contacts connected to some of the multiple source / drain regions, wherein the front contacts are alignable in a vertical direction with a pair of first portions of a back via contact.

[0017] In an embodiment, the method may further include: forming front contacts connected to some of a plurality of source / drain regions, wherein the front contacts may be contacts commonly connected to the pair of source / drain regions and may be aligned in the vertical direction with a pair of first and second portions of a back via contact. Attached Figure Description

[0018] The embodiments will become clearer from the following detailed description taken in conjunction with the accompanying drawings, in which: Figure 1 This is a plan view of the cell blocks of a semiconductor device according to an embodiment; Figure 2 This is a plan view of a semiconductor device according to an embodiment; Figure 3A It is along Figure 2 A cross-sectional view taken by line X1-X1'; Figure 3B It is along Figure 2 A cross-sectional view taken by line X2-X2'; Figure 4A It is along Figure 2 A cross-sectional view taken from line Y1-Y1'; Figure 4B It is along Figure 2 A cross-sectional view taken from line Y2-Y2'; Figure 4C It is along Figure 2 A cross-sectional view taken from line Y3-Y3'; Figure 4D It is along Figure 2 A cross-sectional view taken from line Y4-Y4'; Figure 5 This is a plan view of a semiconductor device according to an embodiment; Figure 6 This is a plan view of a semiconductor device according to an embodiment; Figure 7 This is a plan view of a semiconductor device according to an embodiment; Figure 8 This is a plan view of a semiconductor device according to an embodiment; Figure 9This is a plan view of a semiconductor device according to an embodiment; Figure 10A It is along Figure 9 A cross-sectional view taken by line X1-X1'; Figure 10B It is along Figure 9 A cross-sectional view taken by line X2-X2'; Figure 11A It is along Figure 9 A cross-sectional view taken from line Y1-Y1'; Figure 11B It is along Figure 9 A cross-sectional view taken from line Y2-Y2'; Figure 11C It is along Figure 9 A cross-sectional view taken from line Y3-Y3'; and Figures 12A to 21E This is a cross-sectional view illustrating various operations of a method for manufacturing a semiconductor device according to an embodiment. Detailed Implementation

[0019] In the following, one or more embodiments of the disclosed concept are described in detail with reference to the accompanying drawings. The same reference numerals in the drawings denote the same elements, and repeated descriptions thereof are omitted.

[0020] Figure 1 This is a plan view of the unit block 12 of the semiconductor device 10 according to an embodiment.

[0021] Reference Figure 1 The cell block 12 of the semiconductor device 10 may include a plurality of logic cells LC, which include circuit patterns configured to form various circuits. The logic cells LC may be arranged in a matrix in the width direction (X direction) and height direction (Y direction) within the cell block 12.

[0022] Each logic unit (LC) may include a circuit pattern having a layout designed according to Place and Routing (PnR) technology to perform at least one logic function. The logic unit (LC) may be configured to perform various logic functions. In embodiments, the logic unit (LC) may include a plurality of standard units. In embodiments, at least some of the logic units (LC) may perform the same logic function. In embodiments, at least some of the logic units (LC) may perform different logic functions.

[0023] A logic unit (LC) may include various logic units containing multiple circuit elements. For example, each logic unit (LC) may include AND, NAND, OR, NOR, XOR, XNOR, inverter (INV), adder (ADD), buffer (BUF), delay (DLY), filter (FIL), multiplexer (MXT / MXIT), OR / AND / inverter (OAI), AND / OR (AO), AND / OR / inverter (AOI), D flip-flop, reset flip-flop, master-slave flip-flop, latch, or combinations thereof, but is not limited thereto.

[0024] In cell block 12, at least some of the logic cells LC forming a single row RW1, RW2, RW3, RW4, RW5, or RW6 may have the same width along the width direction (X direction). Furthermore, at least some of the logic cells LC forming a single row RW1, RW2, RW3, RW4, RW5, or RW6 may have the same height. However, one or more embodiments are not limited to this. Figure 1 The embodiments shown, and at least some of the logic cells LC forming a single row RW1, RW2, RW3, RW4, RW5 or RW6, may have different widths and heights.

[0025] The area of ​​each logic cell LC included in the cell block 12 of the semiconductor device 10 may be defined by a cell boundary CBD. A cell boundary contact portion CBC may be disposed between two adjacent logic cells LC that are adjacent to each other in the width direction (X direction) or height direction (Y direction) within the logic cell, wherein the corresponding cell boundaries CBDs of the adjacent logic cells LC intersect.

[0026] In one embodiment, two adjacent logic cells LC that are adjacent to each other in the width direction (X direction) within a logic cell LC forming a single row RW1, RW2, RW3, RW4, RW5, or RW6 may contact each other at the cell boundary contact portion CBC without any gap between them. In another embodiment, two adjacent logic cells LC that are adjacent to each other in the width direction (X direction) within a logic cell LC forming a single row RW1, RW2, RW3, RW4, RW5, or RW6 may be spaced apart by a predetermined distance.

[0027] In one embodiment, two adjacent logic units LC that form a single row RW1, RW2, RW3, RW4, RW5, or RW6 can perform the same function. In this case, the two adjacent logic units LC can have the same structure. In another embodiment, two adjacent logic units LC that form a single row RW1, RW2, RW3, RW4, RW5, or RW6 can perform different functions.

[0028] In an embodiment, any logic cell LC selected from the logic cells LC included in the cell block 12 of the semiconductor device 10 may be symmetrical with respect to the cell boundary contact portion CBC between the selected logic cell LC in the height direction (Y direction). For example, the reference logic cell LC_R in the third row RW3 may be symmetrical with respect to the lower logic cell LC_L in the second row RW2 with respect to the cell boundary contact portion CBC between them. Furthermore, the reference logic cell LC_R in the third row RW3 may be symmetrical with respect to the upper logic cell LC_H in the fourth row RW4 with respect to the cell boundary contact portion CBC between them.

[0029] Figure 1 The illustration shows a cell block 12 comprising six rows RW1 to RW6, but this is merely an example. Cell block 12 may include a variety of numbers of rows as needed, and a row may include a variety of numbers of logical units LC as needed.

[0030] One ground line VSS selected from multiple ground lines VSS and one power line VDD selected from multiple power lines VDD can be arranged between rows RW1 to RW6 formed by logic cells LC arranged in a straight line along the width direction (X direction). The ground line VSS and the power line VDD can each extend in a first horizontal direction (X direction) and can be arranged alternately and spaced apart from each other in a second horizontal direction (Y direction). Therefore, the ground line VSS and the power line VDD can each be arranged to overlap with the cell boundary CBD along the second horizontal direction (Y direction) of the logic cell LC.

[0031] Figure 2 This is a plan view of the semiconductor device 100 according to an embodiment. Figure 3A It is along Figure 2 A cross-sectional view taken by line X1-X1'. Figure 3B It is along Figure 2 The cross-sectional view taken by line X2-X2'. Figure 4A It is along Figure 2 A cross-sectional view taken from line Y1-Y1'. Figure 4B It is along Figure 2 A cross-sectional view taken from line Y2-Y2'. Figure 4C It is along Figure 2 The cross-sectional view taken by line Y3-Y3', and Figure 4D It is along Figure 2 The cross-sectional view taken by line Y4-Y4'. (Refer to...) Figures 2 to 4DThis describes a semiconductor device 100 including a field-effect transistor (FET), the FET having a gate-all-around structure and including an active region in the form of a nanowire or nanosheet and a gate surrounding the active region. However, one or more embodiments are not limited thereto. Figures 2 to 4D As shown in the diagram, semiconductor device 100 may include a FET having a fin-type active region and a fin-type structure surrounding the active region.

[0032] Semiconductor device 100 can be formed Figure 1 Some of the logic units LC shown.

[0033] Reference Figures 2 to 4D The semiconductor device 100 may include a plurality of nanosheet stacks NSS, a plurality of gate lines 160 surrounding the nanosheet stacks NSS, and a plurality of source / drain regions 130 located between two adjacent gate lines 160. The gate lines 160, the nanosheet stacks NSS, and the source / drain regions 130 may each form a plurality of nanosheet transistors.

[0034] The nanosheet stacks (NSS) can be arranged spaced apart from each other in a first horizontal direction (X direction) and a second horizontal direction (Y direction) intersecting the first horizontal direction (X direction). Each nanosheet stack (NSS) may include a first nanosheet N1, a second nanosheet N2, and a third nanosheet N3 that are sequentially stacked and spaced apart from each other in a vertical direction (Z direction). The first nanosheet N1, the second nanosheet N2, and the third nanosheet N3 included in the nanosheet stack (NSS) may each form a channel region.

[0035] As used in this specification, the term "nanosheet" refers to a conductive structure having a cross-section substantially perpendicular to the direction of current flow. It should be understood that nanosheets include nanowires.

[0036] In this specification, although a single nanosheet stack NSS is described as comprising three nanosheets, namely, a first nanosheet N1 to a third nanosheet N3, one or more embodiments are not limited thereto. For example, the number of nanosheets included in the nanosheet stack NSS can be selected in various ways as needed.

[0037] In a single nanosheet stack NSS, the first nanosheets N1 to the third nanosheets N3 may overlap each other in the vertical direction (Z direction) at positions where they are spaced apart from each other. Each of the first nanosheets N1 to the third nanosheets N3 in the single nanosheet stack NSS may be surrounded by a gate line 160. Each of the first nanosheets N1 to the third nanosheets N3 in the single nanosheet stack NSS may serve as a channel region for a nanosheet transistor.

[0038] In an embodiment, the first nanosheet N1 to the third nanosheet N3 may each comprise a silicon (Si) layer, a silicon-germanium (SiGe) layer, or a combination thereof. In an embodiment, the first nanosheet N1 to the third nanosheet N3 may comprise the same material. In an embodiment, the vertical thickness of the first nanosheet N1 to the third nanosheet N3 in the vertical direction (Z direction) may be the same or similar to each other.

[0039] Gate lines 160 may be spaced apart from each other in a first horizontal direction (X direction) and extend in a second horizontal direction (Y direction). Each gate line 160 may surround a first nanosheet N1 to a third nanosheet N3 included in a nanosheet stack NSS. Each gate line 160 may be surrounded by a gate dielectric layer 152.

[0040] Gate lines 160 may surround first nanosheets N1 to third nanosheets N3, while also covering the nanosheet stack NSS. Each gate line 160 may include a main gate portion 160M and a plurality of sub-gate portions 160S, wherein the main gate portion 160M covers the upper surface of the nanosheet stack NSS and extends in a second horizontal direction (Y direction), and the sub-gate portions 160S are integrally connected to the main gate portion 160M and fill the space between the first nanosheets N1 to third nanosheets N3 and the space below the lower surface of the first nanosheet N1. In the vertical direction (Z direction), the thickness of each sub-gate portion 160S may be less than the thickness of the main gate portion 160M.

[0041] Each gate line 160 may comprise a metal, a metal nitride, a metal carbide, or a combination thereof. The metal may be selected from titanium (Ti), tungsten (W), ruthenium (Ru), niobium (Nb), molybdenum (Mo), hafnium (Hf), nickel (Ni), cobalt (Co), platinum (Pt), ytterbium (Yb), terbium (Tb), dysprosium (Dy), erbium (Er), and palladium (Pd). The metal nitride may be selected from titanium nitride (TiN) and tantalum nitride (TaN). The metal carbide may be titanium aluminum carbide (TiAlC). However, the materials forming the gate line 160 are not limited to the examples described above.

[0042] A gate dielectric layer 152 may be disposed between the nanosheet stack NSS and the gate line 160. The gate dielectric layer 152 may have a stacked structure including an interface dielectric layer and a high-k dielectric layer. The interface dielectric layer may include a low-k material having a dielectric constant of about 9 or less, such as a silicon oxide layer, a silicon oxynitride layer, or a combination thereof. In embodiments, the interface dielectric layer may be omitted. The high-k dielectric layer may include a material having a higher dielectric constant than the silicon oxide layer. For example, the high-k dielectric layer may have a dielectric constant ranging from about 10 to about 25. The high-k dielectric layer may include, but is not limited to, hafnium oxide (HfO2).

[0043] Two sidewalls of each of the sub-gate portions 160S included in the gate line 160 may be spaced apart from the source / drain region 130, and a gate dielectric layer 152 is located between the two sidewalls and the source / drain region 130. The gate dielectric layer 152 may include: a portion disposed between the sub-gate portions 160S included in the gate line 160 and each of the first nanosheets N1 to the third nanosheets N3; a portion disposed between the sub-gate portions 160S included in the gate line 160 and the source / drain region 130; and a portion disposed between the sub-gate portion 160S of the gate line 160 that is closest to the back-side insulating pattern BBP and the back-side insulating pattern BBP.

[0044] The two sidewalls of the gate line 160 may be covered by a plurality of main insulating spacers 118. Each main insulating spacer 118 may cover the sidewall of the main gate portion 160M above the upper surface of the nanosheet stack NSS. Each main insulating spacer 118 may be spaced apart from the gate line 160, and a gate dielectric layer 152 is located between each main insulating spacer 118 and the gate line 160.

[0045] The source / drain region 130 may be disposed between two adjacent gate lines 160. The source / drain region 130 may respectively contact the first nanosheet N1, the second nanosheet N2 and the third nanosheet N3 in adjacent nanosheet stacks NSS.

[0046] Each source / drain region 130 may include a semiconductor layer containing a dopant. In an embodiment, the semiconductor device 100 may include a nanosheet transistor, including a PMOS transistor, and each source / drain region 130 may include a SiGe layer doped with a p-type dopant. For example, the p-type dopant may be at least one selected from boron (B) and gallium (Ga), but is not limited thereto.

[0047] In an embodiment, the semiconductor device 100 may include a nanosheet transistor, including an NMOS transistor, and each source / drain region 130 may include a Si layer doped with an n-type dopant or a SiC layer doped with an n-type dopant. For example, the n-type dopant may be at least one selected from phosphorus (P), arsenic (As), and antimony (Sb), but is not limited thereto.

[0048] The front surface of each source / drain region 130 may be covered by an insulating liner 142 and an inter-gate insulating layer 144. The front surface of each source / drain region 130 may be in contact with the insulating liner 142.

[0049] The front source / drain contact CA (hereinafter also referred to as the front contact CA) may be connected to some of the source / drain regions 130. The front source / drain contact CA may penetrate the upper part of its corresponding source / drain region 130 from the front surface of the source / drain region 130 in the vertical direction (Z direction).

[0050] The back-side via contact BCA can be connected to other source / drain regions 130. The back-side via contact BCA can penetrate the lower part of its corresponding source / drain region 130 from the back surface of the source / drain region 130 in the vertical direction (Z direction).

[0051] In the source / drain region 130 included in the semiconductor device 100, the source / drain region 130 connected to the back-side via contact BCA may be different from the source / drain region 130 connected to the front-side source / drain contact CA. In other words, the source / drain region 130 connected to the back-side via contact BCA may be spaced apart from the source / drain region 130 connected to the front-side source / drain contact CA.

[0052] The front metal silicide layer 172 can be disposed between the front source / drain contact CA and the source / drain region 130, connecting to the source / drain region 130 of the front source / drain contact CA. The front source / drain contact CA can be connected to its corresponding source / drain region 130 through the front metal silicide layer 172.

[0053] The front source / drain contact CA can be configured to penetrate the intergate insulating layer 144 and the insulating liner 142 in the vertical direction (Z direction) and be connected to its corresponding source / drain region 130.

[0054] The front source / drain contact CA may include a conductive barrier pattern 174 and a contact plug 176. The conductive barrier pattern 174 may be disposed between the front metal silicide layer 172 and the contact plug 176. The conductive barrier pattern 174 may include a surface that contacts the front metal silicide layer 172 and a surface that contacts the contact plug 176.

[0055] In this embodiment, the conductive barrier pattern 174 may comprise a metal or a metal nitride. For example, the conductive barrier pattern 174 may comprise, but is not limited to, Ti, tantalum (Ta), W, TiN, TaN, WN, WCN, TiSiN, TaSiN, WSiN, or combinations thereof. The contact plug 176 may comprise, but is not limited to, Mo, copper (Cu), W, Co, Ru, manganese (Mn), Ti, Ta, aluminum (Al), or combinations thereof or alloys thereof.

[0056] A back-side metallization layer 192 may be disposed between the back-side via contact BCA and the source / drain region 130 connected to the back-side via contact BCA. The back-side via contact BCA can be connected to its corresponding source / drain region 130 through the back-side metallization layer 192.

[0057] The semiconductor device 100 may include: a plurality of back-side insulating patterns BBP arranged in a row along a first horizontal direction (X direction) and each extending in a second horizontal direction (Y direction); a plurality of semiconductor blocks SB; a plurality of back-side via contacts BCA spaced apart from each other by the back-side insulating patterns BBP in the first horizontal direction (X direction); and a plurality of back-side power rails BPW respectively connected to the back-side via contacts BCA.

[0058] In the semiconductor device 100, the back-side insulating pattern BBP can be spaced apart from the nanosheet stack NSS in the vertical direction (Z direction).

[0059] The back-side insulating pattern BBP may extend in the vertical direction (Z direction) toward a gate line 160 selected from the gate line 160. The back-side insulating pattern BBP may include a pair of back-side insulating patterns BBP respectively disposed on both sides of a back-side via contact BCA, wherein a back-side via contact BCA is located between the pair of back-side insulating patterns BBP in a first horizontal direction (X direction). The pair of back-side insulating patterns BBP may each extend in the vertical direction (Z direction) at a position where each back-side insulating pattern BBP is aligned with a gate line 160 selected from the gate line 160. The pair of back-side insulating patterns BBP may include a portion facing the back-side via contact BCA in the first horizontal direction (X direction). Each back-side insulating pattern BBP may contact the gate dielectric layer 152.

[0060] In an embodiment, each back-side insulating pattern (BBP) may include a nitrogen-containing insulating layer. For example, each back-side insulating pattern (BBP) may include a SiN layer, a SiCN layer, a SiOCN layer, or a combination thereof, but one or more embodiments are not limited thereto.

[0061] Each back-side via contact BCA can be connected to a single back-side power rail BPW selected from the back-side power rails BPW. The back-side via contacts BCA can be arranged in the first horizontal direction (X direction) between the back-side insulation patterns BBP.

[0062] In the vertical direction (Z direction), the back-side via contact BCA may extend between a pair of adjacent back-side insulating patterns BBP within the back-side insulating pattern BBP. The back-side via contact BCA may extend in the second horizontal direction (Y direction).

[0063] The back-side via contact BCA can be connected to the lower surfaces of two source / drain regions 130 that face each other in the second horizontal direction (Y direction). In other words, the back-side via contact BCA can be a common back-side via contact that is commonly connected to the two source / drain regions 130.

[0064] Each back-side via contact BCA may have a width in the first horizontal direction (X direction) that increases in the vertical direction (Z direction) away from its corresponding source / drain region 130.

[0065] The back-side via contact BCA may include a conductive barrier pattern 194 and a contact plug 196. The conductive barrier pattern 194 may be located between the back-side metal silicide layer 192 and the contact plug 196. The conductive barrier pattern 194 may have a surface that contacts the back-side metal silicide layer 192 and a surface that contacts the contact plug 196.

[0066] In this embodiment, the conductive barrier pattern 194 may comprise a metal or a metal nitride. For example, the conductive barrier pattern 194 may comprise Ti, Ta, W, TiN, TaN, WN, WCN, TiSiN, TaSiN, WSiN, or combinations thereof, but is not limited thereto. The contact plug 196 may comprise Mo, Cu, W, Co, Ru, Mn, Ti, Ta, Al, or combinations thereof, or alloys thereof, but is not limited thereto.

[0067] A single back-side via contact BCA may include a second portion BCA2a and a pair of first portions BCA1a. The second portion BCA2a is located between a pair of source / drain regions 130 spaced apart in a second horizontal direction (Y direction), and the first portions BCA1a face the lower surfaces of the pair of source / drain regions 130 having a back-side metal silicide layer 192 therebetween. The first portions BCA1a face each other in the second horizontal direction (Y direction), and the second portion BCA2a is located between the first portions BCA1a. The pair of first portions BCA1a may be formed in a first space BH1, and the second portion BCA2a may be formed in a second space BH2. In this case, the first space BH1 may communicate with the second space BH2.

[0068] The first portions BCA1a can each face the lower surface of the pair of source / drain regions 130 that are commonly connected to a single back-side via contact BCA, with a back-side metal silicide layer 192 located between the first portions BCA1a and the lower surfaces of the source / drain regions 130. The first portions BCA1a can contact the side surface of the semiconductor block SB in the first horizontal direction (X direction), and the second portion BCA2a can contact the device isolation layer 112 and the back-side insulating pattern BBP in the first horizontal direction (X direction).

[0069] The first portion BCA1a of the back-side via contact BCA may have a square shape in the plan view, and the second portion BCA2a of the back-side via contact BCA may have a square shape with rounded corners in the plan view. However, one or more embodiments are not limited thereto. The second portion BCA2a of the back-side via contact BCA may have a polygonal shape with rounded corners in the plan view, for example, a hexagonal shape.

[0070] The first portion BCA1a of the back-side through-hole contact BCA may have a first horizontal width W1, and the second portion BCA2a may have a second horizontal width W2. In an embodiment, the first horizontal width W1 may be smaller than the second horizontal width W2.

[0071] A first portion BCA1a of a back-side via contact BCA between a pair of adjacent back-side insulating patterns BBP disposed within a back-side insulating pattern BBP may be spaced apart from the pair of adjacent back-side insulating patterns BBP in a first horizontal direction (X direction). Conversely, a second portion BCA2a of a back-side via contact BCA between a pair of adjacent back-side insulating patterns BBP may contact the sidewall of the pair of adjacent back-side insulating patterns BBP.

[0072] The upper surface of the first portion BCA1a of the back-side via contact BCA may be located at a vertical level higher than the upper surface of the second portion BCA2a of the back-side via contact BCA. In other words, the upper surface of the second portion BCA2a of the back-side via contact BCA may be located at a vertical level lower than the lower surface of the source / drain region 130 facing the first portion BCA1a of the back-side via contact BCA. As used in this specification, the term "vertical level" refers to the distance in the vertical direction (Z direction or -Z direction) from the lower surface of the back-side via contact BCA closest to the back-side insulating layer 109.

[0073] Some of the semiconductor blocks SB may cover the sidewalls of the back-side via contact BCA in the first horizontal direction (X direction). In an embodiment, some of the semiconductor blocks SB may contact the sidewalls of the back-side insulating pattern BBP in the first horizontal direction (X direction). Some of the semiconductor blocks SB may be located between the back-side insulating pattern BBP and the back-side via contact BCA.

[0074] Each semiconductor block SB may include Si. The semiconductor block SB may contact the gate dielectric layer 152 covering the lowermost surface of the gate line 160. Here, the lowermost surface of the gate line 160 may refer to the surface of the gate line 160 closest to the back-side power rail BPW.

[0075] The two sidewalls of the back-side insulating pattern BBP in the first horizontal direction (X direction) can be covered by the device isolation layer 112. The two sidewalls of the back-side via contact BCA in the second horizontal direction (Y direction) can be covered by the device isolation layer 112. In addition, some of the semiconductor blocks SB have two sidewalls in the second horizontal direction (Y direction) covered by the device isolation layer 112.

[0076] The device isolation layer 112 may have a surface facing the gate line 160 and a surface contacting the back-side insulating pattern BBP, wherein the gate dielectric layer 152 is located between the device isolation layer 112 and the gate line 160. Furthermore, the device isolation layer 112 may have a surface contacting the back-side via contact BCA in the second horizontal direction (Y direction) and a surface contacting the semiconductor block SB in the second horizontal direction (Y direction). The device isolation layer 112 may be an oxide layer, a nitride layer, or a combination thereof.

[0077] The back-side power rail (BPW) can be arranged on the lower surface of the back-side via contact (BCA). Within the back-side power rails (BPW), those connected to the back-side via contact (BCA) are spaced apart from their corresponding source / drain regions 130 in the vertical direction (Z-direction), with the back-side via contact (BCA) located between the back-side power rails (BPW) and their corresponding source / drain regions 130. The back-side power rails (BPW) can extend in a second horizontal direction (Y-direction).

[0078] Each back-side power rail (BPW) may have a width in a first horizontal direction (X direction) that increases in the vertical direction (Z direction) away from its corresponding source / drain region 130.

[0079] An etch stop layer (ESL) covering the upper surface of each semiconductor block SB can be disposed on each semiconductor block SB. The etch stop layer (ESL) can be disposed between the upper surface of each semiconductor block SB and the gate line 160, and in contact with the upper surface of each semiconductor block SB.

[0080] In an embodiment, the etch stop layer (ESL) may be an insulating layer. For example, the etch stop layer (ESL) may include at least one selected from SiN, SiON, SiCN, SiOC, SiOCN, and combinations thereof, but one or more embodiments are not limited thereto.

[0081] The back insulating layer 109 can be disposed on the end face of each back via contact BCA farthest from the source / drain region 130, the end face of the device isolation layer 112 farthest from the source / drain region 130, and the end face of each semiconductor block SB farthest from the source / drain region 130. The lower surface of each back via contact BCA, the lower surface of the device isolation layer 112, and the lower surface of each semiconductor block SB can contact the back insulating layer 109. The back insulating layer 109 can be spaced apart from the etch stop layer ESL in the vertical direction (Z direction), wherein each semiconductor block SB and the device isolation layer 112 are located between the back insulating layer 109 and the etch stop layer ESL.

[0082] In an embodiment, the back-side insulating layer 109 may include a silicon oxide layer, a silicon nitride layer, a silicon carbide layer, a low-k dielectric layer, or a combination thereof. The low-k dielectric layer may include fluorine-doped silicon oxide, organosilicon glass, carbon-doped oxide, porous silicon oxide, porous organosilicon glass, spin-coated organic polymer dielectric, spin-coated silicon-based polymer dielectric, or a combination thereof, but one or more embodiments are not limited thereto.

[0083] like Figure 4A , Figure 4B and Figure 4D As shown, a plurality of side insulating spacers 119 may be arranged on the device isolation layer 112. The side insulating spacers 119 may cover the sidewalls of the source / drain region 130. In an embodiment, each side insulating spacer 119 may be integrally connected to the adjacent main insulating spacer 118.

[0084] The main insulating spacer 118 and the side insulating spacer 119 may each comprise SiN, SiO2, SiOC, SiOCN, SiCN, SiBN, SiON, SiBCN, SiOF, SiOCH, or combinations thereof. The main insulating spacer 118 and the side insulating spacer 119 may be a single layer comprising a material layer selected from the above materials, or multiple layers comprising multiple material layers selected from the above materials.

[0085] The upper surfaces of the gate line 160 and the gate dielectric layer 152 may be covered by a capping insulating pattern 168. Each capping insulating pattern 168 may include a silicon nitride layer.

[0086] Source / drain regions 130, device isolation layer 112, main insulating spacer 118, and side insulating spacer 119 may be covered by insulating liner 142. Inter-gate insulating layer 144 may be disposed on insulating liner 142. Inter-gate insulating layer 144 may be disposed between a pair of adjacent gate lines 160 and between a pair of adjacent source / drain regions 130 along a first horizontal direction (X direction). In embodiments, insulating liner 142 may include SiN, SiCN, SiBN, SiON, SiOCN, SiBCN, or combinations thereof, but one or more embodiments are not limited thereto. Inter-gate insulating layer 144 may include, but is not limited to, a silicon oxide layer.

[0087] A front source / drain contact CA may be disposed above a source / drain region 130 between a pair of adjacent gate lines 160. A single front source / drain contact CA may be connected to a single source / drain region 130 or two adjacent source / drain regions 130, but one or more embodiments are not limited thereto. In a first horizontal direction (X direction), the front source / drain contact CA may be spaced apart from the main gate portion 160M of the gate line 160 adjacent to the front source / drain contact CA, wherein a main insulating spacer 118 is located between the front source / drain contact CA and the main gate portion 160M. A front insulating structure including an insulating liner 142 and an inter-gate insulating layer 144 may surround the sidewall of the front source / drain contact CA.

[0088] The upper surfaces of the front source / drain contacts CA, the capping insulating pattern 168, the insulating liner 142, and the gate-to-gate insulating layer 144 may each be covered by an upper insulating structure 180. The upper insulating structure 180 may include an etch stop layer 182 and an upper insulating layer 184. The etch stop layer 182 may include SiC, SiN, SiCN, SiOC, AlN, AlON, AlOC, or combinations thereof. The upper insulating layer 184 may include an oxide layer, a nitride layer, an ultra-low k (ULK) layer having an ultra-low dielectric constant ranging from about 2.2 to about 2.4, or combinations thereof. For example, the upper insulating layer 184 may include a tetraethyl orthosilicate (TEOS) layer, a high-density plasma (HDP) oxide layer, a borosilicate glass (BPSG) layer, a flowable chemical vapor deposition (FCVD) oxide layer, a SiON layer, a SiN layer, a SiOC layer, a SiCOH layer, or combinations thereof, but one or more embodiments are not limited thereto.

[0089] Source / drain via contacts VA can be disposed on the front source / drain contact CA. The source / drain via contact VA can contact the front source / drain contact CA through the upper insulating structure 180. In the source / drain region 130, the source / drain region 130 connected to the front source / drain contact CA can be electrically connected to the source / drain via contact VA through the front metal silicide layer 172 and the front source / drain contact CA. The source / drain via contacts VA may each contain Mo or W, but are not limited thereto.

[0090] A gate contact CB may be disposed on a gate line 160. The gate contact CB may be connected to the gate line 160 by penetrating the upper insulating structure 180 and the capping insulating pattern 168 in the vertical direction (Z direction). The lower surface of the gate contact CB may contact the upper surface of the gate line 160. The gate contact CB may include a contact plug comprising Mo, Cu, W, Co, Ru, Mn, Ti, Ta, Al, combinations thereof, or alloys thereof, but the material forming the contact plug is not limited thereto. In an embodiment, the gate contact CB may also include a conductive barrier pattern surrounding a portion of the contact plug. The conductive barrier pattern of the gate contact CB may include a metal or a metal nitride. For example, the conductive barrier pattern may include Ti, Ta, W, TiN, TaN, WN, WCN, TiSiN, TaSiN, WSiN, or combinations thereof, but is not limited thereto.

[0091] The upper surface of the upper insulating structure 180 may be covered by a front interlayer insulating layer 186. The material forming the front interlayer insulating layer 186 is substantially the same as the material of the upper insulating layer 184 described above. A plurality of upper wiring layers M1 may be arranged to penetrate the front interlayer insulating layer 186. The upper wiring layers M1 may be connected to source / drain via contacts VA or gate contacts CB. Each of the upper wiring layers M1 may include, but is not limited to, Mo, Cu, W, Co, Ru, Mn, Ti, Ta, Al, combinations thereof, or alloys thereof.

[0092] In the manufacturing process of semiconductor device 100, a first portion BCA1a may be formed in the region where the material used to form the semiconductor block SB is etched, and a second portion BCA2a may be formed in the region where the material used to form the device isolation layer 112 and the back-side insulating pattern BBP is etched. In this case, in existing semiconductor devices where the width of the first portion is the same as the width of the second portion, i.e., in existing semiconductor devices with a rectangular shape in the plan view, the difference in etching selectivity between the material used to form the semiconductor block and the material used to form the device isolation layer and the back-side insulating pattern may lead to insufficient space for the second portion; therefore, problems such as open-circuit faults in back-side via contacts formed after the etching process may occur.

[0093] Conversely, the semiconductor device 100 according to an embodiment of the disclosed concept may include a back-side via contact BCA, which includes a first portion BCA1a having a relatively narrow first horizontal width W1 and contacting the semiconductor block SB, and a second portion BCA2a having a relatively large second horizontal width W2 and contacting the device isolation layer 112 and the back-side insulating pattern BBP. Because the second portion BCA2a has a relatively larger horizontal width than the first portion BCA1a, open-circuit failures of the back-side via contact BCA can be prevented, and therefore, the functional reliability of the semiconductor device 100 can be improved.

[0094] Figure 5 This is a plan view of the semiconductor device 100a according to an embodiment. Because Figure 5 The various components of the semiconductor device 100a are as described above. Figures 2 to 4D Since the components of the semiconductor device 100 described are similar, the following mainly describes the differences between them.

[0095] Reference Figure 5 Except that the semiconductor device 100a includes a back-side via contact BCAa, which includes a second portion of a square with corners, the semiconductor device 100a can be coupled with... Figures 2 to 4D The semiconductor device 100 shown is substantially the same.

[0096] However, one or more embodiments are not limited thereto. The second part of the back-side via contact BCA may have a polygonal shape with angles in the plan view, such as a hexagon.

[0097] Figure 6 This is a plan view of the semiconductor device 100b according to an embodiment. Because Figure 6 The various components of the semiconductor device 100b are in accordance with the above reference. Figures 2 to 4D Since the components of the semiconductor device 100 described are similar, the following mainly describes the differences between them.

[0098] Reference Figure 6 In addition to the semiconductor device 100b including a back-side via contact BCAb with a raised second portion, the semiconductor device 100b can be coupled with... Figures 2 to 4D The semiconductor device 100 shown is substantially the same. As the second portion of the back-side via contact BCAb moves further away from each of the pair of first portions of the back-side via contact BCAb in the second horizontal direction (Y direction), the second portion can protrude outward.

[0099] Figure 7 This is a plan view of the semiconductor device 100c according to an embodiment. Because Figure 7The various components of the semiconductor device 100c are as described above. Figures 2 to 4D Since the components of the semiconductor device 100 described are similar, the following mainly describes the differences between them.

[0100] Reference Figure 7 In addition to the semiconductor device 100c including a second front contact CAa disposed on the first portion BCA1a of the back-side via contact BCA, the semiconductor device 100c can be connected to... Figures 2 to 4D The semiconductor device 100 shown is substantially the same.

[0101] Semiconductor device 100c may include a first front contact CA and a second front contact CAa. The first front contact CA is disposed on some source / drain regions 130 within the source / drain regions 130 that do not face the back-side via contact BCA. The second front contact CAa is disposed on other source / drain regions 130 within the source / drain regions 130 that face the back-side via contact BCA. The second front contact CAa may have the same characteristics as... Figures 2 to 4D The front contact CA of the semiconductor device 100 shown has a substantially the same or similar structure and may include a structure similar to that of the semiconductor device 100 shown. Figures 2 to 4D The front contact CA of the semiconductor device 100 shown is made of substantially the same or similar material. The second front contact CAa may face the upper surface of another portion of the source / drain region 130, which faces the back via contact BCA, and the front metal silicide layer 172 is located between the second front contact CAa and the source / drain region 130.

[0102] In one embodiment, a second front contact CAa may be disposed on each of a pair of first portions of a back via contact BCA, the pair of first portions facing each other in a second horizontal direction (Y direction), with a second portion located between the pair of first portions. In other words, two second front contacts CAa may be disposed on a single back via contact BCA.

[0103] In one embodiment, the second front contact CAa may be disposed on either of a pair of first portions of the back via contact BCA, the pair of first portions facing each other in a second horizontal direction (Y direction), with the second portion located between the pair of first portions, while the second front contact CAa may not be disposed on the other of the pair of first portions of the back via contact BCA. In other words, a single second front contact CAa may be disposed on a single back via contact BCA.

[0104] In an embodiment, the second front contact CAa, the other source / drain regions 130 facing the back via contact BCA, and the first portion of the back via contact BCA can be aligned in the vertical direction (Z direction).

[0105] Figure 8 This is a plan view of the semiconductor device 100d according to an embodiment. (Refer to...) Figure 8 In addition to the semiconductor device 100d including a second front contact CAb disposed on the back via contact BCA, the semiconductor device 100d can be connected to... Figures 2 to 4D The semiconductor device 100 shown is substantially the same.

[0106] Reference Figure 8 The semiconductor device 100d may include first front contacts CA disposed on some source / drain regions 130 that do not face the back-side via contact BCA, and second front contacts CAb disposed on other source / drain regions 130 that face the back-side via contact BCA. The second front contacts CAb may have the same characteristics as... Figures 2 to 4D The front contact CA of the semiconductor device 100 shown has a substantially the same or similar structure, and may include structures similar to those of the semiconductor device 100 shown. Figures 2 to 4D The front contact CA of the semiconductor device 100 shown is made of substantially the same or similar material.

[0107] The second front contact CAb can be connected to the upper surface of each of a pair of source / drain regions 130 facing a single back-side via contact BCA in the source / drain region 130. In other words, the second front contact CAb can be a contact that is commonly connected to the pair of source / drain regions 130. The second front contact CAb can be aligned with the first and second portions of the back-side via contact BCA in the vertical direction (Z direction). That is, with Figure 7 Compared to the second front contact CAa of the semiconductor device 100c, Figure 8 The second front contact CAb of the semiconductor device 100d can extend relatively long in the second horizontal direction (Y direction).

[0108] In an embodiment, in a plan view, the second front contact CAb may have a rectangular shape extending in a second horizontal direction (Y direction).

[0109] In this embodiment, the second front contact CAb, the other source / drain regions 130 facing the back via contact BCA, and the back via contact BCA can be aligned in the vertical direction (Z direction).

[0110] Figure 9 This is a plan view of the semiconductor device 200 according to an embodiment. Figure 10A It is along Figure 9 A cross-sectional view taken by line X1-X1'. Figure 10B It is along Figure 9The cross-sectional view taken by line X2-X2'. Figure 11A It is along Figure 9 A cross-sectional view taken from line Y1-Y1'. Figure 11B It is along Figure 9 The cross-sectional view of line Y2-Y2', and Figure 11C It is along Figure 9 The cross-sectional view taken by line Y3-Y3'. Because Figures 9 to 11C The various components of the semiconductor device 200 are in accordance with the above reference. Figures 2 to 4D Since the components of the semiconductor device 100 described are similar, the following mainly describes the differences between them.

[0111] Reference Figures 9 to 11C In addition to the semiconductor device 200 including a first back-side via contact BCA1 and a second back-side via contact BCA2 with different planar shapes, the semiconductor device 200 may have the same features as the referenced one. Figures 2 to 4D The semiconductor device 100 described has a substantially the same or similar structure.

[0112] The semiconductor device 200 may include a first back-side via contact BCA1 and a second back-side via contact BCA2, wherein the first back-side via contact BCA1 is connected to any pair of source / drain regions 130 spaced apart from each other in the second horizontal direction (Y direction), and the second back-side via contact BCA2 is spaced apart from the aforementioned pair of source / drain regions 130 in the first horizontal direction (X direction) and is connected to another pair of source / drain regions 130 spaced apart from each other in the second horizontal direction (Y direction).

[0113] The first back-side via contact BCA1 may include a second portion BCA2a_1 disposed between any pair of source / drain regions 130 spaced apart from each other along the second horizontal direction (Y direction), and a pair of first portions BCA1a_1 facing the lower surfaces of the pair of source / drain regions 130 and facing each other along the second horizontal direction (Y direction), wherein the second portion BCA2a_1 is located between the pair of first portions BCA1a_1.

[0114] The first portions BCA1a_1 can each face the lower surfaces of a pair of source / drain regions 130 that are commonly connected to a single first back-side via contact BCA1. The first portions BCA1a_1 can contact the side surface of the semiconductor block SB in the first horizontal direction (X direction), and the second portion BCA2a_1 can contact the device isolation layer 112 and the back-side insulating pattern BBP in the first horizontal direction (X direction).

[0115] The first portion BCA1a_1 of the first back-side via contact BCA1 may have a square shape in a plan view, and the second portion BCA2a_1 of the first back-side via contact BCA1 may have a square shape with rounded corners in a plan view. However, one or more embodiments are not limited thereto, and the second portion BCA2a_1 of the first back-side via contact BCA1 may have, for example, a square shape with corners or a convex shape.

[0116] The first portion BCA1a_1 of the first back-side through-hole contact BCA1 may have a first horizontal width W1, and the second portion BCA2a_1 may have a second horizontal width W2. In an embodiment, the first horizontal width W1 may be smaller than the second horizontal width W2.

[0117] The second back-side via contact BCA2 may be spaced apart from the first back-side via contact BCA1 in a first horizontal direction (X direction). The second back-side via contact BCA2 may include a second portion BCA2a_2 and a pair of first portions BCA1a_2, wherein the second portion BCA2a_2 corresponds in the first horizontal direction (X direction) to the second portion BCA2a_1 of the first back-side via contact BCA1, and the first portions BCA1a_2 correspond in the first horizontal direction (X direction) to the pair of first portions BCA1a_1 of the first back-side via contact BCA1. In a plan view, the second back-side via contact BCA2 may have a rectangular shape. In other words, the second portion BCA2a_2 and the pair of first portions BCA1a_2 of the second back-side via contact BCA2 may have the same third horizontal width W3. In an embodiment, the third horizontal width W3 may be substantially the same as the first horizontal width W1.

[0118] The first portions BCA1a_2 may each face the lower surface of a pair of source / drain regions 130 that are commonly connected to a single second back-side via contact BCA2. The first portions BCA1a_2 may contact the side surface of the semiconductor block SB in a first horizontal direction (X direction), and the second portion BCA2a_2 may contact the device isolation layer 112 in the first horizontal direction (X direction). In other words, unlike the second portion BCA2a_1 of the first back-side via contact BCA1, the second portion BCA2a_2 of the second back-side via contact BCA2 may be spaced apart from the back-side insulating pattern BBP in the first horizontal direction (X direction).

[0119] The vertical height BCA2H of the second portion BCA2a_2 of the second back-side via contact BCA2 may be less than the vertical height BCA1H of the second portion BCA2a_1 of the first back-side via contact BCA1. This difference in vertical height may be attributed to the fact that because the second horizontal width W2 of the second portion BCA2a_1 of the first back-side via contact BCA1 is greater than the third horizontal width W3 of the second portion BCA2a_2 of the second back-side via contact BCA2, when the corresponding holes for the second portion BCA2a_1 of the first back-side via contact BCA1 and the second portion BCA2a_2 of the second back-side via contact BCA2 are etched in the manufacturing process of the semiconductor device 200, the holes for the second portion BCA2a_1 of the first back-side via contact BCA1 are etched further than the holes for the second portion BCA2a_2 of the second back-side via contact BCA2.

[0120] The upper surface of the first portion BCA1a_1 of the first back-side through-hole contact BCA1 may be located at the same vertical horizontal position as the upper surface of the first portion BCA1a_2 of the second back-side through-hole contact BCA2.

[0121] The upper surface of the second part BCA2a_1 of the first back-side through-hole contact BCA1 may be located at a vertical horizontal position that is higher than the upper surface of the second part BCA2a_2 of the second back-side through-hole contact BCA2.

[0122] The first back-side via contact BCA1 may include a first conductive blocking pattern 194_1 and a first contact plug 196_1, and the second back-side via contact BCA2 may include a second conductive blocking pattern 194_2 and a second contact plug 196_2. The first conductive blocking pattern 194_1 and the first contact plug 196_1 of the first back-side via contact BCA1, and the second conductive blocking pattern 194_2 and the second contact plug 196_2 of the second back-side via contact BCA2, may respectively connect to… Figures 2 to 4D The conductive barrier pattern 194 and contact plug 196 of the semiconductor device 100 shown are substantially the same or similar.

[0123] Figures 12A to 21E This is a cross-sectional view illustrating various operations of a method for manufacturing a semiconductor device according to an embodiment. In detail, Figures 12A to 21A It is along Figure 2 A cross-sectional view taken by line X1-X1'. Figures 15B to 21B It is along Figure 2 A cross-sectional view taken from line X2-X2'. Figures 12B to 14B and Figures 15C to 21C It is along Figure 2 A cross-sectional view taken from line Y1-Y1'. Figures 12C to 14C and Figures 15D to 21D It is along Figure 2 The cross-sectional view of the line Y2-Y2', and Figures 12D to 14D and Figures 15E to 21E It is along Figure 2 The cross-sectional view taken from line Y3-Y3'.

[0124] Reference Figures 12A to 12D A substrate 102 comprising a front surface 102F and a back surface 102B facing each other can be prepared first. A sacrificial layer PL can be formed on the front surface 102F of the substrate 102, and a stacked structure in which a sacrificial semiconductor layer 104 and a nanosheet semiconductor layer NS are alternately stacked layer by layer can be formed on the sacrificial layer PL.

[0125] In the above-described stacked structure, the sacrificial semiconductor layer 104 and the nanosheet semiconductor layer NS may comprise different semiconductor materials with different etch selectivity. In an embodiment, each nanosheet semiconductor layer NS may comprise a Si layer, while each sacrificial semiconductor layer 104 may comprise a SiGe layer. The SiGe layer forming the sacrificial semiconductor layer 104 may have a constant Ge content selected from about 5 atomic percentages (at%) to about 50 at% (e.g., from about 10 at% to about 40 at%). In an embodiment, each of the sacrificial semiconductor layers 104 may comprise a SiGe layer, and the Ge content of each sacrificial semiconductor layer 104 may be the same.

[0126] The sacrificial layer PL may comprise a SiGe layer in a manner similar to that of the sacrificial semiconductor layer 104. However, the Ge content of the SiGe layer forming the sacrificial layer PL may be greater than the Ge content of the SiGe layer forming the sacrificial semiconductor layer 104. In embodiments, the sacrificial layer PL may have a Ge content selected in the range of about 60 at% to about 70 at%. For example, the sacrificial layer PL may have a Ge content of about 65 at%.

[0127] Reference Figures 13A to 13D , through from Figures 12A to 12D The result is that a portion of each of the sacrificial semiconductor layer 104, the nanosheet semiconductor layer NS, the sacrificial layer PL, and the substrate 102 is etched, which can form a plurality of fin-type active regions F1 defining trench regions T1 in the substrate 102. The stacked structure including the sacrificial layer PL, the sacrificial semiconductor layer 104, and the nanosheet semiconductor layer NS can be retained on the upper surface of each fin-type active region F1.

[0128] The etch stop layer (ESL) can then be used to replace the sacrificial layer PL exposed on the sidewalls of the stacked structure. In an embodiment, to replace the sacrificial layer PL with the ESL, the sacrificial layer PL can first be selectively removed from the sidewalls of the stacked structure, and then the space occupied by the sacrificial layer PL can be filled with the ESL. To selectively remove the sacrificial layer PL, a selective wet etching process utilizing the difference in Ge content can be performed.

[0129] Reference Figures 14A to 14D , can Figures 13A to 13D As a result, a device isolation layer 112 is formed on the filled trench region T1. After the device isolation layer 112 is formed, the sidewalls of each fin active region F1 and the sidewalls of the etch stop layer ESL can be covered by the device isolation layer 112.

[0130] Then, multiple dummy gate structures DGS can be formed on the stacked structure including an etch stop layer ESL, a sacrificial semiconductor layer 104, and a nanosheet semiconductor layer NS. Each dummy gate structure DGS can be formed to extend in a second horizontal direction (Y direction). Each dummy gate structure DGS may have a structure in which an oxide layer D122, a dummy gate layer D124, and a capping layer D126 are sequentially stacked. In an embodiment, the dummy gate layer D124 may include polysilicon, and the capping layer D126 may include a silicon nitride layer.

[0131] After forming a plurality of main insulating spacers 118 covering the two sidewalls of each dummy gate structure DGS, a portion of each of the sacrificial semiconductor layer 104 and the nanosheet semiconductor layer NS can be etched using the dummy gate structure DGS and the main insulating spacers 118 as an etch mask, and the nanosheet semiconductor layer NS can be divided into a plurality of nanosheet stacks NSS; thus, a plurality of recesses R1 can be formed above the etch stop layer ESL. Each nanosheet stack NSS may include a first nanosheet N1, a second nanosheet N2, and a third nanosheet N3. Dry etching, wet etching, or a combination thereof can be performed to form the recesses R1. After forming the recesses R1, a plurality of side insulating spacers 119 can be formed on the device isolation layer 112 such that the plurality of side insulating spacers 119 are adjacent to the recesses R1 on both sides of each fin active region F1.

[0132] Reference Figures 15A to 15E , can Figures 14A to 14D As a result, a source / drain region 130 is formed to fill the recess R1. In order to form the source / drain region 130, a semiconductor material can be epitaxially grown from the sidewalls of each of the first nanosheet N1, the second nanosheet N2, and the third nanosheet N3 in the nanosheet stack NSS exposed in the recess R1.

[0133] An insulating liner 142 can then be formed covering the result of the formation of the active / drain regions 130 thereon. An inter-gate insulating layer 144 can be formed on the insulating liner 142. The upper surface of the capping layer D126 can then be exposed by etching a portion of each of the insulating liner 142 and the inter-gate insulating layer 144. The capping layer D126 can then be removed to expose the dummy gate layer D124, and portions of the insulating liner 142 and the inter-gate insulating layer 144 can be removed such that the upper surface of the inter-gate insulating layer 144 is at substantially the same level as the upper surface of the dummy gate layer D124.

[0134] Reference Figures 16A to 16E ,exist Figures 15A to 15E In the result, the gate space GS can be fabricated by removing the dummy gate layer D124 and the underlying oxide layer D122, and the nanosheet stack NSS can be exposed through the gate space GS. Then, the portion of the sacrificial semiconductor layer 104 retained on the fin active region F1 can be removed through the gate space GS, such that the gate space GS extends to the space between the first nanosheet N1, the second nanosheet N2, and the third nanosheet N3, as well as the space between the first nanosheet N1 and the etch stop layer ESL. In an embodiment, the sacrificial semiconductor layer 104 can be selectively removed using the difference in etch selectivity between the first nanosheet N1 to the third nanosheet N3 and the sacrificial semiconductor layer 104.

[0135] Liquid etchants or gas etchants can be used to selectively remove the sacrificial semiconductor layer 104. In one embodiment, a CH3COOH-based etchant (e.g., an etchant containing a mixture of CH3COOH, HNO3, and HF, or an etchant containing a mixture of CH3COOH, H2O2, and HF) can be used to selectively remove the sacrificial semiconductor layer 104, but one or more embodiments are not limited thereto.

[0136] Reference Figures 17A to 17E ,exist Figures 16A to 16E As a result, a gate dielectric layer 152 can be formed to cover the exposed surfaces of the first nanosheet N1, the second nanosheet N2, the third nanosheet N3, the etch stop layer ESL, and the device isolation layer 112. An atomic layer deposition (ALD) process can be performed to form the gate dielectric layer 152.

[0137] Then, on the gate dielectric layer 152, a gate line 160 filling a portion of the gate space GS can be formed (see...). Figure 16A , Figure 16B and Figure 16E ) and a capping insulating pattern 168 covering the upper surface of each of the gate lines 160 and the gate dielectric layer 152 in the gate space GS.

[0138] Reference Figures 18A to 18E ,exist Figures 17A to 17E As a result, after forming source / drain contact holes exposing source / drain regions 130 by penetrating the inter-gate insulating layer 144 and the insulating liner 142, a portion of the source / drain regions 130 can be anisotropically removed through the source / drain contact holes, allowing the source / drain contact holes to extend further toward the substrate 102. A metal silicide layer 172 can then be formed on the exposed source / drain regions 130 within each of the source / drain contact holes. In an embodiment, to form the metal silicide layer 172, a process including forming a metal liner (not shown) conformally covering the exposed surfaces of the source / drain regions 130 and then heat-treating the metal liner to induce a reaction between the source / drain regions 130 and the metal forming the metal liner can be performed. After forming the metal silicide layer 172, the remaining portion of the metal liner can be removed. During the process of forming the metal silicide layer 172, a portion of the source / drain regions 130 may be consumed. In an embodiment, when the metal silicide layer 172 includes a titanium silicide layer, the metal liner may include a Ti layer.

[0139] Then, a front source / drain contact CA, including a conductive barrier pattern 174 and a contact plug 176, can be formed in each of the source / drain contact holes.

[0140] Next, an etch stop layer 182 and an upper insulating layer 184 may be sequentially formed covering the upper surface of the gate-to-gate insulating layer 144, the front source / drain contact CA, and the capping insulating pattern 168, thereby forming an upper insulating structure 180.

[0141] Then, a source / drain via contact VA can be formed that is connected to the front source / drain contact CA by penetrating the upper insulating structure 180 in the vertical direction (Z direction), and a gate contact CB can be formed that is connected to the gate line 160 by penetrating the upper insulating structure 180 and the capping insulating pattern 168 in the vertical direction (Z direction). Figure 4C The source / drain via contacts VA and the gate contact CB can be formed simultaneously or through separate processes. There are no particular restrictions on the order in which the source / drain via contacts VA and the gate contact CB are formed.

[0142] Then, an interlayer insulating layer 186 covering the upper insulating structure 180 and a plurality of upper wiring layers M1 penetrating the interlayer insulating layer 186 can be formed. Each upper wiring layer M1 may include an upper wiring layer M1 connected to the source / drain via contact VA and an upper wiring layer M1 connected to the gate contact CB.

[0143] Reference Figures 19A to 19E ,according to Figures 18A to 18EAs a result, the fin-type active region F1 and the device isolation layer 112 can be exposed by removing the substrate 102 from the back surface 102B of the substrate 102. In an embodiment, the process for removing the substrate 102 may include at least one process selected from mechanical polishing, chemical mechanical polishing (CMP), wet etching, and combinations thereof.

[0144] Then, a plurality of vertical vias exposing the gate dielectric layer 152 can be formed by etching portions of the fin active region F1 from the exposed fin active region F1 and the back surface of the device isolation layer 112, respectively, and a plurality of back-side insulating patterns BBP can then be formed to fill the vertical vias. When forming the back-side insulating patterns BBP, each fin active region F1 can be divided into a plurality of semiconductor blocks SB separated from each other by the back-side insulating patterns BBP. In embodiments, an ALD process or a chemical vapor deposition (CVD) process can be performed to form the back-side insulating patterns BBP, but one or more embodiments are not limited thereto.

[0145] Reference Figures 20A to 20E ,exist Figures 19A to 19E As a result, a hard mask pattern MB can be formed on the lower surface of each of the exposed semiconductor block SB, the back-side insulating pattern BBP, and the device isolation layer 112. The hard mask pattern MB may include an opening MH that exposes a localized area of ​​the removal target for each of the back-side insulating pattern BBP and the semiconductor block SB.

[0146] Then, by using a hard mask pattern MB as an etching mask and an etch stop layer ESL as the etching endpoint, a local area of ​​the semiconductor block SB exposed through the opening MH can be anisotropically etched to form a first space BH1 exposing the etch stop layer ESL, and a second space BH2 can be formed by anisotropically etching local areas of the back-side insulating pattern BBP and the device isolation layer 112. During the etching process, due to the difference in etch selectivity between the semiconductor block SB, the device isolation layer 112, and the back-side insulating pattern BBP, the first space BH1 can be formed to be relatively deeper than the second space BH2. The first space BH1 can be the region where the first portion BCA1a of the back-side via contact BCA of the semiconductor device 100 is formed, and the second space BH2 can be the region where the second portion BCA2a of the back-side via contact BCA of the semiconductor device 100 is formed.

[0147] The hard mask pattern MB may include a material that has etch selectivity relative to the corresponding material used to form the semiconductor block SB, the device isolation layer 112, and the back-side insulating pattern BBP. For example, the hard mask pattern MB may include a silicon nitride layer, a carbon-containing layer, or a combination thereof, but is not limited thereto.

[0148] Then, the source / drain region 130 can be exposed by etching the etch stop layer ESL exposed through the first space BH1, and some portions of the source / drain region 130 exposed through the first space BH1 can be removed by an anisotropic etching process, so that the first space BH1 can be further extended into the source / drain region 130.

[0149] Reference Figures 21A to 21E ,exist Figures 20A to 20E As a result, a process can be performed to form a back-side metal silicide layer 192 on the surface of the source / drain region 130 exposed through the first space BH1, and a process can be performed to form a back-side via contact BCA filling the first space BH1 and the second space BH2. The back-side via contact BCA may include a conductive barrier pattern 194 and a contact plug 196. To form the back-side metal silicide layer 192 and the back-side via contact BCA, a process can be performed in accordance with reference to... Figures 18A to 18E The process described is similar to that for forming the metal silicide layer 172 and the front source / drain contact CA.

[0150] Next, in Figures 21A to 21E As a result, a back-side insulating layer 109 can be formed to cover the lower surface of each of the exposed semiconductor block SB, the back-side insulating pattern BBP, and the device isolation layer 112, and a back-side power rail BPW that contacts the end of the back-side via contact BCA can be formed by penetrating the back-side insulating layer 109 in the vertical direction (Z direction); therefore, a reference can be manufactured. Figures 2 to 4D The semiconductor device 100 is described.

[0151] Although the disclosed concept has been specifically shown and described with reference to embodiments thereof, it will be understood that various changes in form and detail may be made without departing from the spirit and scope of the appended claims.

Claims

1. A semiconductor device, comprising: Multiple gate lines, the multiple gate lines being adjacent to each other in a first horizontal direction, and each extending in a second horizontal direction perpendicular to the first horizontal direction; Multiple source / drain regions, wherein the multiple source / drain regions are respectively arranged to be adjacent to the multiple gate lines in the first horizontal direction; A back-side via contact is connected to a pair of source / drain regions that face each other in the second horizontal direction among the plurality of source / drain regions. Multiple back-side insulating patterns are aligned with the multiple gate lines in the vertical direction and spaced apart from each other in the first horizontal direction; Multiple semiconductor blocks, the multiple semiconductor blocks contacting the sidewalls of the multiple back-side insulating patterns in the first horizontal direction; as well as A device isolation layer that covers the sidewall of the back-side via contact in the second horizontal direction. in: The back-side via contact includes a pair of first portions facing the pair of source / drain regions and a second portion disposed between the pair of first portions, and The first horizontal width of the first part in the first horizontal direction is less than the second horizontal width of the second part in the first horizontal direction.

2. The semiconductor device according to claim 1, wherein: The pair of first portions are in contact with the plurality of semiconductor blocks in the first horizontal direction, and The second portion contacts some of the device isolation layer and the plurality of back-side insulating patterns in the first horizontal direction.

3. The semiconductor device according to claim 1, wherein, The second part has a polygonal shape with rounded corners in the plan view.

4. The semiconductor device according to claim 1, wherein, The second part has a polygonal shape with angles in the plan view.

5. The semiconductor device according to claim 1, wherein, The second portion has a shape that protrudes outward toward the outside of the second portion as the second portion moves away from each of the pair of first portions in the second horizontal direction.

6. The semiconductor device according to claim 1, wherein, The upper surface of the pair of first parts is located at a vertical level that is higher than the upper surface of the second part.

7. The semiconductor device of claim 1, further comprising a front contact connected to one source / drain region selected from the plurality of source / drain regions, wherein, The selected source / drain region connected to the front contact is not included in the pair of source / drain regions connected to the back via contact.

8. The semiconductor device of claim 1, further comprising a front contact connected to at least one of the pair of source / drain regions connected to the back via contact.

9. The semiconductor device according to claim 8, wherein, The front contact is aligned in the vertical direction with the pair of first portions of the back through-hole contact.

10. The semiconductor device according to claim 8, wherein, The front contact is a contact that is commonly connected to the pair of source / drain regions and is aligned in the vertical direction with the pair of first and second portions of the back via contact.

11. A semiconductor device, comprising: Multiple gate lines, the multiple gate lines being adjacent to each other in a first horizontal direction, and each extending in a second horizontal direction perpendicular to the first horizontal direction; Multiple source / drain regions, wherein the multiple source / drain regions are respectively arranged to be adjacent to the multiple gate lines in the first horizontal direction; A first back-side via contact is connected to a first pair of source / drain regions that face each other in the second horizontal direction among the plurality of source / drain regions. The second back-side via contact is spaced apart from the first back-side via contact in the first horizontal direction and is connected to the second pair of source / drain regions facing each other in the second horizontal direction among the plurality of source / drain regions. Multiple back-side insulating patterns, wherein the multiple back-side insulating patterns are aligned with the multiple gate lines in the vertical direction; Multiple semiconductor blocks, the multiple semiconductor blocks contacting the sidewalls of the multiple back-side insulating patterns in the first horizontal direction; as well as A device isolation layer that covers the sidewalls of the first back-side via contact and the second back-side via contact in the second horizontal direction. The first back-side via contact includes a pair of first portions facing the first pair of source / drain regions and a second portion disposed between the first pair of source / drain regions. The first horizontal width of the first part in the first horizontal direction is less than the second horizontal width of the second part in the first horizontal direction.

12. The semiconductor device according to claim 11, wherein, In the plan view, the second back-side through-hole contact has a third horizontal width in the first horizontal direction, and the third horizontal width is smaller than the second horizontal width.

13. The semiconductor device according to claim 11, wherein: The pair of first portions of the first back-side via contact contact contact the semiconductor block in the first horizontal direction, and The second portion of the first back-side via contact contacts some of the device isolation layer and the plurality of back-side insulating patterns in the first horizontal direction.

14. The semiconductor device of claim 11, wherein: The second back-side via contact includes a pair of third portions corresponding to the pair of first portions of the first back-side via contact in the first horizontal direction, and a fourth portion corresponding to the second portion of the first back-side via contact in the first horizontal direction. The pair of third portions of the second back-side via contact contact contact the plurality of semiconductor blocks in the first horizontal direction, and the fourth portion of the second back-side via contact contact contacts the device isolation layer but is spaced apart from the plurality of back-side insulating patterns.

15. The semiconductor device according to claim 14, wherein, The upper surface of the pair of first portions of the first back-side through-hole contact is located at the same vertical level as the upper surface of the pair of third portions of the second back-side through-hole contact.

16. The semiconductor device according to claim 14, wherein, The upper surface of the second portion of the first back-side through-hole contact is located at a vertical level that is higher than the vertical level of the upper surface of the fourth portion of the second back-side through-hole contact.

17. The semiconductor device according to claim 14, wherein, The vertical height of the second portion of the first back-side through-hole contact is greater than the vertical height of the fourth portion of the second back-side through-hole contact.

18. A semiconductor device, comprising: Multiple gate lines, the multiple gate lines being adjacent to each other in a first horizontal direction, and each extending in a second horizontal direction perpendicular to the first horizontal direction; Multiple source / drain regions, wherein the multiple source / drain regions are respectively arranged to be adjacent to multiple gate lines in the first horizontal direction; A back-side via contact is connected to any pair of source / drain regions that face each other in the second horizontal direction among the plurality of source / drain regions. A front contact element that connects to one of the multiple source / drain regions selected from the plurality of source / drain regions; Multiple back-side insulating patterns are aligned with the multiple gate lines in the vertical direction and spaced apart from each other in the first horizontal direction; Multiple semiconductor blocks, the multiple semiconductor blocks contacting the sidewalls of the multiple back-side insulating patterns in the first horizontal direction; as well as A device isolation layer that covers the sidewall of the back-side via contact in the second horizontal direction. The back-side via contact includes a pair of first portions facing the pair of source / drain regions and a second portion disposed between the pair of first portions. The first horizontal width of the first part in the first horizontal direction is less than the second horizontal width of the second part in the first horizontal direction.

19. The semiconductor device according to claim 18, wherein: The pair of first portions are in contact with the plurality of semiconductor blocks in the first horizontal direction, and The second portion contacts a portion of the device isolation layer and the plurality of back-side insulating patterns in the first horizontal direction.

20. The semiconductor device according to claim 18, wherein, The selected source / drain region connected to the front contact is not included in the pair of source / drain regions connected to the back via contact.

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