Semiconductor devices and their manufacturing methods

Abstract

A semiconductor device and a method for manufacturing the semiconductor device are disclosed. The semiconductor device includes a first source / drain region and a second source / drain region, a nanostructured channel region disposed between the first source / drain region and the second source / drain region, a gate structure, a first contact structure disposed on the front surface of the first source / drain region, a gate spacer disposed between the gate structure and the first contact structure, a second contact structure disposed on the back surface of the first source / drain region, a dielectric liner disposed on the back surface of the gate structure and the second source / drain region and on the sidewalls of the second contact structure, and a first dielectric layer disposed on the dielectric liner and on the sidewalls of the second contact structure.

Description

Technical Field

[0001] Embodiments of this application relate to semiconductor devices and methods of manufacturing the same. Background Technology

[0002] As semiconductor technology advances, the demand for higher storage capacity, faster processing systems, higher performance, and lower costs continues to grow. To meet these demands, the semiconductor industry is constantly scaling down the size of semiconductor devices, such as metal-oxide-semiconductor field-effect transistors (MOSFETs) (including planar MOSFETs), fin field-effect transistors (FinFETs), and gate-all-around field-effect transistors (GAAFETs). This scaling down increases the complexity of semiconductor manufacturing processes. Summary of the Invention

[0003] This application provides a semiconductor device comprising: a first source / drain region and a second source / drain region; a nanostructured channel region disposed between the first source / drain region and the second source / drain region; a gate structure including a gate dielectric layer and a conductive layer, the gate dielectric layer surrounding each of the nanostructured channel regions, and the conductive layer disposed on the gate dielectric layer; a first contact structure disposed on the front surface of the first source / drain region, the first contact structure including a silicide layer having a curved profile; a gate spacer disposed between the gate structure and the first contact structure and extending along the sidewall of the gate structure, wherein the dielectric constant of the gate dielectric layer is greater than the dielectric constant of the gate spacer; a second contact structure disposed on the back surface of the first source / drain region; a dielectric liner disposed on the back surface of the gate structure and the second source / drain region; and a first dielectric layer disposed on the dielectric liner.

[0004] Another aspect of this application provides a method for manufacturing a semiconductor device, comprising: forming a mesa structure on a substrate; forming a first source / drain region and a second source / drain region on the mesa structure; forming a gate structure between the first source / drain region and the second source / drain region and on the mesa structure; replacing the mesa structure with a dielectric structure on the back surface of the first source / drain region, the second source / drain region and the gate structure; etching a portion of the dielectric structure from the back surface of the first source / drain region; and forming a contact structure on the back surface of the first source / drain region, wherein the contact structure includes a silicide layer and a conductive layer, and wherein the conductivity of the conductive layer is greater than the conductivity of the second source / drain region.

[0005] This application provides a method for manufacturing a semiconductor device, comprising: forming a mesa structure on a substrate; forming a superlattice structure including a nanostructure layer and a sacrificial nanostructure layer on the mesa structure; etching the superlattice structure to form a first opening; etching the mesa structure to form a second opening; forming an isolation structure on an exposed surface of the mesa structure in the second opening; epitaxially growing source / drain regions on the exposed surface of the nanostructure layer in the first opening; replacing the sacrificial nanostructure layer with a gate structure; replacing the mesa structure with a dielectric liner and a dielectric layer; and forming a contact structure on the source / drain regions, wherein the contact structure extends perpendicularly through the dielectric liner and the dielectric layer. Attached Figure Description

[0006] When read in conjunction with the accompanying drawings, aspects of this disclosure are best understood from the following detailed description.

[0007] Figure 1A An isometric view of a semiconductor device according to some embodiments is shown.

[0008] Figures 1B to 1K Different cross-sectional views of a semiconductor device with a contact structure according to some embodiments are shown.

[0009] Figure 2 This is a flowchart of a method for manufacturing a semiconductor device having a contact structure according to some embodiments.

[0010] Figures 3A to 18A , Figures 3B to 18B and Figures 19 to 22 Cross-sectional views of a semiconductor device with a contact structure at various stages of its manufacturing process, according to some embodiments, are shown.

[0011] Figure 23 This is a flowchart of a method for manufacturing another semiconductor device having a contact structure, according to some embodiments.

[0012] Figures 24 to 29 Cross-sectional views of another semiconductor device with a contact structure at various stages of its manufacturing process are shown according to some embodiments.

[0013] Exemplary embodiments will now be described with reference to the accompanying drawings. In the drawings, the same reference numerals generally denote the same, functionally similar, and / or structurally similar elements. Detailed Implementation

[0014] The following disclosure provides numerous different embodiments or examples for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below to simplify this disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first component on or over a second component may include embodiments where the first and second components are formed in direct contact, and may also include embodiments where an additional component may be formed between the first and second components such that the first and second components are not in direct contact. As used herein, forming a first component on a second component means that the first component is formed in direct contact with the second component. Furthermore, reference numerals and / or letters may be repeated in various examples. This repetition, in itself, does not indicate a relationship between the various embodiments and / or configurations discussed.

[0015] For ease of description, spatial relative terms such as “below,” “under,” “lower,” “above,” and “upper” are used herein to describe the relationship of one element or component to another, as shown in the figures. In addition to the orientations shown in the figures, spatial relative terms are intended to include different orientations of the device in use or operation. The device may be positioned in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein can be interpreted accordingly.

[0016] It should be noted that references to "an embodiment," "an embodiment," "an exemplary embodiment," etc., in the specification indicate that the described embodiment may include specific components, structures, or features, but each embodiment may not necessarily include specific components, structures, or features. Furthermore, these phrases do not necessarily refer to the same embodiment. Additionally, when a specific component, structure, or feature is described in connection with an embodiment, those skilled in the art will be able to implement such a component, structure, or feature in conjunction with other embodiments (whether explicitly described or not).

[0017] It should be understood that the wording or terminology used herein is for descriptive purposes and not for limitation, and therefore the terminology or terminology used herein should be interpreted by those skilled in the art based on the teachings herein.

[0018] In some embodiments, the terms "about" and "substantially" may refer to the value of a given quantity that varies within 5-20% of the value (e.g., ±1%, ±2%, ±3%, ±4%, ±5%, ±10%, ±10-15%, ±15-20% of the value). These values ​​are merely examples and are not intended to be limiting. The terms "about" and "substantially" may refer to the percentage of the value as interpreted by one of skill in the art based on the teachings herein.

[0019] GAA transistor structures can be patterned using any suitable method. For example, the structure can be patterned using one or more photolithography processes, including dual-patterning or multi-patterning processes. Dual-patterning or multi-patterning processes can combine photolithography and self-alignment processes, allowing the creation of patterns with, for example, smaller pitches than that achievable using a single direct photolithography process. For example, in some embodiments, a sacrificial layer is formed over a substrate and patterned using a photolithography process. Spacers are formed alongside the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers can then be used to pattern the GAA transistor structure.

[0020] This disclosure provides example semiconductor devices (e.g., GAA FETs) with contact structures that electrically connect source / drain (S / D) regions to back-side power rails. In some embodiments, a first back-side dielectric layer can replace the mesa structure (also referred to as a “substrate structure” or “fin substrate structure”) beneath the S / D region and gate structure of the semiconductor device, and contact structures can be formed on the back-side surface of the S / D region through the first back-side dielectric layer. Replacing the mesa structure with the first back-side dielectric layer can reduce the capacitance between the gate structure and the back-side contact structure, thus improving device performance (e.g., device speed).

[0021] In some embodiments, the back-side contact structure can be electrically connected to a back-side power rail formed on a second back-side dielectric layer, the second back-side dielectric layer being disposed on the first back-side dielectric layer. In some embodiments, the formation of the back-side power rail and the electrical connection from one or more S / D regions to the back-side power rail can reduce the device area and the number and size of interconnects between the S / D regions and the power rail, thus reducing device power consumption compared to other semiconductor devices without a back-side power rail. Furthermore, since the back-side power rail can be formed in a larger region than the front-side power rail, the back-side power rail can be formed to have a lower resistance than the front-side power rail formed on the front side of the S / D region.

[0022] Figure 1A An isometric view of a semiconductor device 100 (also referred to as "FET 100" or "GAA FET 100") according to some embodiments is shown. Figure 1B , Figure 1E , Figure 1G and Figure 1I The following is illustrated according to some embodiments. Figure 1A Different cross-sectional views of semiconductor device 100 with line AA. Figure 1C and Figure 1J The following is illustrated according to some embodiments. Figure 1A A cross-sectional view of the semiconductor device 100 of line BB. Figure 1D , Figure 1F , Figure 1H and Figure 1K The following is illustrated according to some embodiments. Figure 1A Different cross-sectional views of the semiconductor device 100 of line CC. Figure 1B , Figure 1C , Figure 1D , Figure 1E , Figure 1F , Figure 1G , Figure 1H , Figure 1I , Figure 1J and Figure 1K The diagram shows additional structures (not shown for simplicity). Figure 1A A cross-sectional view of the semiconductor device 100 shown in the figure. Unless otherwise stated, Figures 1A to 1K Discussions of elements with the same annotations are applicable to each other.

[0023] refer to Figure 1A , Figure 1B , Figure 1C and Figure 1D The semiconductor device 100 may include (i) S / D regions 102A1-102A3 and 102B1-102B3 (S / D regions 102A1, 102A2, 102B1 and 102B2 are in...) Figure 1A(i) Invisible in the middle, (ii) S / D spacer 104, (iii) S / D isolation structure 105A; (iv) Nanostructured channel region 106, (v) Nanostructured layer 107, (vi) Gate structure 108 disposed around the nanostructured channel region 106, (vii) External spacer 110, (viii) Internal spacer 112, (ix) Front side (FS) Etch Stop Layer (ESL) 114F1-114F3, (x) Back side (BS) ESL 114B, (xi) FS Interlayer Dielectric (ILD) Layer 116F1-116F3, (xii) BS ILD layer 116B, (xiii) Shallow Trench Isolation (STI) region 118, (xiv) BS barrier layer 120, (xv) FS contact structure 122F, (xvi) Through-hole structure 123, (xvii) BS contact structure 122B, (xviii) Isolation structure 130, and (xix) BS power rail 132. In the following description, S / D regions 102A1-102A3 are collectively referred to as "S / D region 102A", and S / D regions 102B1-102B3 are collectively referred to as "S / D region 102B". Unless otherwise stated, the discussion of S / D region 102A applies to each of S / D regions 102A1-102A3, and the discussion of S / D region 102B applies to each of S / D regions 102B1-102B3. Depending on the context, each of the S / D regions 102A and 102B may individually or collectively refer to the source or drain. The FS element of the semiconductor device 100 is disposed on the FS surface 102f of the S / D regions 102A and 102B, and the BS element of the semiconductor device 100 is disposed on the BS surface 102b of the S / D regions 102A and 102B.

[0024] In some embodiments, S / D region 102A may be n-type and may include epitaxially grown semiconductor material (such as Si) and n-type dopants (such as phosphorus and other suitable n-type dopants). S / D region 102B may be p-type and may include epitaxially grown semiconductor material (such as Si and SiGe) and p-type dopants (such as boron and other suitable p-type dopants). In some embodiments, both S / D regions 102A and 102B may be n-type or p-type.

[0025] In some embodiments, the epitaxial lateral growth of S / D regions 102A and 102B along the Y-axis can be controlled by an S / D spacer 104. As a result, the S / D spacer 104 can prevent adjacent S / D regions 102A and 102B (such as S / D regions 102A1 and 102B1, 102A2 and 102B2, and 102A3 and 102B3) from merging with each other during the epitaxial growth process of S / D regions 102A and 102B. In some embodiments, the S / D spacer 104 may include a dielectric material such as silicon nitride (SiN), silicon oxynitride (SiON), silicon oxycarbide (SiCO), silicon carbonitride (SiCN), silicon carbonitride (SiCON), and other suitable dielectric materials. In some embodiments, reference is made as follows. Figure 4A and Figure 4B In addition to controlling the epitaxial lateral growth of S / D regions 102A and 102B, S / D spacer 104 can reduce or minimize the etching of STI region 118 during the formation of S / D regions 102A and 102B.

[0026] In some embodiments, the S / D isolation structure 105A may be disposed on the BS surface 102b of the S / D regions 102A and 102B. The sidewalls of the S / D isolation structure 105A, extending along the Y-axis, may be connected to the bottommost internal spacer 112 (e.g., Figure 1B The sidewall of the S / D isolation structure 105A, which extends along the X-axis, can contact the S / D spacer 104 (as shown). Figure 1D (As shown) Contact. In some embodiments, such as Figure 1D As shown, the S / D isolation structure 105A can contact the FS ESL 114F1. This is because the S / D isolation structure 105A is removed during the formation of the BS contact structure 112B (see below). Figures 13A to 17A and Figures 13B to 17B (As described below), therefore, the S / D isolation structure 105A exists on the BS surface 102b of the S / D regions 102A2 and 102B2, which do not have the BS contact structure 122B. See below for reference. Figures 8A to 12A and Figures 8B to 12B The S / D isolation structure 105A can protect the S / D regions 102A and 102B from etching during the replacement of mesa structures 336A and 336B with BS barrier layer 120 and BS ILD layer 116B (“mesa replacement process”).

[0027] In some embodiments, the S / D isolation structure 105A may include a dielectric layer. In some embodiments, the S / D isolation structure 105A may include a dielectric nitride material, such as SiN, SiON, SiCON, and SiCN. In some embodiments, the S / D isolation structure 105A may include a silicon-rich dielectric material. In some embodiments, the silicon-rich dielectric material may include (i) a silicon-rich nitride (SiN) with a silicon atom concentration higher than the nitrogen atom concentration. x N y (ii) Silicon-rich nitrides (Si) with a silicon atom concentration higher than that of oxygen and nitrogen atoms. x O y N z (iii) Silicon-rich carbon oxides (SiO2) with a silicon atom concentration higher than that of oxygen and carbon atoms. x O y C z (iv) Silicon-rich carbon nitrides (SiO2) with silicon atom concentrations higher than those of oxygen, carbon, and nitrogen atoms. w O x C y N z (v) Silicon-rich boron oxynitride (SiO2) with a silicon atom concentration higher than that of oxygen, boron, and nitrogen atoms. w B x O y N z (vi) Silicon-rich boron oxide (SiO2) with a silicon atom concentration higher than that of oxygen, boron, and carbon atoms. w B x O y C z (vii) other suitable silicon-rich silicon nitride or carbide-based dielectric materials. The silicon-rich dielectric material of the S / D isolation structure 105A can provide the S / D isolation structure 105A with high etch resistance to etch chemicals used during mesa replacement processes. In some embodiments, the S / D isolation structure 105A can have a thickness of about 2 nm to about 8 nm. Within this thickness range, the S / D isolation structure 105A can adequately protect the S / D regions 102A and 102B from etching during mesa replacement processes without affecting the device size and manufacturing cost of the semiconductor device 100.

[0028] In some embodiments, the FS contact structure 122F may be directly disposed on the FS surface 102f of one or more S / D regions 102A and 102B (e.g., S / D regions 102A1, 102A2, 102B1, and 102B2) to electrically connect the S / D regions 102A and 102B to other elements of the semiconductor device 100 and / or other active and / or passive devices (not shown) in the integrated circuit. In some embodiments, each of the FS contact structures 122F may include (i) a silicide layer 124F directly disposed on the FS surface 102f, (ii) a conductive layer 126F directly disposed on the silicide layer 124F, and (iii) a diffusion barrier layer 128F directly disposed on the sidewalls of the conductive layer 126F and surrounding the conductive layer 126F. In some embodiments, the silicide layer 124F may extend on the sidewalls of the S / D regions 102A and 102B to increase the contact area with the S / D regions 102A and 102B, thereby increasing the conductivity between the S / D regions 102A and 102B and the FS contact structure 122F. In some embodiments, the silicide layer 124F may have a curved profile. In some embodiments, the widths W1 and W2 of the conductive layer 126F along the Y-axis may be greater than the widths W3 and W4 of the S / D regions 102A and 102B along the Y-axis to prevent misalignment between the FS contact structure 122F and the S / D regions 102A and 102B. Figure 1C and Figure 1D As shown, due to the large widths W1 and W2, the conductive layer 126F can be partially and directly disposed on the FS ESL 114F1 and FS ILD layer 116F1 surrounding the S / D regions 102A1, 102A2, 102B1, and 102B2. Figure 1B As shown, the width of the conductive layer 126F along the X-axis can be smaller than the width of the S / D regions 102A and 102B along the X-axis.

[0029] In some embodiments, the silicide layer 124F may include titanium silicide (Ti) for the n-type S / D regions 102A and 102B. x Si y ), tantalum silicide (Ta x Si y ), molybdenum silicide (Mo x Si y ), zirconium silicide (Zr) x Si y ), Hafnium silicide (Hf) x Si y Scandium silicide (Sc) x Si y ), yttrium silicide (Y x Si y ), terbium silicide (Tb xSi y ), Lutetium silicide (Lu x Si y ), Erbium silicide (Er x Si y ), Ytterbium silicide (Yb x Si y Europium silicide (Eu) x Si y ), Thorium silicide (Th) x Si y Other suitable metal silicide materials or combinations thereof. In some embodiments, the silicide layer 124F may include nickel silicide (Ni) for the p-type S / D regions 102A and 102B. x Si y ), cobalt silicide (Co) x Si y ), manganese silicide (Mn) x Si y ), tungsten silicide (W x Si y ), iron silicide (Fe) x Si y Rhodium silicide (Rh) x Si y ), palladium silicide (Pd) x Si y Ruthenium silicide (Ru) x Si y Platinum silicide (Pt) x Si y ), Iridium silicide (Ir) x Si y ), Os silicide (Os) x Si y Other suitable metal silicide materials or combinations thereof. In some embodiments, conductive layer 126F may include conductive materials such as cobalt (Co), tungsten (W), ruthenium (Ru), iridium (Ir), nickel (Ni), osmium (Os), rhodium (Rh), aluminum (Al), molybdenum (Mo), copper (Cu), zirconium (Zr), tin (Sn), silver (Ag), gold (Au), zinc (Zn), cadmium (Cd), and combinations thereof. In some embodiments, the conductivity of conductive layer 126F may be greater than the conductivity of S / D regions 102A and 102B.

[0030] In some embodiments, the diffusion barrier layer 128F can prevent oxidation of the conductive layer 126F by preventing oxygen atoms from diffusing from adjacent structures (e.g., FS ILD layers 116F1 and 116F2 and FS ESL layers 114F1 and 114F2) to the conductive layer 126F. In some embodiments, the diffusion barrier layer 128B may include a dielectric material such as silicon oxide (SiO2), SiN, SiON, SiCN, SiOCN, aluminum oxide (Al2O3), aluminum oxynitride (AlON), zirconium oxide (ZrO2), hafnium oxide (HfO2), titanium oxide (TiO2), aluminum zirconium oxide (ZrAlO), zinc oxide (ZnO2), and other suitable dielectric materials. In some embodiments, the diffusion barrier layer 128F may have a thickness of about 1.5 nm to about 4 nm. Within this thickness range, the diffusion barrier layer 128F can sufficiently prevent oxidation of the conductive layer 126F without affecting the size and manufacturing cost of the semiconductor device 100.

[0031] In some embodiments, the via structure 123 may be directly disposed on one of the contact structures 122F. In some embodiments, the via structure 123 may include a conductive material, such as W, Ru, Al, Mo, Ir, Ni, Os, other suitable conductive materials, and combinations thereof. In some embodiments, the materials of the conductive layer 126F and the via structure 123 are different from each other.

[0032] In some embodiments, FS ESLs 114F1 and 114F2 and FS ILD layers 116F1 and 116F2 may provide electrical isolation between adjacent FS contact structures 122F and between FS contact structures 122F and gate structure 108. In some embodiments, FS ESL 114F3 and FS ILD layer 116F3 may provide electrical isolation between via structure 123 and other adjacent via structures (not shown). In some embodiments, FS ESL 114F1 may be directly disposed on S / D regions 102A and 102B, S / D spacer 104, and STI region 118. In some embodiments, FS ESL 114F2 and FS ILD layer 116F2 surround FS contact structure 122F. In some embodiments, FS ESL 114F3 and FS ILD layer 116F3 surround via structure 123. In some embodiments, as Figure 1A , Figure 1C and Figure 1DAs shown, a portion of the FS ILD layer 116F1 extending below the S / D spacer 104 may have a rectangular cross-sectional profile, and a portion of the FS ESL 114F1 extending above the S / D spacer 104 may have a U-shaped cross-sectional profile. In some embodiments, FS ESL 114F1-114F3, FS ILD layers 116F1-116F3, and STI region 118 may include dielectric materials such as SiO2, SiN, SiON, SiCO, SiCN, SiCON, and other suitable dielectric materials. In some embodiments, FS ILD layers 116F1-116F3 may include oxide materials, and FS ESL 114F1-114F3 may include nitride materials different from FS ILD layers 116F1-116F3.

[0033] In some embodiments, the BS contact structure 122B can be directly disposed on the BS surface 102b of the S / D regions 102A1, 102A3, 102B1, and 102B3. The BS contact structure 122B can electrically connect the S / D regions 102A1, 102A3, 102B1, and 102B3 to the BS power rail 132 disposed on the BS ESL 114B. The BS power rail 132 may include a metal wire (not shown) of ruthenium (Ru), copper (Cu), or other suitable metal for supplying power to the S / D regions 102A1, 102A3, 102B1, and 102B3 through the BS contact structure 122B. By forming a BS contact structure 122B on the BS surface 102b of the S / D region, the BS contact structure 122B can be formed to have (i) a larger volume compared to the FS contact structure 122F, and (ii) a larger contact area with the S / D region compared to the contact area between the FS contact structure 122F and the S / D region. As a result, the contact resistance between the S / D region and the BS contact structure 122B can be lower than the contact resistance between the S / D region and the FS contact structure 122F.

[0034] In some embodiments, such as Figure 1B As shown, the width W5 of the BS contact structure 122B along the X-axis can be limited by the distance between a pair of internal spacers 112, and as... Figure 1A and Figure 1CAs shown, the width W6 of the BS contact structure 122B along the Y-axis can be limited by the distance between a pair of S / D spacers 104. In some embodiments, the widths W5 and W6 can be from about 5 nm to about 15 nm, and can be equal to or different from each other. Within this width range, the BS contact structure 122B can provide sufficient electrical connection with low resistance between the BS power rail 132 and the S / D regions 102A1, 102A3, 102B1, and 102B3 without affecting the device size and manufacturing cost of the semiconductor device 100.

[0035] In some embodiments, each BS contact structure 122B may include (i) a silicide layer 124B directly disposed on the BS surface 102b of the S / D regions 102A1, 102A3, 102B1, and 102B3, (ii) a conductive layer 126B directly disposed on the silicide layer 124B, and (iii) a diffusion barrier layer 128B directly disposed on the sidewall of the conductive layer 126B and surrounding the conductive layer 126B. Unless otherwise stated, the discussion of the silicide layer 124F applies to the silicide layer 124B. In some embodiments, the silicide layers 124F and 124B may have the same material or different materials. In some embodiments, the conductive layer 126B may include a conductive material such as W, Ru, Co, Cu, Ti, Ta, Mo, Ni, titanium nitride (TiN), tantalum nitride (TaN), and other suitable conductive materials.

[0036] In some embodiments, diffusion barrier layer 128B can prevent oxidation of conductive layer 126B by preventing oxygen atoms from diffusing from adjacent structures (e.g., BS ILD layer 116B and BS barrier layer 120) to conductive layer 126B. In some embodiments, diffusion barrier layer 128B may include a dielectric material such as SiO2, SiN, SiON, SiCN, SiOCN, Al2O3, AlON, ZrO2, HfO2, TiO2, ZrAlO, ZnO2, and other suitable dielectric materials. In some embodiments, diffusion barrier layers 128F and 128B may have the same material or different materials. In some embodiments, diffusion barrier layer 128B may have a thickness of about 1.5 nm to about 4 nm. Within this thickness range, diffusion barrier layer 128B can sufficiently prevent oxidation of conductive layer 126B without affecting the size and manufacturing cost of semiconductor device 100.

[0037] In some embodiments, the BS barrier layer 120 may be directly disposed on the BS surface of the gate structure 108 and on the BS surface 102b of the S / D regions 102A and 102B (such as S / D regions 102A2 and 102B2) that do not have BS contact structures 122B. The BSILD layer 116B may be directly disposed on the BS barrier layer 120. In some embodiments, such as Figure 1B As shown, the BS ILD layer 116B can contact the sidewall of the BS contact structure 122B extending along the Y-axis, and as... Figure 1C As shown, the BS barrier layer 120 can contact the sidewall of the BS contact structure 122B extending along the X-axis. In some embodiments, the BS ILD layer 116B can surround each BS contact structure 122B. In some embodiments, as Figure 1D As shown, the BS surfaces of the BS barrier layer 120 and the BS ILD layer 116B can be substantially coplanar with the BS surface of the STI region 118. See below for reference. Figures 8A to 12A and Figures 8B to 12B The BS barrier layer 120 and BS ILD layer 116B can be formed by replacing the S / D regions 102A and 102B with the mesa structures 336A and 336B below the gate structure 108. By replacing the mesa structures 336A and 336B, which have semiconductor materials, with the BS barrier layer 120 and BS ILD layer 116B, which have dielectric materials, the capacitance between the gate structure 108 and the BS contact structure 122B, and between the gate structure 108 and the BS power rail 132, can be reduced, thus improving device performance (e.g., device speed). Furthermore, the BS barrier layer 120 and BS ILD layer 116B can protect the gate structure 108 and the S / D regions 102A and 102B during the formation of BS elements (such as the BS contact structure 122B and the BS power rail 132). Additionally, the BS barrier layer 120 and BS ILD layer 116B can provide electrical isolation between the BS contact structure 122B and other BS contact structures (not shown).

[0038] In some embodiments, the BS barrier layer 120 may have a thickness T1 of about 1 nm to about 10 nm. In some embodiments, the thickness T2 of the BS ILD layer 116B below the gate structure 108 may be about 10 nm to about 50 nm, and the thickness T3 below the S / D regions 102A2 and 102B2 may be about 10 nm to about 50 nm. Thickness T3 may be greater than thickness T2. Within these thickness ranges, the BS barrier layer 120 and the BS ILD layer 116B can adequately protect the gate structure 108 and the S / D regions 102A and 102B during the formation of the BS element without affecting the device size and manufacturing cost of the semiconductor device 100. Furthermore, if the thicknesses T2 and T3 are less than 10 nm, the BS contact structure 122B is formed with a height of less than approximately 15 nm. This increases the challenge of protecting the gate structure 108 and the S / D regions 102A2 and 102B2 when performing a chemical mechanical polishing (CMP) process on the BS contact structure 122B during its formation process (see below). Figure 17A and Figure 17B (Description to be provided). On the other hand, if the thicknesses T2 and T3 are greater than 50 nm, the BS contact structure 122B is formed with a height greater than 60 nm, which increases the resistivity of the BS contact structure 122B and thus reduces the device performance.

[0039] In some embodiments, the BS barrier layer 120 may include a dielectric material such as SiN, SiON, SiCN, SiOCN, silicon carbide (SiC), and other suitable dielectric materials. In some embodiments, the BS ILD layer 116B may include a low-k dielectric material such as SiO2, SiN, SiON, SiCN, SiOCN, SiC, and other suitable low-k dielectric materials. In some embodiments, the BS barrier layer 120 and the BS ILD layer 116B may include a Si substrate (e.g., a SiOCN layer) with different concentrations of oxygen, nitrogen, and carbon atoms. In some embodiments, the BS barrier layer 120 and the BS ILD layer 116B may include a Si substrate (e.g., a SiON layer) with different concentrations of oxygen and nitrogen atoms. In some embodiments, the BS barrier layer 120 may include a Si substrate (e.g., a SiON layer) with a higher nitrogen atom concentration than oxygen atom concentration, while the BS ILD layer 116B may include a silicon substrate (e.g., a SiON layer) with a higher oxygen atom concentration than nitrogen atom concentration. In some embodiments, the concentration of nitrogen and / or oxygen atoms in the Si substrate of the BS ILD layer 116B may be lower than the concentration of nitrogen and / or oxygen atoms in the Si substrate of the BS barrier layer 120. This relative concentration of nitrogen and / or oxygen atoms in the BS ILD layer 116B and the BS barrier layer 120 results in a lower dielectric constant for the BS ILD layer 116B than for the BS ILD layer 120, which in turn results in a lower capacitance for the BS ILD layer 116B than for the BS ILD layer 120.

[0040] In some embodiments, BS ESL 114B may be directly disposed on BS ILD layer 116B and may surround a portion of BS contact structure 122B that is not in contact with BS barrier layer 120 or BS ILD layer 116B. The BS surface of BS ESL 114B may be substantially coplanar with the BS surface of BS contact structure 122B. Unless otherwise stated, the discussion of the material of FS ESL 114F1 applies to BS ESL 114B. BS power rail 132 may be directly disposed on BS ESL 114B and BS contact structure 122B.

[0041] In some embodiments, the isolation structure 130 may extend vertically between FS ESL 114F2 and BS ESL 114B. The top surface of the isolation structure 130 may contact the BS surface of FS ESL 114F2, and the BS surface of the isolation structure 130 may contact the top surface of BS ESL 114B. The top surface of the isolation structure 130 may be substantially coplanar with the top surfaces of the gate structure 108 and the external spacer 110. Figure 1B As shown, the BS surface of the isolation structure 130 can be substantially coplanar with the BS surfaces of the BS barrier layer 120 and the BS ILD layer 116B, and as... Figure 1A As shown, the BS surface of the isolation structure 130 can be substantially coplanar with the BS surface of the STI region 118. The sidewalls of the isolation structure 130, extending along the Y-axis and located below the S / D regions 102A and 102B, can be coplanar with the STI region 118 (e.g., Figure 1A (as shown) and BS barrier layer 120 (as shown) Figure 1B (As shown) contact. In some embodiments, one of the isolation structures 130 may be disposed between adjacent S / D regions 102A (e.g., between S / D regions 102A2 and 102A3). In some embodiments, each isolation structure 130 may include an oxide-filled layer 130A and a nitride liner 130B surrounding the oxide-filled layer 130A. In some embodiments, the oxide-filled layer 130A may include SiO2 or a SiO2-based material (e.g., silicon oxycarbide), and the nitride liner 130B may include a SiN material.

[0042] In some embodiments, the nanostructured channel region 106 and the nanostructured layer 107 may be in the form of nanosheets, nanowires, nanorods, nanotubes, or other suitable nanostructure shapes. As used herein, the term "nanostructure" defines a structure, layer, and / or region having a horizontal dimension (e.g., along the X-axis and / or Y-axis) and / or a vertical dimension (e.g., along the Z-axis) of less than about 100 nm, such as about 90 nm, about 50 nm, about 10 nm, or other values ​​less than about 100 nm. In some embodiments, the nanostructured channel region 106 and the nanostructured layer 107 may include Si, silicon arsenide (SiAs), silicon phosphide (SiP), silicon carbide (SiC), silicon phosphide carbon (SiCP), silicon germanium (SiGe), silicon germanium boron (SiGeB), germanium boron (GeB), silicon germanium tin boron (SiGeSnB), III-V semiconductor compounds, or other suitable semiconductor materials. The nanostructured channel region 106 and the nanostructured layer 107 may include the same material. Although a stack of three nanostructured channel regions 106 and a stack of three nanostructured layers 107 are shown, the semiconductor device 100 may have any number of nanostructured channel regions 106 and nanostructured layers 107. In some embodiments, the length of the nanostructured channel region 106 along the X-axis may be greater than the length of the nanostructured layer 107. In some embodiments, the nanostructured channel region 106 may be electrically active, and the nanostructured layer 107 may be electrically inert. In some embodiments, the nanostructured channel region 106 may be disposed between S / D regions 102A1 and 102A2 (e.g., Figure 1B (as shown) and between S / D regions 102B1 and 102B2 (not shown). In some embodiments, the nanostructure layer 107 may be disposed between the S / D region 102A and the isolation structure 130 (as shown). Figure 1B(as shown) and between the S / D region 102B and the isolation structure 130 (not shown).

[0043] In some embodiments, the gate structure 108 may be a multilayer structure and may surround each nanostructure channel region 106; therefore, the gate structure 108 may be referred to as a "GAA structure." The semiconductor device 100 may be referred to as a "GAA FET 100." In some embodiments, the gate structure 108 may include (i) an interface oxide (IL) layer 108A disposed on the nanostructure channel region 106, (ii) a high-k gate dielectric layer 108B disposed on the IL layer 108A, (iii) a work function metal (WFM) layer disposed on the high-k gate dielectric layer 108B, and (iv) a gate metal filling layer 108D disposed on the WFM layer 108C. In some embodiments, the IL layer 108A may include an oxide of the material of the nanostructure channel region 106, such as SiO2 or SiGeO. x or germanium oxide (GeO) x In some embodiments, the high-k gate dielectric layer 108B may include a high-k dielectric material, such as hafnium oxide (HfO2), titanium oxide (TiO2), hafnium zirconium oxide (HfZrO), tantalum oxide (Ta2O3), hafnium silicate (HfSiO4), zirconium oxide (ZrO2), aluminum zirconium oxide (ZrAlO), zirconium silicate (ZrSiO2), lanthanum oxide (La2O3), aluminum oxide (Al2O3), zinc oxide (ZnO), hafnium zinc oxide (HfZnO), and yttrium oxide (Y2O3).

[0044] In some embodiments, WFM 108C may include titanium aluminum (TiAl), titanium aluminum carbide (TiAlC), tantalum aluminum (TaAl), tantalum aluminum carbide (TaAlC), Al-doped Ti, Al-doped TiN, Al-doped Ta, Al-doped TaN, or other suitable Al-based materials. In some embodiments, WFM 108C may include substantially Al-free (e.g., without Al) Ti-based or Ta-based nitrides or alloys, such as titanium nitride (TiN), titanium silicon nitride (TiSiN), titanium gold (Ti-Au) alloys, titanium copper (Ti-Cu) alloys, tantalum nitride (TaN), tantalum silicon nitride (TaSiN), tantalum gold (Ta-Au) alloys, and tantalum copper (Ta-Cu). In some embodiments, the gate metal fill layer 108D may include suitable conductive materials such as W, Ti, Ag, Ru, Mo, Cu, Co, Al, Ir, Ni, metal alloys, and combinations thereof.

[0045] In some embodiments, the gate structure 108 may be electrically isolated from the adjacent FS contact structure 122F by an external spacer 110, and a portion of the gate structure 108 surrounding the nanostructured channel region 106 may be electrically isolated from the adjacent S / D regions 102A and 102B by an internal spacer 112. In some embodiments, the external spacer 110 extends along the sidewall of the gate structure 108 and may be directly disposed on the topmost nanostructured channel region 106. The external spacer 110 and the internal spacer 112 may comprise materials similar to or different from each other. In some embodiments, the external spacer 110 and the internal spacer 112 may comprise insulating materials such as SiO2, SiN, SiON, SiCO, SiCN, SiCON, and other suitable insulating materials. In some embodiments, the dielectric constant of the HK gate dielectric layer 108B may be greater than the dielectric constant of the external spacer 110. In some embodiments, the S / D spacer 104 and the external spacer 110 are portions of the same spacer material layer, as referenced below. Figure 3A , Figure 3B , Figure 4A and Figure 4B As stated above.

[0046] refer to Figure 1E In some embodiments, the semiconductor device 100 may have an S / D isolation structure 105 instead of an S / D isolation structure 105A. Through the S / D isolation structure 105, the semiconductor device 100 may have (i) along Figure 1A The line AA Figure 1E The cross-sectional view, (ii) along Figure 1A BB's line Figure 1B The cross-sectional view, and (iii) along Figure 1A The line of CC Figure 1F A cross-sectional view. In some embodiments, the S / D isolation structure 105 may be disposed on the BS surface 102b of the S / D regions 102A and 102B, and may contact the sidewall of the bottommost inner spacer 112. Since the S / D isolation structure 105A (see below) is removed during the formation of the BS contact structure 112B... Figures 13A to 17A and Figures 13B to 17B (As described below), therefore, the S / D isolation structure 105 exists on the BS surface 102b of the S / D regions 102A2 and 102B2, which do not have the BS contact structure 122B. The S / D isolation structure 105 can protect the S / D regions 102A and 102B and the internal spacer 112 from etching during the mesa replacement process, as shown in the following reference. Figure 19 As stated above.

[0047] In some embodiments, the S / D isolation structure 105 may include a dielectric layer 105A and an undoped semiconductor layer 105B. The discussion of the materials and dimensions of the S / D isolation structure 105A applies to the dielectric layer 105A. The sidewalls of the dielectric layer 105A, extending along the Y-axis, may contact the bottommost internal spacer 112 (e.g., Figure 1E As shown), and the sidewalls of the dielectric layer 105A extending along the X-axis can contact the S / D spacer 104 (as shown). Figure 1F As shown). In some embodiments, such as Figure 1F As shown, dielectric layer 105A can contact FS ESL 114F1. In some embodiments, an undoped semiconductor layer 105B can be disposed between dielectric layer 105A and BS barrier layer 120. In some embodiments, undoped semiconductor layer 105B may comprise undoped Si, undoped SiGe, or other suitable undoped semiconductor material. The sidewalls of the undoped semiconductor layer 105B extending along the Y-axis can contact BS barrier layer 120 (e.g., Figure 1E As shown), and the sidewalls of the undoped semiconductor layer 105B extending along the X-axis can contact the STI region 118 and / or the S / D spacer 104 (as shown). Figure 1F As shown). In some embodiments, such as Figure 1E As shown, the undoped semiconductor layer 105B can extend vertically below the BS surface of the bottommost internal spacer 112.

[0048] refer to Figure 1F In some embodiments, the semiconductor device 100 may have an S / D isolation structure 105B instead of an S / D isolation structure 105. Through the S / D isolation structure 105B, the semiconductor device 100 may have (i) along Figure 1A The line AA Figure 1G The cross-sectional view, (ii) along Figure 1A BB's line Figure 1B The cross-sectional view, and (iii) along Figure 1A The line of CC Figure 1H A cross-sectional view. Unless otherwise stated, the discussion of the undoped semiconductor layer 105B applies to the S / D isolation structure 105B. The sidewalls of the S / D isolation structure 105B, extending along the Y-axis, may contact the BS barrier layer 120 (e.g., Figure 1G As shown), and the sidewalls of the S / D isolation structure 105B extending along the X-axis can contact the STI region 118 and the S / D spacer 104 (as shown). Figure 1H As shown). In some embodiments, such as Figure 1H As shown, the S / D isolation structure 105B can contact the FS ESL 114F1.

[0049] refer to Figure 1I In some embodiments, the semiconductor device 100 may have a BS barrier layer 120* and a BS ILD layer 116B* instead of a BS barrier layer 120 and a BS ILD layer 116B. Through the BS barrier layer 120* and the BS ILD layer 116B*, the semiconductor device 100 may have: (i) along Figure 1A The line AA Figure 1I The cross-sectional view, (ii) along Figure 1A BB's line Figure 1J The cross-sectional view, and (iii) along Figure 1A The line AA Figure 1K A cross-sectional view. Unless otherwise stated, the discussion of BS barrier layer 120 and BS ILD layer 116B applies to BS barrier layer 120* and BS ILD layer 116B*. In some embodiments, BS barrier layer 120* may surround BS contact structure 122B and may contact the sidewalls of BS contact structure 122B extending along the X and Y axes. The BS surfaces of BS barrier layer 120* and BS ILD layer 116B* may be substantially coplanar with the BS surface of BS contact structure 122B and may contact BS power rail 132.

[0050] Figure 2 It is according to some embodiments for manufacturing having Figure 1B , Figure 1C and Figure 1D The flowchart of an example method 200 for semiconductor device 100, shown in the cross-sectional view, is provided. For illustrative purposes, reference will be made to... Figures 3A to 18A and Figures 3B to 18B The example manufacturing process for manufacturing semiconductor device 100 is described below. Figure 2 The operation shown. Figures 3A to 18A It is according to some embodiments along Figure 1A A cross-sectional view of the semiconductor device 100 at various stages of its manufacturing process. Figures 3B to 18B It is according to some embodiments along Figure 1A The image shows cross-sectional views of the semiconductor device 100 at various stages of its fabrication. Depending on the specific application, operations may be performed in different sequences or not at all. It should be noted that method 200 may not produce a complete semiconductor device 100. Therefore, it should be understood that additional processes may be provided before, during, and after method 200, and only a few of these other processes may be briefly described herein. Unless otherwise stated, Figures 1A to 1F , Figures 3A to 18A and Figures 3B to 18B Discussions of elements with the same annotations are applicable to each other.

[0051] refer to Figure 2In operation 205, a superlattice structure having nanostructure layers and sacrificial nanostructure layers is formed on a mesa structure on a substrate. For example, as shown in reference... Figure 3A and Figure 3B The superlattice structure 307 (also referred to as "nanosheet stack 307") is formed on mesa structures 336A and 336B, which are formed on a polishing stop layer 335, which is formed on a substrate 334. In some embodiments, the substrate 334 may be a semiconductor material, such as Si, Ge, SiGe, silicon-on-insulator (SOI) structures, and combinations thereof. Additionally, the substrate 334 may be doped with a p-type dopant (e.g., boron, indium, aluminum, or gallium) or an n-type dopant (e.g., phosphorus or arsenic). In some embodiments, the polishing stop layer 335 may comprise a material different from that of the substrate 334. In some embodiments, when the substrate 334 comprises Si, the polishing stop layer 335 may comprise a SiGe layer. In some embodiments, the mesa structures 336A and 336B may comprise a material similar to that of the substrate 334 but different from that of the polishing stop layer 335. The mesa structures 336A and 336B may have elongated sides extending along the X-axis. Each superlattice structure 307 may include nanostructure layers 106 and sacrificial nanostructure layers 306 arranged in an alternating configuration. In some embodiments, nanostructure layers 106 may include Si, and sacrificial nanostructure layers 306 may include SiGe.

[0052] refer to Figure 2 In operation 210, an STI region is formed on the substrate, and a polycrystalline silicon structure is formed on the superlattice structure. For example, as referenced... Figure 3A and Figure 3B The STI region 118 is formed on the polishing stop layer 335, and the polysilicon structures 308A-308C are formed on the superlattice structure 307. The STI region 118 is... Figure 3A It is not visible in the cross-sectional view, and the polycrystalline silicon structure 308A-308C is... Figure 3B The STI region 118 is not visible in the cross-sectional view. In some embodiments, the formation of the STI region 118 may include the following sequential operations: (i) depositing a dielectric layer (not shown) of material having the STI region 118 on the polishing stop layer 335 and the superlattice structure 307; (ii) performing a CMP process to make the top surface of the dielectric layer and the superlattice structure 307 coplanar (not shown); and (iii) performing an etching process on the dielectric layer to form Figure 3BThe STI region 118 is shown. In some embodiments, the top surfaces of the STI region 118 and the mesa structures 336A and 336B may be substantially coplanar with each other. After the formation of the STI region 118, polysilicon structures 308A-308C can be formed on the superlattice structure 307. During subsequent processing, (i) the polysilicon structures 308A and 308C and portions of the superlattice structure 307 below the polysilicon structures 308A and 308C can be replaced with the isolation structure 130, and (ii) in a gate replacement process, the polysilicon structure 308B and portions of the sacrificial nanostructure layer 306 below the polysilicon structure 308B can be replaced with the gate structure 108.

[0053] refer to Figure 2 In operation 215, external spacers and S / D spacers are formed on the superlattice structure. For example, as referenced... Figure 3A , Figure 3B , Figure 4A and Figure 4B External spacers 110 and S / D spacers 104 are formed on the superlattice structure 307. In some embodiments, external spacers 110 and S / D spacers 104 may be formed from the same spacer material (not shown) at different stages of selective dry etching of the spacer material layer. The spacer material layer may include SiO2, SiN, SiON, SiCO, SiCN, SiCON, and other suitable insulating materials. The formation of external spacers 110 and S / D spacers 104 may begin by depositing a substantially conformal spacer material layer (not shown) directly on the polysilicon structures 308A-308C, the superlattice structure 307, and the STI region 118. After depositing the spacer material layer, a first etching process may be performed to etch portions of the spacer material layer from the top surface of the polysilicon structures 308A-308C, the superlattice structure 307, and the STI region 118 to form Figure 3A and Figure 3B The structure. Therefore, after the first etching process, it can be as follows: Figure 3A The external spacer 110 is formed as shown, and can be formed as follows: Figure 3B The spacer portion 304 is shown on the sidewall surface of the superlattice structure 307. The outer spacer 110 is located on... Figure 4B It is not visible in the cross-sectional view, and the spacer portion 304 is in Figure 4B It is not visible in the cross-sectional view.

[0054] In some embodiments, the first etching process can be an anisotropic dry etching process, and can have a higher etching rate along the Z-axis rather than along the X-axis or Y-axis. As a result, the spacer material layer on the top surface of the polysilicon structures 308A-308C, the superlattice structure 307, and the STI region 118 can be removed, while the spacer portions 304 on the sidewall surfaces of the superlattice structure 307 can be retained. Compared to the polysilicon structures 308A-308C and the superlattice structure 307, the etching gas used in the first etching process can have higher selectivity for the spacer material layer.

[0055] A second etching process can be performed after the first etching process to selectively etch portions of the spacer portion 304 to form the S / D spacer 104, and to selectively etch portions of the superlattice structure 307 and mesa structures 336A and 336B to form the S / D opening 402, such as... Figure 4A and Figure 4B As shown. S / D spacer 104 in Figure 4A The cross-sectional view is not visible. In some embodiments, during the second etching process, the top surface of the polysilicon structures 308A-308C and the top surface of the external spacer 110 may be protected by a masking layer (not shown) formed after the first etching process. In some embodiments, the second etching process may include a plasma-based dry etching process using etching gases (such as carbon tetrafluoride (CF4), sulfur dioxide (SO2), hexafluoroethane (C2F6), chlorine (Cl2), nitrogen trifluoride (NF3), sulfur hexafluoride (SF6), and hydrogen bromide (HBr)) and mixed gases (such as hydrogen (H2), oxygen (O2), nitrogen (N2), and argon (Ar)). The second etching process may be performed at a temperature from about 25°C to about 200°C and a pressure from about 5 mTorr to about 50 mTorr. The flow rate of the etching gas may range from about 5 standard cubic centimeters per minute (sccm) to about 100 sccm. The plasma power can range from about 50W to about 200W, with the bias voltage ranging from about 30V to about 200V.

[0056] In some embodiments, the etching gas used in the second etching process may have a higher selectivity for the superlattice structure 307 than for the spacer portion 304, removing the superlattice structure 307 at a higher etching rate than the spacer portion 304. As a result, at the end of the second etching process, portions of the superlattice structure 307 not covered by the polysilicon structures 308A-308C can be completely removed, while the S / D spacer 104 can be retained to control the subsequent epitaxial lateral growth of the S / D regions 102A-102B. In some embodiments, the etching gas used in the second etching process may have a higher selectivity for the STI region 118 than for the spacer portion 304. As a result, portions of the STI region 118 can be etched to form a groove 418 in the STI region 118. In some embodiments, the width of the S / D spacer 104 along the Y-axis may be from about 2 nm to about 15 nm to prevent the groove 418 from extending into the mesa structures 336A and 336B and exposing the sidewalls of the mesa structures 336A and 336B to the etching gas of the second etching process. In some embodiments, after the second etching process, internal spacers 112 can be formed on the sidewall surface of the sacrificial nanostructure layer 306 of the superlattice structure 307, such as Figure 5A As shown. The internal spacer 112 is in Figure 5B It is not visible in the cross-sectional view.

[0057] refer to Figure 2 In operation 220, S / D isolation structures and S / D regions are formed in the S / D openings of the superlattice structure and mesa structure. For example, as referenced... Figure 5A and Figure 5B The S / D isolation structure 105 and S / D regions 102A and 102B are formed in the S / D opening 402. In some embodiments, the formation of the S / D isolation structure 105 may include the following sequential operations: (i) epitaxially growing an undoped semiconductor layer 105B on the exposed surfaces of the mesa structures 336A and 336B in the S / D opening 402, such as... Figure 5A and Figure 5B As shown, and (ii) a dielectric layer 105A is formed on the undoped semiconductor layer 105B, as... Figure 5A and Figure 5B As shown. In some embodiments, when the undoped semiconductor layer 105B is removed during a mesa replacement process (described below) to form a layer with... Figures 1B to 1D When the semiconductor device 100 is shown in the cross-sectional view, the undoped semiconductor layer 105B can be formed having the same semiconductor material (e.g., Si) as the mesa structures 336A and 336B. On the other hand, as described in detail below, when the undoped semiconductor layer 105B is not removed during the mesa replacement process to form the semiconductor device 100 with the cross-sectional view, the undoped semiconductor layer 105B can be formed. Figure 1E and Figure 1FWhen the semiconductor device 100 is shown in cross-sectional view, the undoped semiconductor layer 105B can be formed with a semiconductor material (e.g., SiGe) different from the mesa structures 336A and 336B. In some embodiments, the formation of S / D regions 102A and 102B can include epitaxial growth of semiconductor material on the exposed surface of the nanostructure layer 106 facing the S / D opening 402. In some embodiments, FS ESL 114F1 can be formed after the formation of S / D regions 102A and 102B. Figure 5A and Figure 5B As shown, after the formation of FS ESL 114F1, FS ILD layer 116F1 can be deposited on FS ESL 114F1.

[0058] refer to Figure 2 In operation 225, an isolation structure extending through the superlattice structure and the mesa structure is formed. For example, as in reference... Figure 5A , Figure 5B , Figure 6A and Figure 6B As described above, an isolation structure 130 is formed extending through the superlattice structure 307 and the mesa structures 336A and 336B. The isolation structure 130 in... Figure 6B The isolation structure 130 is not visible in the cross-sectional view. The formation of the isolation structure 130 may include the following sequential operations: (i) forming an isolation opening (not shown) by removing portions of polysilicon structures 308A and 308C and the superlattice structure 307, mesa structures 336A and 336B, polishing stop layer 335 and substrate 334 located below the polysilicon structures 308A and 308C; (ii) depositing a nitride liner 130A along the sidewalls of the isolation opening and the top surface of the external spacers 110, FS ESL 114F1, FS IDL layer 116F1 and polysilicon structure 308B; (iii) depositing an oxide filling layer 130B on the nitride liner 130A to fill the isolation opening; and (iv) performing a CMP process on the nitride liner 130A and the oxide filling layer 130B to make the top surface of the nitride liner 130A and the oxide filling layer 130B flush with the external spacers 110, FS ESL 114F1, FS IDL layer 116F1 and polysilicon structure 308B. The top surfaces of the IDL layer 116F1 and the polycrystalline silicon structure 308B are essentially coplanar, such as Figure 6A As shown.

[0059] refer to Figure 2 In operation 230, the polysilicon structure and the sacrificial nanostructure layer are replaced with a gate structure. For example, as referenced... Figure 7A The polysilicon structure 308B and the sacrificial nanostructure layer 306 beneath it are replaced by a gate structure 108. The gate structure 108 is located in... Figure 7BNot visible in the cross-sectional view. The formation of the gate structure 108 may include the following sequential operations: (i) from Figure 6A (ii) The polysilicon structure 308B and the sacrificial nanostructure layer 306 beneath it are removed to form a gate opening (not shown). An IL layer 108A is formed within the gate opening, as shown in the diagram. Figure 7A As shown, (iii) an HK dielectric layer 108B is deposited on the IL layer 108A, as follows: Figure 7A As shown, (iv) WFM 108C is deposited on the HK dielectric layer 108B, as Figure 7A As shown, (v) a gate metal fill layer 108D is deposited on the WFM 108C, as... Figure 7A As shown. After the gate structure 108 is formed, FS ESL 114F2 can be deposited on the gate structure 108, the external spacer 110, and the FS ILD layer 116F1, as shown. Figure 7A and Figure 7B As shown. Figure 7A and Figure 7B As shown, after the deposition of FS ESL 114F2, FS ILD layer 116F2 can be deposited.

[0060] refer to Figure 2 In operation 235, an FS contact structure is formed on the S / D region. For example, as referenced... Figure 7A and Figure 7B The FS contact structure 122F is formed on the FS surface 102f of the S / D regions 102A1, 102A2, 102B1, and 102B2 (in... Figure 7A and Figure 7B (Not visible in the cross-sectional view). The formation of the FS contact structure 122F may include the following sequential operations: (i) forming a contact opening (not shown) by etching the FS ILD layer 116F2, FS ESL 114F2, FS ILD layer 116F1 and FS ESL 114F1 from the FS surfaces 102f of the S / D regions 102A1, 102A2, 102B1 and 102B2; (ii) forming a diffusion barrier layer 128F along the sidewalls of the contact opening, as shown in the figure. Figure 7A and Figure 7B As shown, (iii) a silicide layer 124F is formed on the exposed surfaces of the S / D regions 102A1, 102A2, 102B1, and 102B2 in the contact opening; (iv) a conductive layer 126F is deposited on the silicide layer 124F to fill the contact opening; and (v) a CMP process is performed to make the top surfaces of the conductive layer 126F and the FS ILD layer 116F2 substantially coplanar to form Figure 7A and Figure 7B The structure.

[0061] In some embodiments, such as Figure 7A and Figure 7B As shown, after the formation of the FS contact structure 122F, FS ESL 114F3 can be deposited on the FS contact structure 122F and the FS ILD layer 116F2. In some embodiments, such as Figure 7A and Figure 7B As shown, after the deposition of FSESL 114F3, an FS ILD layer 116F3 can be deposited on the FSESL 114F3. In some embodiments, such as Figure 7A and Figure 7B As shown, after the deposition of the FS ILD layer 116F3, a via structure 123 can be formed. In some embodiments, after the formation of the via structure 123, an interconnect structure 740 can be formed on the FS ILD layer 116F3, such as... Figure 7A As shown (for simplicity, interconnect structure 740 is not shown in other figures). In some embodiments, interconnect structure 740 may include (i) dielectric layers 742 and 744, (ii) a metal line 746 formed in dielectric layer 742, and (iii) a via structure 748 formed in dielectric layer 744. In some embodiments, such as Figure 7A As shown, metal line 746 can directly contact the top surface of via structure 123, and via structure 748 can directly contact the top surface of metal line 746. In some embodiments, a carrier substrate (not shown) can be bonded to the interconnect structure before performing operation 240.

[0062] refer to Figure 2 In operation 240, the mesa structure is replaced with a dielectric layer. For example, as shown in the reference... Figures 8A to 12A and Figures 8B to 12B In the mesa replacement process, mesa structures 336A and 336B are replaced with BS barrier layer 120 and BS ILD layer 116B. The mesa replacement process may include the following sequential operations: (i) performing a CMP process on the BS surface of substrate 334 until the BS surface of substrate 334 is substantially coplanar with the BS surface of isolation structure 130 (not shown); (ii) etching the remaining portion of substrate 334 to expose the sidewalls of isolation structure 130 and the BS surface of polishing stop layer 335, as shown. Figure 8A and Figure 8B As shown, (iii) the polishing stop layer 355 is etched to expose the BS surfaces of the mesa structures 336A and 336B, as Figure 9A and Figure 9B As shown, and the BS surface of the exposed STI region 118, as Figure 9B As shown (STI region 118 in) Figure 9A(iv) The mesa structures 336A and 336B and the undoped semiconductor layer 105B (e.g., undoped Si layer 105B) are etched using the same etching process to form an opening 1020 and expose the gate structure 108, the dielectric layer 105A, and the BS surface of the bottommost internal spacer 112, as not visible in the cross-sectional view. Figure 10A and Figure 10B As shown, (v) a BS barrier layer 120 is deposited on the BS surface of the opening 1020 and the isolation structure 130, as... Figure 11A and Figure 11B As shown, (vi) a BS ILD layer 116B is deposited on the BS barrier layer 20, as... Figure 11A and Figure 11B As shown, and (vii) performing a CMP process to make the BS surfaces of the BS barrier layer 120 and the BS ILD layer 116B substantially coplanar with the BS surfaces of the isolation structure 130 and the STI region 118, as... Figure 12A and Figure 12B As shown.

[0063] refer to Figure 2 In operation 245, a BS contact structure is formed on the S / D region. For example, as referenced... Figures 13A to 17A and Figures 13B to 17B The BS contact structure 122B is formed on the BS surfaces of the S / D regions 102A1 and 102B1. The formation of the BS contact structure 122B may include the following sequential operations: (i) depositing BS ESL 114B on the BS surfaces of the BS barrier layer 120, the BS ILD layer 116B, the isolation structure 130, and the STI region 118, as... Figure 13A and Figure 13B As shown; (ii) Etching portions of the BS ESL 114B, BS ILD layer 116B, BS barrier layer 120, and dielectric layer 105A beneath the S / D regions 102A1 and 102B1 to form contact openings 1422, as shown. Figure 14A and Figure 14B As shown, (iii) a diffusion barrier layer 128B is deposited along the sidewall of the contact opening 1422 and on the BS surface of the S / D regions 102A1 and 102B1 and the BS ESL 114B, as... Figure 14A and Figure 14B As shown, (iv) the horizontal portion of the diffusion barrier layer 128B is etched to expose the S / D regions 102A1 and 102B1 with the BS surface of BS ESL 114B, as... Figure 15A and Figure 15B As shown, (v) a silicide layer 124B is formed on the exposed BS surfaces of S / D regions 102A1 and 102B1, as... Figure 16A and Figure 16BAs shown, (vi) a conductive layer 126B is deposited to fill the contact opening 1422, as... Figure 16A and Figure 16B As shown, and (vii) a CMP process is performed to reduce the thickness of BS ESL 114B, and to make the BS surfaces of BS ESL 114B, diffusion barrier layer 128B and conductive layer 126B substantially coplanar with each other, as... Figure 17A and Figure 17B As shown. In some embodiments, as Figure 18A and Figure 18B As shown, after the BS contact structure 122B is formed, the BS power rail 132 can be formed on the BS ESL 114B and the BS contact structure 122B.

[0064] In some embodiments, operations 240 and 245 may be referenced as follows. Figure 8A , Figure 8B , Figure 9A , Figure 9B and Figures 19 to 22 The execution, not the reference. Figures 8A to 12A and Figures 8B to 12B The execution is to form a Figure 1E and Figure 1F The cross-sectional view of semiconductor device 100.

[0065] refer to Figure 2 In operation 240, the mesa structure is replaced with a dielectric layer. For example, as shown in the reference... Figure 8A , Figure 8B , Figure 9A , Figure 9B , Figure 19 and Figure 20 In the mesa replacement process, mesa structures 336A and 336B are replaced with BS barrier layer 120 and BS ILD layer 116B. The mesa replacement process may include the following sequential operations: (i) performing a CMP process on the BS surface of substrate 334 until the BS surface of substrate 334 is substantially coplanar with the BS surface of isolation structure 130 (not shown); (ii) etching the remaining portion of substrate 334 to expose the sidewalls of isolation structure 130 and the BS surface of polishing stop layer 335, as shown. Figure 8A and Figure 8B As shown, (iii) the polishing stop layer 355 is etched to expose the BS surfaces of the mesa structures 336A and 336B, as Figure 9A and Figure 9B As shown, and the BS surface of the exposed STI region 118, as Figure 9B As shown (STI region 118 in) Figure 9A(iv) Etching mesa structures 336A and 336B to form opening 1920 and expose gate structure 108, undoped semiconductor layer 105B (e.g., undoped SiGe layer 105B), and the BS surface of bottommost internal spacer 112, as not visible in the cross-sectional view. Figure 19 As shown, (v) a BS barrier layer 120 is deposited in opening 1920, as... Figure 20 As shown, (vi) a BS ILD layer 116B is deposited on the BS barrier layer 120, as follows: Figure 20 As shown, and (vii) performing a CMP process to make the BS surfaces of the BS barrier layer 120 and the BS ILD layer 116B substantially coplanar with the BS surface of the isolation structure 130, as... Figure 20 As shown.

[0066] refer to Figure 2 In operation 245, a BS contact structure is formed on the S / D region. For example, as referenced... Figure 21 and Figure 22 The BS contact structure 122B is formed on the BS surface of the S / D regions 102A1 and 102B1 (on... Figure 21 and Figure 22 (Not visible in the cross-sectional view). The formation of the BS contact structure 122B may include the following sequential operations: (i) depositing BS ESL 114B on the BS surface of the BS barrier layer 120, the BS ILD layer 116B, and the isolation structure 130, as shown in the figure. Figure 21 As shown, (ii) portions of the BS ESL 114B, BS ILD layer 116B, BS barrier layer 120, undoped semiconductor layer 105B, and dielectric layer 105A beneath the S / D regions 102A1 and 102B1 are etched to form contact openings 2122, as shown. Figure 21 As shown, (iii) a diffusion barrier layer 128B is deposited along the sidewall of the contact opening 2122 and on the BS surface of the S / D regions 102A1 and 102B1 and the BS ESL 114B, as... Figure 21 As shown, (iv) the horizontal portion of the diffusion barrier layer 128B is etched to expose the S / D regions 102A1 and 102B1 and the BS surface of the BS ESL 114B; (v) a silicide layer 124B is formed on the exposed BS surfaces of the S / D regions 102A1 and 102B1, as shown. Figure 22 As shown, and (vi) a conductive layer 126B is formed in the contact opening 2122, wherein the BS surfaces of the BS ESL 114B, the diffusion barrier layer 128B, and the conductive layer 126B are substantially coplanar with each other, as shown. Figure 22As shown. In some embodiments, after the formation of the BS contact structure 122B, a BS power rail 132 can be formed on the BS ESL 114B and the BS contact structure 122B, as... Figure 22 As shown.

[0067] Figure 23 It is according to some embodiments for manufacturing having Figure 1I , Figure 1J and Figure 1K The flowchart of an example method 2300 for semiconductor device 100 shown is illustrated in the cross-sectional view. For illustrative purposes, reference will be made to... Figures 24 to 29 The example manufacturing process for fabricating the stacked semiconductor device 100 is described below. Figure 23 The operation shown. Figures 24 to 29 It is according to some embodiments along Figure 1A The image shows cross-sectional views of semiconductor device 100 at different stages of its fabrication. Depending on the specific application, the operations may be performed in different sequences, or not at all. It should be noted that method 2300 may not produce a complete semiconductor device 100. Therefore, it should be understood that additional processes may be provided before, during, and after method 2300, and only a few other processes may be briefly described herein. Unless otherwise stated, Figures 1A to 1K , Figures 3A to 18A , Figures 3B to 18B and Figures 24 to 29 Discussions of elements with the same annotations are applicable to each other.

[0068] refer to Figure 23 Operations 2305 and 2335 are similar. Figure 2 Operations 205 and 235. After operation 2335, a result was formed... Figure 9A and Figure 9B A structure similar to the one described below. See the reference below. Figures 24 to 29 The above, for Figure 9A Structure execution Figure 23 The subsequent operation 2340.

[0069] refer to Figure 23 In operation 2340, a BS contact structure is formed on the S / D region. For example, as referenced... Figure 24 and Figure 25 The BS contact structure 122B is formed on the BS surface of the S / D regions 102A1 and 102B1 (on... Figure 24 and Figure 25 (Not visible in the cross-sectional view). Forming the BS contact structure 122B on the S / D region 102A1 may include the following sequential operations: (i) etching portions of the mesa structure 336A, the undoped semiconductor layer 105B, and the dielectric layer 105A below the S / D region 102A to form a contact opening 2422, as shown. Figure 24 As shown; (ii) a diffusion barrier layer 128B is deposited along the sidewall of the contact opening 2422 and on the BS surface of the S / D region 102A1, the mesa structure 336A, and the isolation structure 130, as shown. Figure 24 As shown, (iii) the horizontal portion of the diffusion barrier layer 128B is etched; (iv) a silicide layer 124B is formed on the BS surface of the S / D region 102A1, as shown. Figure 25 As shown, (v) a conductive layer 126B is deposited to fill the contact opening 2422 (not shown), and (vi) a CMP process is performed to make the BS surfaces of the diffusion barrier layer 128B, the conductive layer 126B, the mesa structure 336A, and the isolation structure 130 substantially coplanar with each other, as... Figure 25 As shown.

[0070] refer to Figure 23 In operation 2345, the mesa structure is replaced with a dielectric layer. For example, as referenced... Figures 26 to 29 As described above, in the countertop replacement process, the countertop structures 336A and 336B are replaced with BS barrier layer 120* and BS ILD layer 116B* (in... Figures 26 to 29 (Not visible in the cross-sectional view). The mesa replacement process may include the following sequential operations: (i) etching the mesa structure 336A and the undoped semiconductor layer 105B (e.g., undoped Si layer 105B) using the same etching process to form an opening 2620 and expose the gate structure 108, the dielectric layer 105A, the BS surface of the bottommost internal spacer 112, and the sidewalls of the BS contact structure 122B, as shown. Figure 26 As shown, (ii) a BS barrier layer 120B* is deposited in the opening 2620 and on the BS surface of the isolation structure 130 and the BS contact structure 122B, as Figure 27 As shown, (iii) a BSILD layer 116B* is deposited on the BS barrier layer 120*, as... Figure 28 As shown, and (iv) performing a CMP process to make the BS surfaces of the BS barrier layer 120* and the BS ILD layer 116B* substantially coplanar with the BS surfaces of the isolation structure 130 and the BS contact structure 122B, as Figure 29 As shown. In some embodiments, as Figure 29 As shown, after the tabletop replacement process, BS power rails 132 can be formed on the BS surface of BS barrier layer 120*, BS ILD layer 116B*, isolation structure 130 and BS contact structure 122B.

[0071] This disclosure provides an example semiconductor device (e.g., semiconductor device 100) with a contact structure that electrically connects a source / drain (S / D) region to a base plate (BS) power rail. In some embodiments, a first BS dielectric layer (e.g., BS barrier layer 120 and BS ILD layer 116B) can be used to replace the mesa structures (e.g., mesa structures 336A and 336B) beneath the S / D regions (e.g., S / D regions 102A and 102B) and the gate structure (e.g., gate structure 108) of the semiconductor device, and a contact structure (e.g., BS contact structure 122B) can be formed on the BS surface of the S / D region through the first BS dielectric layer. Replacing the mesa structure with the first BS dielectric layer can reduce the capacitance between the gate structure and the BS contact structure, thus improving device performance (e.g., device speed).

[0072] In some embodiments, the BS contact structure may be electrically connected to a BS power rail (e.g., BS power rail 132), which is formed on a second BS dielectric layer (e.g., BS ESL 114B) disposed on a first BS dielectric layer. In some embodiments, the formation of the BS power rail and the electrical connection between one or more S / D regions and the BS power rail can reduce the device area and the number and size of interconnects between the S / D regions and the power rail, thus reducing device power consumption compared to other semiconductor devices without BS power rails. Furthermore, since the BS power rail can be formed in a larger region than the front power rail, the BS power rail can be formed to have a lower resistance than the front power rail formed on the front side of the S / D region.

[0073] In some embodiments, the semiconductor device includes a first source / drain region and a second source / drain region, a nanostructured channel region disposed between the first source / drain region and the second source / drain region, and a gate structure. The gate structure includes a gate dielectric layer surrounding each nanostructured channel region and a conductive layer disposed on the gate dielectric layer. The semiconductor device also includes a first contact structure disposed on the front surface of the first source / drain region, a gate spacer disposed between the gate structure and the first contact structure and extending along the sidewall of the gate structure, a second contact structure disposed on the back surface of the first source / drain region, a dielectric liner disposed on the back surfaces of the gate structure and the second source / drain region, and a first dielectric layer disposed on the dielectric liner. The first contact structure includes a silicide layer with a curved profile, and the dielectric constant of the gate dielectric layer is greater than the dielectric constant of the gate spacer.

[0074] In some embodiments, the thickness of a first portion of the first dielectric layer below the second source / drain region is greater than the thickness of a second portion of the first dielectric layer below the gate structure.

[0075] In some embodiments, the semiconductor device further includes a second dielectric layer disposed between the back surface of the second source / drain region and the dielectric liner.

[0076] In some embodiments, the semiconductor device further includes an undoped semiconductor layer disposed between the back surface of the second source / drain region and the dielectric liner.

[0077] In some embodiments, the semiconductor device further includes a second dielectric layer disposed on the first dielectric layer and surrounding a portion of the second contact structure extending beneath the first dielectric layer.

[0078] In some embodiments, the dielectric liner includes a nitrogen atom concentration higher than the oxygen atom concentration and is disposed on the sidewall of the second contact structure.

[0079] In some embodiments, the first dielectric layer includes an oxygen atom concentration higher than that of nitrogen atoms and is disposed on the sidewall of the second contact structure.

[0080] In some embodiments, the oxygen and nitrogen atom concentrations in the dielectric liner are different from those in the first dielectric layer.

[0081] In some embodiments, the semiconductor device further includes a shallow isolation region disposed beneath the gate structure and in contact with the dielectric liner.

[0082] In some embodiments, the semiconductor device further includes an isolation structure extending vertically over and below the first source / drain region and the second source / drain region, wherein the dielectric liner is disposed along the sidewall of the isolation structure.

[0083] In some embodiments, a method includes forming a mesa structure on a substrate, forming a first source / drain region and a second source / drain region on the mesa structure, forming a gate structure between the first source / drain region and the second source / drain region and on the mesa structure, replacing the mesa structure with a dielectric structure on the back surface of the first source / drain region, the second source / drain region and the gate structure, etching a portion of the dielectric structure from the back surface of the first source / drain region, and forming a contact structure on the back surface of the first source / drain region. The contact structure includes a silicide layer and a conductive layer. The conductivity of the conductive layer is greater than the conductivity of the second source / drain region.

[0084] In some embodiments, replacing the mesa structure with the dielectric structure includes: etching the mesa structure to form openings in the first source / drain region and the second source / drain region on the back surface of the gate structure; depositing a dielectric liner having a first dielectric constant in the openings; and depositing a dielectric layer having a second dielectric constant lower than the first dielectric constant on the dielectric liner.

[0085] In some embodiments, the method further includes growing a semiconductor layer in an opening in the mesa structure prior to forming the first source / drain region.

[0086] In some embodiments, replacing the mesa structure includes removing the semiconductor layer.

[0087] In some embodiments, the method further includes depositing a dielectric layer on the semiconductor layer prior to forming the first source / drain region.

[0088] In some embodiments, the method further includes removing the dielectric layer to expose the back surface of the first source / drain region before forming the contact structure.

[0089] In some embodiments, a method includes forming a mesa structure on a substrate, forming a superlattice structure having a nanostructure layer and a sacrificial nanostructure layer on the mesa structure, etching the superlattice structure to form a first opening, etching the mesa structure to form a second opening, forming an isolation structure on an exposed surface of the mesa structure in the second opening, epitaxially growing source / drain regions on the exposed surface of the nanostructure layer in the first opening, replacing the sacrificial nanostructure layer with a gate structure, replacing the mesa structure with a dielectric liner and a dielectric layer, and forming a contact structure on the source / drain regions, the contact structure extending vertically through the dielectric liner and the dielectric layer. In some embodiments, replacing the mesa structure includes etching the mesa structure to expose the back surface of the gate structure. In some embodiments, replacing the mesa structure includes etching the semiconductor layer of the isolation structure. In some embodiments, the method further includes depositing an etch stop layer on the dielectric layer prior to forming the contact structure.

[0090] The foregoing outlines features of several embodiments to enable those skilled in the art to better understand aspects of this disclosure. Those skilled in the art should understand that they can readily use this disclosure as a basis to design or modify other processes and structures for implementing the same purposes and / or achieving the same advantages as the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and alterations can be made to them herein without departing from the spirit and scope of this disclosure.

Claims

1. A semiconductor device, comprising: First source / drain region and second source / drain region; The nanostructured channel region is disposed between the first source / drain region and the second source / drain region; A gate structure comprising: a gate dielectric layer surrounding each of the nanostructure channel regions; and a conductive layer disposed on the gate dielectric layer; A first contact structure is disposed on the front surface of the first source / drain region, and the first contact structure includes a silicide layer with a curved profile. A gate spacer is disposed between the gate structure and the first contact structure and extends along the sidewall of the gate structure, wherein the dielectric constant of the gate dielectric layer is greater than the dielectric constant of the gate spacer. The second contact structure is disposed on the back surface of the first source / drain region; A dielectric liner is disposed on the back surface of the gate structure and the second source / drain region; and A first dielectric layer is disposed on the dielectric liner.

2. The semiconductor device according to claim 1, wherein, The thickness of the first portion of the first dielectric layer below the second source / drain region is greater than the thickness of the second portion of the first dielectric layer below the gate structure.

3. The semiconductor device of claim 1, further comprising a second dielectric layer disposed between the back surface of the second source / drain region and the dielectric liner.

4. The semiconductor device of claim 1, further comprising an undoped semiconductor layer disposed between the back surface of the second source / drain region and the dielectric liner.

5. The semiconductor device of claim 1, further comprising a second dielectric layer disposed on the first dielectric layer and surrounding a portion of the second contact structure extending below the first dielectric layer.

6. The semiconductor device according to claim 1, wherein, The dielectric liner includes a nitrogen atom concentration higher than the oxygen atom concentration, and the dielectric liner is disposed on the sidewall of the second contact structure.

7. The semiconductor device according to claim 1, wherein, The first dielectric layer has an oxygen atom concentration higher than that of nitrogen atoms, and the first dielectric layer is disposed on the sidewall of the second contact structure.

8. The semiconductor device according to claim 1, wherein, The oxygen and nitrogen atom concentrations in the dielectric liner are different from those in the first dielectric layer.

9. A method for manufacturing a semiconductor device, comprising: Forming mesa structures on the substrate; A first source / drain region and a second source / drain region are formed on the mesa structure; A gate structure is formed between the first source / drain region and the second source / drain region and on the mesa structure; The mesa structure is replaced with a dielectric structure on the back surface of the first source / drain region and the second source / drain region and the gate structure; A portion of the dielectric structure is etched from the back surface of the first source / drain region; as well as A contact structure is formed on the back surface of the first source / drain region, wherein the contact structure includes a silicide layer and a conductive layer, and wherein the conductivity of the conductive layer is greater than the conductivity of the second source / drain region.

10. A method for manufacturing a semiconductor device, comprising: Forming mesa structures on the substrate; A superlattice structure comprising a nanostructure layer and a sacrificial nanostructure layer is formed on the mesa structure; The superlattice structure is etched to form a first opening; The mesa structure is etched to form a second opening; An isolation structure is formed on the exposed surface of the platform structure in the second opening; Source / drain regions are epitaxially grown on the exposed surface of the nanostructure layer in the first opening; Replace the sacrificial nanostructure layer with a gate structure; Replace the mezzanine structure with a dielectric liner and a dielectric layer; as well as A contact structure is formed on the source / drain region, and the contact structure extends vertically through the dielectric liner and the dielectric layer.

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