A transistor cell, a semiconductor device and a manufacturing method thereof, and an electronic device

Abstract

The present application relates to the technical field of semiconductor device preparation, and particularly relates to a transistor unit, a semiconductor device and a manufacturing method thereof, and an electronic device, the transistor unit comprising: at least two transistors which are sequentially stacked in a vertical direction, each transistor comprising a gate stack structure and source-drain regions located on both sides of the gate stack structure; wherein all the transistors have the same conductivity type, and a gate isolation structure is arranged between the gate stack structures of adjacent transistors. The present application adopts a same-polarity stacked structure, that is, a plurality of transistors with the same conductivity type are stacked in the vertical direction, and any one of the source-drain regions of two vertically adjacent transistors is electrically connected to each other, forming a common source or common drain connection contact part, which can form a common VDD or VSS power connection part in a circuit and be led out together, thereby significantly reducing the number of power wiring and reducing the parasitic effect.

Description

Technical Field

[0001] This invention relates to the field of semiconductor device fabrication technology, and in particular to a transistor unit, a semiconductor device and its manufacturing method, and an electronic device. Background Technology

[0002] As integrated circuit technology continues to evolve towards nodes of 2nm and below, Gate-All-Around (GAA) devices are gradually approaching their physical limits. Complementary Field-Effect Transistors (CFETs), by vertically stacking n-type and p-type transistors, can theoretically reduce the standard cell area to half that of traditional CMOS, and are considered a key technology for the next generation of transistors.

[0003] However, existing CFET devices still have many shortcomings in terms of process technology, interconnection, and circuit design. In terms of manufacturing, compared to GAA devices, CFETs require the formation of source and drain regions for both upper and lower transistor layers vertically, making epitaxial growth and high aspect ratio metallization processes extremely difficult. Regarding interconnection, vertically stacked devices can hinder contact take-out, thus worsening parasitic effects. Furthermore, traditional CFETs often employ a common-gate structure, where upper and lower devices share the same gate signal. While this structure is suitable for inverters, implementing standard cells such as transmission gates that require nFETs and pFETs to receive complementary signals necessitates additional circuit overhead and a larger layout area, reducing the space utilization of logic circuits and limiting the widespread application of CFETs in standard logic libraries.

[0004] In view of this, the present invention is proposed. Summary of the Invention

[0005] The purpose of this invention is to provide a transistor unit, a semiconductor device and its manufacturing method, and an electronic device. This invention adopts a same polarity stacked structure, in which the source and drain regions of two vertically adjacent transistors are electrically connected to each other to form a common source or common drain connection. In the circuit, a common VDD or VSS can be formed and brought out, which significantly reduces the number of power supply wirings and reduces parasitic effects.

[0006] In a first aspect, the present invention provides a transistor unit, comprising: At least two transistors are stacked sequentially in a vertical direction, each transistor including a gate stack structure and source / drain regions located on both sides of the gate stack structure; All of the transistors have the same conductivity type, and a gate isolation structure is provided between the gate stack structures of adjacent transistors.

[0007] As a preferred embodiment of this technical solution, all the transistors are either P-type transistors or N-type transistors.

[0008] In a preferred embodiment of this technical solution, any one of the source and drain regions of two vertically adjacent transistors is electrically connected to each other to form a common source or common drain connection contact.

[0009] In a preferred embodiment of this technical solution, the common source or common drain connection contact penetrates at least one of the two vertically adjacent source and drain regions of the transistor and wraps at least a portion of the sidewalls of the source and drain regions.

[0010] In a preferred embodiment of this technical solution, the common source or common drain connection contact extends between two vertically adjacent source and drain regions of the transistor, and the source and drain regions are all embedded in the common source or common drain connection contact.

[0011] In a preferred embodiment of this technical solution, the transistors above the gate isolation structure and the transistors below the gate isolation structure are mirror-symmetrical about the central plane of the gate isolation structure.

[0012] As a preferred embodiment of this technical solution, a mirror-symmetrical gate sidewall structure is provided above the uppermost channel of the transistor above the gate isolation structure and below the lowermost channel of the transistor below the gate isolation structure.

[0013] Secondly, the present invention also discloses a semiconductor device, including a substrate, A first transistor unit and a second transistor unit are disposed adjacent to each other in the horizontal direction on the substrate, and both the first transistor unit and the second transistor unit are the transistor units described above. The first transistor unit has the opposite conductivity type to the second transistor unit.

[0014] As a preferred embodiment of this technical solution, the first transistor unit and the second transistor unit have the same number of vertical stacking layers, and in any vertical stacking level, the gate stacking structure of the transistor in the first transistor unit is interconnected with the gate stacking structure of the transistor in the second transistor unit.

[0015] As a preferred embodiment of this technical solution, in any vertical stacking level, the transistors in the first transistor unit and the transistors in the second transistor unit form a set of inverter units.

[0016] As a preferred embodiment of this technical solution, in the inverter unit... The gate stacking structure of the transistors in the first transistor unit is interconnected with the gate stacking structure of the transistors in the second transistor unit to form the input terminal of the inverter unit; The drain contact portion of the transistor in the first transistor unit is connected to the drain contact portion of the transistor in the second transistor unit to form the output terminal of the inverter unit.

[0017] As a preferred embodiment of this technical solution, the semiconductor device includes a first inverter unit and a second inverter unit arranged back to back; In the first inverter unit and the second inverter unit, the source region contact portions of the transistors located in different vertical stacking levels are connected respectively, and form a common power supply terminal lead-out node and a ground terminal lead-out node respectively.

[0018] Thirdly, the present invention also discloses a method for manufacturing a semiconductor device, comprising the following steps: Provide substrate; A first fin stack and a second fin stack are formed on the substrate in a horizontally parallel and spaced-apart manner. The first fin stack and the second fin stack are each formed by alternating stacking of a channel layer and a channel sacrificial layer. The first fin stack and the second fin stack also include an isolation sacrificial layer, which divides the first fin stack and the second fin stack into at least an upper part and a lower part, respectively. A sacrificial gate and sidewalls are formed above the first fin stack and the second fin stack; Using the sacrificial gate and the sidewall as masks, anisotropic etching is performed on the upper and lower parts of the first fin stack and the second fin stack to remove the fin stack portion located in the source and drain regions and expose the ends of each level of channel layer; Source and drain epitaxial regions are formed at the ends of the channel layers of the first fin stack and the second fin stack, respectively. A source and drain region of a first conductivity type is formed at the ends of the channel layers of the first fin stack, and a source and drain region of a second conductivity type is formed at the ends of the channel layers of the second fin stack. The first conductivity type is different from the second conductivity type. Remove the sacrificial gate and the channel sacrificial layer, and release the channel layer to form a gate trench; An alternative gate structure is formed in the gate trench, and the alternative gate structures are isolated from each other by dielectric material between different vertical layers.

[0019] As a preferred embodiment of this technical solution, the source / drain epitaxial regions at the ends of the channel layers of the first and second fin stacks respectively include: Source and drain regions of the first conductivity type are synchronously epitaxially formed at the ends of the top and bottom channel layers of the first fin stack; The source and drain regions of the second conductivity type are synchronously epitaxially formed at the ends of the top and bottom channel layers of the second fin stack.

[0020] As a preferred embodiment of this technical solution, after respectively performing the source / drain epitaxial regions at the ends of the first fin stack and the second fin stack channel layer, the solution further includes: A first dielectric layer is deposited on the surface of the exposed device, and the first dielectric layer is etched back to remove the first dielectric layer outside the source / drain contact location; A second dielectric layer is deposited in the region outside the source / drain contact area, and the material of the second dielectric layer is different from that of the first dielectric layer. The first dielectric layer at the contact location of the source-drain region is selectively removed and filled with metal to form a common source or common drain connection contact between two vertically adjacent transistor source-drain regions.

[0021] Fourthly, the present invention also discloses an electronic device comprising one or more of the transistor units or semiconductor devices described above. Electronic devices include smartphones, personal computers, tablets, artificial intelligence devices, wearable devices, or power banks.

[0022] Beneficial effects: 1. This invention employs a homopolarity stacked structure, where multiple transistors of the same conductivity type are stacked vertically. This layout design allows for simultaneous epitaxial growth of the channel layer ends at the top and bottom of the same transistor cell during the source-drain epitaxial step, significantly simplifying the process and reducing manufacturing costs.

[0023] 2. In each transistor unit of this invention, the gate stack structures of two vertically adjacent transistors are electrically isolated from each other through a gate isolation structure, forming independent split gates, so that the transistors of each layer can be controlled independently. On this basis, the gates of horizontally adjacent transistors of different conductivity types are interconnected in the same vertical layer. Therefore, the devices in the same layer can be regarded as independent GAA devices. At this time, a logic unit can use only the GAA devices in the same layer, and the layout and wiring can be completely consistent with the GAA.

[0024] 3. Since the gates of different levels in this invention can be controlled independently, and the transistors of each level in the same transistor unit have the same conductivity type, when an inverter composed of two transistors in the same level is distributed back to back with an inverter composed of two transistors in another level, the source region contacts of the transistors in different levels can be connected to form common source or common drain connection contacts. These common source or common drain connection contacts can form a common VDD or VSS power connection in the circuit and be led out together. This layout design significantly reduces the number of power supply wirings and reduces parasitic effects.

[0025] 4. The same-polarity stacked transistor units of this invention can also be applied to the connection of BL / BLB / VDD / VSS in memory cells such as SRAM. In SRAM memory cells, since the transistor units are stacked with the same polarity, the six transistors in the SRAM memory cell are located on the same layer, and two SRAM cells will form a back-to-back structure. This solves the problem of Q / QB signal line conflict in traditional CFET SRAM cells and reduces the area occupied by SRAM memory cells. In addition, when two SRAM cells are set back-to-back, the source or drain contacts of transistors located in different layers can be connected to form common source or common drain connection contacts, leading out BL / BLB / VDD / VSS. While solving the Q / QB signal line conflict, the number of wirings and wiring density are reduced. Attached Figure Description

[0026] To more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0027] Figure 1 This is a schematic diagram of the structure of the transistor unit of the present invention; Figure 2 This is a schematic diagram of the structure of the semiconductor device of the present invention; Figure 3 The present invention relates to the application of the semiconductor device in an inverter unit, wherein (a) is a wiring diagram of a conventional CFET inverter unit; and (b) is a wiring diagram of the inverter unit of the semiconductor device of the present invention. Figure 4 The present invention relates to the application of the semiconductor device in an SRAM cell, wherein (a) is a layout of a conventional CFET SRAM cell; and (b) is a layout of an SRAM cell formed by the semiconductor device of the present invention. Figures 5-13 This is a schematic diagram of the fabrication process of the semiconductor device of the present invention.

[0028] Explanation of reference numerals in the attached figures: 100: Gate stack structure; 101: Source / drain region; 102: Common source or common drain connection contact; 200: First transistor unit; 300: Second transistor unit; 400: Substrate; 500: First fin stack; 600: Second fin stack; 700: Channel layer; 701: Channel sacrificial layer; 703: Isolation sacrificial layer; 704: Sacrificial gate; 705: Source / drain region of first conductivity type; 706: Source / drain region of second conductivity type; 707: First dielectric layer; 708: Second dielectric layer; 709: Gate dielectric layer; 710: Metal gate layer; 711: Gate isolation structure. Detailed Implementation

[0029] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. However, it should be understood that these descriptions are merely exemplary and not intended to limit the scope of the invention. Furthermore, descriptions of well-known structures and techniques are omitted in the following description to avoid unnecessarily obscuring the concept of the invention.

[0030] The accompanying drawings illustrate various structural schematic diagrams according to embodiments of the present invention. These drawings are not to scale, and some details have been enlarged and may have been omitted for clarity. The shapes of the various regions and layers shown in the drawings, as well as their relative sizes and positional relationships, are merely exemplary and may deviate from reality due to manufacturing tolerances or technical limitations. Furthermore, those skilled in the art can design regions / layers with different shapes, sizes, and relative positions as needed.

[0031] In the context of this invention, when a layer / element is referred to as being "on" another layer / element, the layer / element may be directly on the other layer / element, or there may be an intermediate layer / element between them. Furthermore, if a layer / element is "on" another layer / element in one orientation, then when the orientation is reversed, the layer / element may be "below" the other layer / element. To make the technical problems, technical solutions, and beneficial effects of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.

[0032] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified. "Several" means one or more, unless otherwise explicitly specified.

[0033] In the description of this invention, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0034] Compared to GAA devices, CFETs require the formation of source and drain regions for both upper and lower transistor layers in the vertical direction, making epitaxial growth and high aspect ratio metallization processes extremely challenging. Regarding interconnection, vertically stacked devices can obstruct contact take-out, thus worsening parasitic effects. Furthermore, traditional CFETs often employ a common-gate structure, where upper and lower devices share the same gate signal. While this structure is suitable for inverters, implementing standard cells such as transmission gates that require nFETs and pFETs to receive complementary signals necessitates additional circuit overhead and a larger layout area, reducing the space utilization of logic circuits and limiting the widespread application of CFETs in standard logic libraries.

[0035] To address the aforementioned problems, the present invention proposes a transistor unit comprising at least two transistors stacked sequentially in a vertical direction, all of which have the same conductivity type, and a gate isolation structure 711 is provided between the gate stack structures 100 of adjacent transistors.

[0036] This invention employs a homopolarity stacked structure, where multiple transistors of the same conductivity type are stacked vertically. This layout design significantly improves the performance of transistor cells and semiconductor devices composed of transistor cells, both in source-drain epitaxial processes and in circuit interconnection. In the source-drain epitaxial process, the upper and lower ends of the channel layer 700 of the same transistor cell can be epitaxially grown simultaneously, greatly simplifying the process flow and reducing the difficulty of source-drain processes. Regarding interconnection, the gate stacked structures 100 of two vertically adjacent transistors are electrically isolated from each other by a gate isolation structure 711, forming independent split gates, allowing each layer of transistors to be controlled independently. Furthermore, horizontally adjacent transistors of different conductivity types are interconnected at their gates in the same vertical layer. Therefore, devices in the same layer can be considered as independent GAA devices. In this case, a logic cell can use only GAA devices in the same layer, and the layout and wiring can be completely consistent with the GAA. Furthermore, devices at different levels can be interconnected. For example, when an inverter composed of two transistors at the same level is distributed back-to-back with an inverter composed of two transistors at another level, the source contacts of the transistors at different levels can be connected to form a common-source or common-drain connection contact 102. This common-source or common-drain connection contact 102 can form a shared VDD or VSS power connection in the circuit and be led out together. This layout design significantly reduces the number of power supply wirings and reduces parasitic effects. The same-polarity stacked transistor units of this invention can also be applied to the connection of BL / BLB / VDD / VSS in memory cells such as SRAM. In SRAM memory cells, since the transistor units are stacked with the same polarity, the six transistors in the SRAM memory cell are located on the same layer, and two SRAM cells will form a back-to-back structure. This effectively solves the problem of Q / QB signal line conflict in traditional CFET SRAM cells and reduces the occupied area of ​​SRAM memory cells.

[0037] Firstly, such as Figure 1 As shown, this embodiment of the invention provides a transistor unit, including at least two transistors stacked sequentially in a vertical direction. Each transistor includes a gate stack structure 100 and source / drain regions 101 located on both sides of the gate stack structure 100. In this embodiment, the invention is described using a transistor unit comprising two transistors at the top and bottom as an example, but the invention is not limited thereto. The transistor unit of the invention may include 3, 4, or more vertically stacked transistors.

[0038] In the transistor cell of this embodiment, the vertically stacked top and bottom transistors have the same conductivity type. For example, both the vertically stacked top and bottom transistors are either P-type or N-type transistors. When transistors of the same conductivity type are epitaxially grown, the fabrication of all levels of source / drain regions 101 can be completed simultaneously in the same epitaxial process, eliminating the need for layered epitaxy and greatly simplifying the epitaxial process. Simultaneously, the same polarity stacking allows the source / drain regions 101 of the top and bottom transistors to be concentrated according to conductivity type, creating conditions for a one-time opening of common-drain / common-source contacts.

[0039] In this embodiment, a gate isolation structure 711 is provided between the gate stack structures 100 of the vertically adjacent top transistor and bottom transistor. Therefore, the gate stack structures of transistors in different levels are electrically isolated from each other and can be controlled independently.

[0040] Based on the above, a source-drain isolation structure is provided between at least one of the source-drain regions 101 of the vertically adjacent top transistor and bottom transistor to physically and electrically isolate the source-drain regions 101 of different levels from each other. Preferably, the source-drain isolation structure is aligned with or at least partially overlaps with the orthogonal projection of the gate isolation structure 711 on the substrate 400 to ensure the isolation effect between the upper and lower layer devices.

[0041] More importantly, the same-polarity stacked transistor cell layout design of this invention allows for direct electrical connection between the source and drain regions 101 of two adjacent transistors. That is, the source or drain region of the top transistor is electrically connected to the source or drain region of the bottom transistor, forming a common-source or common-drain connection contact. By directly connecting the source and drain regions 101 of the upper and lower transistors, additional interconnect metal and contact vias are saved, effectively reducing the cell area. Furthermore, common-source or common-drain connections also help reduce interconnect path length, effectively lowering parasitic resistance and capacitance. The same-polarity stacked transistor cells of this invention can also be applied to the connection of BL / BLB / VDD / VSS in memory cells such as SRAM. In SRAM memory cells, since the transistor cells are stacked with the same polarity, the six transistors in the SRAM memory cell are located on the same layer, and two SRAM cells will form a back-to-back structure. This solves the problem of Q / QB signal line conflict in traditional CFET SRAM cells and reduces the layout area. In addition, when two SRAM cells are set back-to-back, the source or drain contacts of transistors located in different layers can be connected to form common source or common drain connection contacts, leading out BL / BLB / VDD / VSS. While solving the Q / QB signal line conflict, the number of wirings and wiring density are reduced.

[0042] Based on the above, the common-source or common-drain connection contact 102 of the present invention not only connects the source or drain regions of two transistors, but also vertically penetrates the source or drain region of at least one transistor and wraps around at least a portion of the sidewalls of the source or drain region, forming a surrounding contact structure. Conventional contact holes only contact the top surface of the source / drain region 101, resulting in a limited contact area. The common-source or common-drain connection contact 102 of the present invention wraps around the sidewalls of the source / drain region 101, significantly increasing the contact area and reducing contact resistance.

[0043] Based on the above, the common source or common drain connection contact 102 of the present invention extends between two vertically adjacent transistor source and drain regions 101, and the source and drain regions 101 are all embedded in the common source or common drain connection contact 102. That is, the common source or common drain connection contact 102 completely surrounds the source and drain regions 101 from multiple directions such as top, bottom and sidewall, realizing the theoretical maximum contact area and minimizing the contact resistance.

[0044] In the same transistor unit of the present invention, the two transistors located above and below the gate isolation structure 711 are geometrically mirror-symmetrical. Specifically, the arrangement of the gate stack structure 100, the channel layer 700, and the source / drain region 101 of the top transistor is mirror-symmetrical with respect to the corresponding structure of the bottom transistor, relative to the central plane of the gate isolation structure 711.

[0045] Based on the above, and more preferably, a mirror-symmetrical gate sidewall structure is provided above the uppermost channel of the transistor above the gate isolation structure 711 and below the lowermost channel of the transistor below the gate isolation structure 711.

[0046] More preferably, based on the above, each transistor in the transistor unit of the present invention is a gate ring nanowire or nanosheet transistor.

[0047] This invention utilizes the same polarity stacking characteristic of all transistors within a transistor unit having the same conductivity type, allowing the source and drain regions 101 of the top and bottom transistors within the same transistor unit to be formed simultaneously in the same epitaxial process, significantly simplifying the source and drain process. Simultaneously, the same polarity stacking layout enables any one of the source and drain regions 101 of two vertically adjacent transistors to be electrically connected, forming a common source or common drain connection contact 102. This common source or common drain connection contact 102 can form a shared VDD or VSS power connection in the circuit and be led out together. This layout design significantly reduces the number of power wirings and lowers parasitic effects.

[0048] Secondly, such as Figure 2As shown, an embodiment of the present invention provides a semiconductor device, including a substrate 400, a first transistor unit 200, and a second transistor unit 300. The first transistor unit 200 and the second transistor unit 300 are disposed adjacent to each other on the substrate 400 in a horizontal direction. Both the first transistor unit 200 and the second transistor unit 300 are transistor units of the first aspect of the present invention, and the first transistor unit 200 and the second transistor unit 300 have opposite conductivity types.

[0049] Specifically, in this embodiment, all transistors in the first transistor unit 200 are P-type transistors, and all transistors in the second transistor unit 300 are N-type transistors. Alternatively, in another embodiment, all transistors in the first transistor unit 200 are N-type transistors, and all transistors in the second transistor unit 300 are P-type transistors. This invention does not impose strict limitations on these embodiments.

[0050] In the semiconductor device of the present invention, the first transistor unit 200 and the second transistor unit 300 have the same number of vertically stacked layers, and in any vertical stacking level, the gate stacking structure 100 of the transistors at the corresponding level in the first transistor unit 200 and the gate stacking structure 100 of the transistors at the corresponding level in the second transistor unit 300 are electrically connected to each other. Specifically, in the same vertical level, the gate stacking structure 100 of the transistors in the first transistor unit 200 and the gate stacking structure 100 of the transistors in the second transistor unit 300 are electrically connected through an interconnect layer or gate bridging structure located above the transistor unit. The gate stacking structures between different levels are electrically isolated from each other through a gate isolation structure 711. Therefore, the semiconductor device of the present invention retains the area advantage of traditional CFETs while also achieving the flexibility of independently controlling devices at different levels.

[0051] In some embodiments of the present invention, the first transistor unit 200 includes a top P-type transistor and a bottom P-type transistor stacked vertically, and the second transistor unit 300 includes a top N-type transistor and a bottom N-type transistor stacked vertically. In one vertical layer, the top P-type transistor in the first transistor unit 200 and the top N-type transistor in the second transistor unit 300 can form an inverter unit; in another vertical layer, the bottom P-type transistor in the first transistor unit 200 and the bottom N-type transistor in the second transistor unit 300 can form another inverter unit. Therefore, in the semiconductor device of the present invention, each layer can form an independent inverter, which means that the semiconductor device of the present invention can integrate multiple independent logic gates in the vertical direction. In conventional planar CMOS, an inverter requires a horizontally arranged N-type transistor and a P-type transistor, occupying a large horizontal area. In the present invention, the N-type transistor and the P-type transistor are adjacent in the horizontal direction but share the active region with other layers in the vertical direction, allowing multiple inverters to be integrated in the same horizontal area, significantly improving area utilization.

[0052] Based on the above, such as Figure 3 As shown in (a), in any inverter cell, the gate stack structures 100 of transistors in the same layer are electrically connected to each other, forming a common gate contact for that layer, which constitutes the input terminal of the inverter cell. The gate stack structures between different layers are isolated from each other; therefore, each inverter cell in each layer can receive different input signals and achieve independent control. At the same time, the drain contacts of transistors in the same layer are connected to each other, forming the output terminal of the inverter cell.

[0053] In other embodiments of the invention, such as Figure 3 As shown in (b), when inverter cells formed by adjacent layers are arranged back-to-back, the source region contacts of transistors in different vertical stacking layers are connected separately, forming a common VDD power supply terminal lead-out node and VSS ground terminal lead-out node. In a traditional CFET SRAM cell, each inverter needs to bring out VDD and VSS separately, resulting in dense wiring. However, the same polarity stacking arrangement of this invention allows the source region contacts of transistors in different vertical stacking layers to be connected separately, forming a common source connection contact. Therefore, the VDD power supply terminal lead-out node and VSS ground terminal lead-out node of adjacent inverters can be brought out together, significantly reducing the number of wires, reducing parasitic effects, and reducing the occupied area of ​​the inverter cell.

[0054] In this embodiment, in any vertical stacking level, since the N-type transistors and P-type transistors are arranged horizontally adjacent to each other, their gate interconnect and drain interconnect paths and interconnect lengths are shortened, which reduces parasitic resistance and parasitic capacitance and improves the working performance of the inverter.

[0055] In other embodiments of the invention, such as Figure 4 As shown, when the same-polarity stacked semiconductor device of the present invention is applied to the connection of BL / BLB / VDD / VSS in an SRAM cell, since the transistor cells are stacked with the same polarity, the six transistors in the SRAM cell are located on the same layer, and the two SRAM cells form a back-to-back structure. This solves the problem of Q / QB signal line conflict in the traditional CFET SRAM cell and reduces the area occupied by the SRAM cell. In addition, when the two SRAM cells are arranged back-to-back, the source or drain contacts of the transistors located in different layers can be connected to form common source or common drain connection contacts, leading out BL / BLB / VDD / VSS. This reduces the number of wirings and wiring density while solving the Q / QB signal line conflict.

[0056] It should be noted that in the same polarity stacked semiconductor device of the present invention, since the gate stacking structure of N-type transistors and P-type transistors in each layer is independent of each other, the layout method of the present invention can not only be applied to inverters and SRAM cells, but also to various standard logic gates by changing the source-drain connection method of N-type transistors and P-type transistors in the same vertical layer, the combination method of gate input signals, and the interconnection strategy between different layers.

[0057] Thirdly, embodiments of the present invention provide a method for manufacturing a semiconductor device. The structure of the semiconductor device formed by the manufacturing method provided in the third aspect of the present invention is the same as that of the semiconductor device provided in the second aspect. Therefore, the beneficial effects of the second aspect and its various implementations in the embodiments of the present invention can be referred to the analysis of the beneficial effects in the second aspect and its various implementations, and will not be repeated here.

[0058] The following will be based on Figures 5 to 13 The illustrated cross-sectional view describes the manufacturing process. Specifically, the method for manufacturing this semiconductor device includes the following steps: First, such as Figure 5 As shown, a substrate 400 is provided, on which a first fin stack 500 and a second fin stack 600 are formed in a horizontally parallel and spaced-apart manner. The first fin stack 500 and the second fin stack 600 are each formed by alternating stacking of a first semiconductor layer and a second semiconductor layer. The first semiconductor layer serves as a subsequent channel layer 700, and its material may include silicon (Si). The second semiconductor layer serves as a channel sacrificial layer 701, and its material may include silicon germanium (SiGe), wherein the germanium content may be any value between 10% and 60%.

[0059] The first fin stack 500 and the second fin stack 600 also include an isolation sacrificial layer 703 in the middle, which divides the first fin stack 500 and the second fin stack 600 into upper and lower parts, respectively. The isolation sacrificial layer 703 mainly serves as a pre-placement layer. Subsequently, by removing the isolation sacrificial layer 703 and depositing an isolation dielectric, an MDI isolation structure is formed between the upper and lower transistors. The material of the isolation sacrificial layer 703 may include germanium silicon with a high germanium content (e.g., germanium content greater than 30%) to achieve high etch selectivity with adjacent semiconductor layers.

[0060] Specifically, when forming the first fin stack 500 and the second fin stack 600, a lower channel layer 700 / channel sacrificial layer 701, an isolation sacrificial layer 703, and an upper channel layer 700 / channel sacrificial layer 701 can be epitaxially grown sequentially on the substrate 400. Then, the fins are patterned using sidewall transfer technology to form at least two spaced fin structures. Further, a shallow trench isolation region (STI) is formed between two adjacent fin stack structures. At this time, the top surface of the shallow trench isolation region is not higher than the bottom surface of the bottom channel layer 700 in the first fin stack 500 and the second fin stack 600.

[0061] Next, as Figure 6 As shown, a sacrificial gate 704 and sidewalls are formed above the first fin stack 500 and the second fin stack 600. Using the sacrificial gate 704 and sidewalls as masks, anisotropic etching is performed on the upper and lower parts of the first fin stack 500 and the second fin stack 600 to remove the fin stack portion located in the source / drain region 101, exposing the ends of the channel layers 700 of each level, and forming the corresponding nanowire / sheet stack.

[0062] Next, the isolation sacrificial layer 703 in the middle of the first fin stack 500 and the second fin stack 600 is removed, forming a laterally extending cavity in the middle of the fin stack; further, the cavity is filled with an isolation medium to form an MDI isolation structure.

[0063] Specifically, the process for removing the isolation sacrificial layer 703 can employ isotropic etching (such as wet etching or vapor phase etching), utilizing the high etching selectivity between the isolation sacrificial layer 703 and the adjacent semiconductor layer to precisely remove the isolation sacrificial layer 703 without damaging the surrounding channel layer 700.

[0064] Next, the ends of the channel sacrificial layer 701 are etched isotropically to form a controllable transverse groove; further, the inner sidewall medium is deposited in the transverse groove and etched to form the inner sidewall.

[0065] Specifically, isotropic etching (such as wet etching) is used to create a lateral recess in the channel sacrificial layer 701 relative to the channel layer 700, forming a controllable lateral groove. Then, an inner sidewall dielectric (such as silicon nitride or a low-dielectric-constant material) is deposited in the lateral groove and etched back to form the inner sidewall. The inner sidewall is mainly used to isolate the subsequently formed gate and source / drain regions 101 to prevent leakage.

[0066] Next, as Figure 7-8 As shown, the source and drain epitaxial regions of the first fin stack 500 and the second fin stack 600 are defined by photolithography, and the source and drain epitaxial regions at the ends of the channel layers 700 of the first fin stack 500 and the second fin stack 600 are respectively performed.

[0067] Specifically, different source / drain epitaxial regions are defined by photolithographic masks. Selective epitaxial technology is used to simultaneously grow source / drain regions 705 of the first conductivity type at the end of the exposed channel layer 700 of the first fin stack 500, and source / drain regions 706 of the second conductivity type at the end of the exposed channel layer 700 of the second fin stack 600, wherein the first conductivity type is opposite to the second conductivity type.

[0068] For example, SiGe semiconductor material or boron-doped SiGe (SiGe:B) semiconductor material is simultaneously grown at the end of the exposed channel layer 700 of the first fin stack 500 to serve as a P-type transistor; silicon semiconductor material or phosphorus-doped silicon (Si:P) semiconductor material is simultaneously grown at the end of the exposed channel layer 700 of the second fin stack 600 to serve as an N-type transistor; or, silicon semiconductor material or phosphorus-doped silicon (Si:P) semiconductor material is simultaneously grown at the end of the exposed channel layer 700 of the first fin stack 500 to serve as an N-type transistor; and SiGe semiconductor material or boron-doped SiGe (SiGe:B) semiconductor material is simultaneously grown at the end of the exposed channel layer 700 of the second fin stack 600 to serve as a P-type transistor.

[0069] In any transistor cell, the upper and lower transistors have the same conductivity type. Therefore, in the source-drain epitaxial step, the channel layer 700 ends of the upper and lower parts of the same transistor cell can be epitaxially grown simultaneously, which greatly simplifies the process and reduces manufacturing costs.

[0070] Next, as Figure 9-11 As shown, after the source / drain regions 101 at the ends of the channel layer 700 of the first fin stack 500 and the second fin stack 600 are formed, a first dielectric layer 707 is deposited on the surface of the exposed device, and the first dielectric layer 707 is etched back to remove the first dielectric layer 707 outside the contact position of the source / drain regions 101; further, a second dielectric layer 708 is deposited in the region outside the contact position of the source / drain regions 101.

[0071] In the process of forming contact holes, this invention utilizes the etching selectivity ratio between the first dielectric layer 707 and the second dielectric layer 708 to selectively remove the first dielectric layer 707 at the contact location of the source / drain region 101, while retaining the second dielectric layer 708 outside the contact location of the source / drain region 101. Therefore, the first dielectric layer 707 can be selectively removed, and the second dielectric layer 708 is relatively inert to the etchant, with a significant etching selectivity ratio between the two.

[0072] For example, the first dielectric layer 707 is SiO2 and the second dielectric layer 708 is Si3N4, or the first dielectric layer 707 is Si3N4 and the second dielectric layer 708 is SiO2.

[0073] Next, the sacrificial gate 704 and the channel sacrificial layer 701 are removed, and the channel layer 700 is released to form a gate trench.

[0074] Specifically, by utilizing the etching selectivity between the sacrificial gate 704 material and the surrounding material, the sacrificial gate 704 is precisely removed without damaging the sidewalls and the channel layer 700; by utilizing the high etching selectivity between SiGe and Si, the channel layer 700 is released, providing space for subsequent metal gate filling.

[0075] Next, as Figure 12 As shown, a gate dielectric layer 709 and a metal gate layer 710 are sequentially formed on the surface of the released nanowire / sheet stack.

[0076] Specifically, a replacement gate for the lower transistor is first formed. Then, the metal gate layer 710 of the lower transistor is etched back to the top of the lower transistor gate, and a dielectric layer is deposited in the groove formed by the etch-back. Further, the metal gate layer 710 of the upper transistor is formed around and above the upper nanowire / sheet stack. Since the top of the lower gate is covered by the dielectric layer, the upper gate metal gate layer 710 and the lower gate metal gate layer 710 are physically separated by the dielectric layer in the vertical direction, forming electrical isolation between them, thereby realizing a separate gate structure in which the upper gate and the lower gate are separated from each other.

[0077] Finally, as Figure 13 As shown, the first dielectric layer 707 at the contact position of the source / drain region 101 is selectively removed and filled with metal to form a common source or common drain connection contact 102 for two vertically adjacent transistors.

[0078] This completes the fabrication of the semiconductor device of the present invention.

[0079] It should be noted that the foregoing embodiments have described in detail the fabrication method of the same-polarity stacked semiconductor device of the present invention using CFET process as an example, but this does not constitute a limitation on the fabrication method of the present invention. Those skilled in the art should understand that the core of the present invention is to achieve the vertical integration of transistors of the same conductivity type through same-polarity stacking. Therefore, the same-polarity stacked semiconductor device and its fabrication method provided by the present invention are not limited to a specific three-dimensional stacking process. Any process capable of vertically stacking and integrating transistors of the same conductivity type to form a split gate structure, including but not limited to CFET process, Flip FET process, etc., falls within the protection scope of the present invention.

[0080] Fourthly, this embodiment provides an electronic device including the above-described transistor unit or semiconductor device, the electronic device including a smartphone, personal computer, tablet computer, artificial intelligence device, wearable device or power bank.

[0081] The beneficial effects of the fourth aspect and its various implementations in the embodiments of the present invention can be referred to the analysis of the beneficial effects of the first aspect and its various implementations, and will not be repeated here.

[0082] The above description does not provide detailed explanations of the technical aspects of each layer's patterning, etching, etc. However, those skilled in the art should understand that layers and regions of the desired shape can be formed using various technical means. Furthermore, to form the same structure, those skilled in the art can also design methods that are not entirely identical to those described above. Additionally, although various embodiments have been described above, this does not mean that the measures in the various embodiments cannot be effectively combined.

[0083] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the foregoing embodiments, or make equivalent substitutions for some or all of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A transistor unit, characterized in that, include: At least two transistors are stacked sequentially in a vertical direction, each transistor including a gate stack structure and source / drain regions located on both sides of the gate stack structure; All of the transistors have the same conductivity type, and a gate isolation structure is provided between the gate stack structures of adjacent transistors.

2. The transistor unit according to claim 1, characterized in that, All of the transistors mentioned are either P-type or N-type transistors.

3. The transistor unit according to claim 1, characterized in that, Either of the source or drain regions of two vertically adjacent transistors is electrically connected to each other, forming a common source or common drain connection contact.

4. The transistor unit according to claim 3, characterized in that, The common source or common drain connection contact penetrates at least one of the two vertically adjacent source and drain regions of the transistor and wraps at least a portion of the sidewalls of the source and drain regions.

5. The transistor unit according to claim 4, characterized in that, The common source or common drain connection contact extends between two vertically adjacent source and drain regions of the transistor, and the source and drain regions are entirely embedded in the common source or common drain connection contact.

6. The transistor unit according to claim 1, characterized in that, The transistors above the gate isolation structure and the transistors below the gate isolation structure are mirror-symmetrical about the central plane of the gate isolation structure.

7. The transistor unit according to claim 1, characterized in that, A mirror-symmetrical gate sidewall structure is provided above the uppermost channel of the transistor above the gate isolation structure and below the lowermost channel of the transistor below the gate isolation structure.

8. A semiconductor device, characterized in that, Including substrate, The first transistor unit and the second transistor unit are disposed adjacent to each other in the horizontal direction on the substrate, and both the first transistor unit and the second transistor unit are transistor units as described in any one of claims 1-7. The first transistor unit has the opposite conductivity type to the second transistor unit.

9. The semiconductor device according to claim 8, characterized in that, The first transistor unit and the second transistor unit have the same number of vertical stacking layers, and in any vertical stacking level, the gate stacking structure of the transistor in the first transistor unit is interconnected with the gate stacking structure of the transistor in the second transistor unit.

10. The semiconductor device according to claim 8, characterized in that, In any vertical stacking level, the transistors in the first transistor unit and the transistors in the second transistor unit form a set of inverter units.

11. The semiconductor device according to claim 8, characterized in that, In the inverter unit, The gate stacking structure of the transistors in the first transistor unit is interconnected with the gate stacking structure of the transistors in the second transistor unit to form the input terminal of the inverter unit; The drain contact portion of the transistor in the first transistor unit is connected to the drain contact portion of the transistor in the second transistor unit to form the output terminal of the inverter unit.

12. The semiconductor device according to claim 8, characterized in that, The semiconductor device includes a first inverter unit and a second inverter unit arranged back to back; In the first inverter unit and the second inverter unit, the source region contact portions of the transistors located in different vertical stacking levels are connected respectively, and form a common power supply terminal lead-out node and a ground terminal lead-out node respectively.

13. A method for manufacturing a semiconductor device, characterized in that, Includes the following steps: Provide substrate; A first fin stack and a second fin stack are formed on the substrate in a horizontally parallel and spaced-apart manner. The first fin stack and the second fin stack are each formed by alternating stacking of a channel layer and a channel sacrificial layer. The first fin stack and the second fin stack also include an isolation sacrificial layer, which divides the first fin stack and the second fin stack into at least an upper part and a lower part, respectively. A sacrificial gate and sidewalls are formed above the first fin stack and the second fin stack; Using the sacrificial gate and the sidewall as masks, anisotropic etching is performed on the upper and lower parts of the first fin stack and the second fin stack to remove the fin stack portion located in the source and drain regions and expose the ends of each level of channel layer; Source / drain regions are epitaxially formed at the ends of the channel layers of the first fin stack and the second fin stack, respectively. Specifically, source / drain regions of a first conductivity type are formed by epitaxially forming the ends of the channel layers of the first fin stack, and source / drain regions of a second conductivity type are formed by epitaxially forming the ends of the channel layers of the second fin stack. The first conductivity type is different from the second conductivity type. Remove the sacrificial gate and the channel sacrificial layer, and release the channel layer to form a gate trench; An alternative gate structure is formed in the gate trench, and the alternative gate structures are isolated from each other by dielectric material between different vertical layers.

14. The manufacturing method according to claim 13, characterized in that, The epitaxial growth of the source / drain regions at the ends of the channel layers of the first fin stack and the second fin stack, respectively, includes: Source and drain regions of the first conductivity type are synchronously epitaxially formed at the ends of the top and bottom channel layers of the first fin stack; The source and drain regions of the second conductivity type are synchronously epitaxially formed at the ends of the top and bottom channel layers of the second fin stack.

15. The manufacturing method according to claim 13, characterized in that, After epitaxially extending the source / drain regions at the ends of the channel layers of the first fin stack and the second fin stack, respectively, the method further includes: A first dielectric layer is deposited on the surface of the exposed device, and the first dielectric layer is etched back to remove the first dielectric layer outside the source / drain contact location; A second dielectric layer is deposited in the region outside the source / drain contact area, and the material of the second dielectric layer is different from that of the first dielectric layer. The first dielectric layer at the contact location of the source-drain region is selectively removed and filled with metal to form a common source or common drain connection contact between two vertically adjacent transistor source-drain regions.

16. An electronic device, characterized in that, It includes one or more transistor units as described in any one of claims 1-7 or semiconductor devices as described in any one of claims 8-12; Electronic devices include smartphones, personal computers, tablets, artificial intelligence devices, wearable devices, or power banks.

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