Semiconductor device and method of manufacturing the same

Abstract

The present disclosure provides a semiconductor device and a preparation method thereof, and relates to the technical field of semiconductor chips, and aims to improve the performance of the semiconductor device. The semiconductor device comprises a substrate, a plurality of transistors, a first dielectric layer and an insulating structure. The plurality of transistors comprises a first transistor and a second transistor arranged side by side, and at least one of the first transistor and the second transistor is an N-type transistor. A gate dielectric layer covers a channel, and a gate electrode is arranged on a side of the gate dielectric layer away from the substrate. The first dielectric layer is arranged on a side of a plane where the gate electrode of the N-type transistor is away from the substrate, and has a spacing between the first dielectric layer and the gate electrode of the N-type transistor. In the thickness direction of the substrate, the first dielectric layer at least partially overlaps the channel of the N-type transistor. The insulating structure is arranged at least in the region between the plurality of transistors and the region between the first dielectric layer and the gate electrode of the N-type transistor. The above semiconductor device is applied to a memory to realize data reading and writing operations.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor chip technology, and in particular to a semiconductor device and its fabrication method. Background Technology

[0002] As the feature size of memory cells approaches the lower limit of process technology, planar processes and manufacturing technologies become challenging and costly, causing the storage density of 2D or planar NAND flash memory to approach its upper limit. To overcome the limitations of 2D or planar NAND flash memory, the industry has developed memory with a three-dimensional structure (3D NAND), which increases storage density by arranging memory cells three-dimensionally on a substrate.

[0003] As memory integration density increases, the distance between transistors in memory becomes closer and closer. Stress memorization technique (SMT) cannot be reasonably applied to N-type transistors in memory, and cannot improve the performance of N-type transistors, thus leading to a decline in memory performance. Summary of the Invention

[0004] On one hand, a semiconductor structure is provided. The semiconductor structure includes a substrate, a plurality of transistors, a first dielectric layer, and an insulating structure. The plurality of transistors includes a first transistor and a second transistor arranged side-by-side, at least one of the first transistor and the second transistor being an N-type transistor. Each transistor includes a channel, a source, a drain, a gate, and a gate dielectric layer. The channel, the source, and the drain are embedded in the substrate and exposed on a first surface of the substrate, with the channel located between the source and the drain. The first surface is one of two opposing main surfaces of the substrate. The gate dielectric layer covers the channel, and the gate is disposed on a side of the gate dielectric layer away from the substrate. The first dielectric layer is disposed on a side of the plane containing the gate of the N-type transistor away from the substrate and has a spacing between it and the gate of the N-type transistor. In the thickness direction of the substrate, the first dielectric layer at least partially overlaps the channel of the N-type transistor. The insulating structure is disposed at least in the region between the plurality of transistors and in the region between the first dielectric layer and the gate of the N-type transistor.

[0005] In some embodiments, the surface of the first dielectric layer away from and / or close to the substrate is parallel to the surface of the substrate away from the insulating structure.

[0006] In some embodiments, in the thickness direction of the substrate, the first dielectric layer covers the channel, source, and drain of the N-type transistor.

[0007] In some embodiments, the semiconductor device further includes a first contact plug, a second contact plug, and a third contact plug. The first contact plug penetrates the insulating structure and the first dielectric layer and makes electrical contact with the source of the N-type transistor. The second contact plug penetrates the insulating structure and the first dielectric layer and makes electrical contact with the drain of the N-type transistor. The third contact plug penetrates the insulating structure and the first dielectric layer and makes electrical contact with the gate of the N-type transistor.

[0008] In some embodiments, the insulating structure further covers the first dielectric layer, and the first contact plug, the second contact plug, and the third contact plug penetrate the portion of the first dielectric layer, with the insulating structure provided between them and the first dielectric layer.

[0009] In some embodiments, the first transistor is an N-type transistor and the second transistor is a P-type transistor. In the thickness direction of the substrate, the first dielectric layer does not overlap with the channel, source, and drain of the P-type transistor.

[0010] In some embodiments, the semiconductor device further includes a fourth contact plug, a fifth contact plug, and a sixth contact plug. The fourth contact plug penetrates the insulating structure and makes an electrical contact with the source of the P-type transistor. The fifth contact plug penetrates the insulating structure and makes an electrical contact with the drain of the P-type transistor. The sixth contact plug penetrates the insulating structure and makes an electrical contact with the gate of the P-type transistor.

[0011] In some embodiments, the insulating structure includes an isolation structure, a first interlayer dielectric layer, and a second interlayer dielectric layer. The isolation structure extends from a first surface of the substrate into the substrate and is located between two adjacent transistors. The first interlayer dielectric layer includes a first portion and a second portion, the first portion filling the region between the plurality of transistors, and the second portion located between the plane containing the first dielectric layer and the plane containing the gate of the transistor. The second interlayer dielectric layer is disposed on the side of the first interlayer dielectric layer away from the substrate and covers the first dielectric layer.

[0012] In some embodiments, the spacing between the gates of two adjacent transistors is less than or equal to 120 nm.

[0013] In some embodiments, the tensile stress of the first dielectric layer is configured to be 700 MPa to 1600 MPa.

[0014] In some embodiments, the transistor further includes a source extension portion, a drain extension portion, and a package structure. The source extension portion is located between the source and the channel. Both the source extension portion and the source include doped ions, and the concentration of doped ions in the source extension portion is less than the concentration of doped ions in the source. The drain extension portion is located between the drain and the channel. Both the drain extension portion and the drain include doped ions, and the concentration of doped ions in the drain extension portion is less than the concentration of doped ions in the drain. The package structure covers the source extension portion and the drain extension portion, and encapsulates the gate and the gate dielectric layer of the transistor. An insulating structure encapsulates the package structure.

[0015] In some embodiments, the material of the first dielectric layer includes silicon nitride; and / or, the material of the insulating structure includes silicon oxide.

[0016] On the other hand, a storage system is provided. The storage system includes a controller and a semiconductor device as described in some of the embodiments above, the controller being coupled to the semiconductor device to control the semiconductor device to store data.

[0017] In another aspect, a method for fabricating a semiconductor device is provided. The method includes: forming a plurality of transistors on a substrate. The plurality of transistors includes a first transistor and a second transistor arranged side-by-side, at least one of the first transistor and the second transistor being an N-type transistor. Each transistor includes a channel, a source, a drain, a gate, and a gate dielectric layer. The channel, the source, and the drain are embedded in the substrate and exposed on a first surface of the substrate. The first surface is one of two opposing main surfaces of the substrate. The gate dielectric layer covers the channel, and the gate is disposed on the side of the gate dielectric layer away from the substrate. A first interlayer dielectric layer is formed. The first interlayer dielectric layer includes a first portion and a second portion, the first portion being located in a region between the plurality of transistors, and the second portion being located on the side of the plane containing the gate of the transistor away from the substrate. A first dielectric layer is formed. The first dielectric layer is disposed on the side of the first interlayer dielectric layer away from the substrate. In the thickness direction of the substrate, the first dielectric layer at least partially overlaps with the channel of the N-type transistor.

[0018] In some embodiments, forming the first interlayer dielectric layer includes forming a first dielectric film. The first dielectric film covers the plurality of transistors and fills the region between the plurality of transistors, and the surface of the first dielectric film away from the substrate has an uneven morphology. The surface of the first dielectric film away from the substrate is planarized.

[0019] In some embodiments, the first transistor is an N-type transistor and the second transistor is a P-type transistor. Forming the first dielectric layer includes: forming a tensile stress film. The tensile stress film is disposed on the side of the first interlayer dielectric layer away from the substrate, and in the thickness direction of the substrate, the tensile stress film covers both the N-type transistor and the P-type transistor. The portion of the tensile stress film covering the P-type transistor is removed, and the semiconductor device is annealed.

[0020] In some embodiments, after forming the first dielectric layer, the method further includes forming a second interlayer dielectric layer. The second interlayer dielectric layer is disposed on the side of the first interlayer dielectric layer away from the substrate and covers the first dielectric layer. A first contact plug, a second contact plug, a third contact plug, a fourth contact plug, a fifth contact plug, and a sixth contact plug are formed. The first contact plug penetrates the first interlayer dielectric layer, the second interlayer dielectric layer, and the first dielectric layer, and is in electrical contact with the source of the N-type transistor. The second contact plug penetrates the first interlayer dielectric layer, the second interlayer dielectric layer, and the first dielectric layer, and is in electrical contact with the drain of the N-type transistor. The third contact plug penetrates the first interlayer dielectric layer, the second interlayer dielectric layer, and the first dielectric layer, and is in electrical contact with the gate of the N-type transistor. The fourth contact plug penetrates the first interlayer dielectric layer and the second interlayer dielectric layer, and is in electrical contact with the source of the P-type transistor. The fifth contact plug penetrates the first interlayer dielectric layer and the second interlayer dielectric layer, and is in electrical contact with the drain of the P-type transistor; the sixth contact plug penetrates the first interlayer dielectric layer and the second interlayer dielectric layer, and is in electrical contact with the gate of the P-type transistor.

[0021] In some embodiments, prior to forming the second interlayer dielectric layer, the method further includes: etching the first dielectric layer to form a first via, a second via, and a third via. During the formation of the second interlayer dielectric layer, the second interlayer dielectric layer fills the first via, the second via, and the third via. During the formation of the first contact plug, the second contact plug, the third contact plug, the fourth contact plug, the fifth contact plug, and the sixth contact plug, the first contact plug passes through the first via, the second contact plug passes through the second via, and the third contact plug passes through the third via.

[0022] In some embodiments, prior to forming the plurality of transistors on the substrate, the method further includes forming an isolation structure on the substrate. The isolation structure extends from a first surface of the substrate into the substrate and is located between two adjacent transistors. Attached Figure Description

[0023] To more clearly illustrate the technical solutions in this disclosure, the accompanying drawings used in some embodiments of this disclosure will be briefly described below. Obviously, the drawings described below are only drawings of some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings. In addition, the drawings described below can be regarded as schematic diagrams and are not intended to limit the actual size of the product, the actual flow of the method, the actual timing of the signals, etc. involved in the embodiments of this disclosure.

[0024] Figure 1 A block diagram of an electronic device according to some embodiments;

[0025] Figure 2 This is a three-dimensional structural diagram of a memory according to some embodiments;

[0026] Figure 3 A cross-sectional view of a memory according to some embodiments;

[0027] Figure 4 for Figure 2 The equivalent circuit diagram of a string of memory cells shown;

[0028] Figure 5 This is a structural diagram of a semiconductor device according to some embodiments;

[0029] Figure 6 This is a flowchart of a method for fabricating a semiconductor device according to some embodiments;

[0030] Figure 7 This is a diagram illustrating the fabrication steps of a semiconductor device fabrication method according to some embodiments;

[0031] Figure 8 This is a flowchart of a method for fabricating a semiconductor device according to some embodiments;

[0032] Figure 9 This is a diagram illustrating the fabrication steps of a semiconductor device fabrication method according to some embodiments;

[0033] Figure 10 This is a diagram illustrating the fabrication steps of a semiconductor device fabrication method according to some embodiments;

[0034] Figure 11 This is a flowchart of a method for fabricating a semiconductor device according to some embodiments;

[0035] Figure 12 This is a diagram illustrating the fabrication steps of a semiconductor device fabrication method according to some embodiments;

[0036] Figure 13This is a diagram illustrating the fabrication steps of a semiconductor device fabrication method according to some embodiments;

[0037] Figure 14 This is a diagram illustrating the fabrication steps of a semiconductor device fabrication method according to some embodiments;

[0038] Figure 15 This is a flowchart of a method for fabricating a semiconductor device according to some embodiments;

[0039] Figure 16 This is a flowchart of a method for fabricating a semiconductor device according to some embodiments;

[0040] Figure 17 This is a diagram illustrating the fabrication steps of a semiconductor device fabrication method according to some embodiments;

[0041] Figure 18 This is a diagram illustrating the fabrication steps of a semiconductor device fabrication method according to some embodiments;

[0042] Figure 19 This is a flowchart of a method for fabricating a semiconductor device according to some embodiments;

[0043] Figure 20 This diagram illustrates the fabrication steps of a semiconductor device fabrication method according to some embodiments. Detailed Implementation

[0044] The technical solutions in some embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments provided in this disclosure are within the scope of protection of this disclosure.

[0045] In the description of this disclosure, it should be understood that the terms “center,” “upper,” “lower,” “front,” “rear,” “left,” “right,” “vertical,” “horizontal,” “top,” “bottom,” “inner,” and “outer,” etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing this disclosure and simplifying the description, and are not intended to indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this disclosure.

[0046] Unless the context otherwise requires, throughout the specification and claims, the term "comprising" is interpreted as open-ended and encompassing, meaning "including, but not limited to." In the description of the specification, terms such as "one embodiment," "some embodiments," "exemplary embodiment," "exemplary," or "some examples" are intended to indicate that a particular feature, structure, material, or characteristic associated with that embodiment or example is included in at least one embodiment or example of this disclosure. The illustrative representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics mentioned may be included in any suitable manner in any one or more embodiments or examples.

[0047] Hereinafter, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of embodiments of this disclosure, unless otherwise stated, "a plurality of" means two or more.

[0048] In describing some embodiments, the terms "coupled" and "connected," and their derivative expressions, may be used. For example, the term "connected" may be used in describing some embodiments to indicate that two or more components have direct physical or electrical contact with each other. Similarly, the term "coupled" may be used in describing some embodiments to indicate that two or more components have direct physical or electrical contact. However, the term "coupled" may also refer to two or more components that do not have direct contact with each other but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the content of this document.

[0049] "At least one of A, B and C" has the same meaning as "at least one of A, B or C", both including the following combinations of A, B and C: only A, only B, only C, combinations of A and B, combinations of A and C, combinations of B and C, and combinations of A, B and C.

[0050] "A and / or B" includes the following three combinations: A only, B only, and a combination of A and B.

[0051] In this disclosure, the meanings of “on,” “above,” and “above” should be interpreted in the broadest possible sense, such that “on” means not only “directly on” something, but also includes “on” something with intermediate features or layers in between, and “above” or “above” means not only “above” or “above” something, but also “above” or “above” something without intermediate features or layers in between (i.e., directly on something).

[0052] This document describes exemplary embodiments with reference to cross-sectional views and / or plan views, which are idealized exemplary drawings. In the drawings, the thickness of layers and regions is enlarged for clarity. Therefore, variations in shape relative to the drawings are contemplated due to, for example, manufacturing techniques and / or tolerances. Thus, exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing processes. For example, etched regions shown as rectangular would typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to show the actual shapes of the regions of the device, nor are they intended to limit the scope of the exemplary embodiments.

[0053] As used herein, the term "substrate" refers to a material on which subsequent material layers can be added. The substrate itself may be patterned. The material added to the substrate may be patterned or may remain unpatterned. Furthermore, the substrate may include a variety of semiconductor materials such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate may be made of a non-conductive material such as glass, plastic, or sapphire wafer.

[0054] The term "three-dimensional memory" refers to a semiconductor device formed by strings of memory cell transistors (referred to herein as "memory cell strings," such as NAND memory cell strings) arranged in an array on the main surface of a substrate and extending in a direction perpendicular to the substrate. As used herein, the term "perpendicularly" means nominally perpendicular to the main surface of the substrate (i.e., the lateral surface).

[0055] Figure 1 This is a block diagram of an electronic device according to some embodiments. For example... Figure 1 As shown, electronic device 1000 can be a mobile phone, desktop computer, laptop computer, tablet computer, vehicle computer, game console, printer, positioning device, wearable electronic device (e.g., smartwatch, smart bracelet, smart glasses, etc.), smart sensor, virtual reality (VR) device, augmented reality (AR) device, or any other suitable electronic device having storage therein.

[0056] In some embodiments, see Figure 1 The electronic device 1000 includes a processor 100 and a storage system 200, which are connected. The processor 100 can send data to or receive data from the storage system 200.

[0057] Please continue reading. Figure 1The processor 100 may include any one of a central processing unit (CPU), a system-on-chip (SoC), and an application processor (AP).

[0058] Please continue reading. Figure 1 The storage system 200 can be integrated into various types of storage devices, such as memory cards. These memory cards include any of the following: PC cards (PCMCIA, Personal Computer Memory Card International Association), compact flash (CF) cards, smart media (SM) cards, memory sticks, multimedia cards (MMC), secure digital memory cards (SD cards), and universal flash storage (UFS). In other words, the storage system 200 can be applied to and packaged into different types of electronic products.

[0059] Please continue reading. Figure 1 The storage system 200 may include one or more semiconductor devices 10 and a controller 20. Figure 1 The storage system 200 is illustrated by an example comprising three semiconductor devices 10. These semiconductor devices 10 can be, for example, a memory or peripheral circuitry of a memory. Specifically, the semiconductor device 10 can be any semiconductor device 10 with data processing (write, read, or erase) functions, such as dynamic random access memory (DRAM), non-volatile memory (NAND flash), static random access memory (SRAM), or erasable programmable read-only memory (EPROM).

[0060] The controller 20 can be configured to operate in a low duty cycle environment, such as with SD cards, CF cards, Universal Serial Bus (USB) flash drives, or other media used in electronic devices such as personal calculators, digital cameras, and mobile phones. Alternatively, the controller 20 can be configured to operate in a high duty cycle environment with SSDs or eMMC, which are used as data storage in mobile devices such as smartphones, tablets, and laptops, as well as in enterprise storage arrays. Alternatively, the controller 20 can be coupled to the semiconductor device 10 and the processor 100, and configured to control data in the semiconductor device 10 while also communicating with external devices (such as the processor 100).

[0061] Furthermore, controller 20 can manage the data stored in each semiconductor device 10 and communicate with processor 100. Controller 20 can be configured to control the operation of each semiconductor device 10, such as read, write, and refresh operations. Controller 20 can also be configured to manage various functions related to data stored or to be stored in each semiconductor device 10, including but not limited to refresh and timing control, command / request translation, buffering and scheduling, and power management.

[0062] In some implementations, controller 20 is also configured to determine the maximum memory capacity available to the computer system, the number of memory banks, memory type and speed, memory particle data depth and data width, and other important parameters. Controller 20 may also perform any other suitable functions. Controller 20 may communicate with external devices (e.g., processor 100) according to a specific communication protocol. For example, controller 20 may communicate with external devices via at least one of various interface protocols, such as USB, MMC, Peripheral Component Interconnect (PCI), PCI-E, Advanced Technology Attachment (ATA), Serial ATA, Parallel ATA, Small Computer Small Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronics (IDE), FireWire, etc.

[0063] Figure 2 This is a three-dimensional structural diagram of a memory according to some embodiments. Figure 3 This is a cross-sectional view of a memory according to some embodiments. Figure 4 for Figure 2 The diagram shows the equivalent circuit diagram of a string of memory cells.

[0064] like Figure 2 and Figure 3 As shown, the memory 300 includes a semiconductor structure 400 and peripheral devices 500 for controlling the semiconductor structure 400. The semiconductor structure 400 is connected to the peripheral devices 500 to enable the peripheral devices 500 to support the functions of the semiconductor structure 400, such as reading, writing and erasing data in the memory cells.

[0065] Please continue reading. Figure 2 and Figure 3 The memory 300 may also include a source layer SL, which is disposed on the side of the semiconductor structure 400 away from the peripheral device 500 and coupled to the semiconductor structure 400.

[0066] The material of the source layer SL can include semiconductor materials, such as single-crystal silicon, polycrystalline silicon, single-crystal germanium, III-V compound semiconductor materials, II-VI compound semiconductor materials, and other suitable semiconductor materials. The source layer SL can be partially or completely doped. For example, the source layer SL can include doped regions doped with p-type dopant. The source layer SL can also include undoped regions.

[0067] Combination Figure 2 , Figure 3 and Figure 4 The semiconductor structure 400 may include a memory stack layer 410, which includes arrayed memory cell strings 40 (such as NAND memory cell strings). A source layer SL may be coupled to the source terminals of multiple memory cell strings 40. Each memory cell string 40 may include multiple memory transistors T connected in series. Each memory transistor T (e.g., each memory transistor T) may be formed by a semiconductor channel 50 and a gate line G surrounding the semiconductor channel 50. The gate line G is configured to control the on-state of the memory transistor T.

[0068] Please continue reading. Figure 2 , Figure 3 and Figure 4Along the third direction Z, the lowermost gate line among the multiple gate lines G (e.g., the gate line closest to the source layer SL among the multiple gate lines G) is constructed as a source select gate SGS. The source select gate SGS is configured to control the conduction state of the storage transistor T6, thereby controlling the conduction state of the source channel in the memory cell string 40. The uppermost gate line among the multiple gate lines G (e.g., the gate line furthest from the source layer SL among the multiple gate lines G) is constructed as a drain select gate SGD. The drain select gate SGD is configured to control the conduction state of the storage transistor T1, thereby controlling the conduction state of the drain channel in the memory cell string 40. The middle gate line among the multiple gate lines G can be constructed as multiple word lines WL, such as word lines WL0, WL1, WL2, and WL3. By writing different voltages on the word lines WL, data writing, reading, and erasing of each memory cell in the memory cell string 40 can be completed.

[0069] Figure 2 , Figure 3 and Figure 4 The number of storage transistors is merely illustrative. The memory cell string provided in the embodiments of this disclosure may also include other numbers of transistors, such as 4, 16, 32, or 64.

[0070] The aforementioned memory 300 extends in the XY plane. The first direction X and the second direction Y are, for example, two orthogonal directions in the plane where the semiconductor structure 400 is located (e.g., the plane where the source layer SL is located): the first direction X is, for example, the extension direction of the word line WL, and the second direction Y is, for example, the extension direction of the bit line BL. The third direction Z is perpendicular to the plane where the semiconductor structure 400 is located, that is, perpendicular to the XY plane.

[0071] Please continue reading. Figure 3 Peripheral device 500 includes peripheral circuitry (also known as control and sensing circuitry), which may include any suitable digital, analog, and / or mixed-signal circuitry for facilitating the operation of semiconductor structure 400. For example, peripheral circuitry may include page buffers, decoders (e.g., row decoders and column decoders), sense amplifiers, drivers (e.g., word line drivers), input / output (I / O) circuitry, charge pumps, voltage sources or generators, current or voltage references, any portion of the aforementioned functional circuitry (e.g., sub-circuits), or one or more of any active or passive components of the circuitry (e.g., transistors, diodes, resistors, or capacitors).

[0072] For example, the peripheral circuitry can use complementary metal-oxide-semiconductor (CMOS) technology, which can be implemented using logic processes (e.g., technology nodes such as 90nm, 65nm, 60nm, 45nm, 32nm, 28nm, 22nm, 20nm, 16nm, 14nm, 10nm, 7nm, 5nm, 3nm, 2nm, etc.).

[0073] The semiconductor structure 400 and the peripheral device 500 can be arranged side by side in the same plane, for example, on the same wafer. Alternatively, the semiconductor structure 400 and the peripheral device 500 can be formed on different wafers and bonded together face to face.

[0074] Please continue reading. Figure 3 When the semiconductor structure 400 and peripheral devices 500 are formed on different wafers and bonded together face-to-face, a large number of interconnects (e.g., bonding contacts) are formed between the semiconductor structure 400 and peripheral devices 500 through bonding interfaces. Direct, short-distance (e.g., micrometer-level) electrical connections are established between the semiconductor structure 400 and peripheral devices 500, instead of long-distance (e.g., millimeter- or centimeter-level) chip-to-chip data buses on a circuit board (e.g., a printed circuit board, PCB). This eliminates chip interface latency and achieves high-speed I / O throughput with reduced power consumption. Data transfer between the semiconductor structure 400 and peripheral devices 500 can be performed through the interconnects (e.g., bonding contacts) of the bonding interfaces. Thus, by vertically integrating the semiconductor structure 400 and peripheral devices 500, the size of the memory 300 can be reduced, and the storage density of the memory 300 can be increased.

[0075] For example, see Figure 3 The semiconductor structure 400 may also include an array interconnect layer 420, which may be coupled to the memory cell string 40 to enable the transmission of electrical signals between the array interconnect layer 420 and the memory cell string 40.

[0076] The array interconnect layer 420 may include the drain (i.e., bit line BL) of the memory cell string 40, which may be coupled to the semiconductor channel 50 of each memory transistor T in at least one memory cell string 40. The array interconnect layer 420 may include one or more first interlayer insulating layers 421, and may also include a plurality of contacts insulated from each other by these first interlayer insulating layers 421. The contacts may include, for example, bit line contacts BL-CNT coupled to the bit line BL, and drain select gate contacts SGD-CNT coupled to the drain select gate SGD. The array interconnect layer 420 may also include one or more first interconnect conductor layers 422. The first interconnect conductor layer 422 may include multiple connection lines, such as bit lines BL, and word line connection lines WL-CL coupled to word lines WL. The materials of the first interconnect conductor layer 422 and the contacts may be conductive materials, such as one or more combinations of tungsten, cobalt, copper, aluminum, and metal silicides, or other suitable materials; the embodiments disclosed herein are not limited thereto. The material of the first interlayer insulation layer 421 includes an insulating material, such as one or more combinations of silicon oxide, silicon nitride, and high dielectric constant insulating materials, or other suitable materials, and the embodiments disclosed herein are not limited thereto.

[0077] Please continue reading. Figure 3 The peripheral device 500 may include a substrate 510, a peripheral transistor 60 disposed on the substrate 510, and a peripheral interconnect layer 520 disposed on the substrate 510. The peripheral interconnect layer 520 is coupled to the peripheral transistor 60 to realize the transmission of electrical signals between the peripheral transistor 60 and the peripheral interconnect layer 520. The substrate 510 may be made of single-crystal silicon or other suitable materials, such as silicon-germanium, germanium, or silicon-on-insulator thin film.

[0078] The peripheral interconnect layer 520 may include one or more second interlayer insulating layers 521, and may also include one or more second interconnect conductor layers 522. Different second interconnect conductor layers 522 may be coupled to each other via contacts. The materials of the second interconnect conductor layers 522 and the contacts may be conductive materials, such as tungsten, cobalt, copper, aluminum, and combinations of one or more metal silicides, or other suitable materials, as not limited to these in this disclosure. The material of the second interlayer insulating layer 521 includes insulating materials, such as silicon oxide, silicon nitride, and combinations of one or more high-dielectric-constant insulating materials, or other suitable materials, as not limited to these in this disclosure.

[0079] Please continue reading. Figure 3The peripheral interconnect layer 520 can be coupled to the array interconnect layer 420, enabling the semiconductor structure 400 and the peripheral device 500 to be coupled. Since the peripheral interconnect layer 520 is coupled to the array interconnect layer 420, the peripheral circuits in the peripheral device 500 can be coupled to the memory cell string 40 in the semiconductor structure 400 to realize the transmission of electrical signals between the peripheral circuits and the memory cell string.

[0080] However, as memory integration density increases, the distance between transistors in peripheral devices becomes closer and closer. During the formation of high-stress film layers using surface mount technology (SMT), the high-stress film layer fills the area between the gates of adjacent transistors due to the close proximity of their gates. The portion of the high-stress film layer between the transistor gates has a larger film thickness, causing more hydrogen atoms in the high-stress film layer to diffuse into the channel of the N-type transistor, resulting in a decrease in the performance of the N-type transistor. This prevents the performance of the N-type transistor from being improved, thus leading to a decrease in memory performance.

[0081] See Figure 3 The semiconductor device 10 provided in some embodiments of this disclosure can be used to construct peripheral devices 500 in memory 300. For example, semiconductor device 10 is peripheral device 500, or semiconductor device 10 is memory 300 including peripheral devices 500. The embodiments of this disclosure are not specifically limited herein.

[0082] Figure 5 This is a structural diagram of a semiconductor device according to some embodiments. Figure 5 As shown, the semiconductor device 10 includes a substrate 110, a plurality of transistors 120, a first dielectric layer 130, and an insulating structure 140.

[0083] The substrate 110 can be made of single-crystal silicon or other suitable materials, such as silicon-germanium, germanium, or silicon-on-insulator thin film.

[0084] Please continue reading. Figure 5 The plurality of transistors 120 include a first transistor 121 and a second transistor 122 arranged side by side, wherein at least one of the first transistor 121 and the second transistor 122 is an N-type transistor. For example, the first transistor 121 and the second transistor 122 are both N-type transistors, or the first transistor 121 is a P-type transistor and the second transistor 122 is an N-type transistor, or the first transistor 121 is an N-type transistor and the second transistor 122 is a P-type transistor. Figure 5 The diagram illustrates the case with the first transistor 121 being a P-type transistor and the second transistor 122 being an N-type transistor.

[0085] The transistor 120 includes a channel 101, a source 102, a drain 103, a gate 104, and a gate dielectric layer 105. The channel 101, source 102, and drain 103 are embedded in the substrate 110 and exposed on a first surface of the substrate 110, with the channel 101 located between the source 102 and the drain 103. The first surface is one of two opposing main surfaces of the substrate 110. The gate dielectric layer 105 covers the channel 101, and the gate 104 is disposed on the side of the gate dielectric layer 105 away from the substrate 110.

[0086] Furthermore, the spacing between the gates 104 of two adjacent transistors 120 is less than or equal to 120 nm. For example, the spacing between the gates 104 of the first transistor 121 and the gates 104 of the second transistor 122 arranged side by side is less than or equal to 120 nm, resulting in a high degree of integration of the semiconductor device 10.

[0087] Please continue reading. Figure 5 A first dielectric layer 130 is disposed on the side of the plane containing the gate 104 of the N-type transistor away from the substrate 110, and is spaced apart from the gate 104 of the N-type transistor. In the thickness direction (e.g., the third direction Z) of the substrate 110, the first dielectric layer 130 at least partially overlaps with the channel 101 of the N-type transistor. The first dielectric layer 130 has tensile stress to maintain the channel 101 of the N-type transistor in a tensile stress state along the channel 101 direction, thereby changing the band structure of the channel 101 and improving the performance of the N-type transistor, such as accelerating electron mobility, increasing drive current, and reducing leakage current. The tensile stress of the first dielectric layer 130 can be configured, for example, from 700 MPa to 1600 MPa, such as any one of 700 MPa, 750 MPa, 800 MPa, 850 MPa, 900 MPa, 950 MPa, 1000 MPa, 1100 MPa, 1200 MPa, 1300 MPa, 1400 MPa, 1500 MPa and 1600 MPa.

[0088] The material of the first dielectric layer 130 mentioned above includes silicon nitride. In the preparation of the first dielectric layer 130, plasma-enhanced chemical vapor deposition can be used, with silane as the silicon source and ammonia as the nitrogen source. In this process, because the Si-H bonds in the silane and the NH bonds in the ammonia do not completely break during the reaction, some hydrogen atoms will remain in the generated first dielectric layer 130, meaning the first dielectric layer 130 includes hydrogen atoms.

[0089] Please continue reading. Figure 5An insulating structure 140 is disposed at least in the region between the plurality of transistors 120 and in the region between the first dielectric layer 130 and the gate 104 of the N-type transistor 120 to fill the region between the plurality of transistors 120. For example, the insulating structure 140 fills the region between the plurality of transistors 120 and the region between the first dielectric layer 130 and the gate 104 of the N-type transistor 120.

[0090] In this configuration, the first dielectric layer 130 is located on the side of the plane where the gate 104 of the N-type transistor is located, away from the substrate 110. The insulating structure 140 can fill the area between the multiple transistors 120, so that the first dielectric layer 130 will not be deposited between the multiple transistors 120. The distance between the first dielectric layer 130 and the channel 101 of the transistor 120 is relatively large, which can reduce the hydrogen atoms diffusing into the channel 101 of the N-type transistor. This solves the technical problem in the related art that the high-stress film layer cannot improve the performance of the N-type transistor, resulting in a decrease in the performance of the memory 300.

[0091] Furthermore, the insulating structure 140 can fill the area between the multiple transistors 120, preventing the first dielectric layer 130 from depositing between the transistors 120, and the thickness of the first dielectric layer 130 can be set to be relatively uniform. For example, the first dielectric layer 130 is located away from and / or close to the surface of the substrate 110, parallel to the surface of the substrate 110 away from the insulating structure 140. This avoids uneven tensile stress distribution caused by excessive local thickness of the first dielectric layer 130, which would prevent the controllability of the tensile stress on the channel 101 of the N-type transistor. In other words, the thickness of the first dielectric layer 130 is uniform, the tensile stress distribution is uniform, and the tensile stress of the first dielectric layer 130 is easy to configure. In this case, by adjusting the tensile stress of the first dielectric layer 130, the tensile stress on the channel 101 of the N-type transistor can be changed, thereby adjusting the band structure of the channel 101 and improving the performance of the N-type transistor.

[0092] The following describes some embodiments of this disclosure by taking the first transistor 121 as a P-type transistor and the second transistor 122 as an N-type transistor as an example. However, the implementation of this disclosure is not limited to this, and the first transistor 121 can also be an N-type transistor, as long as the same technical concept is applied.

[0093] In some embodiments, see Figure 5 In the thickness direction (e.g., the third direction Z) of the substrate 110, the first dielectric layer 130 covers the channel 101, source 102 and drain 103 of the N-type transistor. In this way, the entire source 102 and drain 103 can participate in the stress transfer process, so that the channel 101 maintains an effective tensile stress state along the channel direction, thereby improving the performance of the N-type transistor.

[0094] Based on this, such as Figure 5 As shown, the semiconductor device 10 further includes a first contact plug 151, a second contact plug 152, and a third contact plug 153. The first contact plug 151 penetrates the insulating structure 140 and the first dielectric layer 130, and makes electrical contact with the source 102 of the N-type transistor, thereby connecting the source 102 of the N-type transistor to the peripheral interconnect layer 520. The second contact plug 152 penetrates the insulating structure 140 and the first dielectric layer 130, and makes electrical contact with the drain 103 of the N-type transistor, thereby connecting the drain 103 of the N-type transistor to the peripheral interconnect layer 520. The third contact plug 153 penetrates the insulating structure 140 and the first dielectric layer 130, and makes electrical contact with the gate 104 of the N-type transistor, thereby connecting the gate 104 of the N-type transistor to the peripheral interconnect layer 520.

[0095] Please continue reading. Figure 5 The insulating structure 140 also covers the first dielectric layer 130, which can protect the first dielectric layer 130. Furthermore, the thickness of the insulating material on the transistor 120 can be adjusted by changing the thickness of the portion of the insulating structure 140 above the first dielectric layer 130 to meet design requirements, allowing the distance between the first dielectric layer 130 and the N-type transistor to be set closer, thus better transferring tensile stress to the N-type transistor. In addition, the portions of the first contact plug 151, the second contact plug 152, and the third contact plug 153 that penetrate the first dielectric layer 130 are provided with the insulating structure 140. Thus, during the fabrication of the first contact plug 151, the second contact plug 152, and the third contact plug 153, the vias corresponding to the first contact plug 151, the second contact plug 152, and the third contact plug 153 can be formed through the insulating structure 140 in a single etching process. The etching process is simple and has low difficulty; the specific process can be referred to below, and will not be elaborated further in this embodiment.

[0096] In some embodiments, see Figure 5 The first transistor 121 is an N-type transistor, and the second transistor 122 is a P-type transistor. In the thickness direction of the substrate 110 (e.g., the third direction Z), the first dielectric layer 130 does not overlap with the channel 101, source 102, and drain 103 of the P-type transistor. This avoids the tensile stress of the first dielectric layer 130 being applied to the P-type transistor, thereby preventing the performance degradation of the P-type transistor.

[0097] Based on this, such as Figure 5As shown, the semiconductor device 10 further includes a fourth contact plug 154, a fifth contact plug 155, and a sixth contact plug 156. The fourth contact plug 154 penetrates the insulating structure 140 and makes electrical contact with the source 102 of the P-type transistor, thereby connecting the source 102 of the P-type transistor to the peripheral interconnect layer 520. The fifth contact plug 155 penetrates the insulating structure 140 and makes electrical contact with the drain 103 of the P-type transistor, thereby connecting the drain 103 of the P-type transistor to the peripheral interconnect layer 520. The sixth contact plug 156 penetrates the insulating structure 140 and makes electrical contact with the gate 104 of the P-type transistor, thereby connecting the gate 104 of the P-type transistor to the peripheral interconnect layer 520.

[0098] It is understandable that, according to the fabrication process of the insulating structure 140, the insulating structure 140 may include multiple film layers, and these multiple film layers may be formed using the same material, meaning there is no interface distinction between the multiple film layers of the insulating structure 140. Of course, the multiple film layers may also be formed using different materials, meaning there is a clear interface distinction between the film layers of different materials in the insulating structure 140.

[0099] In some embodiments, see Figure 5 The insulating structure 140 includes an isolation structure 141, a first interlayer dielectric layer 142 and 143. The isolation structure 141 extends from a first surface of the substrate 110 into the substrate 110 and is located between two adjacent transistors 120 to provide electrical isolation between the adjacent transistors 120.

[0100] The material of the aforementioned isolation structure 141 includes an insulating material, such as one or more combinations of silicon oxide, silicon oxynitride, silicon nitride, and high dielectric constant insulating materials, or other suitable materials. The embodiments disclosed herein are not limited thereto.

[0101] Please continue reading. Figure 5 The first interlayer dielectric layer 142 includes a first portion 1421 and a second portion 1422. The first portion 1421 fills the area between the plurality of transistors 120 to flatten the area between the plurality of transistors 120. The second portion 1422 is located between the plane where the first dielectric layer 130 is located and the plane where the gate 104 of the transistor 120 is located, to cover the gate 104 and the first portion 1421, so that the first dielectric layer 130 can be directly formed on the side of the first interlayer dielectric layer 142 away from the substrate 110, which facilitates the fabrication of the first dielectric layer 130. In addition, the distance between the first dielectric layer 130 and the N-type transistor can be adjusted by changing the thickness of the second portion 1422, so that tensile stress can be better transferred to the N-type transistor.

[0102] The material of the first interlayer dielectric layer 142 mentioned above includes an insulating material, such as one or more combinations of silicon oxide, silicon oxynitride, silicon nitride, and high dielectric constant insulating materials, or other suitable materials. This disclosure is not limited to these. Please continue reading. Figure 5 The second interlayer dielectric layer 143 is disposed on the side of the first interlayer dielectric layer 142 away from the substrate 110 and covers the first dielectric layer 130. This not only protects the first dielectric layer 130, but also allows the overall thickness of the insulating material on the transistor 120 to be adjusted by changing the thickness of the second interlayer dielectric layer 143 to meet design requirements.

[0103] The material of the second interlayer dielectric layer 143 mentioned above includes an insulating material, such as one or more combinations of silicon oxide, silicon oxynitride, silicon nitride, and high dielectric constant insulating materials, or other suitable materials. The embodiments disclosed herein are not limited thereto.

[0104] In some embodiments, see Figure 5 The transistor 120 further includes a source extension portion 161 and a drain extension portion 162. The source extension portion 161 is located between the source 102 and the channel 101, and both the source extension portion 161 and the source 102 include doped ions, with the doped ion concentration in the source extension portion 161 being less than that in the source 102. The drain extension portion 162 is located between the drain 103 and the channel 101, and both the drain extension portion 162 and the drain 103 include doped ions, with the doped ion concentration in the drain extension portion 162 being less than that in the drain 103.

[0105] At this point, a lightly doped region is provided between the source 102 and drain 103 and the channel 101. This reduces the electrostatic coupling between the source 102 and drain 103, lowers the short-channel effect, and improves carrier mobility. Furthermore, the electric field distribution in the lightly doped region is more gradual, which also reduces the electric field strength near the source 102 and drain 103, preventing premature breakdown under high voltage and improving the breakdown voltage performance of the transistor 120.

[0106] Please continue reading. Figure 5The transistor 120 may further include a package structure 170, which covers the source extension portion 161 and the drain extension portion 162, and encapsulates the gate 104 and the gate dielectric layer 105 of the transistor 120 to provide encapsulation protection. In this case, the insulating structure 140 encapsulates the package structure 170. The package structure 170 may include multiple package layers, and the material of the package layers includes at least one of silicon oxide, silicon oxynitride, and silicon nitride; the embodiments disclosed herein are not limited to these. For example, the package structure 170 includes at least one silicon nitride layer and at least one silicon oxide layer, with the silicon nitride layer and silicon oxide layer alternately stacked. Furthermore, except for the silicon nitride layer closest to the gate 104, the other silicon nitride layers and silicon oxide may only be disposed on the periphery of the gate 104, that is, a silicon nitride layer may be disposed on the side of the gate 104 away from the substrate 110. Figure 5 The example shown uses three silicon nitride layers and two silicon oxide layers.

[0107] The embodiments of this disclosure also provide a method for fabricating a semiconductor device 10, which can be used to fabricate the semiconductor device 10 of any of the above embodiments. (See also...) Figure 6 The preparation method includes steps S100 to S300.

[0108] S100: See Figure 7 Multiple transistors 120 are formed on the substrate 110.

[0109] In the above steps, such as Figure 7 As shown, the plurality of transistors 120 include a first transistor 121 and a second transistor 122 arranged side by side, wherein at least one of the first transistor 121 and the second transistor 122 is an N-type transistor. For example, both the first transistor 121 and the second transistor 122 are N-type transistors, or the first transistor 121 is a P-type transistor and the second transistor 122 is an N-type transistor, or the first transistor 121 is an N-type transistor and the second transistor 122 is a P-type transistor. Figure 5 The diagram illustrates the case with the first transistor 121 being a P-type transistor and the second transistor 122 being an N-type transistor.

[0110] The transistor 120 includes a channel 101, a source 102, a drain 103, a gate 104, and a gate dielectric layer 105. The channel 101, source 102, and drain 103 are embedded in a substrate 110 and exposed on a first surface of the substrate 110. The first surface is one of two opposing main surfaces of the substrate 110. The gate dielectric layer 105 covers the channel 101, and the gate 104 is disposed on the side of the gate dielectric layer 105 away from the substrate 110.

[0111] Please continue reading. Figure 7The transistor 120 may also include a source extension portion 161, a drain extension portion 162, and a package structure 170. The structures of the source extension portion 161, the drain extension portion 162, and the package structure 170 can be referred to above, and will not be described in detail here.

[0112] The following describes some embodiments of this disclosure by taking the first transistor 121 as a P-type transistor and the second transistor 122 as an N-type transistor as an example. However, the implementation of this disclosure is not limited to this, and the first transistor 121 can also be an N-type transistor, as long as the same technical concept is applied.

[0113] In some embodiments, see Figure 7 and Figure 8 Before S100, the preparation method also includes S110.

[0114] S110: See also Figure 7 An isolation structure 141 is formed on the substrate 110.

[0115] In the above steps, such as Figure 7 As shown, the isolation structure 141 extends from the first surface of the substrate 110 into the substrate 110 and is located between two adjacent transistors 120.

[0116] The isolation structure 141 can be formed by oxidizing the substrate 110, or by forming an isolation groove on the first surface of the substrate 110 through an etching process, and then filling the isolation groove with an insulating material. The insulating material can include at least one of silicon oxide, silicon oxynitride and silicon nitride, and the embodiments disclosed herein are not limited thereto.

[0117] S200: See also Figure 9 and Figure 10 This forms the first interlayer dielectric layer 142.

[0118] In the above steps, refer to Figure 9 and Figure 10 The first interlayer dielectric layer 142 includes a first portion 1421 and a second portion 1422. The first portion 1421 is located in the region between a plurality of transistors 120, and the second portion 1422 is located on the side of the plane where the gate 104 of the transistor 120 is located away from the substrate 110.

[0119] In some embodiments, see Figure 11 S200 includes S210 and S220.

[0120] S210: See also Figure 9 The first dielectric thin film 142' is formed.

[0121] In the above steps, such as Figure 9As shown, the first dielectric film 142' covers a plurality of transistors 120 and fills the area between the plurality of transistors 120. The surface of the first dielectric film 142' away from the substrate 110 has an uneven morphology.

[0122] The first dielectric thin film 142' can be formed using any of the following thin film deposition processes: chemical vapor deposition (CVD), physical vapor deposition (PVD), and atomic layer deposition (ALD).

[0123] S220: See also Figure 10 The surface of the first dielectric thin film 142' away from the substrate 110 is planarized.

[0124] In the above steps, such as Figure 10 As shown, a first interlayer dielectric layer 142 is formed, and the first interlayer dielectric layer 142 is located away from the surface of the substrate 110 and is parallel to the surface of the substrate 110 that is away from the first interlayer dielectric layer 142.

[0125] The planarization process can employ etching and / or polishing processes. For example, chemical mechanical polishing (CMP) can be used to process the surface of the first dielectric film 142' away from the substrate 110, so that the surface of the first dielectric film 142' away from the substrate 110 is flat.

[0126] S300: See reference Figure 12 , Figure 13 and Figure 14 , forming the first dielectric layer 130.

[0127] In the above steps, such as Figure 14 As shown, the first dielectric layer 130 is disposed on the side of the first interlayer dielectric layer 142 away from the substrate 110. In the thickness direction of the substrate 110, the first dielectric layer 130 at least partially overlaps with the channel 101 of the N-type transistor.

[0128] In some embodiments, see Figure 15 The first transistor is an N-type transistor, and the second transistor is a P-type transistor. At this point, as shown in the figure, S300 includes S310 and S320.

[0129] S310: See also Figure 12 , forming a tensile stress film 131.

[0130] In the above steps, such as Figure 12As shown, the tensile stress film 131 is disposed on the side of the first interlayer dielectric layer 142 away from the substrate 110, and the tensile stress film 131 covers the N-type transistor in the thickness direction of the substrate 110.

[0131] (e.g., second transistor 122) and P-type transistors (e.g., first transistor 121).

[0132] The tensile stress film 131 can be formed using any of the following thin film deposition processes: chemical vapor deposition (CVD), physical vapor deposition (PVD), and atomic layer deposition (ALD). For example, in process S310, plasma-enhanced chemical vapor deposition can be used, with silane as the silicon source and ammonia as the nitrogen source. In this case, because the Si-H bonds in silane and the NH bonds in ammonia do not completely break during the reaction, some hydrogen atoms will remain in the resulting tensile stress film 131, meaning that the tensile stress film 131 includes hydrogen atoms.

[0133] S320: See also Figure 13 and Figure 14 The portion of the tensile stress film 131 covering the P-type transistor is removed, and the semiconductor device 10 is annealed.

[0134] In the above steps, such as Figure 13 and Figure 14 As shown, the remaining portion of the tensile stress film 131 forms a first dielectric layer 130 after annealing. The tensile stress of the first dielectric layer 130 can be configured, for example, from 700 MPa to 1600 MPa, such as any one of 700 MPa, 750 MPa, 800 MPa, 850 MPa, 900 MPa, 950 MPa, 1000 MPa, 1100 MPa, 1200 MPa, 1300 MPa, 1400 MPa, 1500 MPa, and 1600 MPa.

[0135] During the annealing process, the remaining portion of the tensile stress film 131 generates thermal and internal stress effects with the channel 101, source 102, drain 103, and gate 104. These stresses are "memorized" in the channel 101, so even if the first dielectric layer 130 is subsequently removed, the channel 101 of the N-type transistor below the first dielectric layer 130 can still maintain a tensile stress state, thereby improving the performance of the N-type transistor. In other words, the first dielectric layer 130 can be removed after S320.

[0136] The annealing temperature can be in the range of 800℃ to 1200℃. For example, the annealing temperature can be 950℃ to 1000℃, or any one of 800℃, 850℃, 900℃, 950℃, 980℃, 1000℃, 1050℃, 1100℃, 1150℃, and 1200℃.

[0137] Furthermore, the portion of the tensile stress film 131 covering the P-type transistor can be removed using a dry / wet etching process. For example, a first photoresist layer 181 is formed on the side of the tensile stress film 131 away from the substrate 110. This first photoresist layer 181 covers the N-type transistor and exposes the P-type transistor. Using the first photoresist layer 181 as a mask, the tensile stress film 131 is etched, thereby removing the portion of the tensile stress film 131 covering the P-type transistor.

[0138] In some embodiments, see Figure 16 Following S300, the preparation method also includes S400 to S500.

[0139] S400: See Figure 17 and Figure 18 This forms the second interlayer dielectric layer 143.

[0140] In the above steps, such as Figure 17 and Figure 18 As shown, the second interlayer dielectric layer 143 is disposed on the side of the first interlayer dielectric layer 142 away from the substrate 110, and covers the first dielectric layer 130.

[0141] The second interlayer dielectric layer 143 can be deposited using any of the following thin film deposition processes: chemical vapor deposition (CVD), physical vapor deposition (PVD), or atomic layer deposition (ALD), and formed after planarization.

[0142] In some embodiments, see Figure 19 Prior to S400, the preparation method also includes S410.

[0143] S410: See also Figure 17 The first dielectric layer 130 is etched to form the first via, the second via, and the third via.

[0144] In the above steps, refer to Figure 17 The first via, the second via, and the third via are at least partially opposite to the source 102, the drain 103, and the gate 104 of the N-type transistor, respectively.

[0145] Among them, such as Figure 17 As shown, the first dielectric layer 130 can be etched using a dry / wet etching process. For example, a first mask layer 182 and a second photoresist layer 183 are sequentially formed on the side of the first dielectric layer 130 away from the substrate 110. The first mask layer 182 and the second photoresist layer 183 can be formed sequentially using deposition, planarization, and photolithography processes. The hardness of the first mask layer 182 is greater than that of the second photoresist layer 183. Furthermore, the second photoresist layer 183 has a first opening, a second opening, and a third opening, which are at least partially opposite to the source 102, drain 103, and gate 104 of the N-type transistor, respectively. The first dielectric layer 130 is etched using the first mask layer 182 as a mask to form a first via, a second via, and a third via. This results in a first mask layer 182 with high hardness, allowing for etching to deeper target depths, and exhibiting high stability in etching and other processes, enabling accurate pattern transfer.

[0146] At this time, during the S400 process, refer to Figure 17 and Figure 18 The second interlayer dielectric layer 143 fills the first via, the second via, and the third via.

[0147] S500: See Figure 5 , Figure 18 and Figure 20 This forms a first contact plug 151, a second contact plug 152, a third contact plug 153, a fourth contact plug 154, a fifth contact plug 155, and a sixth contact plug 156.

[0148] In the above steps, such as Figure 5 As shown, the first contact plug 151 penetrates the first interlayer dielectric layer 142, the second interlayer dielectric layer 143, and the first dielectric layer 130, and is electrically contacted with the source 102 of the N-type transistor. The second contact plug 152 penetrates the first interlayer dielectric layer 142, the second interlayer dielectric layer 143, and the first dielectric layer 130, and is electrically contacted with the drain 103 of the N-type transistor. The third contact plug 153 penetrates the first interlayer dielectric layer 142, the second interlayer dielectric layer 143, and the first dielectric layer 130, and is electrically contacted with the gate 104 of the N-type transistor. The fourth contact plug 154 penetrates the first interlayer dielectric layer 142 and the second interlayer dielectric layer 143, and is electrically contacted with the source 102 of the P-type transistor. The fifth contact plug 155 penetrates the first interlayer dielectric layer 142 and the second interlayer dielectric layer 143, and is electrically contacted with the drain 103 of the P-type transistor. The sixth contact plug 156 penetrates the first interlayer dielectric layer 142 and the second interlayer dielectric layer 143, and is in electrical contact with the gate 104 of the P-type transistor.

[0149] In the S500 process, the first contact plug 151 passes through the first through hole, the second contact plug 152 passes through the second through hole, and the third contact plug 153 passes through the third through hole.

[0150] In addition, see Figure 5 and Figure 20 The first interlayer dielectric layer 142 and the second interlayer dielectric layer 143 can be etched using a dry / wet etching process, followed by deposition of conductive material and planarization to form a first contact plug 151, a second contact plug 152, a third contact plug 153, a fourth contact plug 154, a fifth contact plug 155, and a sixth contact plug 156. For example, a second mask layer 184 and a third photoresist layer 185 are sequentially formed on the side of the second interlayer dielectric layer 143 away from the substrate 110. The second mask layer 184 and the third photoresist layer 185 can be formed sequentially using deposition, planarization, and photolithography processes. The hardness of the second mask layer 184 is greater than the hardness of the third photoresist layer 185. Furthermore, the third photoresist layer 185 is provided with a fourth, fifth, sixth, seventh, eighth, and ninth opening. The fourth, fifth, and sixth openings are at least partially opposite to the source 102, drain 103, and gate 104 of the first transistor 121 (e.g., a P-type transistor), respectively, while the seventh, eighth, and ninth openings are at least partially opposite to the second transistor 122 (e.g., an N-type transistor). At this time, the first interlayer dielectric layer 142 and the second interlayer dielectric layer 143 are etched using the second mask layer 184 as a mask to form the fourth, fifth, sixth, seventh, eighth, and ninth vias. This results in the second mask layer 184 having high hardness, allowing it to be used for etching deeper target depths, and exhibiting high stability in etching and other processes, enabling accurate pattern transfer. Finally, conductive material is filled into the fourth, fifth, sixth, seventh, eighth, and ninth vias to form the first contact plug 151, the second contact plug 152, the third contact plug 153, the fourth contact plug 154, the fifth contact plug 155, and the sixth contact plug 156.

[0151] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A semiconductor device, characterized in that, include: Substrate; Multiple transistors, including a first transistor and a second transistor arranged side by side, wherein at least one of the first transistor and the second transistor is an N-type transistor; The transistor includes a channel, a source, a drain, a gate, and a gate dielectric layer. The channel, the source, and the drain are embedded in the substrate and exposed on a first surface of the substrate. The channel is located between the source and the drain. The first surface is one of two opposing main surfaces of the substrate. The gate dielectric layer covers the channel, and the gate is disposed on the side of the gate dielectric layer away from the substrate; A first dielectric layer is disposed on the side of the plane where the gate of the N-type transistor is located away from the substrate, and has a gap between it and the gate of the N-type transistor; wherein, in the thickness direction of the substrate, the first dielectric layer at least partially overlaps with the channel of the N-type transistor. An insulating structure is provided at least in the region between the plurality of transistors and in the region between the first dielectric layer and the gate of the N-type transistor.

2. The semiconductor device according to claim 1, characterized in that, The first dielectric layer is located away from and / or close to the surface of the substrate, and is parallel to the surface of the substrate that is away from the insulating structure.

3. The semiconductor device according to claim 1, characterized in that, In the thickness direction of the substrate, the first dielectric layer covers the channel, source, and drain of the N-type transistor.

4. The semiconductor device according to claim 3, characterized in that, Also includes: The first contact plug penetrates the insulating structure and the first dielectric layer, and makes electrical contact with the source of the N-type transistor; The second contact plug penetrates the insulating structure and the first dielectric layer and makes electrical contact with the drain of the N-type transistor; The third contact plug penetrates the insulating structure and the first dielectric layer, and makes electrical contact with the gate of the N-type transistor.

5. The semiconductor device according to claim 4, characterized in that, The insulating structure also covers the first dielectric layer, and the first contact plug, the second contact plug and the third contact plug penetrate the portion of the first dielectric layer, with the insulating structure provided between them and the first dielectric layer.

6. The semiconductor device according to claim 1, characterized in that, The first transistor is an N-type transistor, and the second transistor is a P-type transistor; in the thickness direction of the substrate, the first dielectric layer does not overlap with the channel, source, and drain of the P-type transistor.

7. The semiconductor device according to claim 6, characterized in that, Also includes: The fourth contact plug penetrates the insulating structure and makes electrical contact with the source of the P-type transistor; The fifth contact plug penetrates the insulating structure and makes electrical contact with the drain of the P-type transistor; The sixth contact plug penetrates the insulating structure and makes an electrical contact with the gate of the P-type transistor.

8. The semiconductor device according to any one of claims 1 to 7, characterized in that, The insulating structure includes: An isolation structure extends from a first surface of the substrate into the substrate and is located between two adjacent transistors; The first interlayer dielectric layer includes a first portion and a second portion, wherein the first portion fills the region between the plurality of transistors, and the second portion is located between the plane in which the first dielectric layer is located and the plane in which the gate of the transistor is located; The second interlayer dielectric layer is disposed on the side of the first interlayer dielectric layer away from the substrate and covers the first dielectric layer.

9. The semiconductor device according to any one of claims 1 to 7, characterized in that, The spacing between the gates of two adjacent transistors is less than or equal to 120 nm.

10. The semiconductor device according to any one of claims 1 to 7, characterized in that, The tensile stress of the first dielectric layer is configured to be 700 MPa to 1600 MPa.

11. The semiconductor device according to any one of claims 1 to 7, characterized in that, The transistor also includes: A source extension portion is located between the source and the channel; both the source extension portion and the source include doped ions, and the concentration of doped ions in the source extension portion is less than the concentration of doped ions in the source; A drain extension is located between the drain and the channel; both the drain extension and the drain include doped ions, and the concentration of doped ions in the drain extension is less than the concentration of doped ions in the drain. The package structure covers the source extension portion and the drain extension portion, and encapsulates the gate and the gate dielectric layer of the transistor; the insulating structure encapsulates the package structure.

12. The semiconductor device according to any one of claims 1 to 7, characterized in that, The material of the first dielectric layer includes silicon nitride; and / or, the material of the insulating structure includes silicon oxide.

13. A storage system, characterized in that, include: The controller and the semiconductor device as described in any one of claims 1 to 12, wherein the controller is coupled to the semiconductor device to control the semiconductor device to store data.

14. A method for fabricating a semiconductor device, characterized in that, include: Multiple transistors are formed on the substrate; The plurality of transistors includes a first transistor and a second transistor arranged side by side, wherein at least one of the first transistor and the second transistor is an N-type transistor; The transistor includes a channel, a source, a drain, a gate, and a gate dielectric layer, wherein the channel, the source, and the drain are embedded in the substrate and exposed on a first surface of the substrate; the first surface is one of two opposing main surfaces of the substrate. The gate dielectric layer covers the channel, and the gate is disposed on the side of the gate dielectric layer away from the substrate; Forming the first interlayer dielectric layer; The first interlayer dielectric layer includes a first portion and a second portion, the first portion being located in the region between the plurality of transistors, and the second portion being located on the side of the plane containing the gate of the transistor away from the substrate; Form the first dielectric layer; The first dielectric layer is disposed on the side of the first interlayer dielectric layer away from the substrate; in the thickness direction of the substrate, the first dielectric layer at least partially overlaps with the channel of the N-type transistor.

15. The method for fabricating a semiconductor device according to claim 14, characterized in that, The formation of the first interlayer dielectric layer includes: A first dielectric film is formed; the first dielectric film covers the plurality of transistors and fills the area between the plurality of transistors, and the surface of the first dielectric film away from the substrate has an uneven morphology; The surface of the first dielectric film away from the substrate is planarized.

16. The method for fabricating a semiconductor device according to claim 14, characterized in that, The first transistor is an N-type transistor, and the second transistor is a P-type transistor; The formation of the first dielectric layer includes: A tensile stress film is formed; the tensile stress film is disposed on the side of the first interlayer dielectric layer away from the substrate, and in the thickness direction of the substrate, the tensile stress film covers the N-type transistor and the P-type transistor; Remove the portion of the tensile stress film covering the P-type transistor and anneal the semiconductor device.

17. The method for fabricating a semiconductor device according to claim 16, characterized in that, After the formation of the first dielectric layer, the method further includes: A second interlayer dielectric layer is formed; the second interlayer dielectric layer is disposed on the side of the first interlayer dielectric layer away from the substrate, and covers the first dielectric layer; A first contact plug, a second contact plug, a third contact plug, a fourth contact plug, a fifth contact plug, and a sixth contact plug are formed. The first contact plug penetrates the first interlayer dielectric layer, the second interlayer dielectric layer, and the first dielectric layer, and is in electrical contact with the source of the N-type transistor. The second contact plug penetrates the first interlayer dielectric layer, the second interlayer dielectric layer, and the first dielectric layer, and is in electrical contact with the drain of the N-type transistor. The third contact plug penetrates the first interlayer dielectric layer, the second interlayer dielectric layer, and the first dielectric layer, and is in electrical contact with the gate of the N-type transistor. The fourth contact plug penetrates the first interlayer dielectric layer and the second interlayer dielectric layer, and is in electrical contact with the source of the P-type transistor. The fifth contact plug penetrates the first interlayer dielectric layer and the second interlayer dielectric layer, and is in electrical contact with the drain of the P-type transistor. The sixth contact plug penetrates the first interlayer dielectric layer and the second interlayer dielectric layer, and is in electrical contact with the gate of the P-type transistor.

18. The method for fabricating a semiconductor device according to claim 17, characterized in that, Prior to the formation of the second interlayer dielectric layer, the method further includes: The first dielectric layer is etched to form a first via, a second via, and a third via; During the formation of the second interlayer dielectric layer, the second interlayer dielectric layer fills the first via, the second via, and the third via; During the formation of the first contact plug, the second contact plug, the third contact plug, the fourth contact plug, the fifth contact plug, and the sixth contact plug, the first contact plug passes through the first through hole, the second contact plug passes through the second through hole, and the third contact plug passes through the third through hole.

19. The method for fabricating a semiconductor device according to any one of claims 14 to 18, characterized in that, Prior to forming the plurality of transistors on the substrate, the method further includes: An isolation structure is formed on the substrate; the isolation structure extends from a first surface of the substrate into the substrate and is located between two adjacent transistors.

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