Semiconductor device and method of manufacturing the same

Abstract

A semiconductor device and a method of manufacturing the same are provided. The device includes a first field effect transistor and a second field effect transistor stacked on a substrate and an isolation layer therebetween. The first field effect transistor includes a first channel portion, a first source / drain layer, and a first gate stack. The first channel portion extends along a first direction, includes a plurality of first semiconductor layers stacked apart from each other, and a second semiconductor layer extending vertically between first semiconductor layers adjacent in the vertical direction. The second semiconductor layer is recessed in the second direction at both side ends thereof in the second direction relative to both side ends of the first semiconductor layer in the second direction. The second field effect transistor includes a second channel portion, a second source / drain layer, and a second gate stack. The second channel portion extends along the first direction, includes a plurality of third semiconductor layers stacked apart from each other. The second gate stack at least partially surrounds an outer periphery of the plurality of third semiconductor layers in the second direction.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and more specifically to a semiconductor device and a method for manufacturing the same. Background Technology

[0002] With the continuous development of integrated circuit manufacturing process nodes and key technologies, NS-GAA FET (Nano-SheetGate-All-Around Field-Effect Transistor) will replace the existing Fin FET (Fin Field-Effect Transistor) technology at 3nm and below. Furthermore, 3D Stacked Field Effect Transistor (3DS FET), also known as CFET (Complementary Field Effect Transistor) or VFET (Vertical Field-Effect Transistor), will become the main technology route after the 1nm node.

[0003] However, due to limitations in integrated circuit technology, it is difficult to improve the performance of CFET devices by continuously increasing the number of channel stacking layers. The application of CFET devices still faces many technical challenges. Summary of the Invention

[0004] In view of the above problems, embodiments of this application provide a semiconductor device and a method for manufacturing the same.

[0005] According to a first aspect of the present application, a semiconductor device is provided. The semiconductor device includes a first field-effect transistor (FET) and a second FET stacked vertically on a substrate, and an isolation layer between the first FET and the second FET. The first FET includes a first channel, a first source / drain layer, and a first gate stack. The first channel extends along a first direction and includes a plurality of first semiconductor layers stacked at intervals in the vertical direction and a second semiconductor layer extending vertically between adjacent first semiconductor layers in the vertical direction. The second semiconductor layers have two concave ends in a second direction relative to the two concave ends of the first semiconductor layers in the second direction, and the second direction intersects the first direction. The first source / drain layers are located on opposite sides of the first channel in the first direction. The first gate stack intersects the first channel in the second direction. The second FET includes a second channel, a second source / drain layer, and a second gate stack. The second channel extends along the first direction and includes a plurality of third semiconductor layers stacked at intervals in the vertical direction. The second source / drain layers are located on opposite sides of the second channel in the first direction. The second gate stack at least partially surrounds the periphery of the plurality of third semiconductor layers in the second direction.

[0006] According to a second aspect of the embodiments of this application, a method for manufacturing a semiconductor device is provided. The method includes: disposing on a first stacked structure and a second stacked structure stacked in a vertical direction, and an isolation layer between the first stacked structure and the second stacked structure, on a first substrate, wherein the first stacked structure includes alternately stacked first semiconductor layers and second semiconductor layers, the second stacked structure includes alternately stacked third semiconductor layers and fourth semiconductor layers, the first semiconductor layers and second semiconductor layers having different selective etchability relative to each other, the third semiconductor layer and fourth semiconductor layer having different selective etchability relative to each other, and the second semiconductor layer and fourth semiconductor layer having different selective etchability relative to each other; patterning the first stacked structure, the second stacked structure, and the isolation layer together with the upper portion of the first substrate to form fins extending along a first direction; forming a sacrificial gate extending along a second direction intersecting the first direction and thus intersecting the fins on the first substrate; forming gate sidewalls on the sidewalls of the sacrificial gate; and using the sacrificial gate and the gate sidewalls as masks to pattern the first stacked structure, the second stacked structure, and the isolation layer, thereby patterning the patterned first stacked structure, the second stacked structure, and the isolation layer. The layer has a side surface exposed in a first direction; a first source / drain layer is formed in contact with the side surface exposed in the first direction of the first stacked structure, and a second source / drain layer is formed in contact with the side surface exposed in the first direction of the second stacked structure; a sacrificial gate is removed, and after the sacrificial gate is removed, the first stacked structure, the second stacked structure, and the isolation layer have side surfaces exposed in the second direction; the first semiconductor layer, the second semiconductor layer, the third semiconductor layer, and the fourth semiconductor layer are selectively etched via the side surfaces exposed in the second direction of the first stacked structure, the second stacked structure, and the isolation layer, such that when the selective etching is completed, the second semiconductor layer in the first stacked structure is partially removed and has a remaining portion between the first semiconductor layers, and the fourth semiconductor layer in the second stacked structure is removed and the third semiconductor layer is released; inside the gate sidewall, a first gate stack intersecting with the first channel portion is formed, and a second gate stack at least partially surrounds the outer periphery of the third semiconductor layer in the second direction is formed, the first channel portion including the remaining portions of the first semiconductor layer and the second semiconductor layer.

[0007] According to an embodiment of this application, a semiconductor device is provided. A first channel portion of a first field-effect transistor in this semiconductor device includes first semiconductor layers stacked at intervals in a vertical direction and a second semiconductor layer extending vertically between adjacent first semiconductor layers in a vertical direction, with the ends of the second semiconductor layers recessed in a second direction. A second channel portion of a second field-effect transistor includes a plurality of third semiconductor layers stacked at intervals. Thus, without increasing the number of stacked layers in the vertical direction, the effective conductive channel width of the device can be increased, thereby improving the device performance. Simultaneously, the crystal plane ratio of the first and second semiconductor layers in contact with the gate stack can be optimized to improve the matching of driving performance between different device units. Attached Figure Description

[0008] The above-mentioned contents, other objects, features and advantages of this application will become clearer from the following description of embodiments with reference to the accompanying drawings, which will be explained in conjunction with the drawings.

[0009] Figure 1A The illustration schematically shows a first axial direction extending along a first direction in a semiconductor device according to an embodiment of the present application.

[0010] Figure 1B A schematic diagram of a second axial direction extending along a second direction in a semiconductor device according to an embodiment of this application is shown.

[0011] Figure 2A A schematic cross-sectional view of a semiconductor device according to an embodiment of this application is shown along the X-X' axis.

[0012] Figure 2B A schematic cross-sectional view of a semiconductor device according to an embodiment of this application is shown along the Y-Y' axis.

[0013] Figure 3 A flowchart illustrating a method for manufacturing a semiconductor device according to an embodiment of this application is shown.

[0014] Figures 4-29B Cross-sectional views along various axial directions are schematically shown for some stages in a method for manufacturing a semiconductor device according to embodiments of this application. Detailed Implementation

[0015] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with specific embodiments and the accompanying drawings.

[0016] The endpoints and any values ​​of the ranges disclosed in this application are not limited to the precise ranges or values, and these ranges or values ​​should be understood to include values ​​close to these ranges or values. For numerical ranges, the endpoint values ​​of the various ranges, the endpoint values ​​of the various ranges and individual point values, and individual point values ​​can be combined with each other to obtain one or more new numerical ranges, which should be considered as specifically disclosed in this application.

[0017] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the scope of this application. The terms “comprising,” “including,” etc., as used herein indicate the presence of the stated features, steps, operations, and / or components, but do not exclude the presence or addition of one or more other features, steps, operations, or components.

[0018] All terms used herein (including technical and scientific terms) have the meanings commonly understood by those skilled in the art, unless otherwise defined. It should be noted that the terms used herein are to be interpreted in a manner consistent with the context of this specification, and not in an idealized or overly rigid way.

[0019] In the description of this application, it should be understood that the terms "longitudinal", "length", "circumferential", "front", "rear", "left", "right", "top", "bottom", "inner", "outer", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the subsystem or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application.

[0020] Similarly, to simplify this application and aid in understanding one or more of the various disclosed aspects, in the above description of exemplary embodiments of this application, various features of this application are sometimes grouped together into a single embodiment, figure, or description thereof. The use of terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicates that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of this application. In this specification, illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0021] As integrated circuit manufacturing processes continue to advance towards smaller dimensions, the structural innovation of transistors, as one of the core units of integrated circuits, has become a crucial driving force for the development of the semiconductor industry. NS-GAA FETs have become the mainstream technology to replace FinFETs at 3nm and below. They offer higher performance within the same chip area while maintaining good compatibility with FinFET processes, reducing the cost and risk of technology upgrades. Although NS-GAA FETs have demonstrated significant technological advantages at the 3nm node, horizontal device miniaturization will still face atomic-level physical limits as process nodes further advance to 1nm and below. To overcome this bottleneck, CFETs and VFETs are considered the most promising technological routes. CFETs, by vertically stacking N-type and P-type field-effect transistors on a substrate, can increase the chip's area density and alleviate the challenges of horizontal miniaturization.

[0022] However, the application of CFET devices still faces many severe technical challenges. For example, it is difficult to improve the performance of CFET devices by continuously increasing the number of channel stacking layers. As the number of channel stacking layers increases, the parasitic capacitance and parasitic resistance between channels increase significantly, causing the switching speed improvement of the device to gradually saturate, and even leading to performance degradation. At the same time, the source-drain contact resistance of the upper-layer devices also increases with the number of layers, further limiting the improvement of driving performance. This not only limits the further improvement space of CFET device performance, but also makes performance matching between different device units more difficult, thereby increasing the design complexity of integrated circuits.

[0023] In view of this, embodiments of this application provide a semiconductor device and a method for manufacturing the same, which can improve the performance of CFET devices, enhance the performance matching between N-type and P-type field-effect transistors, and optimize the control of unit circuits. The following description, in conjunction with the accompanying drawings, will further illustrate this.

[0024] Figure 1A This schematically illustrates the position of the X-X' axis extending along a first direction in a semiconductor device according to an embodiment of this application. Figure 1B The schematic diagram illustrates the position of the Y-Y' axis extending along the second direction in a semiconductor device according to an embodiment of this application.

[0025] It should be pointed out that, Figure 1A and Figure 1B The perspective view of the semiconductor device is shown only schematically and is intended to illustrate the location of the cross-sectional views involved in other figures, and is not intended to illustrate a specific three-dimensional structure of the semiconductor device according to embodiments of this application. The structure of the semiconductor device according to embodiments of this application can be understood from the following cross-sectional views.

[0026] More specifically, Figure 1A and Figure 1B The diagram illustrates the main components of a semiconductor device, such as STI (shallow trench isolation), NS (nanosheets), spacers (sidewalls), metal (metal contacts), and gates, and their positional relationships. For example, a semiconductor device may include a first field-effect transistor (FET) and a second FET, each including a corresponding channel. Here, two nanosheets NS stacked at a distance from each other are used to illustrate the respective channels of the first and second FETs. Of course, the number of nanosheets NS is not limited to this. On both sides of the channel in a first direction, there are source / drain layers in contact with the channel (i.e., the nanosheets NS). In the perspective view, the source / drain layers may be obscured by the metal contacts (Metal). The gate stack (Gate) may extend along a second direction intersecting (e.g., perpendicular to) the first direction to at least partially surround the outer periphery of the channel (i.e., the nanosheets NS). The sidewall spacers may be located on the sidewalls of the gate stack (Gate), between the gate stack (Gate) and the source / drain layers and the metal contacts (Metal). Nanosheets (NS) can be formed on top of sub-Si, and the sub-Si can be surrounded by shallow trench isolation (STI).

[0027] According to an embodiment of this application, the X-X' axis can extend along a first direction and is located in the middle of the nanosheet NS in a second direction; the Y-Y' axis can extend along a second direction and is located in the middle of the gate stack in the first direction.

[0028] Figure 2A The illustration schematically shows a cross-sectional view of a semiconductor device according to an embodiment of this application along the X-X' axis. Figure 2B A schematic cross-sectional view of a semiconductor device according to an embodiment of this application is shown along the Y-Y' axis.

[0029] like Figure 2A and Figure 2B As shown, the semiconductor device in this embodiment may include a first field-effect transistor S1 and a second field-effect transistor S2 stacked on a substrate 123 in a vertical direction. An isolation layer 105 may be provided between the first field-effect transistor S1 and the second field-effect transistor S2 for electrical isolation.

[0030] The first field-effect transistor S1 may include a first channel, a first source / drain layer 115, and a first gate stack.

[0031] The first channel portion may extend along a first direction and may include a plurality of first semiconductor layers 101 stacked at intervals in the vertical direction and a second semiconductor layer 102 extending vertically between adjacent first semiconductor layers in the vertical direction. The second semiconductor layer 102 may have a different width in the second direction than the first semiconductor layer 101, and its two end portions are recessed relative to the two end portions of the first semiconductor layer 101 in the second direction. The second semiconductor layer 102 extends between and is in contact with the first source / drain layers on opposite sides in the first direction, is located substantially at the center of the first semiconductor layer 101 in the second direction, and is in contact with the first semiconductor layer 101 in the vertical direction. For example, refer to... Figure 2B The first channel portion can be arranged in a fishbone shape as shown in the figure. The first channel portion can increase the effective channel width in the first field-effect transistor, and the first gate stack has more contact with the upper and lower surfaces of the first semiconductor layer and more contact with the side surfaces of the second semiconductor layer. The crystal planes of the upper and lower surfaces of the first semiconductor layer and the side surfaces of the second semiconductor layer can be different, optimizing the performance of the first field-effect transistor through different crystal plane ratios. The second semiconductor layer 102 can include a semiconductor material with etching selectivity relative to the first semiconductor layer 101. The first semiconductor layer can include Si or Ge. The second semiconductor layer can include SiGe. The number of first semiconductor layers 101 and second semiconductor layers 102 in the first channel portion can be arbitrary and is not limited here. For example, there can be multiple first semiconductor layers 101 and multiple second semiconductor layers 102. Multiple first semiconductor layers 101 and multiple second semiconductor layers 102 are stacked alternately in the vertical direction. For example, the first channel portion can be a nanosheet extending along a first direction and parallel to each other. The first direction corresponds to... Figure 2A In the X-X' axis, the second direction corresponds to Figure 2B In the Y-Y' axis, the second direction can intersect the first direction (e.g., be perpendicular).

[0032] The first source / drain layer 115 may be located on opposite sides of the first channel portion (first semiconductor layer 101 and second semiconductor layer 102) in a first direction. The first gate stack intersects the first channel portion in a second direction. The first gate stack may include a gate dielectric layer 119 and a first gate conductor 120. The gate dielectric layer 119 may include a high-κ dielectric material, where κ represents the dielectric constant. High-κ dielectric materials include HfO2 and HfSiO2. x HfON, HfSiON, HfAlO x HfLaO x Al2O3, ZrO2, ZrSiO xThe first gate conductor 120 may include a first work function layer located on the gate dielectric layer 119 and a conductor layer on the first work function layer. The first work function layer may include a work function material that matches the first field-effect transistor S1. For example, if the first field-effect transistor is an N-type field-effect transistor, the first work function layer may be an N-type work function layer; if the first field-effect transistor is a P-type field-effect transistor, the first work function layer may be a P-type work function layer. The work function material may include titanium nitride, etc. The conductive layer may include metals such as tungsten, etc.

[0033] The second field-effect transistor S2 includes a second channel, a second source / drain layer 117, and a second gate stack.

[0034] The second channel portion may extend along the first direction and may include a plurality of third semiconductor layers 103 stacked at intervals in the vertical direction. The width of the third semiconductor layer in the second direction may be the same as the width of the first semiconductor layer in the second direction. In the vertical direction, the thickness of the third semiconductor layer may be less than the thickness of the first semiconductor layer, or the thickness of the first semiconductor layer in the vertical direction may be substantially equal to the thickness of the third semiconductor layer in the vertical direction. The third semiconductor layer may include Si or Ge. The number of third semiconductor layers 103 in the second channel portion may be arbitrary and is not limited herein. The plurality of third semiconductor layers 103 are stacked at intervals in the vertical direction. For example, the second channel portion may be nanosheets extending along the first direction and parallel to each other.

[0035] The second source / drain layer 117 may be located on opposite sides of the second channel portion (third semiconductor layer 103) in the first direction. The second gate stack may at least partially surround the outer periphery of the plurality of third semiconductor layers 103 in the second direction. The second gate stack may include a gate dielectric layer 119 and a second gate conductor 121. The second gate conductor 121 may include a second work function layer located on the gate dielectric layer 119 and a conductor layer on the second work function layer. The second work function layer may include a work function material that matches the second field-effect transistor S2. For example, if the second field-effect transistor is an N-type field-effect transistor, the second work function layer may be an N-type work function layer; if the second field-effect transistor is a P-type field-effect transistor, the second work function layer may be a P-type work function layer.

[0036] According to an embodiment of this application, the first channel portion of the first field-effect transistor of the semiconductor device includes alternating stacked first and second semiconductor layers in a vertical direction, with the ends of the second semiconductor layers recessed in a second direction; the second channel portion of the second field-effect transistor includes a plurality of third semiconductor layers stacked at intervals from each other. Thus, without increasing the number of stacked layers in the vertical direction of the channel portion, the effective conductive channel width of the device can be increased, thereby improving the device performance. Simultaneously, the crystal plane ratio of the first and second semiconductor layers in the first channel portion to the gate stack contact can be optimized to improve the matching of driving performance between different device units.

[0037] In some embodiments, the first field-effect transistor (FET) can be either an N-type FET or a P-type FET, and the second FET can be either an N-type FET or a P-type FET. For example, if the first FET is an N-type FET, then the second FET can be a P-type FET; or if the first FET is a P-type FET, then the second FET can be an N-type FET. According to other embodiments, the first and second FETs can also be of the same type, for example, both being either N-type or P-type FETs.

[0038] In some embodiments, the first field-effect transistor (FET) can be either an upper FET or a lower FET, and the second FET can be either an upper FET or a lower FET. In other words, the first FET can be stacked on top of the second FET, or the second FET can be stacked on top of the first FET, relative to the substrate. Although the two FETs stacked on top of each other are referred to herein as an "upper" FET and a "lower" FET, "upper" and "lower" are merely relative terms. For example, in... Figure 2A and Figure 2B In the flipped state shown, the "upper layer" field-effect transistor is located at the bottom, while the "lower layer" field-effect transistor is located at the top. Here, "upper" and "lower" are defined relative to the substrate; a position closer to the substrate can be "lower," while a position farther from the substrate can be "upper." Similarly, "top," "bottom," or "top surface," "bottom surface" are defined in the same way. For example, a surface of a structure close to the original substrate can be called the "bottom surface," while a surface farther from the original substrate can be called the "top surface." This definition will become clearer when considered in conjunction with the manufacturing process described below.

[0039] Thus, the semiconductor device in the embodiments of this application can be constructed as any one of the following: an upper layer of an N-type second field-effect transistor and a lower layer of a P-type first field-effect transistor, an upper layer of an N-type first field-effect transistor and a lower layer of a P-type second field-effect transistor, an upper layer of a P-type second field-effect transistor and a lower layer of an N-type first field-effect transistor, or an upper layer of a P-type first field-effect transistor and a lower layer of an N-type second field-effect transistor.

[0040] According to embodiments of this application, the first field-effect transistor and the second field-effect transistor can be matched with different application requirements and circuit designs of CFET devices by different conductivity types and by the lower and upper spaces on the substrate according to application needs, thereby further improving the performance matching between device units, expanding the application scenarios of CFET devices and the practicality of integrated circuits.

[0041] In some embodiments, the proportion of (110) crystal planes in the first channel portion that are connected to the first gate stack can be greater than the proportion of (110) crystal planes in the second channel portion that are connected to the second gate stack. Compared to (100) crystal planes, (110) crystal planes have a significant advantage in improving hole mobility in the channel. The first channel portion can further regulate the driving performance of the first field-effect transistor and the second field-effect transistor by increasing the proportion of (110) crystal planes in the conductive crystal planes, or by using a design with (110) crystal planes as the main conductive crystal planes.

[0042] exist Figure 2A In the example shown, the second gate stack is adjacent to the second source / drain layer 117. In some other embodiments, the semiconductor device may further include an inner sidewall, which may be located between the second gate stack and the second source / drain layer 117. The inner sidewall may include a nitride such as silicon nitride.

[0043] According to embodiments of this application, an inner wall is provided inside the device, which can form physical isolation between the second gate stack and the second source / drain layer, reduce the parasitic capacitance between the gate and source, and between the gate and drain, improve the switching speed of the device, and reduce dynamic power consumption.

[0044] In some embodiments, the isolation layer 105 may further include a first dielectric layer and a second dielectric layer stacked in a vertical direction. The first dielectric layer and the second dielectric layer may be made of the same dielectric material to be formed as the isolation layer by bonding. The formation of the isolation layer will become clearer in conjunction with the manufacturing process described below.

[0045] In some embodiments, the semiconductor device in this application may further include an interlayer dielectric layer and a contact plug 122 that penetrates the interlayer dielectric layer and electrically connects the source / drain layers of the first field-effect transistor and the second field-effect transistor and the gate stack, respectively.

[0046] The method for manufacturing a semiconductor device according to embodiments of this application will be described in more detail below with reference to examples.

[0047] Figure 3 A flowchart illustrating a method for manufacturing a semiconductor device according to an embodiment of this application is shown.

[0048] like Figure 3 As shown, the method for manufacturing a semiconductor device in this embodiment may include operations S310 to S380.

[0049] In operation S310, a first stacked structure and a second stacked structure stacked in a vertical direction and an isolation layer between the first stacked structure and the second stacked structure are disposed on a first substrate, wherein the first stacked structure includes alternating first semiconductor layers and second semiconductor layers, and the second stacked structure includes alternating third semiconductor layers and fourth semiconductor layers.

[0050] In some embodiments, the first semiconductor layer and the second semiconductor layer may have different selective etching properties relative to each other, the third semiconductor layer and the fourth semiconductor layer may have different selective etching properties relative to each other, and the second semiconductor layer and the fourth semiconductor layer may have different selective etching properties relative to each other.

[0051] In operation S320, the upper part of the first stacked structure, the second stacked structure, and the isolation layer together with the first substrate is patterned to form fins extending along the first direction.

[0052] In operation S330, a sacrificial gate is formed on the first substrate, extending along a second direction intersecting the first direction and thus intersecting the fin.

[0053] In operation S340, a gate sidewall is formed on the sidewall of the sacrificial gate.

[0054] In operation S350, using the sacrificial gate and gate sidewall as a mask, the first stacked structure, the second stacked structure, and the isolation layer are patterned, so that the patterned first stacked structure, the second stacked structure, and the isolation layer have side surfaces exposed in a first direction.

[0055] In operation S360, a first source / drain layer is formed that is in contact with the side surface exposed in the first direction of the first stacked structure, and a second source / drain layer is formed that is in contact with the side surface exposed in the first direction of the second stacked structure; the sacrificial gate is removed, and after the sacrificial gate is removed, the first stacked structure, the second stacked structure and the isolation layer have side surfaces exposed in the second direction.

[0056] In operation S370, the first semiconductor layer, the second semiconductor layer, the third semiconductor layer, and the fourth semiconductor layer are selectively etched through the side surfaces exposed in the second direction via the first stacked structure, the second stacked structure, and the isolation layer.

[0057] In some embodiments, when selective etching is completed, the second semiconductor layer in the first stacked structure can be partially removed to have a remaining portion between the first semiconductor layers, and the fourth semiconductor layer in the second stacked structure is removed to release the third semiconductor layer.

[0058] In operation S380, a first gate stack intersecting the first channel portion is formed on the inner side of the gate sidewall, and a second gate stack at least partially surrounding the outer periphery of the third semiconductor layer in a second direction is formed, wherein the first channel portion includes the remaining portions of the first semiconductor layer and the second semiconductor layer.

[0059] To better understand the semiconductor device manufacturing method of this application, the following is based on schematic diagrams of the structure obtained during the manufacturing process of the semiconductor device according to the embodiments of this application, combined with... Figures 1A to 2B , Figures 4-29B The manufacturing method of the embodiments of this application will be described below.

[0060] Figures 4-29B Cross-sectional views along various axes are schematically shown for some stages of a method for manufacturing a semiconductor device according to embodiments of this application. It should be noted that in the various figures shown in this application, when the numbers in the titles of multiple figures are the same, the manufacturing processes corresponding to those multiple figures are the same. When the numbers in the titles of multiple figures are the same but the letters are different, the manufacturing processes corresponding to those multiple figures are the same, but the axes corresponding to those multiple figures are different. For example, Figure 11A and Figure 11B These are cross-sectional views of two axes, representing the same manufacturing process.

[0061] Specifically, Figures 4-7 Cross-sectional views of a semiconductor device according to embodiments of this application are shown at some stages along the X-X' axis and / or the Y-Y' axis; Figures 8A to 29A Cross-sectional views of a semiconductor device according to an embodiment of this application are shown at some stages along the X-X' axis. Figures 8B to 29B The accompanying drawings show cross-sectional views of a semiconductor device according to embodiments of this application at some stages along the Y-Y' axis. The tilde "~" in the drawings represents the space released during the etching process. It should be noted that the following manufacturing method uses a P-type first field-effect transistor as the lower layer and an N-type second field-effect transistor as the upper layer as an example. The manufacturing methods for other types of devices are similar and will not be elaborated upon in this application.

[0062] refer to Figure 4 and Figure 5 A first substrate SUB1 and a second substrate SUB2 can be provided, and pretreatment operations such as trap lithography, ion implantation, annealing, and cleaning can be sequentially performed on the first substrate SUB1 and the second substrate SUB2. The first substrate SUB1 and the second substrate SUB2 can be bulk semiconductor substrates or semiconductor-on-insulator substrates. Bulk semiconductor substrates can include Si or Ge, and semiconductor-on-insulator substrates can include SOI or GeOI.

[0063] refer to Figure 6 and Figure 7 A first stacked structure can be formed on a first substrate SUB1 and a second stacked structure can be formed on a second substrate SUB2 using an epitaxial growth process. The first stacked structure may include alternating first semiconductor layers 101 and 102. The second stacked structure may include alternating third and fourth semiconductor layers 103 and 104. The first semiconductor layer 101 and the third semiconductor layer 103 may include Si or Ge. The doping elements between the first semiconductor layer 101 and the third semiconductor layer 103 may be different; for example, the first semiconductor layer 101 may be N-type doped, and the third semiconductor layer 103 may be P-type doped. The second semiconductor layer 102 and the fourth semiconductor layer 104 may include SiGe.

[0064] The germanium concentrations of the second semiconductor layer 102 and the fourth semiconductor layer 104 can be different. For example, the second semiconductor layer 102 can have a first germanium concentration, and the fourth semiconductor layer 104 can have a second germanium concentration. The first germanium concentration and the second germanium concentration can be different so that the etching rate of the fourth semiconductor layer 104 is higher than the etching rate of the second semiconductor layer 102.

[0065] In some embodiments, the percentage of Ge atoms in the fourth semiconductor layer 104 may be 5% to 50% higher than the percentage of Ge atoms in the second semiconductor layer 102. Specifically, the percentage of Ge atoms in the second semiconductor layer 102 may be 15% to 25%, and the percentage of Ge atoms in the fourth semiconductor layer 104 may be 25% to 35%, etc. Furthermore, the fourth semiconductor layer 104 may be thicker in the vertical direction than the second semiconductor layer 102 in the vertical direction.

[0066] Continue to refer to Figure 6 and Figure 7A first dielectric layer 105A may be formed on the top surface of the first stacked structure, and a second dielectric layer 105B may be formed on the top surface of the second stacked structure. Alternatively, the second substrate SUB2 may be a semiconductor-on-insulator substrate, such as an SOI substrate; the second stacked structure is formed on the SOI substrate. For example, the second substrate SUB2 may include a base substrate, a buried oxide layer 105C on the base substrate, and a top silicon layer on the buried oxide layer 105C, designated as 103 herein, as a third semiconductor layer in the second stacked structure.

[0067] refer to Figure 8A and Figure 8B The first dielectric layer 105A and the second dielectric layer 105B can be bonded together, and the bonded first dielectric layer 105A and the second dielectric layer 105B are used as an isolation layer 105. Then, the second substrate SUB2 can be thinned to use the thinned second substrate SUB2 as the third semiconductor layer 103. Alternatively, the base substrate and buried oxide layer 105C of the second substrate SUB2 can be removed to expose the top silicon layer (as the third semiconductor layer 103).

[0068] refer to Figure 9A and Figure 10A as well as Figure 9B and Figure 10B The fin pattern can be defined using a sidewall transfer (SIT) process. For example, sidewalls 106 can be formed. The material of sidewalls 106 can be silicon nitride, etc. In the embodiments of this application, a mandrel 107 can be formed on the second stacked structure, and the mandrel 107 can be patterned using a photolithography process to obtain a linear pattern extending along the first direction (X-X' axis). The material of the mandrel 107 can be polycrystalline silicon or amorphous silicon, etc. Sidewalls 106 are formed on the sidewalls of the mandrel 107, and the patterned mandrel 107 is removed after the sidewalls 106 are formed, so that only the sidewalls 106 remain on the stacked structure, thereby completing the fabrication of the sidewalls 106. Based on this, the second stacked structure (third semiconductor layer 103 and fourth semiconductor layer 104), the isolation layer 105, the first stacked structure (first semiconductor layer 101 and second semiconductor layer 102) and the first substrate SUB1 can be etched according to the pattern of the sidewall 106 using anisotropic etching process to form fins located on the first substrate SUB1 and etched areas distributed on both sides of the fins in the second direction.

[0069] refer to Figure 11A and Figure 11B Within the etched area, a first dielectric layer 108 is deposited, and the first dielectric layer 108 is etched using a back-etching process to be lower than or equal to the upper surface of the lower fin formed by the first substrate SUB1, thereby using the first dielectric layer 108 as a shallow trench isolation (STI). The dielectric layer in the embodiments of this application may include silicon dioxide or silicon nitride, etc.

[0070] refer to Figures 12A-14A as well as Figures 12B to 14B A sacrificial gate spanning the fins can be formed on the first dielectric layer 108 using processes such as thermal oxidation, chemical vapor deposition, or sputtering. The sacrificial gate, from bottom to top, comprises a gate oxide layer 109, a silicon layer 110, and a hard mask layer 111. The gate oxide layer 109 can be made of materials such as SiO2. The silicon layer 110 is made of amorphous silicon or polycrystalline silicon. The hard mask layer 111 can be made of materials such as nitrides, oxides, carbides, or organic materials. Based on this, a gate sidewall 112 can be formed on the sidewalls of the sacrificial gate using a sidewall formation process. The gate sidewall 112 can be made of materials such as SiCNO. The second stacked structure (third semiconductor layer 103 and fourth semiconductor layer 104), the isolation layer 105, and the first stacked structure (first semiconductor layer 101 and second semiconductor layer 102) can be etched according to the pattern of the sacrificial gate and the gate sidewall 112, thereby exposing the sidewalls of the second stacked structure, the isolation layer 105, and the first stacked structure.

[0071] refer to Figures 15A-16A as well as Figures 15B-16B A first source / drain location defining layer 113, in contact with the first stacked structure, can be formed on both sides of the first stacked structure located below the isolation layer 105. A sidewall 114 is then formed on the first source / drain location defining layer 113 using a sidewall forming process. The material of the first source / drain location defining layer 113 may include, but is not limited to, aC (amorphous carbon). The method for forming the first source / drain location defining layer 113 includes, but is not limited to, spin coating. For example, after depositing aC, the deposited aC can be planarized, and the aC can be etched back to a position no higher than the middle of the isolation layer 105. The material of the sidewall 114 includes, but is not limited to, SiN. x The sidewall 114 is used to protect the second stacked structure located above the isolation layer 105, preventing the growth of source / drain at both ends of the channel of the upper device during the growth of the source / drain of the lower device unit. When the types of upper and lower devices are different, the source / drain materials of the upper and lower devices can be different.

[0072] refer to Figures 17A to 19A as well as Figures 17B to 19BAfter forming the sidewalls 114, the first source / drain location defining layer 113 is removed to expose the sidewalls of the first stacked structure (first semiconductor layer 101 and second semiconductor layer 102) located under the isolation layer 105. Source / drain materials are epitaxially grown and in-situ doped on the exposed sidewalls of the first semiconductor layer 101 and second semiconductor layer 102 to form a first source / drain layer 115 connected to the first stacked structure. In this embodiment, the material of the first source / drain layer 115 may be SiGe, and the first source / drain layer 115 may be doped with a p-type dopant such as boron or indium. Before epitaxially growing the first source / drain layer 115, a silicon liner may be grown on the sidewalls of the first semiconductor layer 101 and second semiconductor layer 102 (and the surface of the substrate SUB1), and the first source / drain layer 115 may be epitaxially grown on the silicon liner. For ease of description, the schematic diagram of this embodiment is not shown in the figures. The sidewalls 114 can be selectively etched to expose the sidewalls of the second stacked structure (third semiconductor layer 103 and fourth semiconductor layer 104) located above the isolation layer 105. A second dielectric layer 116 can be deposited on the first source / drain layer 115, and the second dielectric layer 116 can be etched to a position no higher than the isolation layer 105 to electrically isolate the respective source / drain layers of the upper and lower devices. For example, the second dielectric layer 116 comprises oxide.

[0073] Furthermore, the third semiconductor layer 103 and the fourth semiconductor layer 104 may have different selective etching properties relative to each other, and the end of the fourth semiconductor layer 104 in the first direction may be recessed relative to the third semiconductor layer 103 to form an opening. Based on this, a dielectric material can be filled into the opening in the fin created by the selective etching of the third semiconductor layer 103 and the fourth semiconductor layer 104. The portion of the dielectric material filled at the end of the third semiconductor layer 103 serves as an inner sidewall, which is not shown in the figures.

[0074] refer to Figure 20A and Figure 21B Source / drain materials are epitaxially grown and in-situ doped on the sidewalls of the exposed third semiconductor layer 103 and fourth semiconductor layer 104, or on the sidewall of the third semiconductor layer 103 (in the case of forming inner sidewalls), thereby forming a second source / drain layer 117 in contact with the second stacked structure. In the embodiments of this application, the material of the second source / drain layer 117 can be SiC, and the second source / drain layer 117 can be doped with N-type dopants such as phosphorus, arsenic, indium, etc. The first source / drain layer 115 and the second source / drain layer 117 can be activated, for example, by using a rapid thermal annealing technique below 900°C to activate the impurities in the source / drain layers, thereby forming the activated first source / drain layer 115 and the second source / drain layer 117.

[0075] refer to Figures 21A-23A as well as Figures 21B-23BA third dielectric layer 118 is formed on the first substrate SUB1 and planarized. Planarization removes the hard mask layer 111 in the sacrificial gate, exposing the silicon layer 110. Then, the silicon layer 110 and the gate oxide layer 109 are etched using a selective etching process to expose the sidewalls of the second semiconductor layer 102 and the fourth semiconductor layer 104 (as well as the first semiconductor layer 101 and the third semiconductor layer 103) in the second direction. The second semiconductor layer 102 and the fourth semiconductor layer 104 are etched using a selective etching process via the exposed sidewalls, thereby releasing space inside the gate sidewall 112. Since the released space is subsequently used to form the gate stack, it is therefore referred to hereinafter as the gate space.

[0076] Continue to refer to Figure 23A and Figure 23B The second semiconductor layer 102 and the fourth semiconductor layer 104 can have different selective etching rates relative to each other, so that the fourth semiconductor layer 104 can be etched at a faster rate than the second semiconductor layer 102, thus retaining a portion of the second semiconductor layer 102. Upon completion of selective etching, the second semiconductor layer 102 in the first stacked structure can be partially removed, so that the remaining portion of the second semiconductor layer 102 in the first stacked structure forms a first channel with the first semiconductor layer 101, and the fourth semiconductor layer 104 in the second stacked structure is removed, thus releasing the third semiconductor layer 103 to form a second channel. Since the second semiconductor layer 102 is etched from opposite sides in the second direction, and the etching rates on both sides can be approximately the same, the etching depth of the second semiconductor layer 102 on both sides can be substantially the same, so that the remaining portion can be located in the middle of the first semiconductor layer 101 in the second direction. In some embodiments, the first semiconductor layer 101 and the third semiconductor layer 103 may also have different etching selectivity relative to each other, such that the thicknesses of the first semiconductor layer 101 and the third semiconductor layer 103 in the vertical direction may be substantially different. Furthermore, it should be understood that, based on the different selective etching properties of the second semiconductor layer 102 and the fourth semiconductor layer 104 relative to each other (e.g., this etching selectivity may be determined by the atomic percentage of Ge in the semiconductor layer), the second semiconductor layer 102 and the fourth semiconductor layer 104 may have different thicknesses relative to each other; for example, the thickness of the second semiconductor layer 102 in the vertical direction may be greater than the thickness of the fourth semiconductor layer 104 in the vertical direction. Therefore, after etching the second semiconductor layer 102 and the fourth semiconductor layer 104, the thickness of the second semiconductor layer 102 in the vertical direction is greater than the vertical spacing distance of adjacent third semiconductor layers 103. Furthermore, the thickness of the second semiconductor layer 102 in the vertical direction is greater than the vertical spacing distance between the bottommost third semiconductor layer 103 and the isolation layer 105.

[0077] refer to Figures 24A-26A as well as Figures 24B-26B A first gate stack surrounding a first channel portion and a second gate stack surrounding a second channel portion are sequentially formed on the inner sidewall of the gate space. The first gate stack may include a gate dielectric layer 119 and a first gate conductor 120. The material of the gate dielectric layer 119 may be a high-k dielectric material, where K represents the dielectric constant. High-k dielectric materials include HfO2, HfSiOx, HfON, HfSiON, and HfAlO. x HfLaO x Al2O3, ZrO2, ZrSiO x The first gate conductor 120 may include a first work function layer and a conductor layer. In this embodiment, the first work function layer may be a p-type work function layer, and the material of the first work function layer may be p-type doped titanium nitride, etc.

[0078] In some embodiments, a protective layer may be formed on the first substrate SUB1 and etched to the top surface between the top and bottom surfaces of the isolation layer 105 to shield the cavity for the underlying device, thereby protecting the first work function layer in the gate space below the isolation layer 105 while exposing the gate space above the isolation layer 105.

[0079] The gate dielectric layer 119 above the isolation layer 105 is retained by selectively etching the first work function layer above the isolation layer 105. Then, a second gate conductor 121 is formed surrounding the gate dielectric layer 119 above the isolation layer 105. The second gate stack may include the gate dielectric layer 119 and the second gate conductor 121. The second gate conductor 121 may include a second work function layer and a conductor layer. In this embodiment, the second work function layer may be an N-type work function layer, and the material of the second work function layer may be N-type doped titanium nitride, etc. In this embodiment, the first gate conductor 120 and the second gate conductor 121 are substantially in contact with each other. In other embodiments, the first gate conductor 120 and the second gate conductor 121 may also be isolated from each other.

[0080] Therefore, a first gate stack surrounding the first channel portion and a second gate stack surrounding the second channel portion are formed above and below the isolation layer 105, respectively. Thus, the third semiconductor layer 106, the second gate stack, and the second source / drain layer 117 located above the isolation layer 105 constitute a second field-effect transistor, such as the N-type field-effect transistor in this embodiment; the first semiconductor layer 101, the second semiconductor layer 102, the first gate stack, and the first source / drain layer 115 located below the isolation layer 105 constitute a first field-effect transistor, such as the P-type field-effect transistor in this embodiment, thereby obtaining a stacked field-effect transistor.

[0081] It should be understood that the above is only one embodiment of this application. In the manufacturing process of other embodiments of this application, N-type field-effect transistors or P-type field-effect transistors can be formed as needed by changing the doping type of the source / drain layers and forming corresponding work function layers. For example, the upper N-type field-effect transistor can be formed as a P-type field-effect transistor, or the lower P-type field-effect transistor can be formed as an N-type field-effect transistor.

[0082] After fabricating the first and second field-effect transistors, the protective layer is removed, thereby releasing the cavity beneath the isolation layer 105. Then, conductive material is deposited throughout the gate space to form a conductive layer, thus completing the fabrication of the gate structure. The conductive material in this embodiment may include tungsten or the like. After forming the conductive layer, it can be planarized.

[0083] refer to Figures 27A-28A as well as Figures 27B-28B Dielectric material is deposited on the planarized conductive layer. The deposited dielectric material and the previous third dielectric layer 118 can be used together to form the third dielectric layer 118 (still referred to as 118 here). On this basis, various interconnect structures such as contact plugs 122 can be fabricated in the third dielectric layer 118.

[0084] refer to Figure 29A and Figure 29B as well as Figure 2A and Figure 2B The device is inverted, and a substrate 123 is bonded to the bottom of the inverted device, such as a carrier wafer. The first substrate SUB1 is thinned to near the first dielectric layer 108, exposing the first dielectric layer 108.

[0085] Return to reference Figure 2A and Figure 2B The first substrate SUB1 is selectively etched away until the first gate stack 115 is exposed. The space released by removing the first substrate SUB1 is then filled with a dielectric material such as oxide to form a fourth dielectric layer 124. Various interconnect structures, such as contact plugs 122, can be fabricated in this fourth dielectric layer 124. This results in... Figure 2A and Figure 2B The semiconductor device shown.

[0086] According to an embodiment of this application, the first channel portion of the first field-effect transistor in the semiconductor device includes alternating stacked first and second semiconductor layers in a vertical direction, with the ends of the second semiconductor layers recessed in a second direction; the second channel portion of the second field-effect transistor includes a plurality of third semiconductor layers stacked at intervals. In this way, optimization can be performed separately for the N-type and P-type field-effect transistors of the CFET device, improving the overall performance of the CFET device and synergistically achieving characteristic modulation of different transistors in the unit circuit. The above manufacturing method is compatible with CFET device integration technology and utilizes a fishbone-shaped channel structure to increase the effective conductive channel width, continuously improving the driving performance of the field-effect transistor; it is also more conducive to improving the source / drain epitaxial quality of the CFET device and optimizing the channel stress distribution.

[0087] Those skilled in the art will understand that the features described in the various embodiments of this application can be combined and / or combined in various ways, even if such combinations or combinations are not explicitly described in this application. In particular, the features described in the various embodiments of this application can be combined and / or combined in various ways without departing from the spirit and teachings of this application. All such combinations and / or combinations fall within the scope of this application.

[0088] The embodiments of this application have been described above. However, these embodiments are merely illustrative and not intended to limit the scope of this application. Although various embodiments have been described above, this does not mean that the measures in the various embodiments cannot be used advantageously in combination. Without departing from the scope of this application, those skilled in the art can make various substitutions and modifications, all of which should fall within the scope of this application.

Claims

1. A semiconductor device, characterized in that, include: A first field-effect transistor and a second field-effect transistor are stacked on a substrate in a vertical direction; as well as An isolation layer lies between the first field-effect transistor and the second field-effect transistor, wherein, The first field-effect transistor includes: The first channel portion extending along a first direction includes a plurality of first semiconductor layers stacked at intervals in a vertical direction and a second semiconductor layer extending vertically between adjacent first semiconductor layers in the vertical direction, wherein the two ends of the second semiconductor layer in a second direction are recessed in the second direction relative to the two ends of the first semiconductor layer in the second direction, and the second direction intersects the first direction. The first source / drain layers are located on opposite sides of the first channel portion in a first direction; and A first gate stack intersecting the first channel portion in the second direction; The second field-effect transistor includes: The second channel portion extending along the first direction includes a plurality of third semiconductor layers stacked at intervals from each other in the vertical direction; The second source / drain layer is located on opposite sides of the second channel portion in the first direction; The second gate stack at least partially surrounds the outer periphery of the plurality of third semiconductor layers in the second direction.

2. The semiconductor device according to claim 1, characterized in that, The second semiconductor layer comprises a semiconductor material that has etch selectivity relative to the first semiconductor layer.

3. The semiconductor device according to claim 1, characterized in that, The first field-effect transistor is either an N-type field-effect transistor or a P-type field-effect transistor, and the second field-effect transistor is either an N-type field-effect transistor or a P-type field-effect transistor. Furthermore, the first field-effect transistor is either an upper-layer field-effect transistor or a lower-layer field-effect transistor, and the second field-effect transistor is either an upper-layer field-effect transistor or a lower-layer field-effect transistor.

4. The semiconductor device according to claim 1, characterized in that, The semiconductor device further includes inner sidewalls, with the second gate stack and the second source / drain layer spaced apart from each other via the inner sidewalls, or The second gate stack is adjacent to the second source / drain layer.

5. The semiconductor device according to claim 1, characterized in that, in, The thickness of the second semiconductor layer in the vertical direction is greater than the vertical spacing between adjacent third semiconductor layers; and / or The thickness of the second semiconductor layer in the vertical direction is greater than the distance between the bottom third semiconductor layer and the isolation layer in the vertical direction.

6. The semiconductor device according to claim 1, characterized in that, The isolation layer includes a first dielectric layer and a second dielectric layer stacked in the vertical direction.

7. The semiconductor device according to claim 1, characterized in that, The proportion of the (110) crystal plane in the first channel portion that is connected to the first gate stack is greater than the proportion of the (110) crystal plane in the second channel portion that is connected to the second gate stack.

8. The semiconductor device according to claim 1, characterized in that, The second semiconductor layer extends between and is in contact with the first source / drain layers on opposite sides in the first direction, is located substantially in the middle of the first semiconductor layer in the second direction, and is in contact with the first semiconductor layer in the vertical direction.

9. A method for manufacturing a semiconductor device, characterized in that, include: A first stacked structure and a second stacked structure stacked vertically are disposed on a first substrate, and an isolation layer is disposed between the first stacked structure and the second stacked structure. The first stacked structure includes alternating first semiconductor layers and second semiconductor layers, and the second stacked structure includes alternating third semiconductor layers and fourth semiconductor layers. The first semiconductor layer and the second semiconductor layer have different selective etching properties relative to each other, the third semiconductor layer and the fourth semiconductor layer have different selective etching properties relative to each other, and the second semiconductor layer and the fourth semiconductor layer have different selective etching properties relative to each other. The first stacked structure, the second stacked structure, and the isolation layer, together with the upper part of the first substrate, are patterned to form fins extending along a first direction; A sacrificial gate is formed on the first substrate, extending along a second direction intersecting the first direction and thus intersecting the fin; A gate sidewall is formed on the sidewall of the sacrificial gate; Using the sacrificial gate and the gate sidewall as a mask, the first stacked structure, the second stacked structure, and the isolation layer are patterned, so that the patterned first stacked structure, the second stacked structure, and the isolation layer have side surfaces exposed in the first direction; A first source / drain layer is formed that is in contact with the side surface of the first stacked structure exposed in the first direction, and a second source / drain layer is formed that is in contact with the side surface of the second stacked structure exposed in the first direction. After removing the sacrificial gate, the first stacked structure, the second stacked structure, and the isolation layer have side surfaces exposed in the second direction. Selective etching is performed on the first semiconductor layer, the second semiconductor layer, the third semiconductor layer, and the fourth semiconductor layer via the side surfaces exposed in the second direction of the first stacked structure, the second stacked structure, and the isolation layer, such that when the selective etching is completed, the second semiconductor layer in the first stacked structure is partially removed, leaving a remainder between the first semiconductor layers, and the fourth semiconductor layer in the second stacked structure is removed, thereby releasing the third semiconductor layer; as well as Inside the gate sidewall, a first gate stack is formed that intersects with the first channel portion, and a second gate stack is formed that at least partially surrounds the outer periphery of the third semiconductor layer in the second direction, wherein the first channel portion includes the remaining portions of the first semiconductor layer and the second semiconductor layer.

10. The method according to claim 9, characterized in that, A first stacked structure and a second stacked structure stacked vertically on a first substrate, and an isolation layer between the first stacked structure and the second stacked structure, are disposed thereon, including: The first stacked structure and the first dielectric layer disposed on the top surface of the first stacked structure are disposed on the first substrate; The second stacked structure and the second dielectric layer disposed on the top surface of the second stacked structure are disposed on the second substrate; The first dielectric layer and the second dielectric layer are bonded together, wherein the bonded first dielectric layer and the second dielectric layer serve as the isolation layer.

11. The method according to claim 10, characterized in that, The first substrate is a bulk semiconductor substrate or a semiconductor-on-insulator substrate, and the second substrate is a bulk semiconductor substrate or a semiconductor-on-insulator substrate. The bulk semiconductor substrate includes Si or Ge, and the semiconductor-on-insulator substrate includes SOI or GeOI.

12. The method according to any one of claims 9 to 11, characterized in that, The first semiconductor layer comprises Si or Ge, the third semiconductor layer comprises Si or Ge; the second semiconductor layer and the fourth semiconductor layer comprise SiGe; The second semiconductor layer has a first germanium concentration, and the fourth semiconductor layer has a second germanium concentration. The first germanium concentration is different from the second germanium concentration, so that the etching rate of the fourth semiconductor layer is higher than that of the second semiconductor layer.

13. The method according to claim 12, characterized in that, The percentage of Ge atoms in the fourth semiconductor layer is 5% to 50% higher than the percentage of Ge atoms in the second semiconductor layer.

14. The method according to any one of claims 9 to 11, characterized in that, The fourth semiconductor layer is thicker in the vertical direction than the second semiconductor layer in the vertical direction.

Images