Semiconductor device and method of manufacturing a semiconductor device

Abstract

According to various embodiments, a method of fabricating a semiconductor device includes exposing a first source / drain structure and a second source / drain structure to a selective deposition material, wherein the first source / drain structure includes a first conductivity type dopant and the second source / drain structure includes a second conductivity type dopant, and allowing a first silicide layer to form on the first source / drain structure while no silicide layer forms on the second source / drain structure due to a deposition selectivity of the selective deposition material. According to various embodiments, a height of the first source / drain structure and a width of the first source / drain structure are different, and the first source / drain structure extends into a semiconductor structure. Embodiments of the present application also relate to a semiconductor device and a method of fabricating a semiconductor device.

Description

Technical Field

[0001] Embodiments of this application relate to semiconductor devices and methods of manufacturing semiconductor devices. Background Technology

[0002] The integrated circuit (IC) industry has experienced rapid growth, driven by continuous technological advancements in materials and circuit design. These advancements have enabled successive generations of ICs to feature smaller and more complex circuits than their predecessors. Over time, the functional density of ICs (i.e., the number of interconnect devices per unit chip area) has generally increased, while the minimum geometry (the smallest component or line that can be formed using a given manufacturing process) has decreased. This trend of device scaling has already provided significant benefits, including improved production efficiency and reduced manufacturing costs. However, continued scaling also introduces greater complexity into IC handling and manufacturing, requiring corresponding innovations in manufacturing technologies to fully realize the advantages of advanced IC designs. Summary of the Invention

[0003] Some embodiments of this application provide a semiconductor device including: a first gate formed in a first region of a substrate; a second gate formed in a second region of the substrate; a first source / drain component located above a first opposite side of the first gate; a second source / drain component located above a second opposite side of the second gate; a first silicide structure including a first silicide component located above the first source / drain component; a second silicide structure including a second silicide component located above the second source / drain component; a first source / drain contact electrically coupled to the first silicide structure; and a second source / drain contact electrically coupled to the second silicide structure, wherein: the first silicide component and the second silicide component comprise different materials and have curved profiles; and the second silicide structure comprises at least one of Mo, TiN, W, or Ru.

[0004] Other embodiments of this application provide a method for manufacturing a semiconductor device, comprising: exposing a first source / drain structure and a second source / drain structure to a deposition material, wherein the first source / drain structure includes a first conductivity type dopant and the second source / drain structure includes a second conductivity type dopant; and depositing a first silicide layer on the first source / drain structure, wherein due to the deposition selectivity of the deposition material, the deposition rate of the silicide layer formed on the second source / drain structure is less than the deposition rate of the silicide layer formed on the first source / drain structure, wherein the height and width of the first source / drain structure are different, and the first source / drain structure extends into a semiconductor structure.

[0005] Some embodiments of this application provide a method for manufacturing a semiconductor device, comprising: forming a gate structure over a channel region, wherein the gate structure includes a gate spacer disposed along a sidewall of the gate structure, the gate structure including a gate dielectric layer and a gate electrode located above the gate dielectric layer, wherein the dielectric constant of the gate dielectric layer is greater than the dielectric constant of the gate spacer, and wherein a first thickness of the gate spacer is greater than a second thickness of the gate dielectric layer; exposing a first source / drain structure and a second source / drain structure to a first deposited material, wherein the first source / drain structure includes a first conductivity type dopant, and the... The second source / drain structure includes a second conductivity type dopant; a first silicide layer having a first composition is deposited on the first source / drain structure, and an intermediate silicide layer having a second composition is deposited on the second source / drain structure; an etching operation is performed to remove the intermediate silicide layer having the second composition, wherein the intermediate silicide layer having the second composition exhibits a faster etching rate in the etching operation than the first silicide layer having the first composition; the first silicide layer and the second source / drain structure are exposed to a second deposition material; and a second silicide layer having a third composition is deposited on the second source / drain structure. Attached Figure Description

[0006] Various aspects of the embodiments of this disclosure will be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard industry practice, the various components are not drawn to scale. In fact, for clarity of discussion, the dimensions of the various components may be arbitrarily increased or decreased.

[0007] Figure 1A This is a layout diagram showing a plan view of a semiconductor device according to various embodiments.

[0008] Figure 1B According to the various embodiments, it corresponds to Figure 1A The layout diagram is a circuit diagram of a static random access memory (SRAM) cell, which is a part of a semiconductor device.

[0009] Figure 2A This is a layout diagram showing a plan view of a semiconductor device according to various embodiments.

[0010] Figure 2B It is based on the various embodiments corresponding to Figure 2A A vertical cross-sectional view of a portion of a semiconductor device in a layout diagram.

[0011] Figure 3 This is a layout diagram showing a plan view of a semiconductor device according to various embodiments.

[0012] Figure 4A , Figure 5A , Figure 6A , Figure 7A and Figure 8A According to various embodiments Figure 3 A vertical cross-sectional view of a portion of a semiconductor device, wherein the GAA transistor device has an S / D component of a first conductivity type.

[0013] Figure 4B , Figure 5B , Figure 6B , Figure 7B and Figure 8B According to various embodiments Figure 3 A vertical cross-sectional view of a portion of a semiconductor device, wherein the GAA transistor device has an S / D component of a second conductivity type.

[0014] Figure 9 It is a table of data related to the reaction kinetics of selectively forming MoSiGe on SiGe, according to various embodiments.

[0015] Figures 10A to 10D It is according to the various embodiments for forming Figure 4A and Figure 4B A vertical cross-sectional view of the structure of a GAA transistor device.

[0016] Figure 11 It is a table of data related to the reaction kinetics of selective etching of TiSiGe on SiGe, according to various embodiments.

[0017] Figures 12A to 12D It is according to the various embodiments for forming Figures 6A to 7B A vertical cross-sectional view of the structure of a GAA transistor device.

[0018] Figures 13A to 13D It is according to the various embodiments for forming Figure 8A and Figure 8B A vertical cross-sectional view of the structure of a GAA transistor device.

[0019] Figure 14 This is a flowchart of the operation of a method for manufacturing a semiconductor device according to various embodiments.

[0020] Figure 15 This is a flowchart of the operation of a method for manufacturing a semiconductor device according to various embodiments. Detailed Implementation

[0021] The following disclosure provides numerous different embodiments or instances for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below to simplify embodiments of this disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first component on or over a second component may include embodiments where the first and second components are in direct contact, and may also include embodiments where one or more additional components may be formed between the first and second components, such that the first and second components are not in direct contact. Furthermore, reference numerals and / or characters may be repeated in various instances of embodiments of this disclosure. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0022] Furthermore, for ease of description, this document may use spatial relative terms such as “below,” “under,” “lower,” “above,” and “upper” to describe the relationship between one element or component and another (or other) element or component as shown in the figures. In addition to the orientations depicted in the figures, spatial relative terms are intended to include different orientations of the device in use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein may be interpreted accordingly. Furthermore, the term “made of” may mean either “comprising” or “consisting of.” In embodiments of this disclosure, the phrase “one of A, B, and C” means “A, B, and / or C” (A, B, C, A and B, A and C, B and C, or A, B, and C) and does not mean an element from A, an element from B, and an element from C, unless otherwise described.

[0023] The disclosed embodiments advantageously allow for the individual minimization of source / drain resistance for transistor devices with n-type doped source / drain components and p-type doped source / drain components by using different materials for the first silicide structure formed over the n-type doped S / D component and the second silicide structure formed over the p-type doped S / D component. In this respect, the disclosed devices and methods overcome the disadvantages of using a single silicide material, which, in comparative embodiments, tends to benefit either n-type or p-type transistors, but not both, due to the different Schottky barrier height (SBH) issues. The disclosed method involves self-aligning the first and second silicide structures using selective deposition and etching techniques that require only simple processes (rather than complex individual patterning operations).

[0024] Figure 1A This is a plan view of the layout diagram 100a of the semiconductor device, and Figure 1BAccording to the various embodiments, it corresponds to Figure 1A A circuit diagram 100b is a portion of a static random access memory (SRAM) cell of a semiconductor device, as shown in layout diagram 100a. Layout diagram 100a includes layout patterns corresponding to an oxide diffusion (OD) layer (referred to as "OD" in the legend) and a gate polysilicon (PO) layer (referred to as "PO" in the legend). In some embodiments, the layout pattern included in the OD layer (referred to as the "OD layout pattern") indicates the formation of various active regions of the semiconductor device, and the layout pattern included in the PO layer (referred to as the "PO layout pattern") indicates the formation of a corresponding gate structure. In a corresponding embodiment, the gate structure 214 (e.g., see...) Figure 2B This corresponds to a polysilicon gate structure or a metal gate structure formed using a polysilicon structure as a sacrificial placeholder.

[0025] Figure 1A Some of the OD layout patterns in the diagram correspond to patterns formed by subtracting the removed portions defined by the cut OD (COD) pattern group from a repeating OD pattern group. Similarly, Figure 1A The PO layout pattern in the diagram corresponds to the pattern formed by subtracting the removed portion defined by the cut PO (CPO) pattern group from the repeating PO pattern group (CPO pattern, sometimes also called "cut metal gate" (CMG) pattern).

[0026] exist Figure 1A In the layout diagram 100a, the portion corresponding to the circuit block, such as a memory cell array, includes multiple circuit cells (e.g., based on...). Figure 1B (Exemplary SRAM cell 100b, a memory cell described below). For example, cell regions 102 and 104 represent two memory cells in a memory cell array, each corresponding to... Figure 1B The configuration shown includes a p-type read transfer gate transistor (RPG).

[0027] exist Figure 1A In the layout diagram 100a, among other aspects, OD layout patterns 111, 112, 114, 115, 116, 117, 118, and 119 indicating the active regions of the resulting semiconductor device are included. In this embodiment, the semiconductor device includes active regions corresponding to OD layout patterns 111, 114, 115, and 118 for forming p-type transistors, and active regions corresponding to OD layout patterns 112, 116, 117, and 119 for forming n-type transistors. In some embodiments, the active regions extend along a first horizontal direction (e.g., the X direction) and are located on or at least partially embedded in the substrate 210 of the semiconductor device (e.g., see...). Figure 2B ).exist Figure 1AIn the layout diagram 100a, among other aspects, layout patterns 122, 126, 127, 128, and 129 indicating the gate structure of the resulting semiconductor device are also included. In some embodiments, the gate structure extends along a second horizontal direction (e.g., the Y direction) and is positioned above the corresponding active region.

[0028] For example, in order to form a memory cell corresponding to cell region 102, two pull-down transistors PD1 and PD2 are defined based on the gate structures corresponding to the active regions corresponding to OD layout patterns 126 and 127 (e.g., Figure 1B The pull-down transistors PD1 and PD2 in the diagram). Two pull-up transistors PU1 and PU2 are defined based on the gate structures corresponding to the active regions corresponding to the OD layout patterns 126 and 127 of the PO layout pattern 114 (e.g., ...). Figure 1B Pull-up transistors PU1 and PU2 in the diagram). Furthermore, two write transmission gate transistors WPG1 and WPG2 are defined based on the gate structures corresponding to the active regions corresponding to the OD layout pattern 112 (e.g., ...). Figure 1B The write transmission gate transistors WPG1 and WPG2 in the diagram, and the read transmission gate transistor RPG is defined based on the gate structure corresponding to the active region corresponding to the OD layout pattern 129. Figure 1B (Read transmission gate transistor RPG in the middle).

[0029] refer to Figure 1B As mentioned above, SRAM cell 100b can be used to form a memory cell array, such as Figure 1A The first circuit block 102 or the second circuit block 104. As described above, the SRAM cell 100b includes pull-up transistors PU1 and PU2 and pull-down transistors PD1 and PD2. In some embodiments, pull-up transistors PU1 and PU2 are p-type metal-oxide-semiconductor (PMOS) transistors, while pull-down transistors PD1 and PD2 are n-type metal-oxide-semiconductor (NMOS) transistors. Pull-up transistor PU1 and pull-down transistor PD1 are configured as a first inverter coupled between a first power node CVDD and a second power node CVSS, having an input terminal coupled to node 130 and an output terminal coupled to node 132. Similarly, pull-up transistor PU2 and pull-down transistor PD2 are configured as a second inverter coupled between the first power node CVDD and the second power node CVSS, having an input terminal coupled to node 132 and an output terminal coupled to node 130. Figure 1B The various electrical connections indicated in the middle are Figure 1A Not shown, and provided by various interconnects formed on different metallization layers.

[0030] In some embodiments, the first power node CVDD is electrically coupled to the resulting memory cell array (e.g., ...). Figure 1A The first circuit block 102 in the array has a voltage drain (VDD) supply voltage node and is configured to carry a first supply voltage. A second power supply node CVSS is electrically coupled to a ground reference node or a voltage source (VSS) supply voltage node of the resulting memory cell array and is configured to carry a second supply voltage. In some embodiments, the voltage level of the first supply voltage is greater than the voltage level of the second supply voltage. The voltage difference between the first and second supply voltages can be in the range of 0.5 volts to 2.5 volts.

[0031] In this embodiment, the SRAM cell 100b further includes a first write transmission gate transistor WPG1 and a second write transmission gate transistor WPG2, both of which are NMOS transistors. Figure 1B In this configuration, the second write transmission gate transistor WPG2 is coupled between node 130 and the write bit line WBL, while the first write transmission gate transistor WPG1 is coupled between node 132 and the complementary write bit line WBLB. The gate terminals of both the first write transmission gate transistor WPG1 and the second write transmission gate transistor WPG2 are coupled to the write word line WWL. The SRAM cell 100b also includes a read transmission gate transistor RPG, which is a PMOS transistor. Figure 1B In the read transmission gate transistor RPG, the read bit line RBL is coupled between node 130 and the read bit line RBL, and its gate terminal is coupled to the read word line RWL.

[0032] In operation, pull-up transistors PU1 and PU2 and pull-down transistors PD1 and PD2 form a latch to store data bit values ​​and complementary data bit values ​​at nodes 130 and 132. In some embodiments, when SRAM cell 100b is selected for a write operation, the write word line WWL is configured to carry a first reference voltage to turn on the first write transmission gate transistor WPG1 and the second write transmission gate transistor WPG2, allowing the input data bit values ​​and complementary input data bit values ​​on the write bit line WBL and the complementary write bit line WBLB to be transferred to nodes 130 and 132. In some embodiments, when SRAM cell 100b is selected for a read operation, the read word line RWL is configured to carry a second reference voltage to turn on the read transmission gate transistor RPG, enabling the data bit values ​​stored at node 130 to be transferred to the read bit line RBL.

[0033] In this embodiment, SRAM cell 100b corresponds to a 7-transistor (7T) SRAM cell formed based on seven transistors, including pull-up transistors PU1 and PU2, pull-down transistors PD1 and PD2, write transmission gate transistors WPG1 and WPG2, and read transmission gate transistor RPG. SRAM cell 100b includes three p-type transistors (i.e., transistors PU1, PU2, and RPG) and four n-type transistors (i.e., transistors PD1, PD2, WPG1, and WPG2). In other embodiments, other configurations of SRAM cell 100b are possible. For example, in other embodiments, n-type transistors RPG, WPG1, and WPG2 can be replaced with p-type transistors.

[0034] Figure 2A Layout diagram 200a shows a plan view of a semiconductor device, and Figure 2B According to the various embodiments along Figure 2A A vertical cross-sectional view of the semiconductor device along line B-B'. At this point, Figure 2A Layout diagram 200a is Figure 1A A simplified version of the layout diagram 100a, in which the indications of n-type transistors (WPG1, PD1, PD2, WPG2) and p-type transistors (PU1, PU2, RPG) are omitted. Figure 2B The vertical plane of the cross-sectional view (i.e., Figure 2B The XZ plane in the middle) is composed of Figure 2A The section B-B' is indicated. This plane cuts through a segment of the OD layout pattern 112, which includes multiple transistor structures configured as gate-all-around (GAA) transistor devices. Figure 2B The embodiments (including GAA transistor devices) are provided by way of example only, and various other semiconductor devices (e.g., planar field-effect transistors (FETs), fin field-effect transistors (FinFETs), complementary field-effect transistors (CFETs), etc.) are possible in other embodiments.

[0035] Figure 2B Each GAA device includes multiple stacked semiconductor nanostructure layers configured as channel region 216. While in Figure 2B The illustration shows three stacked channel regions 216, but this disclosure is not limited to these embodiments, and various other embodiments include different numbers of channel regions 216, such that the number of channel regions 216 is ≥1. Each device also includes a gate structure 214, which includes a conductive gate electrode layer 215a surrounding each channel layer 216. The gate electrode layer 215a includes a conductive material separated from the plurality of channel layers 216 by a gate dielectric layer 215b.

[0036] The GAA transistor device also includes source / drain (S / D) components formed over the ends of each of the plurality of channel layers 216. According to some embodiments, the S / D components are of similar structure and are collectively referred to as source / drain components. In other words, a given S / D structure can be used as either a source or a drain, depending on how it is configured in a given circuit. Each GAA device also includes an insulating internal spacer layer 220 that further electrically insulates the gate electrode 215a from the S / D components.

[0037] According to various embodiments, a semiconductor device 100a is formed above a semiconductor substrate 210, the semiconductor substrate 210 having a front side (in... Figure 2B (Middle side up) and dorsal side (in) Figure 2B (Middle facing downwards). In this embodiment, Figure 2B The plane intersects the semiconductor layer 210 along the longitudinal direction (i.e., along the

[110] crystallization direction of the S / D component). In some embodiments, the S / D component has a thickness T along a third direction (Z direction) and a width W along a first direction and a second direction, and the thickness T is different from the width W.

[0038] The GAA device also includes front contacts (e.g., metal-to-drain / source (MD) and via-to-drain / source (VD) structures) and back contacts (back-side VD (BVD) structures). Each of the front contact MD and the back contact BVD includes a conductive material coupled to the S / D component. Each of the front contact MD and the back contact BVD also includes a metal silicide layer 236 formed between the contact structure (MD, BVD) and the S / D component. According to various embodiments, the S / D component is formed of a doped semiconductor material (e.g., silicon, SiGe, etc.), and the conductive material of the front contact MD and the back contact BVD is metallic. Therefore, the silicide layer 236 is selected as a metal / semiconductor alloy, such as TiSi, TiSiGe, MoSi, MoSiGe, etc. According to various embodiments, the silicide layer 236 has a thickness between about 0.5 nm and about 10 nm. According to various embodiments, the first conductivity of the metal silicide layer 236 has a value between the second conductivity of the epitaxial semiconductor S / D component and the third conductivity of the front contact MD and the back contact BVD.

[0039] The gate structure 214 further includes a first gate spacer layer 238a and a second gate spacer layer 238b. In some embodiments, the dielectric constant of the second gate spacer layer 238b exceeds that of the first gate spacer layer 238a, and the second gate spacer layer 238b exhibits greater etch resistance compared to the first gate spacer layer 238a. According to some embodiments, the dielectric constant of the gate dielectric layer 215b is greater than that of at least one of the gate spacers (238a, 238b). Furthermore, according to some embodiments, the first thickness t1 of at least one of the gate spacers (238a, 238b) is greater than the second thickness t2 of the gate dielectric layer 215b.

[0040] According to various embodiments, the first gate spacer layer 238a includes silicon oxide, silicon carbide, or a suitable low-k dielectric material in some embodiments. The second gate spacer layer 238b includes silicon carbonitride, silicon nitride, zirconium oxide, aluminum oxide, or a suitable dielectric material in some embodiments.

[0041] Figure 2B The structure also includes a front etch stop layer 240a, a front dielectric layer 232 (e.g., multiple front dielectric layers) formed above the front etch stop layer 240a, a back etch stop layer 240b, and a back dielectric layer 234 (e.g., multiple back dielectric layers) formed above the back etch stop layer 240b. A VD structure is formed within the front dielectric layer 232 and electrically connects the front contact MD to a first front metallization layer M0, which is also formed within the front dielectric layer 232 (or dielectric layer). A first back metallization layer BMO is formed above the back etch stop layer 240b within the back dielectric layer 234. Figure 2B The structure also includes a contact etch stop layer (CESL) 240c. According to various embodiments, CESL 240c comprises silicon nitride, silicon oxynitride, and / or similar materials, and is formed by atomic layer deposition (ALD), plasma-enhanced chemical vapor deposition (PECVD), or other suitable deposition or oxidation processes.

[0042] Figure 2BThe structure also includes a first interposer L0 and a second interposer 242 formed between the S / D component and the first interposer L0. According to some embodiments, the first interposer L0 is an epitaxially formed semiconductor layer. According to some embodiments, the first interposer L0 is undoped silicon or silicon-germanium. The second interposer 242 is a dielectric layer and is referred to in some embodiments as a “flexible bottom isolation” (FBI) structure. The second interposer 242 reduces or substantially prevents current leakage between the S / D component and the semiconductor layer 210 or additional back-side components (such as back-side contacts BVD). In some embodiments, the second interposer 242 comprises silicon oxide, silicon nitride, SiCN, SiCON, SiOC, SiC, or other suitable materials and is formed by oxidation (e.g., to form silicon oxide) or by a conformal deposition process and subsequent further processing, as follows. In other embodiments, the second interposer 242 is an epitaxial semiconductor layer.

[0043] Figure 3 This is a layout diagram 300 showing a plan view of a semiconductor device according to various embodiments. In this respect, Figure 3 The layout diagram 300 is Figure 1A A simplified version of the layout diagram 100a, in which the indications of n-type transistors (WPG1, PD1, PD2, WPG2) and p-type transistors (PU1, PU2, RPG) are omitted. According to various embodiments, Figure 4A , Figure 5A , Figure 6A , Figure 7A and Figure 8A This is in the corresponding embodiment. Figure 3 A vertical cross-sectional view of the first portion of a semiconductor device, wherein GAA transistor devices (400a, 500a, 600a, 700a, 800a) have an S / D component of a first conductivity type, and Figure 4B , Figure 5B , Figure 6B , Figure 7B and Figure 8B This is in the corresponding embodiment. Figure 3 A vertical cross-sectional view of the second part of a semiconductor device, wherein GAA transistor devices (400b, 500b, 600b, 700b, 800b) have S / D components of a second conductivity type.

[0044] Figure 4A , Figure 5A , Figure 6A , Figure 7A and Figure 8A The vertical plane (i.e., the XZ plane) of the cross-sectional view is determined by Figure 3The section A-A' is indicated. This plane cuts through a segment of the OD layout pattern 116, which includes GAA transistor devices (400a, 500a, 600a, 700a, 800a) with n-type doped S / D components. Figure 4B , Figure 5B , Figure 6B , Figure 7B and Figure 8B The vertical plane (i.e., the XZ plane) of the cross-sectional view is determined by Figure 3 The section B-B' is indicated. This plane cuts through a segment of the OD layout pattern 118, which includes GAA transistor devices (400b, 500b, 600b, 700b, 800b) with p-type doped S / D components.

[0045] Each of the transistor devices (400a, 500a, 600a, 700a, 800a) includes a first region formed on the substrate 210 (e.g., see...). Figure 3 The transistor device (400b, 500b, 600b, 700b, 800b) includes a first gate 214a in cross section A-A', a first S / D component 402a formed above a first opposite side (along the X direction) of the first gate 214a, and a first silicide structure 236a formed above the first S / D component 402a. Each transistor device includes a second region formed on the substrate 210 (e.g., see...). Figure 3 The first silicide structure 236a and the second silicide structure 236b are formed in cross section B-B' of the first silicide structure 236a, above the second opposite side (along the X direction) of the second silicide structure 214a, and above the second silicide structure 402a. According to various embodiments, the first silicide structure 236a and the second silicide structure 236b are formed of different materials. According to various embodiments, the first silicide structure 236a and the second silicide structure 236b also have curved profiles.

[0046] According to various embodiments, Figure 4A , Figure 5A , Figure 6A , Figure 7A and Figure 8A The GAA transistor devices (400a, 500a, 600a, 700a, 800a) include a first S / D component 402a, which comprises n-type doped silicon, and Figure 4B , Figure 5B , Figure 6B , Figure 7B and Figure 8B The GAA transistor devices (400b, 500b, 600b, 700b, 800b) include a first S / D component 402b, which comprises p-type doped silicon germanium (SiGe). Figures 4A to 8B In one embodiment, the first silicide structure 236a comprises TiSi, and the second silicide structure 236b comprises MoSiGe. These materials used for the first silicide structure 236a and the second silicide structure 236b are provided by way of example only, but the embodiments disclosed herein are not limited thereto. Other materials used for the first silicide structure 236a and the second silicide structure 236b are possible in other embodiments. Figures 4A to 8B The embodiments also include a capping layer (404a, 404b) formed over the silicide structure (236a, 236b). According to various embodiments, the capping layer (404a, 404b) includes at least one of Mo, TiN, W or Ru.

[0047] Figures 4A to 8B The GAA transistor devices 400a to 800b include similar structures; however, the first silicide structure 236a and the second silicide structure 236b are formed using different processing methods in the respective embodiments. For example, the GAA transistor devices (400a, 400b, 500a, 500b) are formed using a selective deposition method, wherein the MoSiGe layer of the second silicide structure 236b is formed only above the second S / D component 402b, as shown in the following reference. Figures 9 to 10D More detailed description. Then, Figure 4A The first silicide structure 236a is generated through a further process in which TiSi is deposited on top of two GAA transistor structures (400a, 400b). This process generates... Figure 4A The first silicide structure 236a is formed, and a third silicide structure 236c is further formed, namely, a TiSi layer above the MoSiGe layer of the second silicide structure 236b.

[0048] Figure 4A and Figure 4B GAA transistor devices (400a, 400b) and Figure 5A and Figure 5B The differences between the GAA transistor devices (500a, 500b) partially involve the material composition of the capping layers (404a, 404b). For example, Figure 4A and Figure 4B The capping layers (404a, 404b) in the GAA transistor devices (400a, 400b) are formed on... Figure 4A The first silicide structure 236a above and Figure 4B The Mo layer above the third silicide structure 236c. Conversely... Figure 5A and Figure 5BThe capping layers (404a, 404b) in the GAA transistor devices (500a, 500b) are TiN layers formed to contact the first silicide structure 236a and the second silicide structure 236b. According to certain embodiments, with... Figure 4B The embodiments of the GAA transistor device 400b differ from those in the present invention. Figure 5B The GAA transistor device 500b does not exhibit a distinct third silicide structure 236c. Regarding... Figure 5B The TiN material of the second capping layer 404b and other materials present in such a manner as Figure 4B The TiSi mixing in the third silicide structure 236c shown makes it possible to achieve the desired effect. Figure 5B There is no clear interface between the second silicide structure 236b and the second capping layer 404b.

[0049] Figure 6A and Figure 6B The GAA transistor devices (600a, 600b) have the same characteristics as... Figure 5A and Figure 5B The similar structures of GAA transistor devices (500a, 500b), except... Figure 6A and Figure 6B The structures in the data are generated using different processing methods. Figure 6A and Figure 6B The GAA transistor devices (600a, 600b) are fabricated using a method involving selective etching processes, as shown in the reference below. Figures 11 to 12D More detailed description. At this point, the first deposition process is implemented, wherein... Figure 6A and Figure 6B TiSi is deposited over the first S / D component 402a and the second S / D component 402b, which forms a first silicide structure 236a and an intermediate silicide layer 1202 of TiSiGe over the second S / D component 402b, as shown in the following reference. Figure 12B More detailed description. Figure 6B The dashed line in the image indicates that the intermediate silicide layer 1202 has been removed, as shown below.

[0050] A selective etching process is then performed to selectively etch and remove the TiSiGe intermediate silicide layer 1202 above the second S / D component 402b. A second deposition process is then performed, in which a Mo layer (404a, 404b) is deposited over the top surfaces of the first silicide structure 236a and the second S / D component 402b. This Mo layer (404a, 404b) reacts with the doped SiGe of the second S / D component 402b to form a second silicide layer 236b as a MoSiGe layer, and further generates a first capping layer (404a, 404b) and a second capping layer (404a, 404b) as the Mo layer formed over the first silicide layer 236a and the second silicide layer 236b.

[0051] Figure 7A and Figure 7B The GAA transistor devices (700a, 700b) are used to form Figure 6A and Figure 6B The processing method for the GAA transistor devices (600a, 600b) is as follows (see reference below). Figures 11 to 12D As described. Figure 6A and Figure 6B GAA transistor devices (600a, 600b) and Figure 7A and Figure 7B The differences between the GAA transistor devices (700a, 700b) involve the following: Figure 7A A third silicide structure 236c is formed between the first silicide layer 236a and the first capping layer 404a of the GAA transistor device 700a.

[0052] In this respect, under certain processing conditions, the Mo layer 404a deposited over the first silicide structure 236a reacts with the silicon of the TiSi in the first silicide structure 236a to form a third silicide structure 236c. The third silicide layer 236c is a MoSi layer distinct from both the first silicide structure 236a and the first capping layer 404a. Alternatively, under other processing conditions, the Mo layer 404a is mixed with the MoSi layer, resulting in no clear boundary between the MoSi layer and the first capping layer 404a, such as... Figure 6A As shown in the image.

[0053] Figure 8A and Figure 8B The GAA transistor devices (800a, 800b) have the same characteristics as... Figure 5A and Figure 5B The GAA transistor devices (700a, 700b) have essentially the same structure, but are generated using different processing methods. Figure 8A and Figure 8BThe GAA transistor devices (800a, 800b) are fabricated using a method involving selective deposition processes, as shown in the reference below. Figures 13A to 13D More detailed description. Figures 13A to 13D Selective deposition process and Figures 9 to 10D The difference between selective deposition processes and selective deposition processes lies in that, firstly, in Figure 8A A TiSi layer is selectively deposited on the first S / D component 402a of the GAA transistor device 800a, instead of... Figure 8B A similar layer is deposited on the second S / D component 402b of the GAA transistor device 800b.

[0054] Figures 13A to 13D The selective deposition of the process by means of Figure 8B The second S / D component 402b of the GAA transistor device 800b is p-type doped (e.g., ion implanted) without... Figure 8A The first S / D component 402a of the GAA transistor device 800a is implemented using a similar doping operation. This selective doping of the second S / D component 402b makes it less sensitive to the formation of the TiSi layer. Therefore, the TiSi layer is selectively formed on the first S / D component 402a. A second deposition process is then performed to... Figure 8A and Figure 8B A layer of Mo is deposited above the GAA transistor devices (800a, 800b). The Mo layer (404a, 404b) deposited above the second S / D component 402b reacts with the SiGe material of the second S / D component 402b to form a second silicide layer 236b as a MoSiGe layer. Additional Mo deposition results in the formation of a first capping layer 404a and a second capping layer 404b as Mo layers. Reference Figure 8A Under certain processing conditions, the Mo layer 404a deposited above the first silicide structure 236a reacts with the TiSi of the first silicide structure 236a to form a third silicide layer 236c, which is a MoSi layer formed between the first silicide structure 236a and the first capping layer 404a.

[0055] Figure 9 This is a graph 900 showing data related to the reaction kinetics of selectively forming MoSiGe on SiGe according to various embodiments, as used for Figure 4B and Figure 5B The formation of the second silicide layer 236b in the GAA transistor devices (400b, 500b) in the embodiments is as described above. According to various embodiments, the deposition of a MoSiGe layer over an epitaxial SiGe substrate is performed using a thermochemical vapor deposition (CVD) process, which is applied to the epitaxial SiGe layer (e.g., ...). Figure 4B and Figure 5B Above the second S / D component 402b and the silicon layer (e.g., Figure 4A and Figure 5A Molybdenum pentachloride (MoCl5) is introduced above the first S / D component 402a as a gaseous precursor.

[0056] refer to Figure 9 As shown in Figure 900, the energy barrier of 1.55 eV for the adsorption of MoCl5 on SiGe and the formation of MoCl3-Ge is lower than the energy barrier of 1.74 eV for the adsorption of MoCl5 on Si and the formation of MoCl3-Ge. Furthermore, the energy barrier of 1.21 eV for the formation of H-MoCl3 and the release of hydrogen chloride (HCl) above the SiGe surface is lower than the energy barrier of 1.33 eV for the formation of H-MoCl3 and the release of HCl above the Si surface. Therefore, MoCl5 preferentially reacts with the SiGe surface of the second S / D component 402b to form the second MoSiGe silicide layer 236b, rather than forming the corresponding first silicide layer 236a above the first S / D component 402a.

[0057] Selective deposition methods introduce MoCl5 into a deposition chamber while maintaining the substrate at an elevated temperature, for example, ranging from about 500°C to about 700°C. Under these conditions, MoCl5 reacts directly with the surface of the SiGe layer, extracting silicon and germanium atoms to form a MoSiGe alloy layer at the interface. The reaction also generates volatile byproducts, such as HCl, which are removed from the chamber by a vacuum pump or a carrier gas flow.

[0058] According to one embodiment, an epitaxial SiGe layer is exposed to MoCl5-containing vapor to generate a series of gas-phase and solid-phase reactions, which form a MoSiGe alloy layer as... Figure 4B and Figure 5B The second silicide layer 236b is formed. According to various embodiments, during the deposition process, MoCl5 undergoes thermal decomposition at elevated temperatures to form low-valent molybdenum chloride, such as:

[0059]

[0060] In the presence of hydrogen, which can be used as a carrier or reducing gas, MoCl5 can react to produce reduced molybdenum chloride and hydrogen chloride:

[0061]

[0062] According to various embodiments, the volatile intermediate is formed through the interaction between MoCl5 and germanium from the substrate. For example, a molybdenum-germanium chloride complex can be generated in the gas phase.

[0063]

[0064] At the substrate surface, MoCl5 reacts with silicon and germanium atoms from the SiGe layer. These reactions reduce the molybdenum precursor and extract silicon and germanium from the solid to form molybdenum silicide, molybdenum germanide, or ternary MoSiGe alloys.

[0065]

[0066]

[0067] Once molybdenum is formed via reduction, it can alloy with silicon and germanium atoms diffusing from the substrate to form a MoSiGe layer:

[0068]

[0069] The hydrogen chloride formed during these reactions can further react with exposed silicon or germanium to generate volatile etching byproducts.

[0070]

[0071] Furthermore, partially reduced molybdenum chloride (such as MoCl3) can remain as an intermediate and continue to react with the substrate to facilitate the formation of MoSiGe:

[0072]

[0073] This combination of vapor-phase chemistry, surface reaction, and solid-state alloying enables the direct formation of MoSiGe layers from the interaction between MoCl5 and the SiGe substrate. This approach eliminates the need for external silicon or germanium precursors and offers advantages for selective deposition and interface engineering in semiconductor device structures.

[0074] In another embodiment, the MoSiGe layer is formed using a solid-state reaction process. In this method, a layer containing MoCl5 or reduced molybdenum is deposited onto an epitaxial SiGe substrate, and the structure is subsequently subjected to a thermal annealing step. During annealing, the molybdenum reacts with silicon and germanium atoms from the substrate to form a MoSiGe alloy. The reaction proceeds via interdiffusion and alloy formation at the metal-semiconductor interface. The annealing temperature and duration are selected to promote uniform film formation and control the composition and thickness of the resulting MoSiGe. This method enables the formation of metal-silicide-germanide contact structures and may be advantageous for applications requiring precise control of the metal-semiconductor interface.

[0075] Figures 10A to 10D It is according to the various embodiments for forming Figure 4A and Figure 4BVertical cross-sectional views of the structures (1000a, 1000b, 1000c, 1000d) of the GAA transistor devices (400a, 400b). Cross-sectional views of the structures (1000a, 1000b, 1000c, 1000d) and... Figures 4A to 8B Those are the same. In this respect, each of the structures (1000a, 1000b, 1000c, 1000d) includes: a GAA transistor device with an S / D component 402a, which comprises n-type doped silicon on the left-hand side of each figure; and a GAA transistor device with an S / D component 402b, which comprises p-type doped silicon germanium on the right-hand side of each figure. The vertical plane (i.e., the XZ plane) of the cross-sectional view of each structure on the left-hand side is defined by… Figure 3 The section A-A' indicates that section A-A' cuts through... Figure 3 The OD layout pattern 116 segments. The vertical plane (i.e., the XZ plane) of the cross-sectional view of each structure on the right side is composed of... Figure 3 The section B-B' indicates that section B-B' cuts through... Figure 3 The OD layout pattern has 118 segments.

[0076] Each of the structures (1000a, 1000b, 1000c, 1000d) includes a plurality of stacked semiconductor nanostructure layers configured as channel regions 216. Each device also includes a gate structure (214a, 214b) comprising a conductive gate electrode layer 215a surrounding each channel layer 216. The gate electrode layer 215a includes a conductive material separated from the plurality of channel layers 216 by the gate dielectric layer 215b. Each of the structures (1000a, 1000b, 1000c, 1000d) includes source / drain (S / D) components (402a, 402b) formed above the ends of each of the plurality of channel layers 216. The structures (1000a, 1000b, 1000c, 1000d) also include an insulating internal spacer layer 220 electrically insulating the gate electrode 215a from the S / D components.

[0077] Each of the structures (1000a, 1000b, 1000c, 1000d) includes a front dielectric layer 232, a front etch stop layer 240a, and a contact etch stop layer (CESL) 240c. After forming the etch stop layers (240a, 240c) and the front dielectric layer 232, a via opening 1002 is formed in the front dielectric layer 232 to the top surface of the S / D components (402a, 402b). The via opening 1002 is formed by first forming a patterned etch mask above the front dielectric layer. Then, one or more anisotropic etch operations are performed to etch portions through the front dielectric layer 232, the etch stop layers (240a, 240c), and the S / D components (402a, 402b).

[0078] After forming the via opening 1002, a conformal pad layer 1004 comprising silicon nitride is deposited along the via sidewalls and bottom surface to provide dielectric isolation and mechanical support. The conformal pad layer 1004 is then subjected to a controlled thinning process (sometimes called silicon nitride removal (SNR)) in which the pad layer 1004 is partially etched to reduce its thickness while maintaining sidewall coverage.

[0079] Then, structure 1000a is formed by selective deposition using the MoCl5 precursor as described above. Figure 10B Structure 1000b. Reference Figure 10B This process allows the formation of a second silicide layer 236b as a MoSiGe layer over the second S / D component 402b, which includes p-type doped silicon germanium, without forming a corresponding layer over the first S / D component 402a, which includes n-type doped silicon. In some embodiments, a MoSi layer is also formed on the first S / D component 402a, having a thickness significantly smaller than that of the MoSiGe layer formed over the second S / D component 402b. Furthermore, in some embodiments, the resulting thin MoSi layer is removed in a subsequent cleaning process.

[0080] As described above, according to various embodiments, this selective deposition process involves implementing a CVD process that introduces molybdenum pentachloride (MoCl5) as a gas-phase precursor over silicon and SiGe layers. Due to different reaction kinetics, molybdenum preferentially deposits over the SiGe layer rather than the silicon layer, as referenced above. Figure 9 As described.

[0081] Then, the structure 1000b is formed by performing a deposition process to form a first silicide layer 236a comprising TiSi over the first S / D component 402a. Figure 10C The structure is 1000c. According to various embodiments, the titanium-containing material used as a precursor to form titanium silicide (TiSi) includes elemental titanium deposited via physical vapor deposition (PVD) techniques such as sputtering or evaporation. Alternatively, titanium precursors suitable for chemical vapor deposition (CVD) or atomic layer deposition (ALD) processes can be employed. Examples of such precursors include titanium tetrachloride (TiCl4), tetra(dimethylamino)titanium (TDMAT), titanium isopropoxide (TTIP), and alkoxytitanium. These precursors enable the controlled deposition of titanium-containing films, which are subsequently reacted with the underlying silicon substrate by thermal annealing to form TiSi. The choice of titanium precursor depends on the deposition technique, desired film consistency, and process integration requirements.

[0082] According to various embodiments, elemental titanium is sputtered onto the exposed surface of an n-type silicon layer of a first S / D component 402a and a MoSiGe second silicide layer 236b formed over a p-type SiGe second S / D component 402b. Following deposition, the structure undergoes thermal annealing to initiate a solid-state reaction between the titanium film and the underlying material. During annealing, TiSi preferentially forms on the n-type doped silicon layer of the first S / D component 402a, which has a higher silicon content and greater chemical reactivity with titanium compared to the MoSiGe second silicide layer 236b. MoSiGe, which contains molybdenum and germanium in addition to silicon, exhibits reduced reactivity, resulting in a thinner or less extensive TiSi layer. At this point, a third silicide layer 236c comprising TiSi is formed over the MoSiGe second silicide layer 236b. The difference in reactivity enables different silicide formation processes, in which TiSi is formed to a greater extent on the first S / D component 402a comprising n-type silicon, while a smaller or incomplete third silicide layer 236c comprising TiSi is formed on the second silicide layer 236b comprising MoSiGe.

[0083] A molybdenum capping layer (404a, 404b) is then formed over the silicide layers (236a, 236b, 236c) through a further deposition process. The molybdenum capping layer (404a, 404b) is formed to enhance the thermal stability and electromigration resistance of the contact structure. The process begins with surface conditioning of the silicide layers (236a, 236b, 236c) to ensure cleanliness and promote uniform adhesion of the subsequent metal layers. According to embodiments, the process involves a brief in-situ plasma cleaning or wet chemical treatment to remove any residual contaminants or oxide regrowth. Subsequently, the molybdenum capping layer (404a, 404b) is conformally deposited over the silicide region using a physical vapor deposition (PVD) method such as sputtering. According to various embodiments, the molybdenum capping layer (404a, 404b) independently has a thickness ranging from about 10 nm to about 50 nm, depending on design requirements and integration considerations. According to some embodiments, using a selective deposition process, molybdenum capping layers (404a, 404b) are preferentially formed over the silicide region.

[0084] Deposition is performed under controlled vacuum conditions to ensure film purity and uniformity. The molybdenum capping layer (404a, 404b) provides multiple functions: it acts as a diffusion barrier to prevent mixing between the silicide and subsequent metallization layers, improves the overall mechanical and electrical reliability of the contact stack, and provides compatibility with subsequent contact filling or metallization steps. In some embodiments, post-deposition annealing is performed to densify the molybdenum capping layer (404a, 404b) and enhance its adhesion to the underlying silicide. The use of the molybdenum capping layer (404a, 404b) helps improve contact resistance control and device reliability at advanced technology nodes.

[0085] Then, by forming the front contact 1006 (e.g., as...) Figure 2B The MD structure shown in the figure) and subsequent planarization processes (e.g., chemical mechanical planarization (CMP)) are then processed by... Figure 10C The structure is formed at 1000c. Figure 10D Structure 1000d. In this respect, the front contact 1006 is formed by depositing a conductive material over a molybdenum overlay (404a, 404b) within the via opening 1002. According to various embodiments, the conductive material is a combination of a metal liner layer (such as a metal nitride or metal carbide) and a metal filler material. In some embodiments, the metal liner layer comprises one or more of TiN, TaN, WN, TiC, TaC, or WC, and the metal filler material portion comprises W, Cu, Al, Co, Ru, Mo, Ta, Ti, alloys thereof, and / or combinations thereof. Other suitable metal liner and metal filler materials are within the scope of consideration for embodiments of this disclosure and may also be used.

[0086] Figure 11 Table 1100 contains data related to the reaction kinetics of selective etching of TiSiGe on SiGe, according to various embodiments. In this respect, the 0.7 eV energy barrier for desorbing SiCl4 from the TiSiGe layer is lower than the corresponding 0.8 eV energy barrier for desorbing SiCl4 from the TiSi layer. Therefore, according to various embodiments, a selective etching process is performed to remove the TiSiGe layer formed over the second S / D component 402b, while leaving the TiSi layer as the first silicide layer 236a formed over the first S / D component 402a, as referenced above. Figures 6A to 7B The description and the references below Figures 12A to 12D As described.

[0087] Figures 12A to 12D It is according to the various embodiments for forming Figures 6A to 7B Vertical cross-sectional views of the structures (1200a, 1200b, 1020c, 1200d) of the GAA transistor devices. The initial structure 1200a is formed according to the method used to form structure 1000a, and is consistent with the description above. Figure 10A The structure 1000a is substantially the same. Structure 1200b is formed from structure 1200a by performing a deposition process to form a first silicide layer 236a comprising TiSi over the first S / D component 402a and an intermediate silicide layer 1202 comprising TiSiGe over the second S / D component 402b. According to various embodiments, the first silicide layer 236a and the intermediate silicide layer 1202 are formed as follows.

[0088] According to some embodiments, a surface cleaning step is first performed to remove native oxides and contaminants from both materials. This may include a dilute hydrofluoric acid (HF) treatment to ensure the surface is hydrogen-sealed and free of interface barrier layers that could inhibit silanization. Subsequently, physical vapor deposition (PVD) techniques, such as sputtering, are used on... Figure 12A A blanket layer of titanium (Ti) is deposited over structure 1200a. The Ti layer is uniformly deposited across n-type Si and p-type SiGe S / D components (402a, 402b) and over any isolation or spacer structure, but silicide will only selectively occur at locations where Ti is in direct contact with the exposed Si or SiGe surface.

[0089] Then, a first rapid thermal annealing (RTA) step is performed in an inert or vacuum environment at a temperature typically ranging from about 400°C to about 550°C. During this annealing, titanium reacts with silicon and silicon-germanium below to form a metal-rich silicide compound. Specifically, this includes titanium silicide (TiSi). x The first silicide layer 236a is formed above the n-type Si S / D component 402a, and includes titanium germanium silicon (TiSi). x An intermediate silicide layer 1202 of Ge is formed above the p-type SiGe S / D component 402b. The reaction kinetics and the resulting phase composition may vary locally, depending on the Si or Ge content, but process parameters are selected to ensure simultaneous and self-aligned formation of the desired silicide phase across both material types.

[0090] Following silicide formation, unreacted titanium remaining on the non-reactive surface is selectively removed using wet etching chemicals, such as sulfur peroxide mixtures or ammonium peroxide mixtures. These wet etching chemicals etch Ti without significantly eroding the silicide layer. An optional second RTA step can be performed at a higher temperature to stabilize the silicide phase or reduce the sheet resistance, provided the thermal budget is compatible with the underlying SiGe strain and device integration requirements.

[0091] Then, structure 1200b is formed by performing a selective etching process to remove the intermediate silicide layer 1202, which includes TiSiGe. Figure 12CStructure 1200c. According to an embodiment, a selective etching process introduces a molybdenum pentachloride (MoCl5) precursor into structure 1200b, which interacts with a first silicide layer 236a comprising TiSi formed over an n-type silicon first S / D layer 402a and an intermediate silicide layer 1202 comprising TiSiGe formed over a p-type SiGe second S / D layer 402b. Under thermal conditions, MoCl5 is selectively etched and the TiSiGe layer is removed, while leaving the TiSi layer substantially intact. The selective etching stems from the higher chemical reactivity between MoCl5 and the germanium-containing silicide phase, compared to the relatively lower reactivity of MoCl5 with TiSi.

[0092] Then, structure 1200c is formed through further interaction with MoCl5. Figure 12D The structure is 1200d. At this point, after removing the intermediate layer 1202 comprising TiSiGe, MoCl5 reacts with the exposed p-type SiGe second S / D layer 402b to form a second silicide layer 236b comprising MoSiGe via a solid-state reaction. (See above reference.) Figure 9 The process of selectively etching TiSiGe and forming a second silicide layer 236b is described.

[0093] According to various embodiments, the process deposits molybdenum (Mo) capping layers (404a, 404b) over a second silicide layer 236b comprising MoSiGe and a first silicide layer 236a comprising TiSi. In some embodiments, the substrate temperature or partial pressure of MoCl5 is adjusted during or after the solid-state reaction so that excess Mo is deposited directly onto both materials as a conformal metal layer. According to various embodiments, the Mo capping layer (404a, 404b) enhances electrical contact performance, improves thermal stability, and serves as a diffusion barrier layer or seed layer for subsequent metallization steps. This integrated sequence of TiSiGe removal, MoSiGe formation, and Mo capping enables the integration of bimetallic contacts for n-type and p-type S / D components (402a, 402b) into a full-to-the-loop gate transistor without requiring additional photolithography or masking operations.

[0094] Other embodiments may include other selective etching processes. For example, according to various embodiments, optional metal-containing precursors are used instead of molybdenum pentachloride (MoCl5) to achieve similar selective etching and deposition effects. For example, tungsten pentachloride (WCl5) or tantalum pentachloride (TaCl5) is introduced to selectively react with germanium-containing silicide layers (such as TiSiGe) while leaving titanium silicide (TiSi) substantially unaffected. These precursors selectively remove the TiSiGe layer and subsequently react with the underlying p-type SiGe epitaxial region to form WSiGe or TaSiGe layers, respectively.

[0095] In other embodiments, the process forms a conformal metal capping layer, such as W or Ta, over the n-type TiSi and p-type silicide-germanide regions. Deposition conditions, including precursor temperature and partial pressure, are adjusted to facilitate metal deposition after the selective etching step. In some embodiments, additional precursors, such as molybdenum hexacarbonyl (Mo(CO)6) or molybdenum oxychloride (e.g., MoO2Cl2), are also used to deposit molybdenum or molybdenum-containing films. These variations provide flexibility for integrating different contact materials while maintaining compatibility with selective processing strategies in all-to-the-loop transistor structures.

[0096] Figures 13A to 13D It is according to the various embodiments for forming Figure 8A and Figure 8B A vertical cross-sectional view of the structure of the GAA transistor device. The initial structure 1300a uses the above information regarding... Figure 10A and Figure 12A The formation processes described above for structures 1000a and 1200a are used to form them, except for how the S / D components (402a, 402b) are doped. In structure 1200a, the second S / D component 402b, comprising silicon and germanium, is doped with a p-type dopant, while the first S / D component 402a, comprising silicon, remains undoped or lightly doped. This doping difference causes deposition selectivity for the S / D components (402a, 402b). Reference Figure 13B As described above, a selective deposition process can then be performed, in which a first silicide layer 236a comprising TiSi is formed, while no corresponding layer is formed over the second S / D component 402b. This approach fully utilizes the inherent difference in reactivity between Si and p-type SiGe in the initial stages of metal-silicon interaction.

[0097] In some embodiments, a first silicide layer 236a comprising TiSi is formed as follows. According to various embodiments, the surfaces of the S / D components (402a, 402b) are cleaned, for example, with dilute hydrofluoric acid (HF) to remove native oxides before forming the first silicide layer 236a. Following this preparation of the semiconductor surface, a blanket layer of titanium (Ti) is deposited over the exposed source / drain regions using a physical vapor deposition (PVD) method (such as sputtering). A rapid thermal annealing (RTA) step is then performed at a temperature sufficient to initiate silicide formation over the silicon region (e.g., ranging from about 400°C to about 500°C). Under these conditions, Ti readily reacts with undoped or lightly doped Si in the first S / D component 402a to form the first silicide layer 236a comprising TiSi. However, due to the presence of germanium and p-type dopant materials (such as boron) in the second S / D component 402b, the reaction kinetics change to such that little to no silicide is formed on the p-type SiGe. The dopant and germanium content suppress the Ti-SiGe reaction by modifying the surface energy and reaction interface, effectively passivating the SiGe surface during the annealing process. Therefore, silicide formation selectively occurs on the first S / D component 402a, while the second S / D component 402b, which includes p-type SiGe, remains unreacted.

[0098] This selective silicide process eliminates the need for photolithographic masking or etch-back steps to define silicide regions, thus simplifying fabrication and improving alignment accuracy. This is particularly advantageous for advanced transistor architectures, including gate-all-around (GAA) devices, as described above, where precise control over contact formation is critical for electrical performance and device scaling.

[0099] exist Figure 13B After the first silicide layer 236a is formed above the first S / D component 402a, a deposition process forms a second silicide layer 236b and a molybdenum capping layer (404a, 404b). Figure 13C Structure 1300c. The deposition process is similar to that used to form structure 1200d from structure 1200c. In some embodiments, the deposition process uses a MoCl5 precursor to form a second silicide layer 236b comprising MoSiGe, and forms molybdenum capping layers (404a, 404b). As described above, MoCl5 reacts with exposed p-type SiGe in the second S / D component 402b to form the second silicide layer 236b comprising MoSiGe by a solid-state reaction.

[0100] In some embodiments, the substrate temperature or partial pressure of MoCl5 is adjusted during or after the solid-state reaction to allow excess Mo to be directly deposited onto the MoSiGe of the second silicide layer 236b and the TiSi material of the first silicide layer 236a as a conformal metal layer. According to various embodiments, this Mo capping layer (404a, 404b) enhances electrical contact performance, improves thermal stability, and serves as a diffusion barrier layer or seed layer for subsequent metallization steps. Furthermore, under certain processing conditions, a third silicide layer 236c comprising MoSi is formed between the first silicide layer 236a and the first capping layer 404a, as referenced above. Figure 8A As described.

[0101] Then, by forming the front contact 1006 (e.g., as...) Figure 2B The MD structure shown in the figure) and subsequent planarization processes (e.g., chemical mechanical planarization (CMP)) are then processed by... Figure 13C The structure is formed at 1300c. Figure 13D Structure 1300d. In this respect, the front contact 1006 is formed by depositing a conductive material over a cover layer (404a, 404b) within the via opening 1002. According to various embodiments, the conductive material is a combination of a metal liner layer (such as a metal nitride or metal carbide) and a metal filler material. In some embodiments, the metal liner layer comprises one or more of TiN, TaN, WN, TiC, TaC, or WC, and the metal filler material portion comprises W, Cu, Al, Co, Ru, Mo, Ta, Ti, alloys thereof, and / or combinations thereof. Other suitable metal liner and metal filler materials are within the scope of consideration for embodiments of this disclosure and may also be used.

[0102] Figure 14 This is a flowchart of the operation of method 1400 for manufacturing semiconductor devices (400a to 800b) according to various embodiments. In operation 1402, method 1400 includes exposing a first source / drain structure (one of 402a or 402b) and a second source / drain structure (the other of 402a or 402b) to a selectively deposited material, wherein the first source / drain structure (one of 402a or 402b) includes a first conductivity type dopant, and the second source / drain structure (the other of 402a or 402b) includes a second conductivity type dopant. In operation 1404, method 1400 includes allowing a first silicide layer (236a or 236b) to form on the first source / drain structure (one of 402a or 402b), while, due to the deposition selectivity of the selectively deposited material, no silicide layer is formed on the second source / drain structure (the other of 402a or 402b). Figure 10B or Figure 13BAccording to various embodiments, the height T and width W of the first source / drain structure 402a are different, and the first source / drain structure S / D extends into the semiconductor structure (e.g., see...). Figure 2B ).

[0103] According to various embodiments, the first source / drain structure 402b includes p-type doped SiGe ( Figures 10A to 10D ), and the second source / drain structure 402a includes n-type doped silicon ( Figures 10A to 10D According to various embodiments, method 1400 further includes: exposing the first source / drain structure 402b and the second source / drain structure 402a to a vapor precursor comprising molybdenum pentachloride (MoCl5) in a chemical vapor deposition process; and allowing a first silicide layer 236b comprising MoSiGe to form over the p-type doped SiGe of the first source / drain structure 402b. Figure 10B According to various embodiments, method 1400 further includes exposing the n-type doped silicon of the second source / drain structure 402a and the MoSiGe of the first silicide layer 236b to a titanium-containing precursor in a deposition process, the deposition process causing the second silicide layer 236a comprising TiSi to be formed over the n-type doped silicon. Figure 10C ).

[0104] According to various embodiments, method 1400 further includes depositing a capping layer (400b, 400a) comprising at least one of Mo, TiN, W, or Ru over the first silicide layer 236b and the second silicide layer 236a. Figure 10C and Figure 10D According to various embodiments, the deposited capping layers (400b, 400a) further include a TiN layer deposited over the first silicide layer 236b and the second silicide layer 236a, such that the TiN layer contacts the first silicide layer 236b and the second silicide layer 236a. Figure 5A and Figure 5B ).

[0105] According to various embodiments, a first silicide layer 236b comprising MoSiGe is exposed to a titanium-containing precursor, further such that a third silicide layer 236c comprising TiSi is formed over the first silicide layer 236b. Figure 4B According to various embodiments, method 1400 further includes depositing a Mo layer over the first silicide layer 236b and the second silicide layer 236a, such that a first portion 404a of the Mo layer contacts the second silicide layer 236a, and a second portion 404b of the Mo layer contacts a third silicide layer 236c comprising TiSi, such that the third silicide layer 236c separates the second portion 404b from the first silicide layer 236b. Figure 4B ).

[0106] According to various embodiments, the first source / drain structure 402a includes n-type doped silicon ( Figure 13A ), and the second source / drain structure 402b includes p-type doped SiGe ( Figure 13B According to various embodiments, method 1400 further includes: exposing the first source / drain structure 402a and the second source / drain structure 402b to a titanium-containing precursor in a deposition process, the deposition process causing a first silicide layer 236a comprising TiSi to be formed over the n-type doped silicon of the first source / drain structure 402a. Figure 13B ); and in a chemical vapor deposition process, the first source / drain structure 402a and the second source / drain structure 402b are exposed to a vapor precursor including molybdenum pentachloride (MoCl5), the chemical vapor deposition process causing a second silicide layer 236b including MoSiGe to be formed over the p-type doped SiGe of the second source / drain structure 402b ( Figure 13C ).

[0107] According to various embodiments, method 1400 further includes: allowing a third silicide layer 236c comprising MoSi to be formed over the first silicide layer 236a. Figure 13C ); and depositing a capping layer (404a, 404b) comprising at least one of Mo, TiN, W or Ru over the second silicide layer 236b, such that the capping layer 404b contacts the second silicide layer 236b and the capping layer 404a contacts the third silicide layer 236c, such that the third silicide layer 236c separates the first silicide layer 236a from the capping layer (404a, 404b).

[0108] Figure 15 This is a flowchart of the operation of a method 1500 for manufacturing semiconductor devices (400a, 400b, 500a, 500b, 600a, 600b, 700a, 700b, 800a, 800b) according to various embodiments. In operation 1502, method 1500 includes forming gate structures (214, 214a, 214b) over a channel region 216. According to various embodiments, the gate structures (214, 214a, 214b) include gate spacers 220 disposed along the sidewalls of the gate structures (214, 214a, 214b), and the gate structures (214, 214a, 214b) include a gate dielectric layer 215b and a gate electrode 215a above the gate dielectric layer 215b. According to various embodiments, the dielectric constant of the gate dielectric layer 215b is greater than the dielectric constant of the gate spacer 220, wherein the first thickness t1 of the gate spacer 220 is greater than the second thickness t2 of the gate dielectric layer 215b.

[0109] In operation 1504, method 1500 includes exposing a first source / drain structure 402a and a second source / drain structure 402b to a first deposited material, wherein the first source / drain structure 402a includes a first conductivity type dopant, and the second source / drain structure 402b includes a second conductivity type dopant. In operation 1506, method 1500 includes allowing a first silicide layer 236a having a first composition to form on the first source / drain structure 402a, and an intermediate silicide layer 1202 having a second composition to form on the second source / drain structure 402b. Figure 12B In some embodiments, the first component differs from the second component. In some embodiments, the first component includes TiSi. In some embodiments, the second component includes TiSiGe.

[0110] In operation 1508, method 1500 includes performing a selective etching operation to remove the intermediate silicide layer 1202 having a second composition. Figure 12C In operation 1510, method 1500 includes exposing a first silicide layer 236a and a second source / drain structure 402b to a second deposited material. In operation 1512, method 1500 includes allowing a second silicide layer 236b having a third composition to form on the second source / drain structure 402b. In some embodiments, the third composition includes MoSiGe. In operation 1514, method 1500 includes allowing a capping layer (400a, 400b) to form over the first silicide layer 236a and the second silicide layer 236b. Figure 12D ).

[0111] According to various embodiments, the first source / drain structure 402a includes n-type doped silicon ( Figures 12A to 12D The second source / drain structure 402b includes p-type doped SiGe ( Figures 12A to 12D According to various embodiments, exposing the first source / drain structure 402a and the second source / drain structure 402b to the first deposition material further includes performing a first deposition process using a titanium-containing precursor, the first deposition process causing a first silicide layer 236a comprising TiSi to be formed over n-type doped silicon, and an intermediate silicide layer 1202 comprising TiSiGe to be formed over p-type doped SiGe. Figure 12B ).

[0112] According to various embodiments, exposing the first silicide layer 236a and the second source / drain structure 402b to the second deposited material further includes exposing the first silicide layer 236a and the second source / drain structure 402b to a metal-containing precursor comprising a metal selectively etched over p-type doped SiGe 402b and removing TiSiGe 1202. Figure 12C), reacting with p-type doped SiGe 402b to form a second silicide layer 236b above the p-type doped SiGe as a metallic SiGe layer ( Figure 12D ), and a metal-based capping layer (400a, 400b) is formed over the first silicide layer 236a and the second silicide layer 236b. Figure 12D According to various embodiments, the metal precursor includes at least one of molybdenum pentachloride (MoCl5), tungsten pentachloride (WCl5), tantalum pentachloride (TaCl5), molybdenum hexacarbonyl (Mo(CO)6), or molybdenum oxychloride (e.g., MoO2Cl2), such that the metal is one of Mo, W, or Ta.

[0113] Referring to all the accompanying drawings and various embodiments of the present disclosure, semiconductor devices (400a to 800b) are disclosed. The semiconductor devices (400a to 800b) include a first gate 214a formed in a first region (having a cross-section A-A') of a substrate 210, a second gate 214b formed in a second region (having a cross-section B-B') of the substrate 210, a first source / drain component 402a located above a first opposite side of the first gate 214a, a second source / drain component 402b located above a second opposite side of the second gate 214b, a first silicide structure 236a located above the first source / drain component 402a, and a second silicide structure 236b located above the second source / drain component 402b.

[0114] According to various embodiments, the first silicide structure 236a and the second silicide structure 236b comprise different materials and have curved profiles. According to various embodiments, the first silicide structure 236a comprises TiSi, and the second silicide structure 236b comprises MoSiGe. According to various embodiments, the first source / drain component 402a comprises n-type doped silicon, and the second source / drain component 402b comprises p-type doped SiGe. According to various embodiments, the semiconductor device (400a to 800b) further includes capping layers (404a, 404b), which comprise at least one of Mo, TiN, W, or Ru. According to various embodiments, the capping layers (404a, 404b) include a TiN layer formed to contact the first silicide structure 236a and the second silicide structure 236b. Figure 5A and Figure 5B According to various embodiments, the capping layers (404a, 404b) include a Mo layer formed over the first silicide structure 236a and the second silicide structure 236b. Figure 4A , Figure 4B and Figures 6A to 8B ).

[0115] According to various embodiments, the semiconductor device (400a to 800b) further includes: a TiSi layer 236c formed to contact the second silicide structure 236b; a first portion 404a of a Mo layer contacting the first silicide structure 236a; and a second portion 404b of the Mo layer contacting the TiSi layer 236b, such that the TiSi layer 236c separates the second portion 404b from the second silicide structure 236b. Figure 4A and Figure 4B According to various embodiments, the semiconductor device (400a to 800b) further includes: a MoSi layer 236c formed to contact the first silicide structure 236a; a first portion 404a of the Mo layer contacting the MoSi layer, such that the MoSi layer 236c separates the first portion 404a from the first silicide structure 236a. Figure 7A ); and the second portion 404b of the Mo layer, contacting the second silicide structure 236b ( Figure 7B ).

[0116] The disclosed embodiments advantageously allow for the individual minimization of source / drain resistances for transistor devices (400a, 500a, 600a, 700a, 800a) and for transistor devices (400b, 500b, 600b, 700b, 800b) with n-type doped S / D components 402a and p-type doped S / D components 402b, respectively. In this respect, the disclosed devices and methods overcome the disadvantages of using a single silicide material, which, in comparative embodiments, tends to benefit either n-type or p-type transistors, but not both, due to the different Schottky barrier height (SBH) issues. The disclosed method generates the self-aligned formation of the first silicide structure 236a and the second silicide structure 236b using selective deposition and etching techniques that require only simple processes (rather than complex individual patterning operations).

[0117] According to various embodiments, the semiconductor device includes: a first gate formed in a first region of a substrate; a second gate formed in a second region of the substrate; a first source / drain component located above a first opposite side of the first gate; a second source / drain component located above a second opposite side of the second gate; a first silicide structure including a first silicide component located above the first source / drain component; a second silicide structure including a second silicide component located above the second source / drain component; a first source / drain contact electrically coupled to the first silicide structure; and a second source / drain contact electrically coupled to the second silicide structure.

[0118] According to various embodiments, the first silicide component and the second silicide component comprise different materials and have curved profiles. According to various embodiments, the second silicide structure comprises at least one of Mo, TiN, W, or Ru. According to various embodiments, the first silicide structure comprises TiSi, and the second silicide structure comprises MoSiGe. According to various embodiments, the first source / drain component comprises n-type doped silicon, and the second source / drain component comprises p-type doped SiGe.

[0119] According to various embodiments, at least one of the first silicide structure and the second silicide structure includes a capping layer, the capping layer including at least one of Mo, TiN, W, or Ru. According to various embodiments, the capping layer includes a TiN layer formed to contact the first silicide component and the second silicide component. According to various embodiments, the capping layer includes a Mo layer formed over the first silicide structure and the second silicide structure. According to various embodiments, the semiconductor device further includes: a TiSi layer formed to contact the second silicide structure; a first portion of the Mo layer contacting the first silicide structure; and a second portion of the Mo layer contacting the TiSi layer, such that the TiSi layer separates the second portion from the second silicide structure. According to various embodiments, the semiconductor device further includes: a MoSi layer formed to contact the first silicide structure; a first portion of the Mo layer contacting the MoSi layer, such that the MoSi layer separates the first portion from the first silicide structure; and a second portion of the Mo layer contacting the second silicide structure.

[0120] According to various embodiments, a method of manufacturing a semiconductor device includes: exposing a first source / drain structure and a second source / drain structure to a deposition material, wherein the first source / drain structure includes a first conductivity type dopant, and the second source / drain structure includes a second conductivity type dopant; and depositing a first silicide layer on the first source / drain structure, wherein due to the deposition selectivity of the deposition material, the deposition rate of the silicide layer formed on the second source / drain structure is less than the deposition rate of the silicide layer formed on the first source / drain structure. According to various embodiments, the height and width of the first source / drain structure are different, and the first source / drain structure extends into a semiconductor structure.

[0121] According to various embodiments, the first source / drain structure comprises p-type doped SiGe, and the second source / drain structure comprises n-type doped silicon, and the deposition material is a vapor-phase precursor comprising molybdenum pentachloride (MoCl5). According to various embodiments, the method further includes: introducing the deposition material in a chemical vapor deposition process; and allowing a first silicide layer to form as a MoSiGe layer over the p-type doped SiGe. According to various embodiments, the method further includes: exposing the n-type doped silicon and the MoSiGe layer to a titanium-containing precursor in a deposition process, the deposition process causing a second silicide layer comprising TiSi to form over the n-type doped silicon.

[0122] According to various embodiments, the method further includes depositing a capping layer comprising at least one of Mo, TiN, W, or Ru over the first silicide layer and the second silicide layer. According to various embodiments, depositing the capping layer further includes depositing a TiN layer over the first silicide layer and the second silicide layer, such that the TiN layer contacts the first silicide layer and the second silicide layer. According to various embodiments, exposing the first silicide layer to a titanium-containing precursor further forms a TiSi layer over the first silicide layer. According to various embodiments, the method further includes depositing a Mo layer over the first silicide layer and the second silicide layer, such that a first portion of the Mo layer contacts the second silicide layer, and a second portion of the Mo layer contacts the TiSi layer, such that the TiSi layer separates the second portion from the second silicide layer.

[0123] According to various embodiments, the first source / drain structure comprises n-type doped silicon, and the second source / drain structure comprises p-type doped SiGe, and the deposition material is a titanium-containing precursor. According to various embodiments, the method further includes: performing a deposition process such that a first silicide layer comprising TiSi is formed over the n-type doped silicon; and exposing the first and second source / drain structures to a vapor precursor comprising molybdenum pentachloride (MoCl5) in a chemical vapor deposition process, such that the second silicide layer is formed as a MoSiGe layer over the p-type doped SiGe.

[0124] According to various embodiments, the method further includes: allowing a MoSi layer to form over a first silicide layer; and depositing a capping layer comprising at least one of Mo, TiN, W, or Ru over a second silicide layer, such that the capping layer contacts the second silicide layer and the capping layer contacts the MoSi layer, thereby causing the MoSi layer to separate the first silicide layer from the capping layer.

[0125] According to various embodiments, a method of manufacturing a semiconductor device includes: forming a gate structure over a channel region, wherein the gate structure includes a gate spacer disposed along a sidewall of the gate structure, the gate structure includes a gate dielectric layer and a gate electrode above the gate dielectric layer, wherein the dielectric constant of the gate dielectric layer is greater than the dielectric constant of the gate spacer, and wherein a first thickness of the gate spacer is greater than a second thickness of the gate dielectric layer.

[0126] According to various embodiments, the method further includes: exposing a first source / drain structure and a second source / drain structure to a first deposition material, wherein the first source / drain structure includes a first conductivity type dopant, and the second source / drain structure includes a second conductivity type dopant; depositing a first silicide layer having a first composition on the first source / drain structure; and depositing an intermediate silicide layer having a second composition on the second source / drain structure. According to various embodiments, the method further includes: performing an etching operation to remove the intermediate silicide layer having the second composition, wherein the intermediate silicide layer having the second composition exhibits a faster etching rate in the etching operation than the first silicide layer having the first composition. According to various embodiments, the method further includes: exposing the first silicide layer and the second source / drain structure to a second deposition material; and depositing a second silicide layer having a third composition on the second source / drain structure.

[0127] According to various embodiments, the first source / drain structure includes n-type doped silicon, and the second source / drain structure includes p-type doped SiGe. According to various embodiments, exposing the first source / drain structure and the second source / drain structure to the first deposition material further includes performing a first deposition process using a titanium-containing precursor, the first deposition process causing a first silicide layer including TiSi to be formed over the n-type doped silicon, and causing an intermediate silicide layer including TiSiGe to be formed over the p-type doped SiGe.

[0128] According to various embodiments, exposing the first silicide layer and the second source / drain structure to the second deposited material further includes: exposing the first silicide layer and the second source / drain structure to a metal-containing precursor comprising a metal: selectively etching and removing TiSiGe from above p-type doped SiGe; reacting with p-type doped SiGe to form a second silicide layer as a metal SiGe layer above the p-type doped SiGe; and forming a metal-based capping layer above the first silicide layer and the second silicide layer. According to various embodiments, the method further includes: forming a capping layer above the first silicide layer and the second silicide layer, and the metal-containing precursor comprising at least one of molybdenum pentachloride (MoCl5), tungsten pentachloride (WCl5), tantalum pentachloride (TaCl5), molybdenum hexacarbonyl (Mo(CO)6), or molybdenum oxychloride (e.g., MoO2Cl2), such that the metal is one of Mo, W, or Ta.

[0129] Some embodiments of this application provide a semiconductor device including: a first gate formed in a first region of a substrate; a second gate formed in a second region of the substrate; a first source / drain component located above a first opposite side of the first gate; a second source / drain component located above a second opposite side of the second gate; a first silicide structure including a first silicide component located above the first source / drain component; a second silicide structure including a second silicide component located above the second source / drain component; a first source / drain contact electrically coupled to the first silicide structure; and a second source / drain contact electrically coupled to the second silicide structure, wherein: the first silicide component and the second silicide component comprise different materials and have curved profiles; and the second silicide structure comprises at least one of Mo, TiN, W, or Ru.

[0130] In some embodiments, the first silicide structure comprises TiSi; and the second silicide structure comprises MoSiGe. In some embodiments, the first source / drain component comprises n-type doped silicon; and the second source / drain component comprises p-type doped SiGe. In some embodiments, at least one of the first silicide structure and the second silicide structure further comprises a capping layer comprising at least one of Mo, TiN, W, or Ru. In some embodiments, the capping layer comprises a TiN layer formed to contact the first silicide component and the second silicide component. In some embodiments, the capping layer comprises a Mo layer formed over the first silicide structure and the second silicide structure. In some embodiments, the semiconductor device further comprises: a TiSi layer formed to contact the second silicide structure; a first portion of the Mo layer contacting the first silicide structure; and a second portion of the Mo layer contacting the TiSi layer, such that the TiSi layer separates the second portion from the second silicide structure. In some embodiments, the semiconductor device further includes: a MoSi layer formed to contact the first silicide structure; a first portion of the Mo layer contacting the MoSi layer such that the MoSi layer separates the first portion from the first silicide structure; and a second portion of the Mo layer contacting the second silicide structure.

[0131] Other embodiments of this application provide a method for manufacturing a semiconductor device, comprising: exposing a first source / drain structure and a second source / drain structure to a deposition material, wherein the first source / drain structure includes a first conductivity type dopant and the second source / drain structure includes a second conductivity type dopant; and depositing a first silicide layer on the first source / drain structure, wherein due to the deposition selectivity of the deposition material, the deposition rate of the silicide layer formed on the second source / drain structure is less than the deposition rate of the silicide layer formed on the first source / drain structure, wherein the height and width of the first source / drain structure are different, and the first source / drain structure extends into a semiconductor structure.

[0132] In some embodiments, the first source / drain structure comprises p-type doped SiGe; the second source / drain structure comprises n-type doped silicon; the deposition material is a vapor precursor comprising molybdenum pentachloride (MoCl5); and the method further comprises: introducing the deposition material into a chemical vapor deposition process; and allowing the first silicide layer to be formed as a MoSiGe layer formed over the p-type doped SiGe. In some embodiments, the method further comprises: exposing the n-type doped silicon and the MoSiGe layer to a titanium-containing precursor in a deposition process, the deposition process causing a second silicide layer comprising TiSi to be formed over the n-type doped silicon. In some embodiments, the method further comprises: depositing a capping layer comprising at least one of Mo, TiN, W, or Ru over the first silicide layer and the second silicide layer. In some embodiments, depositing the capping layer further comprises: depositing a TiN layer over the first silicide layer and the second silicide layer, such that the TiN layer contacts the first silicide layer and the second silicide layer. In some embodiments, exposing the first silicide layer to the titanium-containing precursor further forms a TiSi layer over the first silicide layer; and the method further includes: depositing a Mo layer over the first silicide layer and the second silicide layer, such that a first portion of the Mo layer contacts the second silicide layer, and a second portion of the Mo layer contacts the TiSi layer, such that the TiSi layer separates the second portion from the second silicide layer. In some embodiments, the first source / drain structure comprises n-type doped silicon; the second source / drain structure comprises p-type doped SiGe; the deposition material is a titanium-containing precursor; and the method further includes: performing a deposition process such that the first silicide layer comprising TiSi is formed over the n-type doped silicon; and exposing the first source / drain structure and the second source / drain structure to a vapor precursor comprising molybdenum pentachloride (MoCl5) in a chemical vapor deposition process such that the second silicide layer is formed as a MoSiGe layer over the p-type doped SiGe. In some embodiments, the method further includes: allowing a MoSi layer to be formed over the first silicide layer; and depositing a capping layer comprising at least one of Mo, TiN, W, or Ru over the second silicide layer, such that the capping layer contacts the second silicide layer and the capping layer contacts the MoSi layer, such that the MoSi layer separates the first silicide layer from the capping layer.

[0133] Some embodiments of this application provide a method for manufacturing a semiconductor device, comprising: forming a gate structure over a channel region, wherein the gate structure includes a gate spacer disposed along a sidewall of the gate structure, the gate structure including a gate dielectric layer and a gate electrode located above the gate dielectric layer, wherein the dielectric constant of the gate dielectric layer is greater than the dielectric constant of the gate spacer, and wherein a first thickness of the gate spacer is greater than a second thickness of the gate dielectric layer; exposing a first source / drain structure and a second source / drain structure to a first deposited material, wherein the first source / drain structure includes a first conductivity type dopant, and the... The second source / drain structure includes a second conductivity type dopant; a first silicide layer having a first composition is deposited on the first source / drain structure, and an intermediate silicide layer having a second composition is deposited on the second source / drain structure; an etching operation is performed to remove the intermediate silicide layer having the second composition, wherein the intermediate silicide layer having the second composition exhibits a faster etching rate in the etching operation than the first silicide layer having the first composition; the first silicide layer and the second source / drain structure are exposed to a second deposition material; and a second silicide layer having a third composition is deposited on the second source / drain structure.

[0134] In some embodiments, the first source / drain structure comprises n-type doped silicon; the second source / drain structure comprises p-type doped SiGe; and exposing the first source / drain structure and the second source / drain structure to the first deposition material further comprises: performing a first deposition process using a titanium-containing precursor, the first deposition process causing the first silicide layer comprising TiSi to form over the n-type doped silicon, and the intermediate silicide layer comprising TiSiGe to form over the p-type doped SiGe. In some embodiments, exposing the first silicide layer and the second source / drain structure to the second deposition material further comprises: exposing the first silicide layer and the second source / drain structure to a metal-containing precursor comprising metal, wherein the metal: selectively etches and removes the TiSiGe from over the p-type doped SiGe; reacts with the p-type doped SiGe to form the second silicide layer as a metal SiGe layer over the p-type doped SiGe; and forms a metal-based capping layer over the first silicide layer and the second silicide layer. In some embodiments, the method further includes forming a capping layer over the first silicide layer and the second silicide layer, wherein the metal-containing precursor includes at least one of molybdenum pentachloride (MoCl5), tungsten pentachloride (WCl5), tantalum pentachloride (TaCl5), molybdenum hexacarbonyl (Mo(CO)6), or molybdenum oxychloride (e.g., MoO2Cl2), such that the metal is one of Mo, W, or Ta.

[0135] The foregoing outlines features of several embodiments to enable those skilled in the art to better understand various aspects of the embodiments of this disclosure. Those skilled in the art should understand that they can readily use the embodiments of this disclosure as a basis to design or modify other processes and structures for performing the same purposes and / or achieving the same advantages as the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of the embodiments of this disclosure, and that various changes, substitutions, and modifications can be made to them herein without departing from the spirit and scope of the embodiments of this disclosure.

Claims

1. A semiconductor device, comprising: A first gate is formed in a first region of the substrate; A second gate is formed in a second region of the substrate; The first source / drain component is located above the first opposite side of the first gate; The second source / drain component is located above the second opposite side of the second gate; The first silicide structure includes a first silicide component located above the first source / drain component; The second silicide structure includes a second silicide component located above the second source / drain component. The first source / drain contact is electrically coupled to the first silicide structure; as well as The second source / drain contact is electrically coupled to the second silicide structure. Wherein: the first silicide component and the second silicide component comprise different materials and have curved profiles; and the second silicide structure comprises at least one of Mo, TiN, W or Ru.

2. The semiconductor device according to claim 1, wherein: The first silicide structure includes TiSi; and The second silicide structure includes MoSiGe.

3. The semiconductor device according to claim 2, wherein: The first source / drain component comprises n-type doped silicon; and The second source / drain component includes p-type doped SiGe.

4. The semiconductor device according to claim 2, wherein, At least one of the first silicide structure and the second silicide structure further includes a capping layer, the capping layer comprising at least one of Mo, TiN, W or Ru.

5. The semiconductor device according to claim 4, wherein, The capping layer includes a TiN layer formed to contact the first silicide component and the second silicide component.

6. The semiconductor device according to claim 4, wherein, The capping layer includes a Mo layer formed over the first silicide structure and the second silicide structure.

7. The semiconductor device according to claim 6, further comprising: A TiSi layer is formed to contact the second silicide structure; The first portion of the Mo layer contacts the first silicide structure; as well as The second portion of the Mo layer contacts the TiSi layer, thereby causing the TiSi layer to separate the second portion from the second silicide structure.

8. The semiconductor device according to claim 6, further comprising: A MoSi layer is formed to contact the first silicide structure; The first portion of the Mo layer contacts the MoSi layer, thereby causing the MoSi layer to separate the first portion from the first silicide structure. as well as The second portion of the Mo layer contacts the second silicide structure.

9. A method for manufacturing a semiconductor device, comprising: A first source / drain structure and a second source / drain structure are exposed to a deposited material, wherein the first source / drain structure includes a first conductivity type dopant, and the second source / drain structure includes a second conductivity type dopant; and A first silicide layer is deposited on the first source / drain structure. Due to the deposition selectivity of the deposition material, the deposition rate of the silicide layer formed on the second source / drain structure is lower than the deposition rate of the silicide layer formed on the first source / drain structure. The height and width of the first source / drain structure are different, and the first source / drain structure extends into the semiconductor structure.

10. A method for manufacturing a semiconductor device, comprising: A gate structure is formed above a channel region, wherein the gate structure includes a gate spacer disposed along a sidewall of the gate structure, the gate structure includes a gate dielectric layer and a gate electrode located above the gate dielectric layer, wherein the dielectric constant of the gate dielectric layer is greater than the dielectric constant of the gate spacer, and wherein a first thickness of the gate spacer is greater than a second thickness of the gate dielectric layer. A first source / drain structure and a second source / drain structure are exposed to a first deposited material, wherein the first source / drain structure includes a first conductivity type dopant, and the second source / drain structure includes a second conductivity type dopant. A first silicide layer having a first composition is deposited on the first source / drain structure, and an intermediate silicide layer having a second composition is deposited on the second source / drain structure; An etching operation is performed to remove the intermediate silicide layer having the second composition, wherein the intermediate silicide layer having the second composition exhibits a faster etching rate in the etching operation than the first silicide layer having the first composition. Exposing the first silicide layer and the second source / drain structure to the second deposited material; and A second silicide layer with a third composition is deposited on the second source / drain structure.

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