Heterogeneously integrated complementary semiconductor devices and methods of making the same

Abstract

The application discloses a kind of heterogeneous integrated complementary semiconductor devices and preparation method thereof.The heterogeneous integrated complementary semiconductor device includes: heterojunction device, the heterojunction device includes substrate, heterojunction, p-type semiconductor layer and gate electrode;Wherein, the heterojunction is located substrate side;The p-type semiconductor layer is located the side of heterojunction away from substrate;The gate electrode is located the side of p-type semiconductor layer away from substrate;Gate insulating layer, located the side of gate electrode away from substrate;P-type channel layer, located the side of gate insulating layer away from substrate, the material of p-type channel layer includes tellurium oxide;First source and first drain, all located the side of p-type channel layer away from substrate.The application can improve the yield of heterogeneous integrated complementary semiconductor device.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a heterogeneous integrated complementary semiconductor device and its fabrication method. Background Technology

[0002] Gallium nitride-based field-effect transistors (GaN-based MOSFETs) have advantages such as high-frequency switching characteristics, low dynamic loss, and high voltage withstand capability, and have broad application prospects in the field of modern electronic technology.

[0003] However, most existing gallium nitride (GaN)-based field-effect transistors are n-channel devices, meaning they utilize electron conduction. For GaN p-channel devices, the effective mass of the two-dimensional hole gas generated by piezoelectric polarization is relatively large, resulting in low two-dimensional hole mobility and difficulty in achieving good gate control. Because of the low yield of GaN p-channel devices, the yield of GaN complementary logic circuits is also low. Therefore, in industrial applications, GaN complementary logic circuits are rarely used; instead, GaN direct-coupled logic circuits, which have higher electrostatic power consumption, are more commonly employed. Summary of the Invention

[0004] This invention provides a heterogeneous integrated complementary semiconductor device and its fabrication method to improve the yield of heterogeneous integrated complementary semiconductor devices.

[0005] According to one aspect of the present invention, a heterogeneous integrated complementary semiconductor device is provided, the heterogeneous integrated complementary semiconductor device comprising: A heterojunction device includes a substrate, a heterojunction, a p-type semiconductor layer, and a gate electrode; wherein the heterojunction is located on one side of the substrate; the p-type semiconductor layer is located on the side of the heterojunction away from the substrate; and the gate electrode is located on the side of the p-type semiconductor layer away from the substrate. A gate insulating layer is located on the side of the gate electrode away from the substrate; A p-type channel layer is located on the side of the gate insulating layer away from the substrate, and the material of the p-type channel layer includes tellurium oxide; The first source and the first drain are both located on the side of the p-type channel layer away from the substrate.

[0006] Optionally, the thickness of the p-type channel layer ranges from 1 nanometer to 50 nanometers.

[0007] Optionally, the heterojunction complementary semiconductor device further includes a second source and a second drain, both of which are in contact with the heterojunction and located on the side of the heterojunction away from the substrate.

[0008] Optionally, the orthographic projection of the gate insulating layer on the substrate is located within the orthographic projection of the gate electrode on the substrate; the orthographic projection of the p-type channel layer on the substrate is located within the orthographic projection of the gate insulating layer on the substrate.

[0009] Optionally, the heterojunction complementary semiconductor device further includes a first passivation layer, which is located on the side of the heterojunction away from the substrate and is in contact with the heterojunction; The first passivation layer covers the side of the p-type semiconductor layer and the side of the gate electrode; the side of the first passivation layer away from the substrate is flush with the side of the gate electrode away from the substrate. The orthographic projection area of ​​the gate insulating layer on the substrate is greater than the orthographic projection area of ​​the gate electrode on the substrate; and the orthographic projection of the gate electrode on the substrate is located within the orthographic projection of the gate insulating layer on the substrate; the orthographic projection of the p-type channel layer on the substrate coincides with the orthographic projection of the gate insulating layer on the substrate.

[0010] Optionally, the heterojunction includes a channel layer and a barrier layer sequentially located away from the substrate.

[0011] Optionally, the heterogeneous integrated complementary semiconductor device further includes: A second passivation layer covers the first source, the first drain, the second source, and the second drain; the second passivation layer has a first opening exposing the first source, a second opening exposing the first drain, a third opening exposing the second source, and a fourth opening exposing the second drain. A first vertical connection structure, wherein the vertical connection structure fills the first opening and is connected to the first source electrode; A second vertical connection structure, wherein the second vertical connection structure fills the third opening and is connected to the second source electrode; A third vertical connection structure is provided, which fills the second opening and the fourth opening, and is connected to both the first drain and the second drain.

[0012] According to another aspect of the present invention, a method for fabricating a heterogeneous integrated complementary semiconductor device is provided, the method comprising: A heterojunction device is provided, the heterojunction device comprising a substrate, a heterojunction, a p-type semiconductor layer, and a gate electrode; wherein the heterojunction is located on one side of the substrate; the p-type semiconductor layer is located on the side of the heterojunction away from the substrate; and the gate electrode is located on the side of the p-type semiconductor layer away from the substrate. A gate insulating layer is formed on the side of the gate electrode away from the substrate; A p-type channel layer is formed on the side of the gate insulating layer away from the substrate; wherein the material of the p-type channel layer includes tellurium oxide; A first source and a first drain are formed on the side of the p-type channel layer away from the substrate.

[0013] Optionally, forming a p-type channel layer on the side of the gate insulating layer away from the substrate includes: A tellurium material layer is formed on the side of the gate insulating layer away from the substrate; The tellurium material layer is annealed to form the p-type channel layer.

[0014] Optionally, before forming a gate insulating layer on the side of the gate electrode away from the substrate, the method further includes: A first passivation layer is formed on the side of the heterojunction away from the substrate. The first passivation layer covers the side of the p-type semiconductor layer and the side of the gate electrode. The side of the first passivation layer away from the substrate is flush with the side of the gate electrode away from the substrate.

[0015] The technical solution of this invention employs a heterojunction device comprising: a heterojunction device, which includes a substrate, a heterojunction, a p-type semiconductor layer, and a gate electrode; wherein the heterojunction is located on one side of the substrate; the p-type semiconductor layer is located on the side of the heterojunction away from the substrate; the gate electrode is located on the side of the p-type semiconductor layer away from the substrate; a gate insulating layer is located on the side of the gate electrode away from the substrate; a p-type channel layer is located on the side of the gate insulating layer away from the substrate, and the material of the p-type channel layer includes tellurium oxide; a first source and a first drain are both located on the side of the p-type channel layer away from the substrate. The p-type channel layer, being made of tellurium oxide, allows for efficient hole transport even in amorphous states, exhibiting high hole mobility; tellurium oxide can be fabricated at relatively low temperatures, making it temperature-compatible with the heterojunction device; and the tellurium oxide film exhibits good uniformity, resulting in better device consistency. In other words, by incorporating a tellurium oxide p-type channel layer, the yield of p-channel devices can be significantly improved, thereby increasing the yield of heterojunction complementary semiconductor devices.

[0016] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of the present invention, nor is it intended to limit the scope of the invention. Other features of the invention will become readily apparent from the following description. Attached Figure Description

[0017] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0018] Figure 1 This is a schematic diagram of the structure of a heterogeneous integrated complementary semiconductor device provided in an embodiment of the present invention; Figure 2 This is a schematic diagram of the structure of another heterogeneous integrated complementary semiconductor device provided in an embodiment of the present invention; Figure 3 A flowchart illustrating a method for fabricating a heterogeneous integrated complementary semiconductor device according to an embodiment of the present invention; Figures 4-10 This is a schematic diagram of the product structure corresponding to the main steps of a method for fabricating a heterogeneous integrated complementary semiconductor device provided in an embodiment of the present invention. Detailed Implementation

[0019] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0020] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0021] Figure 1 This is a schematic diagram of a heterogeneous integrated complementary semiconductor device provided in an embodiment of the present invention, with reference to... Figure 1The heterojunction complementary semiconductor device includes a heterojunction device 11, a gate insulating layer 121, a p-type channel layer 122, a first source 123, and a first drain 124. The heterojunction device 11 includes a substrate 111, a heterojunction, a p-type semiconductor layer 116, and a gate electrode 117. The heterojunction is located on one side of the substrate. The p-type semiconductor layer 116 is located on the side of the heterojunction away from the substrate 111. The gate electrode 117 is located on the side of the p-type semiconductor layer 116 away from the substrate 111. The gate insulating layer 121 is located on the side of the gate electrode 117 away from the substrate 111. The p-type channel layer 122 is located on the side of the gate insulating layer 121 away from the substrate 111. The material of the p-type channel layer 122 includes tellurium oxide. The first source 123 and the first drain 124 are both located on the side of the p-type channel layer 122 away from the substrate 111.

[0022] Specifically, the heterojunction complementary semiconductor device includes a p-channel device and an n-channel device, wherein the heterojunction device 11 is the n-channel device.

[0023] The heterojunction device 11 has a heterojunction comprising a channel layer 112 and a barrier layer 113. The channel layer 112 is located on one side of the substrate 111, while the barrier layer 113 is located on the side of the channel layer 112 away from the substrate 111. The barrier layer 112 is in contact with the channel layer 111, and the band gap of the barrier layer 113 is larger than that of the channel layer 112. After the barrier layer 113 is grown on the channel layer 112, a quantum well is formed at the heterojunction interface due to the band discontinuity. Furthermore, the strong spontaneous polarization and piezoelectric polarization effects of the channel layer 112 and the barrier layer 113 cause a very high concentration of electrons to accumulate in the quantum well, thus forming a two-dimensional electron gas (2DEG). The heterojunction device 11 also includes a p-type semiconductor layer 116 and a gate electrode 117. The p-type semiconductor layer 116 is used to deplete the underlying two-dimensional electron gas. The p-type semiconductor layer 116 is a p-type doped III-V group semiconductor layer. The p-type semiconductor layer 116 is in contact with the heterojunction, and the two are lattice-matched. Specifically, the p-type semiconductor layer 116 is in contact with the barrier layer 113, and the two are lattice-matched. The p-type semiconductor layer 116 contains a large number of holes. These holes recombine with the two-dimensional electron gas in the heterojunction, thus depleting the two-dimensional electron gas in the heterojunction and causing the channel of the heterojunction device to close, i.e., the heterojunction device is turned off. The gate electrode 117 of the heterojunction device 11 is in contact with the p-type semiconductor layer 116. When the voltage applied between the gate electrode 117 and the corresponding source electrode of the heterojunction device 11 is less than the threshold voltage of the heterojunction device 11, the p-type semiconductor layer 116 depletes the two-dimensional electron gas beneath it, and the heterojunction device 11 is turned off. When the voltage applied between the gate electrode 117 and the source corresponding to the heterojunction device 11 is greater than or equal to the threshold voltage of the heterojunction device 11, the holes in the p-type semiconductor layer 116 are attracted by the gate electrode 117 and move toward the side away from the heterojunction, thereby restoring the two-dimensional electron gas in the heterojunction and turning on the channel of the heterojunction, that is, the heterojunction device 11 is turned on at this time.

[0024] In this embodiment, the heterogeneous integrated complementary semiconductor device further includes a p-channel device, specifically comprising a gate electrode 117, a gate insulating layer 121, a p-type channel layer 122, a first source 123, and a first drain 124. The majority carriers of the p-type channel layer 122 are holes. When a sufficient negative voltage is not applied between the gate electrode 117 and the first source 123, the amount of holes accumulated in the p-type channel layer 122 is small, and the conductive channel between the first source 123 and the first drain 124 is not open, thus the p-channel device is turned off. When a sufficient negative voltage is applied between the gate electrode 117 and the first source 123, a large number of holes accumulate in the p-type channel layer 122, causing the conductive channel between the first source 123 and the first drain 124 to open, and the p-channel device is turned on. In other words, when a negative voltage is applied to the gate electrode of a p-channel device, the p-channel device turns on; when a positive voltage is applied to the gate electrode of a p-channel device, the p-channel device turns off.

[0025] In summary, when a positive voltage is applied to the gate electrode 117, the p-channel device is turned off, while the heterojunction device is turned on; when a negative voltage is applied to the gate electrode 117, the p-channel device is turned on, while the heterojunction device is turned off. That is, the p-channel device and the heterojunction device have complementary conduction states under the same bias voltage, thus forming complementary devices. It can be understood that in this embodiment, the p-channel device and the heterojunction device share the gate electrode 117.

[0026] Traditional p-channel devices are extremely difficult to integrate with heterojunction devices. In this embodiment, the p-channel material of the p-channel device includes tellurium oxide (TeO). x TeO tellurium oxide x Tellurium oxide-based p-channel devices exhibit significant advantages in both key performance and manufacturing yield. Specifically, on the one hand, tellurium oxide-based TeO x The hole mobility of tellurium oxide (TeO) is improved by at least an order of magnitude compared to gallium nitride (GaN) materials. On the other hand, traditional GaN-type p-channel devices suffer from low manufacturing yields because p-type ions are difficult to activate in GaN materials. Silicon-based p-channel devices, on the other hand, generate a large number of defects, resulting in poor uniformity. x The tellurium oxide-based p-channel device exhibits high hole mobility even in the amorphous state, demonstrating efficient hole transport in the p-type channel layer. Furthermore, tellurium oxide can be fabricated at relatively low temperatures, making it temperature-compatible with the heterojunction device 11. Additionally, the tellurium oxide film exhibits good uniformity, resulting in better device consistency. In summary, tellurium oxide TeO x The manufacturing yield of p-channel devices based on gallium nitride (GaN) is much higher than that of p-channel devices based on gallium nitride (GaN) and silicon. Therefore, the heterogeneous integrated complementary semiconductor device of this embodiment has a high yield.

[0027] Furthermore, in this embodiment, the p-channel device and the heterojunction device 11 are vertically stacked. On one hand, the vertically stacked structure significantly reduces the footprint compared to a planar arrangement, making monolithic integration more feasible and providing a solid foundation for large-scale complementary logic circuits. On the other hand, the vertically stacked structure allows the gate electrode 117 to be fabricated before the p-channel layer 122, with the gate electrode 117 covering the p-type semiconductor layer 116. Therefore, during the extended thermal annealing process of the p-channel layer 122, the gate electrode 117 can prevent impurities from penetrating the p-type semiconductor layer 116, thus preventing the p-type semiconductor layer 116 from failing and further improving the yield of the heterogeneously integrated complementary semiconductor device.

[0028] The technical solution of this embodiment employs a heterojunction device comprising: a heterojunction device, which includes a substrate, a heterojunction, a p-type semiconductor layer, and a gate electrode; wherein the heterojunction is located on one side of the substrate; the p-type semiconductor layer is located on the side of the heterojunction away from the substrate; the gate electrode is located on the side of the p-type semiconductor layer away from the substrate; a gate insulating layer is located on the side of the gate electrode away from the substrate; a p-type channel layer is located on the side of the gate insulating layer away from the substrate, and the material of the p-type channel layer includes tellurium oxide; a first source and a first drain are both located on the side of the p-type channel layer away from the substrate. The p-type channel layer, being made of tellurium oxide, allows for efficient hole transport even in amorphous states, exhibiting high hole mobility; tellurium oxide can be fabricated at relatively low temperatures, making it temperature-compatible with the heterojunction device; and the thin film uniformity of tellurium oxide is good, resulting in good device consistency. In other words, by incorporating a tellurium oxide p-type channel layer, the yield of p-channel devices can be significantly improved, thereby increasing the yield of heterojunction complementary semiconductor devices.

[0029] Optionally, the substrate 111 may be made of silicon, silicon carbide, sapphire, gallium nitride, aluminum nitride, diamond, or silicon-on-insulator.

[0030] Optionally, the material of the channel layer 112 may include gallium nitride, indium gallium nitride, or silicon nitride.

[0031] Alternatively, the material of the barrier layer 113 may include aluminum gallium nitride, indium aluminum nitride, or indium aluminum potassium nitride.

[0032] Optionally, the material of the p-type semiconductor layer 116 includes p-type doped gallium nitride, p-type doped indium gallium nitride, or p-type doped aluminum gallium nitride, etc. Among them, the p-type doping can be magnesium doping.

[0033] Alternatively, tellurium oxide TeO x The value of x in the equation is between 0 and 1, such as 0, 0.2, 0.4, 0.6, 0.8, or 1.

[0034] Optionally, such as Figure 1 As shown, the thickness of the p-type channel layer 122 ranges from 1 nanometer to 50 nanometers.

[0035] Specifically, if the p-type channel layer 122 is too thin, its mobility will decrease, causing the threshold voltage of the p-channel device to drift, and there is also a risk of source-drain breakdown. Conversely, if the p-type channel layer 122 is too thick, the control capability of the gate electrode 117 over the p-channel device will decrease. The thickness of the p-type channel layer 122 in this embodiment ensures both high mobility and a stable threshold voltage for the p-channel device, while also maintaining strong control capability of the gate electrode 117 over the p-channel device. Optionally, the thickness of the p-type channel layer 122 can be 1 nm, 5 nm, 10 nm, 15 nm, 20 nm, 25 nm, 30 nm, 35 nm, 40 nm, 45 nm, or 50 nm, etc.

[0036] Optionally, the material of the gate insulating layer 121 may include aluminum oxide, aluminum nitride, silicon nitride, silicon oxide, or gallium oxynitride.

[0037] Optionally, the thickness of the gate insulating layer 121 ranges from 1 nanometer to 50 nanometers. For example, the thickness of the gate insulating layer 121 can be 1 nanometer, 5 nanometers, 10 nanometers, 15 nanometers, 20 nanometers, 25 nanometers, 30 nanometers, 35 nanometers, 40 nanometers, 45 nanometers, or 50 nanometers, etc.

[0038] Optionally, continue to refer to Figure 1 The heterojunction complementary semiconductor device also includes a second source 114 and a second drain 115. Both the second source 114 and the second drain 115 are in contact with the heterojunction and are located on the side of the heterojunction away from the substrate 111.

[0039] Specifically, the second source 114 is in contact with the barrier layer 113, and an ohmic contact is formed between them. The second drain 115 is in contact with the barrier layer 113, and an ohmic contact is formed between them. The second source 114 and the second drain 115 serve as the source and drain of the heterojunction device 11, respectively. The second source 114 and the second drain 115 are located on opposite sides of the p-type semiconductor layer 116. When the channel of the heterojunction device is turned on and a voltage is applied between the second source 114 and the second drain 115, a current can be generated in the channel of the heterojunction device 11.

[0040] Optionally, in some embodiments, the second source 114 may be a titanium / aluminum / nickel / gold stacked structure. The second drain 115 may be a titanium / aluminum / nickel / gold stacked structure.

[0041] Alternatively, in some embodiments, the first source 123 may be nickel. The first drain 124 may also be made of nickel.

[0042] Optionally, in some embodiments, the orthographic projection of the first source 123 on the substrate 111 is located between and close to the orthographic projection of the second source 114 on the substrate 111 and the second drain 115 on the substrate 111. Similarly, the orthographic projection of the first drain 124 on the substrate 111 is located between and close to the orthographic projection of the second source 114 on the substrate 111 and the second drain 115 on the substrate 111. This arrangement facilitates subsequent connection of the first drain 124 and the second drain 115 to enable the p-channel device and the heterojunction device to be connected in series as a complementary logic circuit.

[0043] Optionally, refer to Figure 1 The heterogeneous integrated complementary semiconductor device further includes a second passivation layer 132, a first vertical connection structure 141, a second vertical connection structure 142, and a third vertical connection structure 143. The second passivation layer 132 covers a first source 114, a first drain 115, a second source 123, and a second drain 124. A first opening exposing the first source 114, a second opening exposing the first drain 115, a third opening exposing the second source 123, and a fourth opening exposing the second drain 124 are formed on the second passivation layer 132. The first vertical connection structure 141 fills the first opening and is connected to the first source 123. The second vertical connection structure 142 fills the third opening and is connected to the second source 114. The third vertical connection structure 143 fills the second and fourth openings and is connected to both the first drain 124 and the second drain 115.

[0044] Specifically, the material of the second passivation layer 132 can be an insulating material such as silicon nitride or silicon oxide. The second passivation layer 132 serves to isolate and protect the various vertical connection structures, sources, and drains, preventing these structures from being corroded by external water, oxygen, etc., and preventing short circuits in the relevant structures.

[0045] The first vertical connection structure 141 is used to bring the first source 141 to the surface of the heterojunction complementary semiconductor device. The second vertical connection structure 142 is used to bring the second source 142 to the surface of the heterojunction complementary semiconductor device. The third vertical connection structure 143 is used to connect the first drain 124 and the second drain 115, thereby connecting the heterojunction device 11 in series with the p-channel device. Through each vertical connection structure, the corresponding electrode can be brought to the surface of the heterojunction complementary semiconductor device, facilitating subsequent packaging or connection with other external circuits.

[0046] Optionally, the material of the above-mentioned vertical connection structure can be a titanium / aluminum laminate structure.

[0047] Optionally, refer to Figure 1 The orthogonal projection of the gate insulating layer 121 on the substrate 111 is located within the orthogonal projection of the gate electrode 117 on the substrate 111; the orthogonal projection of the p-type channel layer 122 on the substrate 111 is located within the orthogonal projection of the gate insulating layer 121 on the substrate 111.

[0048] Specifically, in this embodiment, the overall planar dimension of the p-channel device is defined by the planar dimension of the gate electrode 117. That is, the overall planar dimension of the p-channel device is less than or equal to the planar dimension of the gate electrode 117. After forming the gate electrode 117, a gate insulating layer 121 can be directly fabricated on the gate electrode 117, and a p-type channel layer 122 can be fabricated on the gate insulating layer 121. The surface of the gate insulating layer 121 near the substrate 111 only contacts the gate electrode 117, resulting in high surface uniformity of the gate insulating layer 121 near the substrate 111 and reducing interface defects of the gate insulating layer 121. Similarly, the surface of the p-type channel layer 122 near the substrate 111 only contacts the gate insulating layer 121, which can also reduce interface defects of the p-type channel layer 122. That is, the configuration of this embodiment can further improve the yield of heterogeneous integrated complementary semiconductor devices.

[0049] Optionally, in the above embodiments, the orthogonal projection of the gate insulating layer 121 on the substrate 111 can coincide with the orthogonal projection of the gate electrode 117 on the substrate 111.

[0050] Optionally, in the above embodiments, the orthogonal projection of the p-type channel layer 122 on the substrate 111 can coincide with the orthogonal projection of the gate insulating layer 121 on the substrate 111.

[0051] Optionally, in some embodiments, the threshold voltage can be adjusted by controlling the thickness of the gate insulating layer 121, so that the threshold voltage of the p-channel device matches that of the heterojunction device 11.

[0052] Optionally, Figure 2 This is a schematic diagram of another heterogeneous integrated complementary semiconductor device provided in an embodiment of the present invention, with reference to... Figure 2 In some embodiments, the heterojunction complementary semiconductor device further includes a first passivation layer 131, which is located on the side of the heterojunction away from the substrate 111 and is in contact with the heterojunction.

[0053] The first passivation layer 131 covers the side surface of the p-type semiconductor layer 114 and the side surface of the gate electrode 117. The side of the first passivation layer 131 away from the substrate 111 is flush with the side of the gate electrode 117 away from the substrate 111. The orthogonal projection area of ​​the gate insulating layer 121 on the substrate 111 is larger than the orthogonal projection area of ​​the gate electrode 117 on the substrate 111; and the orthogonal projection of the gate electrode 117 on the substrate 111 is located within the orthogonal projection of the gate insulating layer 121 on the substrate 111. The orthogonal projection of the p-type channel layer 122 on the substrate 111 coincides with the orthogonal projection of the gate insulating layer 121 on the substrate 111.

[0054] Specifically, in this embodiment, by providing the first passivation layer 131, the mesa area supporting the gate insulating layer 121 can be expanded. That is, after forming the gate electrode 117, the gate insulating layer 121 is not immediately fabricated; instead, a first passivation layer 131 is fabricated first. Furthermore, the first passivation layer 131 is flush with the surface of the gate electrode 117. Then, the gate insulating layer 121 can be fabricated on a larger mesa, meaning the gate insulating layer 121 can have a larger planar dimension, which in turn allows the p-type channel layer 122 to also have a larger planar dimension. This results in a lower on-resistance for the p-channel device, which is beneficial for improving the performance of heterogeneous integrated complementary semiconductor devices.

[0055] Optionally, in some embodiments, the material of the first passivation layer 131 is the same as the material of the second passivation layer 132, such as silicon nitride or silicon oxide.

[0056] Optionally, in some embodiments, the outer contour of the orthogonal projection of the gate insulating layer 121 on the substrate 111 coincides with the outer contour of the orthogonal projection of the first passivation layer 131 on the substrate 111.

[0057] Optionally, in some embodiments, the orthographic projection of the first passivation layer 131 onto the substrate 111 lies between the orthographic projections of the second source 114 and the second drain 115 onto the substrate 111. Furthermore, the two can be in contact; that is, the first passivation layer 131 is in contact with both the second source 114 and the second drain 115. In this case, the second passivation layer 132 can have a larger planar dimension, thereby allowing the gate insulating layer 121 and the p-type channel layer 122 to also have larger planar dimensions.

[0058] Optionally, in other embodiments, the first passivation layer 131 is located between the second source 114 and the second drain 115, and there is a preset interval between the first passivation layer 131 and the second source 114, and a preset interval between the first passivation layer 131 and the second drain 115. In this case, there is a certain lateral spacing between the gate insulating layer 121, the p-type channel layer 122, and the first source 123 and the second source 114, and correspondingly, there is also a certain lateral spacing between them and the second vertical connection structure 142, to avoid short circuits with the second vertical connection structure 142. Furthermore, there is also a certain lateral spacing between the gate insulating layer 121 and the p-type channel layer 122 and the third vertical connection structure 142, to avoid short circuits with the third vertical connection structure 143.

[0059] Based on the same inventive concept, this invention also provides a method for fabricating a heterogeneous integrated complementary semiconductor device, used to fabricate the heterogeneous integrated complementary semiconductor device provided in any embodiment of this invention. For example... Figure 3 As shown, Figure 3 This is a flowchart illustrating a method for fabricating a heterogeneous integrated complementary semiconductor device according to an embodiment of the present invention. The method includes: Step S101: Provide a heterojunction device, which includes a substrate, a heterojunction, a p-type semiconductor layer, and a gate electrode; wherein the heterojunction is located on one side of the substrate; the p-type semiconductor layer is located on the side of the heterojunction away from the substrate; and the gate electrode is located on the side of the p-type semiconductor layer away from the substrate. Specifically, heterojunction devices are formed on a substrate through processes such as epitaxy.

[0060] Step S102: A gate insulating layer is formed on the side of the gate electrode away from the substrate; Specifically, for example, a gate insulating layer can be formed by deposition.

[0061] Step S103: A p-type channel layer is formed on the side of the gate insulating layer away from the substrate; wherein the material of the p-type channel layer includes tellurium oxide; Specifically, p-type channel layers can be formed through deposition or other methods. Materials for p-type channel layers include tellurium oxide. Holes in p-type channel layers can still transport efficiently even in the amorphous state, meaning they have high hole mobility. Tellurium oxide can be fabricated at relatively low temperatures, making it temperature-compatible with heterojunction devices. Furthermore, tellurium oxide films exhibit good uniformity, resulting in better device consistency. Therefore, by incorporating tellurium oxide p-type channel layers, the yield of p-channel devices can be significantly improved, thereby increasing the yield of heterojunction complementary semiconductor devices.

[0062] Step S104: A first source and a first drain are formed on the side of the p-type channel layer away from the substrate.

[0063] Specifically, the first source and the first drain can be formed by methods such as vapor deposition.

[0064] The method for fabricating heterogeneous integrated complementary semiconductor devices in this embodiment can produce heterogeneous integrated complementary semiconductor devices with high yield.

[0065] Optionally, Figures 4-10 This is a schematic diagram of the product structure corresponding to the main steps of a method for fabricating a heterogeneous integrated complementary semiconductor device according to an embodiment of the present invention. (Reference) Figures 4-10 The preparation method will be described in detail.

[0066] Heterojunction devices include: Figure 4 As shown, a heterojunction epitaxial wafer is first provided, comprising a substrate 111, a channel layer 112, a barrier layer 113, and a p-type semiconductor layer 116 stacked sequentially. Mesa isolation is then performed to form... Figure 1 The structure shown is an example of mesa isolation, which involves dividing the wafer into multiple heterojunction complementary semiconductor devices (HMS / MS) and isolating the heterojunctions of different HMS / MS. Specifically, this can be achieved by using a mixed plasma of Cl2 / BCl3 to etch the passive regions, preventing interference between the individual HMS / MS devices.

[0067] Then, as Figure 5 As shown, a mixed plasma of Cl2 / BCl3 is used to etch the p-type semiconductor layer 116, thereby removing the p-type semiconductor layer 116 that is subsequently used to prepare the second source and the second drain.

[0068] Then, as Figure 6 As shown, a titanium / aluminum / nickel / gold stacked structure, or a titanium / aluminum / nickel / titanium nitride stacked structure, is formed by electron beam evaporation. Then, rapid thermal annealing is performed to form ohmic contacts, i.e., to form the second source 114 and the second drain 115. The rapid thermal annealing temperature range is 800℃~1000℃.

[0069] Then, as Figure 7 As shown, a titanium / titanium nitride stacked structure is formed on the p-type semiconductor layer 116 by electron beam evaporation, which forms the gate electrode 117. At this point, the heterojunction device fabrication is complete. The gate electrode 117 can also be a tungsten / titanium nitride / titanium / nickel / copper / aluminum stacked structure.

[0070] Then, before forming the gate insulating layer 121, the gate electrode 117 can be pretreated to make the surface of the gate electrode 117 flat and reduce surface defects.

[0071] Then, as Figure 8As shown, a dielectric thin film (alumina, aluminum nitride, silicon nitride, silicon oxide, or gallium oxynitride, etc.) is deposited above the gate electrode 117 by enhanced plasma atomic layer deposition / thermal atomic layer deposition / magnetron sputtering, which forms the gate insulating layer 121.

[0072] Optionally, in some embodiments, a first passivation layer may be formed on the side of the heterojunction away from the substrate before forming the gate insulating layer. The first passivation layer is then flush with the surface of the gate electrode. Subsequently, a gate insulating layer is formed on the common surface of the first passivation layer and the gate electrode.

[0073] After forming p-gate insulation, as Figure 8 As shown, a p-type channel layer is formed. Specifically, a tellurium material layer can first be formed on the side of the gate insulating layer away from the substrate. This tellurium material layer can be formed through methods such as enhanced plasma atomic layer deposition (IPD), thermal atomic layer deposition (TDP), magnetron sputtering, metal-organic chemical vapor deposition (MOCVD), or molecular beam epitaxy (MBE). Then, the tellurium material layer is annealed to form tellurium oxide, thus forming the p-type channel layer. The annealing temperature range is 400℃ to 500℃. It is evident that the p-type channel layer formation process requires a lower temperature, making it compatible with the process temperature of heterojunction devices and improving the yield of heterogeneous integrated complementary semiconductor devices. It should be noted that the growth conditions of the tellurium material layer affect the mobility of the p-type channel layer. Furthermore, during the thermal annealing of the tellurium material layer after the first passivation layer is fabricated, the first passivation layer can also protect the exposed surface of the barrier layer 113, preventing damage to the barrier layer 113.

[0074] Then, as Figure 9 As shown, the first source 123 and the first drain 124 are formed by electron beam evaporation. Since the first source 123 and the first drain 124 are in direct contact with the p-type channel layer, after the evaporation is completed, the first source 123 and the first drain 124 form an ohmic contact with the p-type channel layer, and no thermal annealing or other processes are required.

[0075] Then, as Figure 10 As shown, a second passivation layer 132 of 100 nm to 500 nm is formed using plasma-enhanced chemical vapor deposition or other methods, and a first opening G1, a second opening G2, a third opening G3 and a fourth opening G4 are formed on the second passivation layer 132 by reactive ion etching or inductively coupled plasma etching or other methods.

[0076] Finally, the vertical interconnect structures are formed by electron beam evaporation, thus forming... Figure 1 or Figure 2 The structure shown.

[0077] It should be understood that the various forms of processes shown above can be used, with steps reordered, added, or deleted. For example, the steps described in this invention can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution of this invention can be achieved, and this is not limited herein.

[0078] The specific embodiments described above do not constitute a limitation on the scope of protection of this invention. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this invention should be included within the scope of protection of this invention.

Claims

1. A heterogeneous integrated complementary semiconductor device, characterized in that, The heterogeneous integrated complementary semiconductor device includes: A heterojunction device includes a substrate, a heterojunction, a p-type semiconductor layer, and a gate electrode; wherein the heterojunction is located on one side of the substrate; the p-type semiconductor layer is located on the side of the heterojunction away from the substrate; and the gate electrode is located on the side of the p-type semiconductor layer away from the substrate. A gate insulating layer is located on the side of the gate electrode away from the substrate; A p-type channel layer is located on the side of the gate insulating layer away from the substrate, and the material of the p-type channel layer includes tellurium oxide; The first source and the first drain are both located on the side of the p-type channel layer away from the substrate.

2. The heterogeneous integrated complementary semiconductor device according to claim 1, characterized in that, The thickness of the p-type channel layer ranges from 1 nanometer to 50 nanometers.

3. The heterogeneous integrated complementary semiconductor device according to claim 1, characterized in that, The heterojunction complementary semiconductor device further includes a second source and a second drain, both of which are in contact with the heterojunction and located on the side of the heterojunction away from the substrate.

4. The heterogeneous integrated complementary semiconductor device according to claim 1, characterized in that, The orthographic projection of the gate insulating layer on the substrate is located within the orthographic projection of the gate electrode on the substrate; the orthographic projection of the p-type channel layer on the substrate is located within the orthographic projection of the gate insulating layer on the substrate.

5. The heterogeneous integrated complementary semiconductor device according to claim 1, characterized in that, The heterojunction complementary semiconductor device further includes a first passivation layer, which is located on the side of the heterojunction away from the substrate and is in contact with the heterojunction. The first passivation layer covers the side surface of the p-type semiconductor layer and the side surface of the gate electrode; The side of the first passivation layer away from the substrate is flush with the side of the gate electrode away from the substrate; The projected area of ​​the gate insulating layer on the substrate is greater than the projected area of ​​the gate electrode on the substrate; Furthermore, the orthogonal projection of the gate electrode onto the substrate is located within the orthogonal projection of the gate insulating layer onto the substrate; The orthographic projection of the p-type channel layer on the substrate coincides with the orthographic projection of the gate insulating layer on the substrate.

6. The heterogeneous integrated complementary semiconductor device according to claim 1, characterized in that, The heterojunction includes a channel layer and a barrier layer that are sequentially located away from the substrate.

7. The heterogeneous integrated complementary semiconductor device according to claim 3, characterized in that, The heterogeneous integrated complementary semiconductor device further includes: A second passivation layer covers the first source, the first drain, the second source, and the second drain; the second passivation layer has a first opening exposing the first source, a second opening exposing the first drain, a third opening exposing the second source, and a fourth opening exposing the second drain. A first vertical connection structure, wherein the vertical connection structure fills the first opening and is connected to the first source electrode; A second vertical connection structure, wherein the second vertical connection structure fills the third opening and is connected to the second source electrode; A third vertical connection structure is provided, which fills the second opening and the fourth opening, and is connected to both the first drain and the second drain.

8. A method for fabricating a heterogeneous integrated complementary semiconductor device, characterized in that, The method for fabricating the heterogeneous integrated complementary semiconductor device includes: A heterojunction device is provided, the heterojunction device comprising a substrate, a heterojunction, a p-type semiconductor layer, and a gate electrode; wherein the heterojunction is located on one side of the substrate; the p-type semiconductor layer is located on the side of the heterojunction away from the substrate; and the gate electrode is located on the side of the p-type semiconductor layer away from the substrate. A gate insulating layer is formed on the side of the gate electrode away from the substrate; A p-type channel layer is formed on the side of the gate insulating layer away from the substrate; wherein the material of the p-type channel layer includes tellurium oxide; A first source and a first drain are formed on the side of the p-type channel layer away from the substrate.

9. The method for fabricating a heterogeneous integrated complementary semiconductor device according to claim 8, characterized in that, The formation of a p-type channel layer on the side of the gate insulating layer away from the substrate includes: A tellurium material layer is formed on the side of the gate insulating layer away from the substrate; The tellurium material layer is annealed to form the p-type channel layer.

10. The method for fabricating a heterogeneous integrated complementary semiconductor device according to claim 8, characterized in that, Before forming a gate insulating layer on the side of the gate electrode away from the substrate, the method further includes: A first passivation layer is formed on the side of the heterojunction away from the substrate. The first passivation layer covers the side of the p-type semiconductor layer and the side of the gate electrode. The side of the first passivation layer away from the substrate is flush with the side of the gate electrode away from the substrate.

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