Semiconductor device and method of manufacturing the same

Abstract

The application provides a semiconductor device and a preparation method thereof. A substrate comprises a first region and a second region. A first gate structure is located on the first region of the substrate, and a second gate structure is located on the second region of the substrate. The first gate structure and the second gate structure each comprise, from bottom to top, an interface layer, a high dielectric constant dielectric layer, a work function layer, a doped semiconductor layer, a conductive layer and an insulating cover layer. The high dielectric constant dielectric layer of the first gate structure contains rare earth metal elements and halogen elements. The application can better adjust the work function layer of the first gate structure and improve the electrical performance of the semiconductor device.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a semiconductor device and its fabrication method. Background Technology

[0002] As integrated circuit manufacturing processes continue to evolve towards smaller nodes, HKMG (High-K Metal Gate) technology has become one of the core modules of advanced chip manufacturing. The HKMG structure uses a high-k dielectric material (such as HfSiON) instead of traditional SiO2, and is paired with a metal gate, effectively solving the Fermi level pinning and gate leakage problems of polysilicon gates. While both NMOS and PMOS gate structures use the same high-k dielectric layer, adjusting the elements in the high-k dielectric layer of the NMOS requires different methods to adjust the threshold voltage. Therefore, a solution for adjusting the high-k dielectric layer is needed. Summary of the Invention

[0003] The purpose of this invention is to provide a semiconductor device and its fabrication method, which can better adjust the work function layer of the first gate structure and improve the electrical performance of the semiconductor device.

[0004] To achieve the above objectives, the present invention provides a semiconductor device comprising:

[0005] The substrate includes a first region and a second region;

[0006] A first gate structure is located on a first region of the substrate;

[0007] The second gate structure is located on the second region of the substrate;

[0008] Both the first gate structure and the second gate structure include, from bottom to top, an interface layer, a high dielectric constant layer, a work function layer, a doped semiconductor layer, a conductive layer, and an insulating capping layer. The high dielectric constant layer of the first gate structure contains rare earth metal elements and halogen elements.

[0009] Optionally, the rare earth metal element is La, the halogen element is F, and the high dielectric constant dielectric layer further contains Hf.

[0010] Optionally, the concentration peak position of the rare earth metal element is closer to the work function layer than the concentration peak position of the halogen element.

[0011] Optionally, the peak concentration position of the halogen element is closer to the peak concentration position of Hf in the high dielectric constant dielectric layer than the peak concentration position of the rare earth metal element.

[0012] Optionally, the average concentration of the rare earth metal element in the upper half of the high dielectric constant dielectric layer is greater than the average concentration in the lower half of the high dielectric constant dielectric layer.

[0013] Optionally, the average concentration of the halogen element in the upper half of the high dielectric constant dielectric layer is the same as or has a difference from the average concentration in the lower half of the high dielectric constant dielectric layer, wherein the difference is within 10% of the average concentration of the halogen element in the entire high dielectric constant dielectric layer.

[0014] Optionally, the concentration of the halogen element is greater than the concentration of the rare earth metal element.

[0015] Optionally, a channel strain layer may also be included, located between the second region of the substrate and the second gate structure.

[0016] Optionally, it also includes a sidewall structure located on the sidewall of the first gate structure and the second gate structure.

[0017] Optionally, the conductive layer may be made of at least one of Ti, TiN, WSi2, and W.

[0018] This invention also provides a method for fabricating a semiconductor device, comprising:

[0019] A substrate is provided, comprising a first region and a second region;

[0020] A first gate structure is formed on a first region of the substrate, and a second gate structure is formed on a second region of the substrate;

[0021] Both the first gate structure and the second gate structure include, from bottom to top, an interface layer, a high dielectric constant layer, a work function layer, a doped semiconductor layer, a conductive layer, and an insulating capping layer. The high dielectric constant layer of the first gate structure contains rare earth metal elements and halogen elements.

[0022] Optionally, a channel strain layer is further formed between the second region of the substrate and the second gate structure.

[0023] Optionally, the step of forming the high dielectric constant dielectric layer includes:

[0024] The interface layer, the high dielectric constant dielectric layer, and the rare earth metal element material layer are sequentially formed in the first and second regions of the substrate, wherein the rare earth metal element material layer contains the rare earth metal element.

[0025] A photoresist layer is formed to cover a rare earth metal element material layer on a first region of the substrate, the photoresist layer containing halogen elements, and the rare earth metal element material layer on a second region of the substrate is etched away.

[0026] The photoresist layer is subjected to heat treatment or ultraviolet light treatment, so that the halogen elements in the photoresist layer enter the rare earth metal element material layer on the first region of the substrate.

[0027] Remove the photoresist layer and heat-treat the rare earth metal element material layer on the first region of the substrate, so that the rare earth metal elements and halogen elements in the rare earth metal element material layer enter the high dielectric constant dielectric layer on the first region of the substrate.

[0028] Optionally, after removing the photoresist layer, the rare earth metal element material layer on the first region and the high dielectric constant dielectric layer on the second region are passivated using a DHF solution.

[0029] Optionally, after heat-treating the rare earth metal element material layer on the first region of the substrate, the remaining rare earth metal element material layer is removed, and the work function layer, the doped semiconductor layer, the conductive layer and the insulating capping layer are deposited sequentially.

[0030] Optionally, the rare earth metal element is La, the halogen element is F, and the high dielectric constant dielectric layer further contains Hf.

[0031] Optionally, the concentration peak position of the rare earth metal element is closer to the work function layer than the concentration peak position of the halogen element.

[0032] Optionally, the peak concentration position of the halogen element is closer to the peak concentration position of Hf in the high dielectric constant dielectric layer than the peak concentration position of the rare earth metal element.

[0033] Optionally, the average concentration of the rare earth metal element in the upper half of the high dielectric constant dielectric layer is greater than the average concentration in the lower half of the high dielectric constant dielectric layer.

[0034] Optionally, the average concentration of the halogen element in the upper half of the high dielectric constant dielectric layer is the same as or has a difference from the average concentration in the lower half of the high dielectric constant dielectric layer, wherein the difference is within 10% of the average concentration of the halogen element in the entire high dielectric constant dielectric layer.

[0035] Optionally, the concentration of the halogen element is greater than the concentration of the rare earth metal element.

[0036] Optionally, after forming the first gate structure and the second gate structure, the method further includes forming a sidewall structure located on the sidewalls of the first gate structure and the second gate structure.

[0037] In the semiconductor device and its fabrication method provided by this invention, the substrate includes a first region and a second region. A first gate structure is located on the first region of the substrate, and a second gate structure is located on the second region of the substrate. Both the first and second gate structures include, from bottom to top, an interface layer, a high-dielectric-constant dielectric layer, a work function layer, a doped semiconductor layer, a conductive layer, and an insulating capping layer. The high-dielectric-constant dielectric layer of the first gate structure contains rare-earth metal elements and halogen elements. By including rare-earth metal elements and halogen elements in the high-dielectric-constant dielectric layer of the first gate structure, this invention better adjusts the work function layer of the first gate structure, thereby improving the electrical performance of the semiconductor device. Attached Figure Description

[0038] Figure 1 This is a cross-sectional schematic diagram of a semiconductor device provided in an embodiment of the present invention.

[0039] Figure 2 This is a schematic diagram showing the concentration positions of various elements contained in a high dielectric constant dielectric layer in a semiconductor device according to an embodiment of the present invention.

[0040] Figures 3-8 This is a cross-sectional schematic diagram of a corresponding step in a method for fabricating a semiconductor device according to an embodiment of the present invention.

[0041] The attached figures are labeled as follows:

[0042] 100 - Substrate; 100A - First region; 100B - Second region; 110 - Isolation trench; 120 - First isolation layer; 130 - Second isolation layer; 140 - Third isolation layer; 200a - First gate structure; 200b - Second gate structure; 210 - Interface layer; 220 - High dielectric constant dielectric layer; 230 - Work function layer; 240 - Doped semiconductor layer; 250 - Conductive layer; 260 - Insulating cap layer; 300 - Channel strain layer; 410 - First sidewall layer; 420 - Second sidewall layer; 430 - Third sidewall layer; 440 - Fourth sidewall layer; 500 - Rare earth metal element material layer; 600 - Photoresist layer. Detailed Implementation

[0043] To make the objectives, advantages, and features of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be noted that the drawings are all in a very simplified form and are not drawn to scale, and are only used to facilitate and clarify the explanation of the embodiments of this invention. Furthermore, the structures shown in the drawings are often part of the actual structures. In particular, different figures may emphasize different aspects and may sometimes use different scales.

[0044] Figure 1 This is a cross-sectional schematic diagram of the semiconductor device provided in this embodiment. Please refer to... Figure 1This embodiment provides a semiconductor device, including: a substrate 100, a first gate structure 200a, and a second gate structure 200b. The substrate 100 can be a silicon substrate, a gallium arsenide substrate, a germanium substrate, a germanium-silicon substrate, or a fully depleted silicon-on-insulator substrate, and is not limited thereto. The substrate 100 includes a first region 100A and a second region 100B, where the first region 100A is an NMOS region and the second region 100B is a PMOS region. A plurality of isolation trenches 110 are disposed in the substrate 100, located between the first region 100A and the second region 100B, for isolating the first region 100A and the second region 100B. An isolation trench 110 is provided with a first isolation layer 120, a second isolation layer 130, and a third isolation layer 140. The first isolation layer 120 covers the inner wall of the isolation trench 110, the second isolation layer 130 is located on the first isolation layer 120, and the third isolation layer 140 is located on the second isolation layer 130 and fills the isolation trench 110. The first isolation layer 120 and the third isolation layer 140 can be made of the same material, while the second isolation layer 130 is made of a different material than the first isolation layer 120 and the third isolation layer 140. For example, the first isolation layer 120 and the third isolation layer 140 can be made of silicon oxide, while the second isolation layer 130 can be made of silicon nitride.

[0045] A first gate structure 200a is located on a first region 100A of the substrate 100, and a second gate structure 200b is located on a second region 100B of the substrate 100. The first gate structure 200a is an NMOS gate structure, and the second gate structure 200b is a PMOS gate structure. Both the first gate structure 200a and the second gate structure 200b include, from bottom to top, an interface layer 210, a high-dielectric-constant dielectric layer 220, a work function layer 230, a doped semiconductor layer 240, a conductive layer 250, and an insulating cap layer 260. The interface layer 210 is made of silicon oxide, the high-dielectric-constant dielectric layer 220 is made of a high-dielectric-constant dielectric material, such as HfSiON, the work function layer 230 is made of titanium nitride, the doped semiconductor layer 240 is made of doped polysilicon, the conductive layer 250 is made of at least one of Ti, TiN, WSi2, and W, and the insulating cap layer 260 is made of silicon nitride. In this embodiment, the high-dielectric-constant dielectric layer 220 of the first gate structure 200a contains rare-earth metal elements and halogen elements, wherein the rare-earth metal element is La and the halogen element is F. The high-dielectric-constant dielectric layer 220 also contains Hf, and may also contain at least one of Zr, Ti, Ta, Al, Si, O, and N. For example, the high-dielectric-constant dielectric layer 220 may include silicon oxynitride (SiO2). x N y ), Hafnium oxide (HfO) x Such as HfO2), hafnium silicate (HfSi) x O ySuch as HfSiO4), hafnium oxynitride (HfSi x O y N z ), hafnium oxynitride (HfO) x N y ), Hafnium aluminate (HfAl) x O y Hafnium aluminum silicate (HfAl) x Si y O z Hafnium aluminum silicon oxynitride (HfAlSi) x O y N z Zirconium oxide (ZrO) x Such as ZrO2), zirconium silicate (ZrSi) x O y Such as ZrSiO4), zirconium oxynitride silicon (ZrSiO4) x O y N z ), zirconium oxynitride (ZrO) x N y ), aluminum oxide (Al2O3 or AlO) x ), aluminum oxide (AlO) x N y ), aluminum silicate (AlSi) x O y ), aluminum oxynitride silicon (AlSi) x O y N z Titanium oxide (TiO) x Or TiO2), titanium oxynitride (TiO2) x N y ), tantalum oxide (TaO) x (or Ta2O5) or tantalum oxynitride (TaO) x N y ).

[0046] Figure 2 This is a schematic diagram showing the concentration positions of each element in the high-dielectric-constant dielectric layer of the semiconductor device provided in this embodiment. Please refer to... Figure 2 , Figure 2 The vertical axis represents the concentration of the element, with the concentration gradually increasing from bottom to top. Figure 2 The specific concentrations are not indicated; only that the concentration gradually increases from bottom to top. Figure 2 The horizontal axis represents the position of each film layer. From left to right, the horizontal axis represents the positions of the work function layer, the high dielectric constant dielectric layer, and the interface layer. The positions of the horizontal axis from left to right correspond to... Figure 1The structure consists of a work function layer 230, a high dielectric constant dielectric layer 220, and an interface layer 210, arranged from top to bottom. In this embodiment, the peak concentration position of rare earth metal element (La) is closer to the work function layer than the peak concentration position of halogen element (F), such as... Figure 2 The concentration peak positions of rare earth metal element (La) are shown at peak line L1, and those of halogen element (F) are shown at peak line L2. L1 is closer to the work function layer than L2. The concentration peak position of halogen element (F) is closer to the concentration peak position of Hf in the high dielectric constant dielectric layer than that of rare earth metal element (La). Figure 2 In the middle L2, the concentration peak of Hf is closer than that of L1 (not shown in the figure).

[0047] In this embodiment, the high-dielectric-constant dielectric layer is divided into an upper half near the work function layer and a lower half near the interface layer, with the peak concentration of Hf in the high-dielectric-constant dielectric layer as the boundary. The average concentration of rare earth metal element (La) in the upper half of the high-dielectric-constant dielectric layer is greater than that in the lower half. The average concentration of halogen element (F) in the upper half of the high-dielectric-constant dielectric layer is the same as or differs from that in the lower half, with the difference being within 10% of the average concentration of halogen element (F) throughout the entire high-dielectric-constant dielectric layer. The concentration of halogen element (F) is greater than that of rare earth metal element (La), such as... Figure 2 As shown.

[0048] Furthermore, it also includes a channel strain layer 300, which is located between the second region 100B and the second gate structure 200b of the substrate 100. The size of the channel strain layer 300 may be larger than the size of the second gate structure 200b. The material of the channel strain layer 300 includes germanium silicon.

[0049] Furthermore, it also includes a sidewall structure located on the sidewalls of the first gate structure 200a and the second gate structure 200b. The sidewall structure includes a first sidewall layer 410, a second sidewall layer 420, a third sidewall layer 430, and a fourth sidewall layer 440 stacked outward from the sidewalls of the first gate structure 200a and the second gate structure 200b. Specifically, the first sidewall layer 410 is located on the sidewalls of the first gate structure 200a and the second gate structure 200b, the second sidewall layer 420 is located on the first sidewall layer 410, the third sidewall layer 430 is located on the second sidewall layer 420 and the insulating cap layer 260, and may also be located on the substrate 100 between adjacent first gate structures 200a and second gate structures 200b; the fourth sidewall layer 440 is located on the third sidewall layer 430. The first sidewall layer 410 and the third sidewall layer 430 may be made of the same material, the second sidewall layer 420 and the fourth sidewall layer 440 may be made of the same material, the first sidewall layer 410 and the second sidewall layer 420 may be made of different materials, the third sidewall layer 430 and the fourth sidewall layer 440 may be made of different materials, and the materials of the first sidewall layer 410, the second sidewall layer 420, the third sidewall layer 430 and the fourth sidewall layer 440 include at least two of silicon oxide, silicon nitride and silicon oxynitride.

[0050] In this embodiment, by setting the high dielectric constant dielectric layer 220 of the first gate structure 200a (the gate structure of NMOS) to contain rare earth metal elements and halogen elements, the work function layer 230 of the first gate structure 200a can be better adjusted, thereby improving the electrical performance of the semiconductor device.

[0051] This embodiment also provides a method for fabricating a semiconductor device, including:

[0052] Step S1: Provide a substrate, including a first region and a second region;

[0053] Step S2: Form a first gate structure on a first region of the substrate, and form a second gate structure on a second region of the substrate;

[0054] Both the first gate structure and the second gate structure include, from bottom to top, an interface layer, a high dielectric constant dielectric layer, a work function layer, a doped semiconductor layer, a conductive layer, and an insulating capping layer. The high dielectric constant dielectric layer of the first gate structure contains rare earth metal elements and halogen elements.

[0055] Figures 3-8 This is a cross-sectional schematic diagram of a corresponding step in the fabrication method of the semiconductor device provided in this embodiment. The following is in conjunction with... Figures 3-8 The method for fabricating the semiconductor device provided in this embodiment will be described in detail.

[0056] Please refer to Figure 3Step S1: Provide a substrate 100. The substrate 100 can be a silicon substrate, a gallium arsenide substrate, a germanium substrate, a germanium-silicon substrate, or a fully depleted silicon-on-insulator substrate, and is not limited thereto. The substrate 100 includes a first region 100A and a second region 100B. The first region 100A is an NMOS region, and the second region 100B is a PMOS region. A plurality of isolation trenches 110 are provided in the substrate 100. The isolation trenches 110 are located between the first region 100A and the second region 100B and are used to isolate the first region 100A and the second region 100B. An isolation trench 110 is provided with a first isolation layer 120, a second isolation layer 130, and a third isolation layer 140. The first isolation layer 120 covers the inner wall of the isolation trench 110, the second isolation layer 130 is located on the first isolation layer 120, and the third isolation layer 140 is located on the second isolation layer 130 and fills the isolation trench 110. The first isolation layer 120 and the third isolation layer 140 can be made of the same material, while the second isolation layer 130 is made of a different material than the first isolation layer 120 and the third isolation layer 140. For example, the first isolation layer 120 and the third isolation layer 140 can be made of silicon oxide, while the second isolation layer 130 can be made of silicon nitride.

[0057] Step S2: A first gate structure is formed on a first region of the substrate, and a second gate structure is formed on a second region of the substrate. A channel strain layer is also formed between the second region of the substrate and the second gate structure. For details, please refer to [link / reference]. Figure 3 First, a channel strain layer 300 is formed on the second region 100B of the substrate 100. The channel strain layer 300 is made of germanium-silicon. Then, an interface layer 210, a high dielectric constant dielectric layer 220, and a rare earth metal element material layer 500 are sequentially formed in the first region 100A and the second region 100B of the substrate 100. The rare earth metal element material layer 500 contains a rare earth metal element, specifically La, and is made of lanthanum oxide (LaO). The interface layer 210 is made of silicon oxide. The high dielectric constant dielectric layer 220 also contains Hf and may contain at least one of Zr, Ti, Ta, Al, Si, O, and N. For example, the high dielectric constant dielectric layer 220 may include silicon oxynitride (SiO2). x N y ), Hafnium oxide (HfO) x Such as HfO2), hafnium silicate (HfSi) x O y Such as HfSiO4), hafnium oxynitride (HfSi x O y N z ), hafnium oxynitride (HfO) x N y ), Hafnium aluminate (HfAl) x O y Hafnium aluminum silicate (HfAl)x Si y O z Hafnium aluminum silicon oxynitride (HfAlSi) x O y N z Zirconium oxide (ZrO) x Such as ZrO2), zirconium silicate (ZrSi) x O y Such as ZrSiO4), zirconium oxynitride silicon (ZrSiO4) x O y N z ), zirconium oxynitride (ZrO) x N y ), aluminum oxide (Al2O3 or AlO) x ), aluminum oxide (AlO) x N y ), aluminum silicate (AlSi) x O y ), aluminum oxynitride silicon (AlSi) x O y N z Titanium oxide (TiO) x Or TiO2), titanium oxynitride (TiO2) x N y ), tantalum oxide (TaO) x (or Ta2O5) or tantalum oxynitride (TaO) x N y The high dielectric constant dielectric layer 220 and the rare earth metal element material layer 500 will also extend to cover the isolation layer within the isolation trench 110 between the first region 100A and the second region 100B.

[0058] Please refer to Figure 4 A photoresist layer 600 is formed to cover a rare earth metal element material layer 500 on the first region 100A of the substrate 100. The photoresist layer 600 contains a halogen element, specifically F. Then, the rare earth metal element material layer 500 on the second region 100B of the substrate 100 is etched away using the photoresist layer 600 as a mask.

[0059] Please continue to refer to this. Figure 4 After etching away the rare earth metal element material layer 500 on the second region 100B of the substrate 100, the photoresist layer 600 is subjected to heat treatment or ultraviolet light treatment, so that the halogen element (F) in the photoresist layer 600 enters the rare earth metal element material layer 500 on the first region 100A of the substrate 100. Thus, there is no need to inject additional halogen elements, but the halogen elements in the photoresist layer 600 migrate into the rare earth metal element material layer 500 on the first region 100A of the substrate 100.

[0060] Please refer to Figure 5and Figure 6 The photoresist layer 600 is removed, and the rare earth metal element material layer 500 on the first region 100A of the substrate 100 is heat-treated so that the rare earth metal elements and halogen elements in the rare earth metal element material layer 500 enter the high dielectric constant dielectric layer 220 on the first region 100A of the substrate 100, so that the high dielectric constant dielectric layer 220 on the first region 100A of the substrate 100 and the high dielectric constant dielectric layer 220 on the second region 100B of the substrate 100 contain different elements.

[0061] For further information, please continue to refer to [link / reference]. Figure 5 After removing the photoresist layer 600, before heat-treating the rare earth metal element material layer 500 on the first region 100A of the substrate 100, the rare earth metal element material layer 500 on the first region 100A and the high dielectric constant dielectric layer 220 on the second region 100B can be passivated using DHF solution (dilute hydrofluoric acid solution). Passivation using DHF solution can supplement additional F sources.

[0062] For further information, please continue to refer to [link / reference]. Figure 6 After heat treatment of the rare earth metal element material layer 500 on the first region 100A of the substrate 100, the remaining rare earth metal element material layer 500 is removed.

[0063] After the above steps, in the high dielectric constant dielectric layer 220 on the first region 100A, the peak concentration position of rare earth metal element (La) is closer to the work function layer 230 than the peak concentration position of halogen element (F), such as... Figure 2 The concentration peak positions of rare earth metal element (La) are shown at peak line L1, and those of halogen element (F) are shown at peak line L2. L1 is closer to the work function layer than L2. The concentration peak position of halogen element (F) is closer to the concentration peak position of Hf in the high dielectric constant dielectric layer than that of rare earth metal element (La). Figure 2 In the middle L2, the concentration peak of Hf is closer than that of L1 (not shown in the figure).

[0064] Because rare earth metal element (La) migrates from rare earth metal element material layer 500 to high dielectric constant dielectric layer 220 on the first region 100A, and because La has a larger atomic radius than F and Hf, La diffuses more slowly in the lattice of high dielectric constant dielectric layer 220 (e.g., HfO2 lattice). Therefore, La is mainly concentrated in the upper half of high dielectric constant dielectric layer 220, making the average concentration of rare earth metal element (La) in the upper half of high dielectric constant dielectric layer greater than the average concentration of rare earth metal element (La) in the lower half of high dielectric constant dielectric layer.

[0065] Although halogen (F) migrates from the photoresist layer 600 to the rare earth metal material layer 500 and then to the high dielectric constant dielectric layer 220, F can penetrate the entire high dielectric constant dielectric layer 220. The distribution of F is consistent with that of Hf. F has a very small atomic radius and strong electronegativity, and its ability to diffuse along oxygen vacancies or grain boundaries in the lattice of the high dielectric constant dielectric layer 220 (e.g., an HfO2 lattice) is much stronger than that of La. Therefore, F diffuses deeper and more uniformly than the previously deposited La. That is, the average concentration of halogen (F) in the upper half of the high dielectric constant dielectric layer is the same as or differs from the average concentration in the lower half of the high dielectric constant dielectric layer, with the difference being within 10% of the average concentration of halogen (F) throughout the entire high dielectric constant dielectric layer. The concentration of halogen (F) is greater than the concentration of rare earth metal (La), such as... Figure 2 As shown.

[0066] Further, please refer to Figure 7 A work function layer 230, a doped semiconductor layer 240, a conductive layer 250, and an insulating capping layer 260 are sequentially deposited on a high dielectric constant dielectric layer 220. The work function layer 230 is made of titanium nitride, the doped semiconductor layer 240 is made of doped polysilicon, the conductive layer 250 is made of at least one of Ti, TiN, WSi2, and W, and the insulating capping layer 260 is made of silicon nitride. Please refer to [reference needed]. Figure 8 An interface layer 210, a high dielectric constant dielectric layer 220, a work function layer 230, a doped semiconductor layer 240, a conductive layer 250, and an insulating capping layer 260 are etched to form a first gate structure 200a and a second gate structure 200b. Both the first gate structure 200a and the second gate structure 200b include an interface layer 210, a high dielectric constant dielectric layer 220, a work function layer 230, a doped semiconductor layer 240, a conductive layer 250, and an insulating capping layer 260 stacked sequentially from bottom to top.

[0067] For further information, please continue to refer to [link / reference]. Figure 1After forming the first gate structure 200a and the second gate structure 200b, the method further includes forming sidewall structures located on the sidewalls of the first gate structure 200a and the second gate structure 200b. The sidewall structures include a first sidewall layer 410, a second sidewall layer 420, a third sidewall layer 430, and a fourth sidewall layer 440 stacked outward from the sidewalls of the first gate structure 200a and the second gate structure 200b. Specifically, the first sidewall layer 410 is located on the sidewalls of the first gate structure 200a and the second gate structure 200b, the second sidewall layer 420 is located on the first sidewall layer 410, the third sidewall layer 430 is located on the second sidewall layer 420 and the insulating cap layer 260, and may also be located on the substrate 100 between adjacent first gate structures 200a and second gate structures 200b; the fourth sidewall layer 440 is located on the third sidewall layer 430. The first sidewall layer 410 and the third sidewall layer 430 may be made of the same material, the second sidewall layer 420 and the fourth sidewall layer 440 may be made of the same material, the first sidewall layer 410 and the second sidewall layer 420 may be made of different materials, the third sidewall layer 430 and the fourth sidewall layer 440 may be made of different materials, and the materials of the first sidewall layer 410, the second sidewall layer 420, the third sidewall layer 430 and the fourth sidewall layer 440 include at least two of silicon oxide, silicon nitride and silicon oxynitride.

[0068] In this embodiment, by simultaneously removing the rare earth metal element material layer 500 on the second region 100B and migrating the F in the photoresist layer 600 to the rare earth metal element material layer 500 on the first region 100A using the photoresist layer 600, process steps can be saved, and the work function layer 230 of the first gate structure 200a can be better adjusted. Furthermore, La is concentrated in the upper half of the high dielectric constant dielectric layer 220 on the first region 100A (close to the gate side), while F is uniformly distributed throughout the high dielectric constant dielectric layer 220. The spatial distribution difference between La and F allows them to synergistically reduce the effective work function from two dimensions: interface dipole and bulk defect passivation, thereby better adjusting the work function layer of the first gate structure and improving the electrical performance of the semiconductor device.

[0069] In summary, in the semiconductor device and its fabrication method provided by this invention, the substrate includes a first region and a second region. A first gate structure is located on the first region of the substrate, and a second gate structure is located on the second region of the substrate. Both the first and second gate structures include, from bottom to top, an interface layer, a high-dielectric-constant dielectric layer, a work function layer, a doped semiconductor layer, a conductive layer, and an insulating capping layer. The high-dielectric-constant dielectric layer of the first gate structure contains rare-earth metal elements and halogen elements. By including rare-earth metal elements and halogen elements in the high-dielectric-constant dielectric layer of the first gate structure, this invention better regulates the work function layer of the first gate structure, thereby improving the electrical performance of the semiconductor device.

[0070] The above are merely preferred embodiments of the present invention and do not constitute any limitation on the present invention. Any equivalent substitutions or modifications made by those skilled in the art to the technical solutions and content disclosed in the present invention without departing from the scope of the present invention shall be deemed to have remained within the protection scope of the present invention.

Claims

1. A semiconductor device, characterized in that, include: The substrate includes a first region and a second region; A first gate structure is located on a first region of the substrate; The second gate structure is located on the second region of the substrate; Both the first gate structure and the second gate structure include, from bottom to top, an interface layer, a high dielectric constant layer, a work function layer, a doped semiconductor layer, a conductive layer, and an insulating capping layer. The high dielectric constant layer of the first gate structure contains rare earth metal elements and halogen elements.

2. The semiconductor device as claimed in claim 1, characterized in that, The rare earth metal element is La, the halogen element is F, and the high dielectric constant dielectric layer also contains Hf.

3. The semiconductor device as described in claim 1, characterized in that, The concentration peak position of the rare earth metal element is closer to the work function layer than the concentration peak position of the halogen element.

4. The semiconductor device as described in claim 2, characterized in that, The peak concentration position of the halogen element is closer to the peak concentration position of Hf in the high dielectric constant dielectric layer than the peak concentration position of the rare earth metal element.

5. The semiconductor device as claimed in claim 1, characterized in that, The average concentration of the rare earth metal element in the upper half of the high dielectric constant dielectric layer is greater than the average concentration in the lower half of the high dielectric constant dielectric layer.

6. The semiconductor device as claimed in claim 1, characterized in that, The average concentration of the halogen element in the upper half of the high dielectric constant dielectric layer is the same as or differs from the average concentration in the lower half of the high dielectric constant dielectric layer, wherein the difference is within 10% of the average concentration of the halogen element in the entire high dielectric constant dielectric layer.

7. The semiconductor device as claimed in claim 1, characterized in that, The concentration of the halogen element is greater than the concentration of the rare earth metal element.

8. The semiconductor device as claimed in claim 1, characterized in that, It also includes a channel strain layer located between the second region of the substrate and the second gate structure.

9. The semiconductor device as claimed in claim 1, characterized in that, It also includes sidewall structures located on the sidewalls of the first gate structure and the second gate structure.

10. The semiconductor device as claimed in claim 1, characterized in that, The conductive layer is made of at least one of Ti, TiN, WSi2, and W.

11. A method for fabricating a semiconductor device, characterized in that, include: A substrate is provided, comprising a first region and a second region; A first gate structure is formed on a first region of the substrate, and a second gate structure is formed on a second region of the substrate; Both the first gate structure and the second gate structure include, from bottom to top, an interface layer, a high dielectric constant layer, a work function layer, a doped semiconductor layer, a conductive layer, and an insulating capping layer. The high dielectric constant layer of the first gate structure contains rare earth metal elements and halogen elements.

12. The method for fabricating a semiconductor device as described in claim 11, characterized in that, A channel strain layer is also formed between the second region of the substrate and the second gate structure.

13. The method for fabricating a semiconductor device as described in claim 11, characterized in that, The steps for forming the high dielectric constant dielectric layer include: The interface layer, the high dielectric constant dielectric layer, and the rare earth metal element material layer are sequentially formed in the first and second regions of the substrate, wherein the rare earth metal element material layer contains the rare earth metal element. A photoresist layer is formed to cover a rare earth metal element material layer on a first region of the substrate, the photoresist layer containing halogen elements, and the rare earth metal element material layer on a second region of the substrate is etched away. The photoresist layer is subjected to heat treatment or ultraviolet light treatment, so that the halogen elements in the photoresist layer enter the rare earth metal element material layer on the first region of the substrate. Remove the photoresist layer and heat-treat the rare earth metal element material layer on the first region of the substrate, so that the rare earth metal elements and halogen elements in the rare earth metal element material layer enter the high dielectric constant dielectric layer on the first region of the substrate.

14. The method for fabricating a semiconductor device as described in claim 13, characterized in that, After removing the photoresist layer, the rare earth metal element material layer on the first region and the high dielectric constant dielectric layer on the second region are passivated using DHF solution.

15. The method for fabricating a semiconductor device as described in claim 13, characterized in that, After heat-treating the rare earth metal element material layer on the first region of the substrate, the remaining rare earth metal element material layer is removed, and the work function layer, the doped semiconductor layer, the conductive layer and the insulating capping layer are deposited in sequence.

16. The method for fabricating a semiconductor device as described in claim 11, characterized in that, The rare earth metal element is La, the halogen element is F, and the high dielectric constant dielectric layer also contains Hf.

17. The method for fabricating a semiconductor device as described in claim 11, characterized in that, The concentration peak position of the rare earth metal element is closer to the work function layer than the concentration peak position of the halogen element.

18. The method for fabricating a semiconductor device as described in claim 16, characterized in that, The peak concentration position of the halogen element is closer to the peak concentration position of Hf in the high dielectric constant dielectric layer than the peak concentration position of the rare earth metal element.

19. The method for fabricating a semiconductor device as described in claim 11, characterized in that, The average concentration of the rare earth metal element in the upper half of the high dielectric constant dielectric layer is greater than the average concentration in the lower half of the high dielectric constant dielectric layer.

20. The method for fabricating a semiconductor device as described in claim 11, characterized in that, The average concentration of the halogen element in the upper half of the high dielectric constant dielectric layer is the same as or differs from the average concentration in the lower half of the high dielectric constant dielectric layer, wherein the difference is within 10% of the average concentration of the halogen element in the entire high dielectric constant dielectric layer.

21. The method for fabricating a semiconductor device as described in claim 11, characterized in that, The concentration of the halogen element is greater than the concentration of the rare earth metal element.

22. The method for fabricating a semiconductor device as described in claim 11, characterized in that, After forming the first gate structure and the second gate structure, the method further includes forming a sidewall structure located on the sidewalls of the first gate structure and the second gate structure.

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