Display panel and display device

Abstract

The application relates to a display panel and a display device, which comprise a substrate and an array layer; the array layer is arranged on one side of the substrate, and the array layer comprises a first transistor, a second transistor, a storage capacitor and a plurality of insulating layers; the first transistor and the second transistor each comprise a semiconductor layer, a gate, a first electrode and a second electrode arranged between the plurality of insulating layers, and the first electrode and the second electrode are arranged in the same layer; the storage capacitor comprises a first transparent capacitor electrode, a first connecting part, a second transparent capacitor electrode and a second connecting part arranged between the plurality of insulating layers; the first transparent capacitor electrode is connected with the first connecting part through a first via hole; the second transparent capacitor electrode is connected with the second connecting part through a second via hole; the first connecting part is electrically connected with the first transistor, and the second connecting part is electrically connected with the second transistor; and at least one of the first connecting part and the second connecting part is arranged in the same layer with one of the gate and the first electrode. In this way, the transmittance of the display panel can be improved.

Description

Technical Field

[0001] This application relates to the field of display technology, and in particular to a display panel and display device. Background Technology

[0002] OLED (Organic Light-Emitting Diode) has the characteristics of self-illumination, high brightness, wide viewing angle, high contrast, flexibility, and low power consumption, and has therefore attracted widespread attention. As a new generation of display technology, it has begun to gradually replace traditional LCD displays and is widely used in mobile phone screens, computer monitors, full-color TVs, etc.

[0003] With the development of display technology, various new technologies are constantly emerging, among which transparent display technology is attracting increasing attention. Transparent display devices allow the displayed image to be seen from the front of the screen, and also allow the viewer to see objects behind the transparent display device through the screen. Transparent display devices have many potential applications, such as windows in buildings, cars, and shopping malls. Besides these large-scale applications, small devices such as handheld tablets can also benefit from transparent displays. It is anticipated that a significant portion of the existing display market will be replaced by transparent displays, for example, in the fields of architecture, advertising, and public information.

[0004] However, in related technologies, transparent display devices still suffer from low transmittance, which greatly limits their development. Summary of the Invention

[0005] Based on this, this application provides a display panel and a display device that can improve the transmittance of the display panel.

[0006] According to one aspect of this application, a display panel is provided, comprising:

[0007] Substrate;

[0008] An array layer is disposed on one side of the substrate, and the array layer includes a first transistor, a second transistor, a storage capacitor, and multiple insulating layers;

[0009] Both the first transistor and the second transistor include a semiconductor layer, a gate, a first electrode, and a second electrode disposed between the plurality of insulating layers, wherein the first electrode and the second electrode are disposed in the same layer;

[0010] The storage capacitor includes a first transparent capacitor electrode, a first connecting portion, a second transparent capacitor electrode, and a second connecting portion disposed between the plurality of insulating layers;

[0011] The first transparent capacitor electrode is connected to the first connection portion through a first via; the first via penetrates the insulating layer located between the first transparent capacitor electrode and the first connection portion along the thickness direction of the substrate;

[0012] The second transparent capacitor electrode is connected to the second connection portion through the second via; the second via penetrates the insulating layer located between the second transparent capacitor electrode and the second connection portion along the thickness direction of the substrate;

[0013] The first connection portion is electrically connected to the first transistor, and the second connection portion is electrically connected to the second transistor; at least one of the first connection portion and the second connection portion is disposed on the same layer as the gate and the first electrode.

[0014] In one embodiment, the orthographic projection of the first transparent capacitor electrode on the substrate overlaps the orthographic projection of the first connection portion on the substrate;

[0015] Optionally, the ratio of the projected area of ​​the first connection portion on the substrate to the projected area of ​​the first transparent capacitor electrode on the substrate is 2% to 10%.

[0016] Optionally, the orthographic projection of the first via on the substrate is located within the orthographic projection range of the first transparent capacitor electrode on the substrate;

[0017] Optionally, the orthographic projection of the first via on the substrate overlaps with the orthographic projection of the first connection portion on the substrate;

[0018] Optionally, the orthographic projection of the second transparent capacitor electrode on the substrate overlaps the orthographic projection of the second connection portion on the substrate;

[0019] Optionally, the ratio of the projected area of ​​the second connection portion on the substrate to the projected area of ​​the second transparent capacitor electrode on the substrate is 2% to 10%.

[0020] Optionally, the orthogonal projection of the second via on the substrate is located within the orthogonal projection range of the second transparent capacitor electrode on the substrate;

[0021] Optionally, the orthographic projection of the second via on the substrate overlaps with the orthographic projection of the second connection portion on the substrate;

[0022] Optionally, the orthographic projection of the second connecting portion on the substrate does not overlap with the orthographic projection of the first connecting portion on the substrate.

[0023] In one embodiment, at least one of the insulating layers is disposed between the second transparent capacitor electrode and the first transparent capacitor electrode; the orthographic projection of the first transparent capacitor electrode on the substrate overlaps with the orthographic projection of the second transparent capacitor electrode on the substrate;

[0024] Optionally, the orthographic projection of the first transparent capacitor electrode on the substrate is located within the orthographic projection range of the second transparent capacitor electrode on the substrate;

[0025] Optionally, the transmittance of the first transparent capacitor electrode is 80% to 100%;

[0026] Optionally, the transmittance of the second transparent capacitor electrode is 80% to 100%;

[0027] Optionally, both the first transparent capacitor electrode and the second transparent capacitor electrode are made of transparent conductive oxide.

[0028] In one embodiment, the second transparent capacitor electrode is located on the side of the first transparent capacitor electrode away from the substrate;

[0029] Optionally, the first transparent capacitor electrode is located on the side of the first connection portion away from the substrate;

[0030] Optionally, the second transparent capacitor electrode is located on the side of the second connection portion away from the substrate;

[0031] Optionally,

[0032] Optionally, the first connecting portion and the second connecting portion are disposed in different layers;

[0033] Optionally, the first transparent capacitor electrode and the second connecting portion are disposed in the same layer and arranged at intervals; or, the first transparent capacitor electrode and the second connecting portion are disposed in different layers.

[0034] Optionally, the first connection portion is disposed on the same layer as the gate and arranged at intervals.

[0035] In one embodiment, the first electrode is disposed on the side of the semiconductor layer away from the substrate; the first electrode is connected to the semiconductor layer through a third via; the third via penetrates the insulating layer located between the first electrode and the semiconductor layer along the thickness direction of the substrate; the second electrode is connected to the semiconductor layer through a fourth via; the fourth via penetrates the insulating layer located between the second electrode and the semiconductor layer along the thickness direction of the substrate; the gate electrode is located between the semiconductor layer and the substrate; and the first transparent capacitor electrode is located between the semiconductor layer and the first electrode.

[0036] Optionally, the plurality of insulating layers include a plurality of inorganic insulating layers, and the first electrode, the semiconductor layer, the gate electrode and the first transparent capacitor electrode are disposed at intervals between the plurality of inorganic insulating layers.

[0037] In one embodiment, the first electrode is disposed on the side of the semiconductor layer away from the substrate; the first electrode is connected to the semiconductor layer through a third via; the third via penetrates the insulating layer located between the first electrode and the semiconductor layer along the thickness direction of the substrate; the second electrode is connected to the semiconductor layer through a fourth via; the fourth via penetrates the insulating layer located between the second electrode and the semiconductor layer along the thickness direction of the substrate; the gate electrode is located between the semiconductor layer and the first electrode; and the first transparent capacitor electrode is located between the gate electrode and the first electrode.

[0038] In one embodiment, the second transparent capacitor electrode is disposed in the same layer as both the first electrode and the second electrode, and is arranged at intervals.

[0039] In one embodiment, the second transparent capacitor electrode is disposed on the side of the first electrode away from the substrate;

[0040] Optionally, the plurality of insulating layers further includes multiple organic insulating layers; the multiple organic insulating layers are stacked on the side of the first electrode away from the substrate; the second transparent capacitor electrode is disposed between two adjacent organic insulating layers.

[0041] In one embodiment, the first transparent capacitor electrode is disposed in the same layer as both the first electrode and the second electrode, and is arranged at intervals;

[0042] Optionally, the second transparent capacitor electrode is disposed on the side of the first electrode away from the substrate;

[0043] Optionally, the display panel further includes a pixel definition layer and a plurality of first electrodes; the pixel definition layer is disposed on the side of the array layer away from the substrate; and a plurality of pixel openings are formed on the pixel definition layer;

[0044] The plurality of first electrodes are spaced apart between the pixel definition layer and the array layer; the pixel opening exposes the corresponding first electrode; the first electrode is connected to one of the first pole and the second pole.

[0045] Optionally, the display panel further includes at least one buffer layer disposed between the substrate and the array layer.

[0046] According to another aspect of this application, a display device is provided, including a display panel as described in any of the above embodiments.

[0047] The aforementioned display panel comprises a storage capacitor including a first transparent capacitor electrode, a first connecting portion, a second transparent capacitor electrode, and a second connecting portion disposed between multiple insulating layers; the first transparent capacitor electrode is connected to the first connecting portion through a first via; the first via penetrates the insulating layer between the first transparent capacitor electrode and the first connecting portion along the substrate thickness direction; the second transparent capacitor electrode is connected to the second connecting portion through a second via; the second via penetrates the insulating layer between the second transparent capacitor electrode and the second connecting portion along the substrate thickness direction; the first connecting portion is electrically connected to a first transistor, and the second connecting portion is electrically connected to a second transistor; at least one of the first connecting portion and the second connecting portion is disposed on the same layer as one of the gate and the first electrode. In this way, it is equivalent to replacing the capacitor electrodes made of metal layers in the array layer in related technologies with transparent capacitor electrodes and connecting parts. On the one hand, this can greatly reduce the area of ​​the film layer in the storage capacitor that is disposed in the same layer as the metal layer in the array layer, increase the transmittance of the area where the storage capacitor is located, and thus improve the transmittance of the display panel. On the other hand, since at least one of the first connecting part and the second connecting part is disposed in the same layer as the gate and the first electrode, that is, at least one of the first connecting part and the second connecting part is disposed in the same layer as the metal layer in the array layer, the first connecting part and the second connecting part can facilitate the connection between the storage capacitor and the first transistor and the second transistor, ensuring the display effect of the display panel. Attached Figure Description

[0048] Figure 1 This is a first cross-sectional view of a display panel provided in some embodiments of this application.

[0049] Figure 2 A second cross-sectional view of a display panel provided in some embodiments of this application.

[0050] Figure 3 A third cross-sectional view of a display panel provided in some embodiments of this application.

[0051] Figure 4 A fourth cross-sectional view of a display panel provided in some embodiments of this application.

[0052] Figure 5 A fifth cross-sectional view of a display panel provided in some embodiments of this application.

[0053] Figure 6 This is a schematic diagram of the structure of a display device provided in some embodiments of this application.

[0054] Explanation of reference numerals in the attached figures:

[0055] 1. Display device; 10. Display panel; 11. Substrate; 111. First flexible substrate; 112. First barrier layer; 113. Second flexible substrate; 114. Second barrier layer; 12. Array layer; 121. First transistor; 122. Second transistor; 123. Storage capacitor; 1231. First transparent capacitor electrode; 1232. First connection portion; 1233. Second transparent capacitor electrode; 1234. Second connection portion; 124. Insulating layer; 1241. Inorganic insulating layer; 1242. Organic insulating layer; 1211. Semiconductor layer; 1212. Gate; 1213. First electrode; 1214. Second electrode; 125. First via; 126. Second via; 127. Third via; 128. Fourth via; 13. Pixel definition layer; 131. Pixel opening; 14. First electrode; 15. Buffer layer; 16. Isolation pillar. Detailed Implementation

[0056] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings. Preferred embodiments of this application are shown in the drawings. However, this application can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to provide a thorough and complete understanding of the disclosure of this application.

[0057] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the specification of this application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0058] When describing positional relationships, unless otherwise specified, when an element such as a layer, film, or substrate is referred to as being "on" another element, it can be directly on the other element or there may be intermediate elements. Furthermore, when a layer is referred to as being "below" another layer, it can be directly below it. It is also understood that when a layer is referred to as being "between" two layers, it can be the only layer between the two layers.

[0059] When using the terms “including,” “having,” and “comprising” as described herein, another component may be added unless explicitly qualifying terms such as “only,” “consisting of,” etc. are used. Unless otherwise stated, singular terms may include plural forms and should not be construed as having a quantity of one.

[0060] It should be understood that although the terms “first,” “second,” etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used only to distinguish one element from another. For example, without departing from the scope of this application, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element.

[0061] It should also be understood that, in interpreting an element, although not explicitly described, the element is interpreted as including a range of error, which should be within the acceptable deviation range of a particular value as determined by a person skilled in the art. For example, "approximately," "about," or "substantially" can mean within one or more standard deviations, without limitation herein.

[0062] Furthermore, in the instruction manual, the phrase "planar distribution diagram" refers to the diagram when the target part is viewed from above, and the phrase "cross-sectional diagram" refers to the diagram when the target part is viewed from the side as a cross-section taken by vertically cutting the target part.

[0063] Furthermore, the accompanying drawings are not drawn to a 1:1 scale, and the relative dimensions of the components are shown in the drawings only as examples and not necessarily to actual scale.

[0064] OLED (Organic Light-Emitting Diode) has the characteristics of self-illumination, high brightness, wide viewing angle, high contrast, flexibility, and low power consumption, and has therefore attracted widespread attention. As a new generation of display technology, it has begun to gradually replace traditional LCD displays and is widely used in mobile phone screens, computer monitors, full-color TVs, etc.

[0065] With the development of display technology, various new technologies are constantly emerging, among which transparent display technology is attracting increasing attention. Transparent display devices allow the displayed image to be seen from the front of the screen, and also allow the viewer to see objects behind the transparent display device through the screen. Transparent display devices have many potential applications, such as windows in buildings, cars, and shopping malls. Besides these large-scale applications, small devices such as handheld tablets can also benefit from transparent displays. It is anticipated that a significant portion of the existing display market will be replaced by transparent displays, for example, in the fields of architecture, advertising, and public information.

[0066] However, in related technologies, transparent display devices still suffer from low transmittance, which greatly limits their development.

[0067] In view of the above-mentioned technical problems, this application provides a display panel and a display device that can improve the transmittance of the display panel.

[0068] Firstly, such as Figure 1As shown, this application embodiment provides a display panel 10, which can be an organic light-emitting diode display panel (OLED) or a quantum dot light-emitting diode display panel (QLED).

[0069] The display panel 10 includes a substrate 11 and an array layer 12. The array layer 12 is disposed on one side of the substrate 11 and includes a first transistor 121, a second transistor 122, a storage capacitor 123, and multiple insulating layers 124. The first transistor 121 and the second transistor each include a semiconductor layer 1211, a gate 1212, a first electrode 1213, and a second electrode 1214 disposed between the multiple insulating layers 124. The first electrode 1213 and the second electrode 1214 are disposed on the same layer. The storage capacitor 123 includes a first transparent capacitor electrode 1231, a first connecting portion 1232, a second transparent capacitor electrode 1233, and a second connecting portion 1234 disposed between the multiple insulating layers 124. The first transparent capacitor electrode 1231 passes through a first via 12. 5 is connected to the first connection portion 1232; the first via 125 penetrates the insulating layer 124 located between the first transparent capacitor electrode 1231 and the first connection portion 1232 along the thickness direction of the substrate 11; the second transparent capacitor electrode 1233 is connected to the second connection portion 1234 through the second via 126; the second via 126 penetrates the insulating layer 124 located between the second transparent capacitor electrode 1233 and the second connection portion 1234 along the thickness direction of the substrate 11; the first connection portion 1232 is electrically connected to the first transistor 121, and the second connection portion 1234 is electrically connected to the second transistor 122; at least one of the first connection portion 1232 and the second connection portion 1234 is disposed in the same layer as one of the gate 1212 and the first electrode 1213.

[0070] Specifically, such as Figure 1As shown, substrate 11 can be a rigid substrate or a flexible substrate. When substrate 11 is a rigid substrate, the material of substrate 11 can be glass or silicon wafer, etc. When substrate 11 is a flexible substrate, the material of substrate 11 can include polyimide. Optionally, substrate 11 includes alternately stacked flexible substrates and barrier layers, the barrier layers being used to prevent film contamination. Substrate 11 typically includes a first flexible substrate 111, a first barrier layer 112, a second flexible substrate 113, and a second barrier layer 114 stacked together. The first barrier layer 112 and the second barrier layer 114 can be inorganic layers. During the fabrication of substrate 11, the film layers are usually fabricated layer by layer. Optionally, generally, the first flexible substrate 111 is first fabricated on a rigid substrate (e.g., a glass substrate) (which can be fabricated by coating), then the second barrier layer 114, the second flexible substrate 113, and the second barrier layer 114 are fabricated sequentially, and finally, the rigid substrate is peeled off to obtain substrate 11.

[0071] The array layer 12 includes a driving circuit layer disposed on one side of the substrate 11. The driving circuit layer includes a pixel driving circuit for driving sub-pixels. The pixel driving circuit may include a first transistor 121, a second transistor 122, a storage capacitor 123, and multiple insulating layers 124. The storage capacitor 123 is electrically connected to the first transistor 121 and the second transistor 122. Further, the pixel driving circuit may be a 7T1C pixel circuit (i.e., including 7 transistors and 1 storage capacitor 123). Of course, the pixel driving circuit may also be an 8T1C pixel circuit (including 8 transistors and 1 storage capacitor 123).

[0072] Both the first transistor 121 and the second transistor include a semiconductor layer 1211, a gate 1212, a first electrode 1213, and a second electrode 1214 disposed between multiple insulating layers 124. The multiple insulating layers 124 can separate the gate 1212, the semiconductor layer 1211, and the first electrode 1213 and the second electrode 1214. The gate 1212 may be made of at least one of molybdenum, titanium, and copper. The first electrode 1213 and the second electrode 1214 are respectively the source and the drain. The first electrode 1213 and the second electrode 1214 are disposed in the same layer, that is, the first electrode 1213 and the second electrode 1214 are obtained by etching the same metal film layer. The first electrode 1213 and the second electrode 1214 are made of at least one of molybdenum, titanium, and copper. The first transparent capacitor electrode 1231, the first connection portion 1232, the second transparent capacitor electrode 1233, and the second connection of the storage capacitor 123 can be separated by multiple insulating layers 124.

[0073] In related technologies, to facilitate the connection between the storage capacitor 123 and the transistor and to simplify wiring, the metal layer of the array layer 12 is often used to fabricate the capacitor electrode of the storage capacitor 123. However, the transmittance of the metal layer is very low, and the area of ​​the capacitor electrode of the storage capacitor 123 is relatively large, resulting in low transmittance in the area where the storage capacitor 123 is located, which in turn leads to low transmittance of the display panel 10. Therefore, in this embodiment, the storage capacitor 123 includes a first transparent capacitor electrode 1231, a first connecting portion 1232, a second transparent capacitor electrode 1233, and a second connecting portion 1234 disposed between multiple insulating layers 124; the first transparent capacitor electrode 1231 is connected to the first connecting portion 1232 through a first via 125; the first via 125 penetrates the insulating layer 124 located between the first transparent capacitor electrode 1231 and the first connecting portion 1232 along the thickness direction of the substrate 11; the second transparent capacitor electrode 1233... Electrode 1233 is connected to second connection portion 1234 through second via 126; second via 126 penetrates insulating layer 124 located between second transparent capacitor electrode 1233 and second connection portion 1234 along the thickness direction of substrate 11; first connection portion 1232 is electrically connected to first transistor 121, and second connection portion 1234 is electrically connected to second transistor; at least one of first connection portion 1232 and second connection portion 1234 is disposed in the same layer as one of gate 1212 and first electrode 1213. In this way, it is equivalent to replacing the capacitor electrode made of the metal layer in the array layer in the related technology with a transparent capacitor electrode and a connection part. On the one hand, this can greatly reduce the area of ​​the film layer in the storage capacitor 123 that is disposed in the same layer as the metal layer in the array layer 12, increase the transmittance of the area where the storage capacitor 123 is located, and thus improve the transmittance of the display panel 10. On the other hand, since at least one of the first connection part 1232 and the second connection part 1234 is disposed in the same layer as the gate 1212 and the first electrode 1213, that is, at least one of the first connection part 1232 and the second connection part 1234 is disposed in the same layer as the metal layer in the array layer 12, the storage capacitor 123 can be easily connected to the first transistor 121 and the second transistor through the first connection part 1232 and the second connection part 1234, thus ensuring the display effect of the display panel 10.

[0074] In summary, the display panel 10 provided in this application embodiment includes a storage capacitor 123 comprising a first transparent capacitor electrode 1231, a first connecting portion 1232, a second transparent capacitor electrode 1233, and a second connecting portion 1234 disposed between multiple insulating layers 124; the first transparent capacitor electrode 1231 is connected to the first connecting portion 1232 through a first via 125; the first via 125 penetrates the insulating layer 124 located between the first transparent capacitor electrode 1231 and the first connecting portion 1232 along the thickness direction of the substrate 11; the second transparent capacitor electrode 1233 is connected to the first connecting portion 1232 through a first via 125. Two transparent capacitor electrodes 1233 are connected to a second connection portion 1234 through a second via 126; the second via 126 penetrates an insulating layer 124 located between the second transparent capacitor electrode 1233 and the second connection portion 1234 along the thickness direction of the substrate 11; the first connection portion 1232 is electrically connected to the first transistor 121, and the second connection portion 1234 is electrically connected to the second transistor; at least one of the first connection portion 1232 and the second connection portion 1234 is disposed in the same layer as one of the gate 1212 and the first electrode 1213. In this way, it is equivalent to replacing the capacitor electrode made of the metal layer in the array layer 12 in the related technology with a transparent capacitor electrode and a connection part. On the one hand, this can greatly reduce the area of ​​the film layer in the storage capacitor 123 that is disposed in the same layer as the metal layer in the array layer 12, increase the transmittance of the area where the storage capacitor 123 is located, and thus improve the transmittance of the display panel 10. On the other hand, since at least one of the first connection part 1232 and the second connection part 1234 is disposed in the same layer as one of the gate 1212 and the first electrode 1213, that is, at least one of the first connection part 1232 and the second connection part 1234 is disposed in the same layer as the metal layer in the array layer 12, the storage capacitor 123 can be easily connected to the first transistor 121 and the second transistor through the first connection part 1232 and the second connection part 1234, thus ensuring the display effect of the display panel 10.

[0075] In one embodiment, see [reference] Figures 1 to 5 As shown, the orthographic projection of the first transparent capacitor electrode 1231 on the substrate 11 covers the orthographic projection of the first connection portion 1232 on the substrate 11.

[0076] This allows the first light-transmitting capacitor electrode to have a larger area and the first connecting portion 1232 to have a smaller area, reducing the light blockage by the first connecting portion 1232 and increasing the transmittance of the area where the storage capacitor 123 is located, thereby improving the transmittance of the display panel 10.

[0077] In one embodiment, the ratio of the projected area of ​​the first connection portion 1232 on the substrate 11 to the projected area of ​​the first transparent capacitor electrode 1231 on the substrate 11 is 2% to 10%.

[0078] Therefore, by controlling the ratio of the projected area of ​​the first connection portion 1232 on the substrate 11 to the projected area of ​​the first transparent capacitor electrode 1231 on the substrate 11 within the above-mentioned range, the area occupied by the first connection portion 1232 in the region where the storage capacitor 123 is located can be smaller, which can effectively reduce the shading of light by the first connection portion 1232, improve the transmittance of the region where the storage capacitor 123 is located, and thus improve the transmittance of the display panel 10.

[0079] In one embodiment, see [reference] Figures 1 to 5 As shown, the orthogonal projection of the first via 125 on the substrate 11 is located within the orthogonal projection range of the first transparent capacitor electrode 1231 on the substrate 11.

[0080] In this way, the first transparent capacitor electrode 1231 can be easily connected to the first connection portion 1232 through the first through hole 125, thereby facilitating the connection between the storage capacitor 123 and the first transistor 121.

[0081] In one embodiment, see [reference] Figures 1 to 5 As shown, the orthographic projection of the first via 125 on the substrate 11 overlaps with the orthographic projection of the first connection portion 1232 on the substrate 11.

[0082] In this way, while ensuring that the first transparent capacitor electrode 1231 is connected to the first connecting portion 1232 through the first via 125, it is beneficial to reduce the area of ​​the first connecting portion 1232, reduce the light blocking by the first connecting portion 1232, and improve the transmittance of the area where the storage capacitor 123 is located, thereby improving the transmittance of the display panel 10.

[0083] In one embodiment, see [reference] Figures 1 to 5 As shown, the orthographic projection of the second transparent capacitor electrode 1233 on the substrate 11 covers the orthographic projection of the second connection portion 1234 on the substrate 11.

[0084] This allows the second transparent capacitor electrode 1233 to have a larger area and the second connecting portion 1234 to have a smaller area, reducing the light blockage by the second connecting portion 1234 and increasing the transmittance of the area where the storage capacitor 123 is located, thereby improving the transmittance of the display panel 10.

[0085] In one embodiment, the ratio of the projected area of ​​the second connection portion 1234 on the substrate 11 to the projected area of ​​the second transparent capacitor electrode 1233 on the substrate 11 is 2% to 10%.

[0086] Therefore, by controlling the ratio of the projected area of ​​the second connection portion 1234 on the substrate 11 to the projected area of ​​the second transparent capacitor electrode 1233 on the substrate 11 within the above-mentioned range, the area occupied by the second connection portion 1234 in the region where the storage capacitor 123 is located can be reduced, which can effectively reduce the shading of light by the second connection portion 1234, improve the transmittance of the region where the storage capacitor 123 is located, and thus improve the transmittance of the display panel 10.

[0087] In one embodiment, see [reference] Figures 1 to 5 As shown, the orthogonal projection of the second via 126 on the substrate 11 is located within the orthogonal projection range of the second transparent capacitor electrode 1233 on the substrate 11.

[0088] In this way, the second transparent capacitor electrode 1233 can be easily connected to the second connection portion 1234 through the second via 126, thereby facilitating the connection between the storage capacitor 123 and the second transistor.

[0089] In one embodiment, see [reference] Figures 1 to 5 As shown, the orthographic projection of the second via 126 on the substrate 11 overlaps with the orthographic projection of the second connection portion 1234 on the substrate 11.

[0090] In this way, while ensuring that the second transparent capacitor electrode 1233 is connected to the second connection portion 1234 through the second via 126, it is beneficial to reduce the area of ​​the second connection portion 1234, reduce the light blocking by the second connection portion 1234, and improve the transmittance of the area where the storage capacitor 123 is located, thereby improving the transmittance of the display panel 10.

[0091] In one embodiment, see [reference] Figures 1 to 5 As shown, the orthographic projection of the second connecting portion 1234 on the substrate 11 does not overlap with the orthographic projection of the first connecting portion 1232 on the substrate 11.

[0092] Therefore, the orthographic projection of the first via 125 on the substrate 11 and the orthographic projection of the second via 126 on the substrate 11 do not overlap, which facilitates the connection of the first capacitor electrode to the first connection portion 1232 through the first via 125 and the connection of the second capacitor electrode to the second connection portion 1234 through the second via 126, thereby reducing the risk of short circuit.

[0093] In one embodiment, see [reference] Figure 1 , Figure 3 As shown, at least one insulating layer 124 is disposed between the second transparent capacitor electrode 1233 and the first transparent capacitor electrode 1231; the orthographic projection of the first transparent capacitor electrode 1231 on the substrate 11 overlaps with the orthographic projection of the second transparent capacitor electrode 1233 on the substrate 11.

[0094] This ensures the facing area of ​​the first transparent capacitor electrode 1231 and the second transparent capacitor electrode 1233, thereby guaranteeing the capacitance value between them. This allows the storage capacitor 123 to maintain the pixel voltage state for a longer period during the off-state of the first transistor 121 and the second transistor, improving the display image quality of the display panel 10 and reducing flicker. Furthermore, the insulating layer 124 prevents direct contact between the first transparent capacitor electrode 1231 and the second transparent capacitor electrode 1233, reducing the risk of short circuits.

[0095] In one embodiment, see [reference] Figure 2 , Figure 4 and Figure 5 As shown, the orthogonal projection of the first transparent capacitor electrode 1231 on the substrate 11 is within the orthogonal projection range of the second transparent capacitor electrode 1233 on the substrate 11.

[0096] This increases the facing area of ​​the first transparent capacitor electrode 1231 and the second transparent capacitor electrode 1233, thereby increasing the capacitance between the first transparent capacitor electrode 1231 and the second transparent capacitor electrode 1233. This allows the storage capacitor 123 to maintain the pixel voltage state for a longer period of time during the off-state of the first transistor 121 and the second transistor, improving the display image quality of the display panel 10 and reducing flickering.

[0097] In one embodiment, the transmittance of the first transparent capacitor electrode 1231 is 80% to 100%.

[0098] This increases the transmittance of the area where the storage capacitor 123 is located, thereby increasing the transmittance of the display panel 10.

[0099] In one embodiment, the transmittance of the second transparent capacitor electrode 1233 is 80% to 100%.

[0100] This increases the transmittance of the area where the storage capacitor 123 is located, thereby increasing the transmittance of the display panel 10.

[0101] In one embodiment, both the first transparent capacitor electrode 1231 and the second transparent capacitor electrode 1233 are made of transparent conductive oxide. Specifically, both the first transparent capacitor electrode 1231 and the second transparent capacitor electrode 1233 can be indium tin oxide (ITO).

[0102] In one embodiment, see [reference] Figures 1 to 5 As shown, the second transparent capacitor electrode 1233 is located on the side of the first transparent capacitor electrode 1231 away from the substrate 11.

[0103] This effectively increases the overall area of ​​the storage capacitor 123, improves its capacitance, and allows it to better maintain pixel voltage, reduce voltage drop caused by leakage current, reduce flicker, improve the display image quality of the display panel 10, and enhance its stability and consistency. Furthermore, a higher capacitance value reduces refresh rate requirements, thereby lowering the overall power consumption of the display panel 10. In addition, it fully utilizes the space in the thickness direction of the display panel 10, increasing the capacitance value without increasing the planar dimensions and preventing interference between the second transparent capacitor electrode 1233 and the first transparent capacitor electrode 1231 and other circuit components.

[0104] In one embodiment, see [reference] Figures 1 to 5 As shown, the first transparent capacitor electrode 1231 is located on the side of the first connection portion 1232 away from the substrate 11.

[0105] This ensures a shorter and better electrical path between the first transparent capacitor electrode 1231 and the first connection portion 1232, reducing resistance and signal delay, improving the display quality of the display panel 10, and reducing the power consumption of the display panel 10.

[0106] In one embodiment, see [reference] Figures 1 to 5 As shown, the second transparent capacitor electrode 1233 is located on the side of the second connection portion 1234 away from the substrate 11.

[0107] This ensures a shorter and better electrical path between the second transparent capacitor electrode 1233 and the second connection portion 1234, reducing resistance and signal delay, improving the display quality of the display panel 10, and reducing the power consumption of the display panel 10.

[0108] In one embodiment, see [reference] Figures 1 to 5 As shown, the first connecting part 1232 and the second connecting part 1234 are arranged in different layers.

[0109] Therefore, the first connecting part 1232 and the second connecting part 1234 can be insulated from each other, which facilitates the electrical connection of the first connecting part 1232 to the first transistor 121 and the electrical connection of the second connecting part 1234 to the second transistor, thus avoiding interference between the first connecting part 1232 and the second connecting part 1234.

[0110] In one embodiment, see [reference] Figures 1 to 4 As shown, the first transparent capacitor electrode 1231 and the second connecting part 1234 are disposed on the same layer and arranged at intervals.

[0111] Therefore, when manufacturing the first transparent capacitor electrode 1231, the second connecting part 1234 can be manufactured simultaneously, which can reduce the manufacturing process of the display panel 10, reduce manufacturing costs, and reduce the thickness of the display panel 10, which is beneficial to making the display panel 10 thinner and lighter.

[0112] In another embodiment, see Figure 5 As shown, the first transparent capacitor electrode 1231 and the second connecting portion 1234 are disposed in different layers.

[0113] This reduces electromagnetic interference between the first transparent capacitor electrode 1231 and the second connection portion 1234, ensuring the purity of signal transmission. In addition, it enables electrical isolation between the first transparent capacitor electrode 1231 and the second connection portion 1234, reducing the probability of crosstalk and improving the overall performance of the array layer 12.

[0114] In one embodiment, see [reference] Figures 1 to 5 As shown, the first connection portion 1232 is disposed on the same layer as the gate 1212 and is arranged at intervals.

[0115] Therefore, when manufacturing the gate 1212, the first connection portion 1232 can be manufactured simultaneously, which can reduce the manufacturing process of the display panel 10, reduce manufacturing costs, and reduce the thickness of the display panel 10, which is beneficial to making the display panel 10 thinner and lighter.

[0116] In one embodiment, see [reference] Figures 3 to 4 As shown, the first electrode 1213 is disposed on the side of the semiconductor layer 1211 away from the substrate 11; the first electrode 1213 is connected to the semiconductor layer 1211 through a third via 127; the third via 127 penetrates the insulating layer 124 located between the first electrode 1213 and the semiconductor layer 1211 along the thickness direction of the substrate 11; the second electrode 1214 is connected to the semiconductor layer 1211 through a fourth via 128; the fourth via 128 penetrates the insulating layer 124 located between the second electrode 1214 and the semiconductor layer 1211 along the thickness direction of the substrate 11; the gate electrode 1212 is located between the semiconductor layer 1211 and the substrate 11; and the first transparent capacitor electrode 1231 is located between the semiconductor layer 1211 and the first electrode 1213.

[0117] Therefore, the first transparent capacitor electrode 1231 can be disposed in a different layer from the semiconductor layer 1211, the gate 1212, and the first electrode 1213, which can avoid the influence of the fabrication of the first transparent capacitor electrode 1231 on the fabrication of the semiconductor layer 1211, the gate 1212, and the first electrode 1213. In addition, the gate 1212 is located between the semiconductor layer 1211 and the substrate 11, that is, the gate 1212 is located on the side of the semiconductor layer 1211 closer to the substrate 11, which is a bottom gate structure. This reduces the influence of external factors on the semiconductor layer 1211, improves the reliability of the display panel 10, and the fabrication process of the bottom gate structure is relatively mature, which can reduce the manufacturing cost of the display panel 10.

[0118] In one embodiment, see [reference] Figures 3 to 4 As shown, the plurality of insulating layers 124 include a plurality of inorganic insulating layers 1241, and the first electrode 1213, the semiconductor layer 1211, the gate electrode 1212 and the first transparent capacitor electrode 1231 are disposed between the plurality of inorganic insulating layers 1241 at intervals.

[0119] Therefore, by using multiple inorganic insulating layers 1241, the first electrode 1213, semiconductor layer 1211, gate 1212, and first transparent capacitor electrode 1231 can be separated, effectively preventing direct contact between the layers and avoiding short circuits; it can also reduce interference between different signal lines, ensure the purity of signal transmission, and improve the overall performance of the array layer 12. In addition, the inorganic insulating layer 1241 has an extremely high dielectric constant, which is beneficial to increasing the capacitance value of the gate 1212 and improving the switching characteristics and driving capability of the transistor.

[0120] It should be noted that the inorganic insulating layer 1241 is made of at least one of silicon nitride and silicon oxide.

[0121] In one embodiment, see [reference] Figure 1 , Figure 2 As shown, the first electrode 1213 is disposed on the side of the semiconductor layer 1211 away from the substrate 11; the first electrode 1213 is connected to the semiconductor layer 1211 through a third via 127; the third via 127 penetrates the insulating layer 124 located between the first electrode 1213 and the semiconductor layer 1211 along the thickness direction of the substrate 11; the second electrode 1214 is connected to the semiconductor layer 1211 through a fourth via 128; the fourth via 128 penetrates the insulating layer 124 located between the second electrode 1214 and the semiconductor layer 1211 along the thickness direction of the substrate 11; the gate electrode 1212 is located between the semiconductor layer 1211 and the first electrode 1213; and the first transparent capacitor electrode 1231 is located between the gate electrode 1212 and the first electrode 1213.

[0122] Therefore, the first transparent capacitor electrode 1231 can be disposed in a different layer from the semiconductor layer 1211, the gate 1212, and the first electrode 1213, which avoids the influence of the fabrication of the first transparent capacitor electrode 1231 on the fabrication of the semiconductor layer 1211, the gate 1212, and the first electrode 1213. In addition, the gate 1212 is located between the semiconductor layer 1211 and the first electrode 1213, that is, the gate 1212 is located on the side of the semiconductor layer 1211 away from the substrate 11, which is a top gate structure. The top gate structure can directly contact the surface of the active layer, which helps to improve carrier mobility and switching speed, thereby improving the overall performance of the transistor. In addition, the top gate structure is more flexible and easier to implement complex circuit designs, which can meet the requirements of the high-performance display panel 10.

[0123] In one embodiment, see [reference] Figure 1 and Figure 3 As shown, the second transparent capacitor electrode 1233 is disposed in the same layer as the first electrode 1213 and the second electrode 1214, and they are arranged at intervals.

[0124] Therefore, the second transparent capacitor electrode 1233 can be fabricated simultaneously when the first electrode 1213 and the second electrode 1214 are fabricated, which can reduce the number of fabrication steps of the display panel 10, reduce the manufacturing cost, and reduce the thickness of the display panel 10, which is beneficial to the thinning of the display panel 10.

[0125] In one embodiment, see [reference] Figure 2 and Figure 4 As shown, the second transparent capacitor electrode 1233 is disposed on the side of the first electrode 1213 away from the substrate 11.

[0126] Therefore, the second transparent capacitor electrode 1233 and the first electrode 1213 are set in different layers, which can avoid the influence of the fabrication of the second transparent capacitor electrode 1233 on the fabrication of the first electrode 1213 and the second electrode 1214. The first electrode 1213 and the second electrode 1214 can be fabricated using existing materials and manufacturing processes without the need to introduce new materials and manufacturing processes, thereby reducing the manufacturing cost of the display panel 10.

[0127] In one embodiment, see [reference] Figure 2 and Figure 4 As shown, the plurality of insulating layers 124 also include a multilayer organic insulating layer 1242; the multilayer organic insulating layer 1242 is stacked on the side of the first electrode 1213 away from the substrate 11; the second transparent capacitor electrode 1233 is disposed between two adjacent organic insulating layers 1242.

[0128] Therefore, the organic insulating layer 1242 can separate the first electrode 1213 and the second transparent capacitor electrode 1233, avoiding direct contact between the two and short circuit, thus reducing interference.

[0129] It should be noted that the organic insulating layer 1242 can be a planarization layer. By setting multiple organic insulating layers 1242, the multiple organic insulating layers 1242 are stacked on the side of the first electrode 1213 away from the substrate 11. The second transparent capacitor electrode 1233 is disposed between two adjacent organic insulating layers 1242, which is beneficial to improving the flatness of the surface of the array layer 12 away from the substrate 11, which is beneficial to the fabrication of the film layer on the side of the array layer 12 away from the substrate 11, and which is beneficial to improving the manufacturing yield and manufacturing efficiency of the display panel 10.

[0130] In one embodiment, see [reference] Figure 5 As shown, the first transparent capacitor electrode 1231, the first electrode 1213, and the second electrode 1214 are disposed on the same layer and arranged at intervals.

[0131] Therefore, the first transparent capacitor electrode 1231 can be fabricated simultaneously when the first electrode 1213 and the second electrode 1214 are fabricated, which can reduce the number of fabrication steps of the display panel 10, reduce the manufacturing cost, and reduce the thickness of the display panel 10, which is beneficial to the thinning of the display panel 10.

[0132] In one embodiment, see [reference] Figure 5 As shown, the second transparent capacitor electrode 1233 is disposed on the side of the first electrode 1213 away from the substrate 11.

[0133] This allows the second transparent capacitor electrode 1233 and the first transparent capacitor electrode 1231 to be isolated from each other, ensuring the normal operation of the storage capacitor 123. Furthermore, it avoids the impact of the fabrication of the second transparent capacitor electrode 1233 on the fabrication of the semiconductor layer 1211, the gate 1212, and the first electrode 1213.

[0134] Further, see Figure 5 As shown, the plurality of insulating layers 124 also includes multiple organic insulating layers 1242; the multiple organic insulating layers 1242 are stacked on the side of the first electrode 1213 away from the substrate 11; the second transparent capacitor electrode 1233 is disposed between two adjacent organic insulating layers 1242. Thus, the organic insulating layers 1242 can separate the first electrode 1213 and the second transparent capacitor electrode 1233, avoiding direct contact between the two and short circuit, and reducing interference.

[0135] In one embodiment, see [reference] Figures 1 to 5As shown, the display panel 10 also includes a pixel definition layer 13 and a plurality of first electrodes 14; the pixel definition layer 13 is disposed on the side of the array layer 12 away from the substrate 11; a plurality of pixel openings 131 are formed on the pixel definition layer 13; the plurality of first electrodes 14 are spaced apart between the pixel definition layer 13 and the array layer 12; the pixel openings 131 expose the corresponding first electrodes 14; the first electrodes 14 are connected to one of the first pole 1213 and the second pole 1214.

[0136] It should be noted that the first electrode 14 can be an anode. The display panel 10 also includes a light-emitting functional part and a second electrode. At least a portion of the light-emitting functional part is disposed within the pixel opening 131. The second electrode is located on the side of the light-emitting functional part away from the substrate 11, and the second electrode can be a cathode. The first electrode 14, the light-emitting functional part, and the second electrode constitute a sub-pixel. The first electrode 14 is connected to one of the first electrode 1213 and the second electrode 1214 so that the state of the sub-pixel can be precisely controlled by the pixel driving circuit to achieve high-quality display of the display panel 10.

[0137] For example, the light-emitting functional unit includes an organic light-emitting layer (EML), and further includes at least one of a hole injection layer (HIL), a hole transport layer (HTL), an electron transport layer (ETL), an electron injection layer (EIL), a hole block layer (HBL), and an electron block layer (EBL). The light-emitting functional unit may also be a stacked light-emitting layer, that is, it includes at least two light-emitting layers and a charge generation layer (CGL) located between adjacent light-emitting layers.

[0138] For example, the pixel definition layer 13 may be an organic layer or an inorganic layer.

[0139] In one embodiment, see [reference] Figures 1 to 5 As shown, the display panel 10 also includes at least one buffer layer 15, which is disposed between the substrate 11 and the array layer 12. Specifically, the display panel 10 may include three stacked buffer layers 15, the material of which includes at least one of silicon nitride and silicon oxide. This can isolate moisture and oxygen, and prevent moisture or impurities from diffusing into the display panel 10 through the substrate 11.

[0140] In one embodiment, see [reference] Figures 1 to 5As shown, the display panel 10 also includes an isolation pillar 16 disposed on the side of the pixel definition layer 13 away from the substrate 11. The isolation pillar 16 is used to support the mask or glass substrate and prevent damage to the film layers in the display panel 10.

[0141] For example, the isolation column 16 may be an organic layer.

[0142] Secondly, see Figure 6 As shown, this application embodiment also provides a display device, including the display panel 10 described in any of the above embodiments. This improves the transmittance of the display device 1.

[0143] The display device 1 can be a laptop computer, mobile phone, wireless device, personal digital assistant (PDA), handheld or portable computer, GPS receiver / navigator, camera, MP4 video player, camcorder, game console, watch, clock, calculator, TV monitor, flat panel display, computer monitor, car display (e.g., odometer display, etc.), navigator, cockpit controller and / or display, camera view display (e.g., display of a rearview camera in a vehicle), electronic photograph, electronic billboard or sign, projector, etc.

[0144] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0145] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. A display panel, characterized in that, include: Substrate; An array layer is disposed on one side of the substrate, and the array layer includes a first transistor, a second transistor, a storage capacitor, and multiple insulating layers; Both the first transistor and the second transistor include a semiconductor layer, a gate, a first electrode, and a second electrode disposed between the plurality of insulating layers, wherein the first electrode and the second electrode are disposed in the same layer; The storage capacitor includes a first transparent capacitor electrode, a first connecting portion, a second transparent capacitor electrode, and a second connecting portion disposed between the plurality of insulating layers; The first transparent capacitor electrode is connected to the first connection portion through a first via; the first via penetrates the insulating layer located between the first transparent capacitor electrode and the first connection portion along the thickness direction of the substrate. The second transparent capacitor electrode is connected to the second connection portion through a second via; the second via penetrates the insulating layer located between the second transparent capacitor electrode and the second connection portion along the thickness direction of the substrate. The first connection portion is electrically connected to the first transistor, and the second connection portion is electrically connected to the second transistor; at least one of the first connection portion and the second connection portion is disposed on the same layer as the gate and the first electrode.

2. The display panel according to claim 1, characterized in that, The orthographic projection of the first transparent capacitor electrode on the substrate overlaps with the orthographic projection of the first connection portion on the substrate; Optionally, the ratio of the projected area of ​​the first connection portion on the substrate to the projected area of ​​the first transparent capacitor electrode on the substrate is 2% to 10%. Optionally, the orthographic projection of the first via on the substrate is located within the orthographic projection range of the first transparent capacitor electrode on the substrate; Optionally, the orthographic projection of the first via on the substrate overlaps with the orthographic projection of the first connection portion on the substrate; Optionally, the orthographic projection of the second transparent capacitor electrode on the substrate overlaps the orthographic projection of the second connection portion on the substrate; Optionally, the ratio of the projected area of ​​the second connection portion on the substrate to the projected area of ​​the second transparent capacitor electrode on the substrate is 2% to 10%. Optionally, the orthogonal projection of the second via on the substrate is located within the orthogonal projection range of the second transparent capacitor electrode on the substrate; Optionally, the orthographic projection of the second via on the substrate overlaps with the orthographic projection of the second connection portion on the substrate; Optionally, the orthographic projection of the second connecting portion on the substrate does not overlap with the orthographic projection of the first connecting portion on the substrate.

3. The display panel according to claim 1, characterized in that, At least one of the insulating layers is disposed between the second transparent capacitor electrode and the first transparent capacitor electrode; the orthographic projection of the first transparent capacitor electrode on the substrate overlaps with the orthographic projection of the second transparent capacitor electrode on the substrate; Optionally, the orthographic projection of the first transparent capacitor electrode on the substrate is located within the orthographic projection range of the second transparent capacitor electrode on the substrate; Optionally, the transmittance of the first transparent capacitor electrode is 80% to 100%; Optionally, the transmittance of the second transparent capacitor electrode is 80% to 100%; Optionally, both the first transparent capacitor electrode and the second transparent capacitor electrode are made of transparent conductive oxide.

4. The display panel according to any one of claims 1 to 3, characterized in that, The second transparent capacitor electrode is located on the side of the first transparent capacitor electrode that is away from the substrate; Optionally, the first transparent capacitor electrode is located on the side of the first connection portion away from the substrate; Optionally, the second transparent capacitor electrode is located on the side of the second connection portion away from the substrate; Optionally, the first connecting portion and the second connecting portion are disposed in different layers; Optionally, the first transparent capacitor electrode and the second connecting portion are disposed in the same layer and arranged at intervals; or, the first transparent capacitor electrode and the second connecting portion are disposed in different layers. The first connection portion is disposed on the same layer as the gate and is arranged at intervals.

5. The display panel according to claim 4, characterized in that, The first electrode is located on the side of the semiconductor layer away from the substrate; the first electrode is connected to the semiconductor layer through a third via. The third via penetrates the insulating layer located between the first electrode and the semiconductor layer along the thickness direction of the substrate. The second electrode is connected to the semiconductor layer through the fourth via; The fourth via penetrates the insulating layer located between the second electrode and the semiconductor layer along the thickness direction of the substrate. The gate is located between the semiconductor layer and the substrate; The first transparent capacitor electrode is located between the semiconductor layer and the first electrode; Optionally, the plurality of insulating layers include a plurality of inorganic insulating layers, and the first electrode, the semiconductor layer, the gate electrode and the first transparent capacitor electrode are disposed at intervals between the plurality of inorganic insulating layers.

6. The display panel according to claim 4, characterized in that, The first electrode is located on the side of the semiconductor layer away from the substrate; the first electrode is connected to the semiconductor layer through a third via. The third via penetrates the insulating layer located between the first electrode and the semiconductor layer along the thickness direction of the substrate. The second electrode is connected to the semiconductor layer through the fourth via; The fourth via penetrates the insulating layer located between the second electrode and the semiconductor layer along the thickness direction of the substrate. The gate is located between the semiconductor layer and the first electrode; the first transparent capacitor electrode is located between the gate and the first electrode.

7. The display panel according to claim 5 or 6, characterized in that, The second transparent capacitor electrode is disposed in the same layer as the first electrode and the second electrode, and is arranged at intervals.

8. The display panel according to claim 5 or 6, characterized in that, The second transparent capacitor electrode is disposed on the side of the first electrode away from the substrate; Optionally, the plurality of insulating layers further includes multiple organic insulating layers; the multiple organic insulating layers are stacked on the side of the first electrode away from the substrate; the second transparent capacitor electrode is disposed between two adjacent organic insulating layers.

9. The display panel according to claim 4, characterized in that, The first transparent capacitor electrode is disposed in the same layer as both the first electrode and the second electrode, and is arranged at intervals; Optionally, the second transparent capacitor electrode is disposed on the side of the first electrode away from the substrate; Optionally, the display panel further includes a pixel definition layer and a plurality of first electrodes; A pixel definition layer is located on the side of the array layer away from the substrate; the pixel definition layer has multiple pixel openings; The plurality of first electrodes are spaced apart between the pixel definition layer and the array layer; the pixel opening exposes the corresponding first electrode; the first electrode is connected to one of the first pole and the second pole. Optionally, the display panel further includes at least one buffer layer disposed between the substrate and the array layer.

10. A display device, characterized in that, Includes the display panel according to any one of claims 1 to 9.

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