Array substrate and display panel

Abstract

The application discloses an array substrate and a display panel. The array substrate comprises a substrate and pixel circuits, data signal lines arranged on the substrate. The pixel circuits comprise a driving module, a data writing module, a first initialization module, a light-emitting control module and a light-emitting module. The first initialization module comprises a first thin film transistor, which is a double-gate thin film transistor and comprises a first gate and a second gate arranged in a direction away from the substrate. The data writing module comprises a second thin film transistor, one end of which is electrically connected to the data signal line through a first via. In a direction parallel to the substrate, a first distance between the first gate and the first via is smaller than a second distance between the second gate and the first via. By increasing the second distance between the second gate and the first via, the second gate is prevented from being short-circuited by residual overlap of the first via during preparation, and the yield of the array substrate is improved.

Description

Technical Field

[0001] This application relates to the field of display technology, and in particular to an array substrate and a display panel. Background Technology

[0002] With the development of display technology, the number of pixels per inch (PPI) is getting higher and higher, the pixel wiring space is getting smaller and smaller, and the line spacing is getting larger and larger. Since the film layer overlap in the array substrate is prone to residue during the manufacturing process, when the residue overlaps with other film layers, it can easily cause short circuits, affecting the yield of the array substrate.

[0003] There is an urgent need to optimize the membrane design to avoid short circuits. Summary of the Invention

[0004] This application mainly provides an array substrate and a display panel, which can solve the problem of short circuits caused by film residue.

[0005] To solve the above-mentioned technical problems, the technical solution adopted in this application is as follows: An array substrate is provided, comprising a substrate and pixel circuits and data signal lines disposed on the substrate. The pixel circuit includes a driving module, a data writing module, a first initialization module, a light-emitting control module, and a light-emitting module. The first initialization module is electrically connected to the control terminal of the driving module and is used to write a first initialization voltage to the control terminal of the driving module during a first initialization phase. The data writing module is electrically connected to the control terminal of the driving module and is used to write a data voltage to the driving module during a data writing phase. The light-emitting control module, the driving module, and the light-emitting module are connected in series to form a driving branch. The light-emitting control module is used to conduct during the light-emitting phase to connect the driving branch. The first initialization module includes a first thin-film transistor. The first end of the body transistor is electrically connected to the control terminal of the driving module, and the second end of the first thin-film transistor is used to be electrically connected to the first reference voltage line. The first thin-film transistor is a dual-gate thin-film transistor, including a first gate and a second gate stacked sequentially in the direction away from the substrate. The data writing module includes a second thin-film transistor, one end of which is electrically connected to the data signal line through a first via. The orthogonal projections of the first gate and the second gate on the substrate overlap, the orthogonal projections of the first gate and the first via on the substrate are spaced apart, the orthogonal projections of the second gate and the first via on the substrate are spaced apart, and in the direction parallel to the substrate, the first distance between the first gate and the first via is less than the second distance between the second gate and the first via.

[0006] Wherein, in a direction parallel to the substrate, the first distance between the first gate and the first via ranges from 1.7 to 2.1 μm.

[0007] Wherein, in a direction parallel to the substrate, the second distance between the second gate and the first via ranges from 2.3 to 3.3 μm.

[0008] The pixel circuit further includes a threshold compensation module connected between the second end of the driving module and the control end. The threshold compensation module is used to compensate the threshold voltage of the driving module.

[0009] The light-emitting control module includes a first light-emitting control unit and a second light-emitting control unit. The first light-emitting control unit is connected between a first power supply voltage input terminal and a first terminal of the driving module. The second light-emitting control unit is connected between a second terminal of the driving module and a first terminal of the light-emitting module. The control terminals of the first and second light-emitting control units are simultaneously connected to light-emitting control signals. The second terminal of the light-emitting module is electrically connected to a second power supply voltage input terminal.

[0010] The pixel circuit further includes a first storage module, a first end of which is electrically connected to the control terminal of the driving module, and a second end of which is electrically connected to the first power supply voltage input terminal.

[0011] The pixel circuit further includes a second initialization module. 其 It is electrically connected to the first terminal of the light-emitting module and is used to write the second initialization voltage to the second terminal of the light-emitting module during the second initialization phase.

[0012] The second initialization module includes a third thin-film transistor, the second end of which is electrically connected to the first end of the light-emitting module, and the first end of which is electrically connected to the second reference voltage line. The second initialization module also includes a fourth thin-film transistor, the first end of which is electrically connected to the first end of the control module, and the second end of which is electrically connected to the third reference voltage line. The control terminals of the fourth and third thin-film transistors are both connected to the fourth scan line.

[0013] The material of the first gate includes at least one of a metal material and a transparent conductive oxide (TCO) material; the material of the second gate includes at least one of a metal material and a transparent conductive oxide (TCO) material.

[0014] Another technical solution adopted in this application is to provide a display panel that includes the array substrate described in the above embodiments.

[0015] The beneficial effects of this application are as follows: In the array substrate of this application, the first initialization module includes a first thin-film transistor, which is a dual-gate thin-film transistor, including a first gate and a second gate sequentially stacked in the direction away from the substrate; the data writing module includes a second thin-film transistor, one end of which is electrically connected to a data signal line through a first via; wherein, in the direction parallel to the substrate, the distance between the first gate and the first via is smaller than the distance between the second gate and the first via. By increasing the distance between the second gate and the first via, overlap of the second gate in the first via is avoided during the fabrication of the second gate, thus preventing a short circuit between the second gate and the first via and improving the yield of the array substrate. Attached Figure Description

[0016] To more clearly illustrate the technical solutions in the embodiments of this application, the drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort. Among them:

[0017] Figure 1 This is a cross-sectional structural diagram of one embodiment of the first gate and the second gate in an array substrate in the prior art;

[0018] Figure 2 This is a cross-sectional structural diagram of one embodiment of the first gate and the second gate in the array substrate of this application;

[0019] Figure 3 This is a top view of one embodiment of the array substrate in this application;

[0020] Figure 4 This is a schematic diagram of one embodiment of the pixel circuit in the array substrate of this application;

[0021] Figure 5 This is a schematic diagram of one embodiment of the equivalent circuit of the pixel circuit in the array substrate of this application.

[0022] Reference numerals in the attached figures: 10 Substrate; 11 First gate; 12 Second gate; 13 First via; 100 Driving module; 200 Data writing module; 300 First initialization module; 400 Light emission control module; 500 Light emission module; 600 Threshold compensation module; 700 Light emission control module; 701 First light emission control unit; 702 Second light emission control unit; 800 First storage module; 900 Second initialization module; 1000 Third initialization module; D1 First distance; D2 Second distance; S1 First scan line; ELVDD First power signal line Data voltage line; S1 first scan line; S2 second scan line; S3 third scan line; S4 fourth scan line; EM light emission control signal; ELVSS second power signal line; T1 first thin film transistor; T2 second thin film transistor; T3 third thin film transistor; T4 fourth thin film transistor; T5 fifth thin film transistor; T6 sixth thin film transistor; T7 seventh thin film transistor; C1 first capacitor; EL organic light emission diode; Vref1 first reference voltage line; Vref2 second reference voltage line; Vref3 third reference voltage line. Detailed Implementation

[0023] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0024] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains; the terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the application; the terms “comprising” and “having”, and any variations thereof, in the specification, claims, and foregoing description of the drawings are intended to cover non-exclusive inclusion.

[0025] In the description of the embodiments of this application, technical terms such as "first" and "second" are used only to distinguish different objects and should not be construed as indicating or implying relative importance or implicitly specifying the number, specific order, or primary and secondary relationship of the indicated technical features. In the description of the embodiments of this application, "multiple" means two or more, unless otherwise explicitly defined.

[0026] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0027] In the description of the embodiments of this application, unless otherwise expressly specified and limited, technical terms such as "installation," "connection," "joining," and "fixing" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. For those skilled in the art, the specific meaning of the above terms in the embodiments of this application can be understood according to the specific circumstances.

[0028] Please see Figure 1 In the prior art, since the second gate is closer to the first via 13 than the first gate 11, and the second gate 12 is bent on the side close to the first via 13, there is a tendency for residue to remain at the end of the second gate 12 close to the first via 13. At the same time, the second distance D2 between the second gate 12 and the first via 13 is close, which can easily cause the second gate 12 and the first via 13 to overlap, resulting in a short circuit between the second gate 12 and the first via 13.

[0029] Please see Figure 1 , Figure 2 , Figure 3 and Figure 4This application provides an array substrate, which includes a substrate 10 and pixel circuits and data signal lines Data disposed on the substrate 10. The pixel circuits include a driving module 100, a data writing module 200, a first initialization module 300, a light emission control module 700, and a light emission module 500. The first initialization module 300 is electrically connected to the control terminal of the driving module 100 and is used to write a first initialization voltage to the control terminal of the driving module 100 during the first initialization stage. The data writing module 200 is electrically connected to the control terminal of the driving module 100 and is used to write a data voltage to the driving module 100 during the data writing stage. The light emission control module 700, the driving module 100, and the light emission module 500 are connected in series to form a driving branch. The light emission control module 700 is used to conduct during the light emission stage to connect the driving branch. The first initialization module 300 includes a first thin-film transistor T1. The first end of the first thin-film transistor T1 is electrically connected to the control terminal of the driving module 100, and the second end of the first thin-film transistor T1 is electrically connected to the first reference voltage line Vref1. The first thin-film transistor T1 is a dual-gate thin-film transistor, including a first gate 11 and a second gate 12 stacked sequentially in the direction away from the substrate 10. The data writing module 200 includes a second thin-film transistor T2, one end of which is electrically connected to the data signal line Data through a first via 13. The orthogonal projections of the first gate 11 and the second gate 12 on the substrate 10 overlap, the orthogonal projections of the first gate 11 and the first via 13 on the substrate 10 are spaced apart, the orthogonal projections of the second gate 12 and the first via 13 on the substrate 10 are spaced apart, and in the direction parallel to the substrate 10, the first distance D1 between the first gate 11 and the first via 13 is less than the distance D2 between the second gate 12 and the first via 13.

[0030] Specifically, the first via 13 is used to connect the data signal line Data to the second thin-film transistor T2 to realize data signal transmission. In the direction perpendicular to the plane of the substrate 10, the first gate 11 is located between the end of the second gate 12 away from the first via and the first via. In the direction parallel to the plane of the substrate 10, the distance D2 between the second gate 12 and the first via 13 is greater than the first distance D1 between the first gate 11 and the first via 13. At the same time, the second gate 12 is routed in a straight line on the side close to the first via 13, reducing or even avoiding residues during the fabrication process. By increasing the distance between the second gate 12 and the first via 13, short circuits caused by the second gate 12 overlapping in the first via 13 during fabrication are avoided, thus improving the yield of the array substrate.

[0031] In one embodiment, the array substrate includes a substrate 10 and pixel circuits and data signal lines Data disposed on the substrate 10. The substrate 10 provides support and facilitates the fabrication of the pixel circuits and data signal lines Data. The pixel circuit includes a driving module 100, a data writing module 200, a first initialization module 300, a light emission control module 700, and a light emission module 500 interconnected to control the light emission of the pixels. The first terminal of the first initialization module 300 is electrically connected to the control terminal of the driving module 100, and the control terminal of the first initialization module 300 is electrically connected to the first scan line S1, used to write a first initialization voltage to the control terminal of the driving module 100 during the first initialization stage, thus initializing the first terminal and control terminal of the driving module. The control terminal of the data writing module 200 is electrically connected to the second scan line S2, and the second terminal of the data writing module 200 is ultimately electrically connected to the control terminal of the driving module 100 via the first and second terminals of the driving module, enabling the writing of data voltage into the driving module 100 during the data writing stage. The driving branch includes a light-emitting control module 700, a driving module 100, and a light-emitting module 500 connected in series. During the light-emitting stage, the light-emitting control module 700 is turned on to connect the driving branch, thereby illuminating the light-emitting module 500. The first initialization module 300 includes a first thin-film transistor T1. The control terminal of the driving module 100 is electrically connected to the first terminal of the first thin-film transistor T1, and the first reference voltage line Vref1 is electrically connected to the second terminal of the first thin-film transistor T1. The first thin-film transistor T1 is a dual-gate thin-film transistor, including a first gate 11 and a second gate 12 sequentially stacked in the direction away from the substrate 10. The second gate 12 plays a control role, while the first gate 11 mainly plays a light-shielding role.

[0032] Please continue reading. Figure 2 In a direction parallel to the substrate 10, the first distance D1 between the first gate 11 and the first via 13 ranges from 1.7 to 2.1 μm. Specifically, the first distance D1 can be 1.7, 1.8, 1.9, 2, or 2.1 μm. By designing the first distance D1, and ensuring that the first gate 11 is a straight trace without bends, it can be guaranteed that the first gate 11 does not overlap with the first via 13, thereby improving the yield of the array substrate.

[0033] Please continue reading. Figure 2In a direction parallel to the substrate 10, the second distance D2 between the second gate 12 and the first via 13 ranges from 2.3 to 3.3 μm. Specifically, the second distance D2 can be 2.3, 2.4, 2.5, 2.6, 2.7, 2.8, 2.9, 3, 3.1, 3.2, or 3.3 μm. By designing the second distance D2, and by using a straight trace on the side of the second gate 12 closest to the first via 13 and a bent trace on the side of the second gate 12 furthest from the first via 13, it can be ensured that the second gate 12 does not overlap with the first via 13, thereby improving the yield of the array substrate.

[0034] In one embodiment, the material of the first gate 11 includes at least one of a metal material and a transparent conductive oxide (TCO) material.

[0035] Specifically, metallic materials include aluminum (Al), molybdenum (Mo), chromium (Cr), and copper (Cu). Among them, aluminum has high conductivity and good ductility, enabling it to be made into very thin films, which is beneficial for reducing costs and achieving thinner display panels. In one embodiment, aluminum is often alloyed by adding small amounts of other elements (such as silicon and copper) to form alloys, such as Al-Si-Cu alloys. Molybdenum has a high melting point, high hardness, and good conductivity, and its chemical stability is also good, maintaining stable performance under high temperatures and various chemical environments. Molybdenum has low contact resistance with semiconductor materials, which is beneficial for improving the driving performance of the gate. In organic light-emitting diode (OLED) display panels, molybdenum is often used as a gate material to meet its requirements for high stability and high performance. Chromium has good corrosion resistance and oxidation resistance, which can maintain the stability of the gate performance in harsh environments. At the same time, chromium has strong adhesion to substrate materials such as glass, which is beneficial for improving the reliability of the gate structure. However, the conductivity of chromium is slightly worse than that of metals such as aluminum and copper, and its conductivity usually needs to be improved by optimizing the thin film preparation process. In some display panels with high stability requirements, such as high-end products using liquid crystal displays (LCDs) and organic light-emitting diode (OLED) displays, chromium is used as the gate material or as one layer in a multilayer gate metal structure. Copper has excellent conductivity, being one of the best conductive materials among common metals, which can effectively reduce gate resistance and improve signal transmission speed. When using copper as a gate material, special encapsulation processes or the addition of barrier layers are employed to prevent its oxidation and diffusion.

[0036] Transparent conductive oxide (TCO) materials include indium tin oxide (ITO) and zinc oxide (ZnO)-based materials. ITO, in particular, exhibits excellent transparency and conductivity, with a transmittance exceeding 90% in the visible light range, while also possessing low resistivity, meeting the conductivity requirements of the gate electrode. Furthermore, ITO shows good compatibility with transparent substrates such as glass, facilitating fabrication processes. Due to its superior overall performance, ITO is widely used as a transparent gate electrode in liquid crystal displays (LCDs) and organic light-emitting diode (OLED) display panels. Pure zinc oxide itself is a wide-bandgap semiconductor material; doping it with elements such as aluminum (Al) and gallium (Ga) can significantly improve its conductivity, forming transparent conductive materials such as AZO (aluminum-doped zinc oxide) and GZO (gallium-doped zinc oxide). ZnO-based materials have advantages such as abundant raw materials, low cost, non-toxicity, and good chemical stability. They also have good adhesion to flexible substrates 10, making them suitable for flexible display panels. In some display fields that are sensitive to cost and have high flexibility requirements, such as flexible liquid crystal displays (LCDs) and organic light-emitting diode (OLED) displays, they have been gradually and widely used.

[0037] The material of the second gate 12 includes at least one of a metallic material and a transparent conductive oxide (TCO) material. Specifically, the metallic material includes aluminum (Al), molybdenum (Mo), chromium (Cr), copper (Cu), etc., and the transparent conductive oxide (TCO) material includes indium tin oxide (ITO), zinc oxide (ZnO) based materials, etc.

[0038] In one embodiment, the second gate material further includes a molybdenum-titanium (MoTi) alloy. MoTi alloy, as a top gate, offers advantages such as high conductivity, high stability, good compatibility with semiconductor materials, strong resistance to electromigration, and good etchability. Specifically, MoTi alloy exhibits excellent conductivity, effectively reducing gate resistance, minimizing signal transmission delay, and ensuring the transistor can respond quickly to electrical signals, enabling high-speed switching and thus improving the operating speed and frequency of the transistor and the entire integrated circuit. Molybdenum and titanium are both metals with high chemical and thermal stability. During transistor operation, MoTi alloy can withstand high temperatures and electric field strengths without easily deforming, melting, or undergoing chemical reactions, ensuring the gate's performance stability over long-term use and contributing to improved transistor reliability and lifespan. MoTi alloy also demonstrates good compatibility with common semiconductor materials (such as silicon), forming a stable interface, reducing defects and charge accumulation at the interface, and lowering contact resistance, thereby improving transistor performance and stability and facilitating the realization of high-performance transistor structures and integrated circuit designs. Electromigration refers to the phenomenon of metal atoms moving and causing material damage under the influence of electric current. MoTi alloys exhibit strong resistance to electromigration, maintaining structural stability under high current densities, reducing gate failure caused by electromigration, and improving the reliability of transistors under high current operating conditions. During manufacturing, the gate material requires precise etching to form the desired pattern and structure. MoTi alloys possess excellent etchability, allowing for precise control of the gate's size and shape through photolithography and etching processes, meeting the requirements of ultra-fine manufacturing and contributing to smaller transistor sizes and higher integration density.

[0039] Please see Figure 3 and Figure 4 The pixel circuit also includes a threshold compensation module 600, connected between the second terminal and the control terminal of the driving module 100. The threshold compensation module 600 is used to compensate the threshold voltage of the driving module 100. Specifically, the first terminal of the threshold compensation module 600 is connected to the second terminal of the driving module 100, the second terminal of the threshold compensation module 600 is connected to the control terminal of the driving module 100, and the control terminal of the threshold compensation module 600 is electrically connected to the third scan line S3.

[0040] Please see Figure 3 and Figure 4The light-emitting control module 700 includes a first light-emitting control unit 701 and a second light-emitting control unit 702. The first light-emitting control unit 701 is connected between a first power supply voltage input terminal and a first terminal of the driving module 100. The second light-emitting control unit 702 is connected between a second terminal of the driving module 100 and a first terminal of the light-emitting module 500. Both the control terminals of the first and second light-emitting control units 701 and 702 are simultaneously connected to light-emitting control signals. The second terminal of the light-emitting module 500 is electrically connected to a second power supply voltage input terminal. Specifically, the first power supply voltage input terminal is connected to a first power signal line ELVDD, and the second power supply voltage input terminal is connected to a second power signal line ELVSS, such that the second terminal of the first light-emitting control unit 701 is connected to the first power signal line ELVDD, and the first terminal of the first light-emitting control unit 701 is connected to the first terminal of the driving module 100. The second terminal of the second light-emitting control unit 702 is connected to the second terminal of the driving module 100, and the first terminal of the second light-emitting control unit 702 is connected to the first terminal of the light-emitting module 500. The light-emitting signal is connected to both the control terminals of the first and second light-emitting control units 701 and 702, thereby realizing light-emitting control of the light-emitting unit.

[0041] Please continue reading. Figure 4 The pixel circuit also includes a first storage module 800. A first terminal of the first storage module 800 is electrically connected to the control terminal of the drive module 100, and a second terminal of the first storage module 800 is electrically connected to the first power supply voltage input terminal. Specifically, the control terminal of the drive module 100 is connected to the first terminal of the first storage module 800, and the first terminal of the drive module 100 is connected to the second terminal of the first storage module 800.

[0042] Please continue reading. Figure 4 The array substrate also includes a second initialization module 900, which is electrically connected to the first terminal of the light-emitting module 500, and is used to write a second initialization voltage to the second terminal of the light-emitting module 500 during the second initialization phase. The second initialization phase can be located between the first initialization phase and the data writing phase, or between the data writing phase and the light-emitting phase.

[0043] Please continue reading. Figure 4 and Figure 5The second initialization module 900 includes a third thin-film transistor T3. The second terminal of the third thin-film transistor T3 is electrically connected to the first terminal of the light-emitting module 500, and the first terminal of the third thin-film transistor T3 is electrically connected to the second reference voltage line Vref2. The second initialization module also includes a fourth thin-film transistor T4. The first terminal of the fourth thin-film transistor T4 is electrically connected to the second terminal of the driving module 100, and the second terminal is electrically connected to the third reference voltage line Vref3. The control terminals of both the fourth and third thin-film transistors T4 are connected to the fourth scan line S4. Specifically, the switching on and off of the third and fourth thin-film transistors T3 and T4 is controlled by the signal from the fourth scan line S4.

[0044] Please continue reading. Figure 4 and Figure 5 Specifically, the driving module 100 includes a driving thin-film transistor (DTFT), the control terminal of the driving thin-film transistor (DTFT) is the control terminal of the driving module 100, the first terminal of the driving thin-film transistor (DTFT) is the first terminal of the driving module 100, and the second terminal of the driving thin-film transistor (DTFT) is the second terminal of the driving module 100.

[0045] The first initialization module 300 includes a first thin-film transistor T1, the control terminal of the first thin-film transistor T1 is the control terminal of the first initialization module 300, the first terminal of the first thin-film transistor T1 is the first terminal of the first initialization module 300, and the second terminal of the first thin-film transistor T1 is the second terminal of the first initialization module 300.

[0046] The data writing module 200 includes a second thin-film transistor T2. The control terminal of the second thin-film transistor T2 is the control terminal of the data writing module 200. The first terminal of the second thin-film transistor T2 is the first terminal of the data writing module 200. The second terminal of the second thin-film transistor T2 is the second terminal of the data writing module 200.

[0047] The threshold compensation module 600 includes a fifth thin-film transistor T5. The control terminal of the fifth thin-film transistor T5 is the control terminal of the threshold compensation module 600. The first terminal of the fifth thin-film transistor T5 is the first terminal of the threshold compensation module 600. The second terminal of the fifth thin-film transistor T5 is the second terminal 41 of the threshold compensation module 600.

[0048] The first storage module 800 includes a first capacitor C1, the first end of the first capacitor C1 being the first end of the first storage module 800, and the second end of the first capacitor C1 being the second end of the first storage module 800.

[0049] The light-emitting module 500 includes an organic light-emitting diode (OLED). The first terminal of the OLED is the first terminal of the light-emitting module 500, and the second terminal of the OLED is the second terminal of the light-emitting module 500. The anode 15 and cathode 18 of the OLED serve as the first and second terminals of the light-emitting module 500, respectively. The anode 15 is connected to the light-emitting layer. Different light-emitting layers are separated by a pixel definition layer, which prevents crosstalk between different colored lights.

[0050] The first light-emitting control unit 701 includes a sixth thin-film transistor T6. The control terminal of the sixth thin-film transistor T6 is the control terminal of the first light-emitting control unit 701. The first terminal of the sixth thin-film transistor T6 is the first terminal of the first light-emitting control unit 701. The second terminal of the sixth thin-film transistor T6 is the second terminal of the first light-emitting control unit 701.

[0051] The second light-emitting control unit 702 includes a seventh thin-film transistor T7. The control terminal of the seventh thin-film transistor T7 is the control terminal of the second light-emitting control unit 702. The first terminal of the seventh thin-film transistor T7 is the first terminal of the second light-emitting control unit 702. The second terminal of the seventh thin-film transistor T7 is the second terminal of the second light-emitting control unit 702.

[0052] The second initialization module 900 includes a third thin-film transistor T3 and a fourth thin-film transistor T4, and the control terminals of the third thin-film transistor T3 and the fourth thin-film transistor T4 are the control terminals of the second initialization module 900.

[0053] Furthermore, the fifth thin-film transistor T5 and the first thin-film transistor T1 in this application are P-type thin-film transistors, which are turned on at low voltage and turned off at high voltage. That is, the states of the fifth thin-film transistor T5 and the first thin-film transistor T1 are related to the positive and negative waveform inputs of the first scan line S1 and the third scan line S3. Specifically, during the data writing stage, the third scan line S3 inputs a low level, and the fifth thin-film transistor T5 and the second thin-film transistor T2 are turned on. During the light-emitting stage t2, the third scan line S3 inputs a high level, and the fifth thin-film transistor T5 and the second thin-film transistor T2 are turned off. During the initialization stage, the first scan line S1 inputs a low level, and the first thin-film transistor T1 is turned on. After the initialization stage ends, the first scan line S1 inputs a high level, and the first thin-film transistor T1 is turned off.

[0054] Of course, in other embodiments, the fifth thin-film transistor T5 and the first thin-film transistor T1 can be single-gate thin-film transistors.

[0055] In one embodiment, the fifth thin-film transistor T5 and the first thin-film transistor T1 are made of indium gallium zinc oxide (IGZO), which results in a smaller leakage current during operation and improves the stability of the pixel circuit.

[0056] The pixel circuit includes a charging circuit, a light-emitting circuit, and a reset circuit. The charging circuit is used to charge and write data to the driving thin-film transistor (DTFT). The light-emitting circuit responds to the light-emitting control signal EM, i.e., the light-emitting signal, to realize the light emission of the organic light-emitting diode (EL). The reset circuit resets the thin-film transistor in the pixel circuit and includes a first reference voltage line Vref1, a second reference voltage line Vref2, and a third reference voltage line Vref3.

[0057] Furthermore, the reset circuit includes a reference voltage line Vref, a second reference voltage line Vref2, and a third reference voltage line Vref3. The first reference voltage line Vref1 is connected to the control terminal of the driving thin-film transistor DTFT and is used to reset the control terminal of the driving thin-film transistor DTFT. At the same time, the second reference voltage line Vref2 is connected to the anode of the organic light-emitting diode EL and is used to reset the anode of the organic light-emitting diode EL. In addition, the third reference voltage line Vref3 is connected to the source of the driving thin-film transistor DTFT and is used to reset the source of the driving thin-film transistor DTFT.

[0058] In one embodiment, the charging circuit includes a data signal line Data, a second thin-film transistor T2, a driving thin-film transistor DTFT, and a fifth thin-film transistor T5. The second terminal of the second thin-film transistor T2 is connected to the data signal line Data, the first terminal of the second thin-film transistor T2 is connected to the first terminal of the driving thin-film transistor, the second terminal of the driving thin-film transistor DTFT is connected to the second terminal of the fifth thin-film transistor T5, and the first terminal of the fifth thin-film transistor T5 is connected to the control terminal of the driving thin-film transistor DTFT. In the charging circuit, the signal of the data signal line Data passes through the second terminal of the second thin-film transistor T2, then through the first terminal of the second thin-film transistor T2 to the first terminal of the driving thin-film transistor DTFT, then flows out through the second terminal of the driving thin-film transistor DTFT to the second terminal of the fifth thin-film transistor T5, and then through the first terminal of the fifth thin-film transistor T5 to the control terminal of the driving thin-film transistor DTFT, thereby charging and writing data to the driving thin-film transistor DTFT.

[0059] In one embodiment, the light-emitting circuit includes a first power signal line ELVDD, a light-emitting control signal EM, a sixth thin-film transistor T6, a driving thin-film transistor DTFT, a seventh thin-film transistor T7, and an organic light-emitting diode EL. The second terminal of the sixth thin-film transistor T6 is connected to the first power signal line ELVDD, the control terminal of the sixth thin-film transistor T6 is connected to the light-emitting control signal EM, the first terminal of the sixth thin-film transistor T6 is connected to the first terminal of the driving thin-film transistor DTFT, the second terminal of the driving thin-film transistor DTFT is connected to the second terminal of the seventh thin-film transistor T7, the control terminal of the seventh thin-film transistor T7 is connected to the light-emitting control signal EM, and the first terminal of the seventh thin-film transistor T7 is connected to the anode of the organic light-emitting diode EL. In the light-emitting circuit, the control terminals of both the sixth thin-film transistor T6 and the seventh thin-film transistor T7 are connected to the light-emitting control signal EM, and the sixth thin-film transistor T6 and the seventh thin-film transistor T7 are turned on in response to the signal emitted by the light-emitting control signal EM.

[0060] Furthermore, the pixel circuit in this application has an 8T1C structure, meaning it includes eight thin-film transistors and one storage capacitor. Wherein:

[0061] The driving thin-film transistor (DTFT) can be electrically connected between the first power signal line ELVDD and the organic light-emitting diode (EL) (or between the first node N1 and the second node N2), and can be turned on in response to the third node voltage at the third node N3.

[0062] The second thin-film transistor T2 is used for data writing. The second thin-film transistor T2 (or switching thin-film transistor) can be electrically connected between the data signal line Data and the first node N1, and can be turned on in response to the signal of the second scan line S2.

[0063] The fifth thin-film transistor T5 is used for threshold compensation. It can be electrically connected between the third node N3 and the fourth node N4, and can be turned on by the third scan line S3. That is, the second thin-film transistor T2 and the fifth thin-film transistor T5 can transmit data signals to the third node N3 in response to the third scan line S3. The first capacitor C1 can be electrically connected between the first power supply signal line ELVDD and the third node N3, and can store the data signals supplied to the third node N3.

[0064] The first thin-film transistor T1 is used to reset the control terminal of the driving thin-film transistor DTFT. The first thin-film transistor T1 can be electrically connected between the fourth node N4 and the first reference voltage line Vref1, and can be turned on in response to the signal of the first scan line S1. Here, the first capacitor C1 can be initialized to be charged (or have) voltage.

[0065] The sixth thin-film transistor T6 is used to control the organic light-emitting diode EL to emit light during the light-emitting stage. The sixth thin-film transistor T6 can be electrically connected between the first power signal line ELVDD and the first node N1, and can be turned on in response to the light-emitting control signal EM.

[0066] The seventh thin-film transistor T7 is used to control the light emission of the organic light-emitting diode EL during the light-emitting phase. The seventh thin-film transistor T7 can be electrically connected between the second node N2 and the fifth node N5, and can be turned on in response to the light emission control signal EM. That is, the sixth thin-film transistor T6 and the seventh thin-film transistor T7 can form a current path from the first power supply signal line ELVDD to the organic light-emitting diode EL in response to the light emission control signal EM.

[0067] The third thin-film transistor T3 is used to reset the organic light-emitting diode EL. The third thin-film transistor T3 can be electrically connected between the second reference voltage line Vref2 and the fifth node N5, and can be turned on in response to the signal of the fourth scan line S4. That is, the third thin-film transistor T3 can form a bypass path (or bypass route) between the fifth node N5 and the second reference voltage line Vref2 in response to the fourth scan line S4. The organic light-emitting diode EL can be an organic light-emitting diode EL.

[0068] The fourth thin-film transistor T4 is used to reset the source of the driving thin-film transistor DTFT and shares a gate line with the third thin-film transistor T3. The fourth thin-film transistor T4 can be electrically connected between the second node N2 and the third reference voltage line Vref3, and can be turned on in response to the fourth scan line S4. This resets the source of the driving thin-film transistor DTFT.

[0069] An organic light-emitting diode (OLED) EL can be electrically connected between the fifth node N5 and the second power signal line ELVSS. Similarly, the anode of the OLED EL can be electrically connected to the fifth node N5, and the cathode of the OLED EL can be electrically connected to the second power signal line ELVSS. The OLED EL emits light based on the current transmitted through the driving thin-film transistor DTFT (i.e., the driving current). The OLED EL works in conjunction with the first capacitor C1, as... Figure 5 As shown, the first capacitor C1 can be represented as a parasitic capacitor connected in parallel with the organic light-emitting diode EL.

[0070] In one embodiment, the thin-film transistor described above can be made of low-temperature polysilicon (LTPS).

[0071] This application also provides a display panel including the array substrate described in the above embodiments. This embodiment provides an array substrate that can be applied to display panels such as electronic paper, mobile phones, tablets, televisions, monitors, laptops, digital photo frames, smart bracelets, smartwatches, supercomputers, navigators, and other mobile or fixed terminals. The array substrate can be an organic light-emitting diode (OLED) array substrate, a micro light-emitting diode (Micro LED or μLED) array substrate, or a liquid crystal display (LCD) array substrate.

[0072] The above description is merely an embodiment of this application and does not limit the patent scope of this application. Any equivalent structural or procedural transformations made using the content of this application's specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of this application.

Claims

1. An array substrate, characterized in that, Includes a substrate and pixel circuitry and data signal lines disposed on the substrate, wherein the pixel circuitry includes: The module consists of a driver module, a data writing module, a first initialization module, a light-emitting control module, and a light-emitting module. The first initialization module is electrically connected to the control terminal of the drive module; The data writing module is electrically connected to the control terminal of the drive module; The light-emitting control module, the driving module, and the light-emitting module are connected in series to form a driving branch. The light-emitting control module is turned on during the light-emitting stage to connect the driving branch. The first initialization module includes a first thin-film transistor. The first terminal of the first thin-film transistor is electrically connected to the control terminal of the driving module, and the second terminal of the first thin-film transistor is used to be electrically connected to a first reference voltage line. The first thin-film transistor is a dual-gate thin-film transistor, including a first gate and a second gate that are sequentially stacked in the direction away from the substrate. The data writing module includes a second thin-film transistor, one end of which is electrically connected to the data signal line through a first via. Wherein, the orthogonal projections of the first gate and the second gate on the substrate partially overlap, the orthogonal projections of the first gate and the first via on the substrate are spaced apart, the orthogonal projections of the second gate and the first via on the substrate are spaced apart, and in a direction parallel to the substrate, the first distance between the first gate and the first via is less than the second distance between the second gate and the first via.

2. The array substrate according to claim 1, characterized in that, In a direction parallel to the substrate, the first distance between the first gate and the first via ranges from 1.7 to 2.1 μm.

3. The array substrate according to claim 1, characterized in that, In a direction parallel to the substrate, the second distance between the second gate and the first via ranges from 2.3 to 3.3 μm.

4. The array substrate according to claim 1, characterized in that, The pixel circuit also includes: A threshold compensation module is connected between the second end of the drive module and the control end. The threshold compensation module is used to compensate the threshold voltage of the drive module.

5. The array substrate according to claim 1, characterized in that, The light-emitting control module includes a first light-emitting control unit and a second light-emitting control unit, wherein the first light-emitting control unit is connected between a first power supply voltage input terminal and a first terminal of the driving module, and the second light-emitting control unit is connected between a second terminal of the driving module and a first terminal of the light-emitting module. The control terminals of the first light-emitting control unit and the second light-emitting control unit are simultaneously connected to light-emitting control signals. The second end of the light-emitting module is electrically connected to the second power supply voltage input terminal.

6. The array substrate according to claim 5, characterized in that, The pixel circuit further includes a first storage module, a first end of which is electrically connected to the control terminal of the driving module, and a second end of which is electrically connected to the first power supply voltage input terminal.

7. The array substrate according to claim 1, characterized in that, The pixel circuit also includes: The second initialization module is electrically connected to the first terminal of the light-emitting module and is used to write the second initialization voltage into the second terminal of the light-emitting module during the second initialization phase.

8. The array substrate according to claim 7, characterized in that, The second initialization module includes a third thin-film transistor, the second terminal of which is electrically connected to the first terminal of the light-emitting module, and the first terminal of which is used for electrical connection to a second reference voltage line. Meanwhile, the second initialization module also includes a fourth thin-film transistor. The first end of the fourth thin-film transistor is electrically connected to the first end of the control module, and the second end is used to be electrically connected to the third reference voltage line. The control ends of the fourth thin-film transistor and the third thin-film transistor are both connected to the fourth scan line.

9. The array substrate according to claim 1, characterized in that, The material of the first gate includes at least one of a metallic material and a transparent conductive oxide material; The material of the second gate includes at least one of a metallic material and a transparent conductive oxide material.

10. A display panel, characterized in that, Includes the array substrate as described in any one of claims 1 to 9.

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