Driving substrate and display panel

Abstract

The application discloses a driving substrate and a display panel, and belongs to the technical field of display. The driving substrate comprises a substrate and a first transistor. The first transistor comprises a first electrode, a first semiconductor layer, a first insulating layer, a second electrode, a second insulating layer and a first gate electrode. The first electrode is arranged on one side of the substrate. The first semiconductor layer is arranged on the side of the first electrode away from the substrate, and comprises a main body part and a first active part connected to one side of the main body part. The first insulating layer is arranged on the side of the main body part away from the substrate. At least part of the second electrode is arranged on the side of the first active part away from the substrate. The second insulating layer covers at least the side surface of the first electrode, the side surface of the first active part and the second electrode. The first gate electrode is arranged on the side of the second insulating layer away from the first active part, and overlaps with the side surface of the first active part. The application can improve the device stability of the thin film transistor, improve the switching speed of the thin film transistor, and improve the refresh rate of the display panel.

Description

Technical Field

[0001] This application relates to the field of display technology, and more particularly to a driving substrate and a display panel. Background Technology

[0002] In a thin-film transistor (TFT) with a vertical channel formed by stacking source, semiconductor layer, and drain, the gate is disposed on the side of the semiconductor layer. When the TFT is turned on, a portion of the semiconductor layer near the gate forms a vertical channel that can conduct the source and drain. Charge carriers transfer between the source and drain through the vertical channel, creating a voltage difference between them. The portion of the semiconductor layer away from the gate cannot conduct the source and drain. At this point, the source, the portion of the semiconductor layer away from the gate, and the drain form a stacked structure. Because of the voltage difference between the source and drain, the portion of the semiconductor layer away from the gate is located in an electric field.

[0003] To further improve the refresh rate of display panels, it is necessary to increase the switching speed of thin-film transistors (TFTs). Increasing the switching speed can be achieved by shortening the channel length, thereby reducing the carrier migration time from the source to the drain. In the aforementioned TFT with a vertical channel, the length of the vertical channel is equal to the thickness of the semiconductor layer. To improve the switching speed of the TFT, the thickness of the semiconductor layer needs to be reduced. However, after reducing the thickness of the semiconductor layer, the thickness of the portion of the semiconductor layer away from the gate also decreases. This reduces the source-drain distance on both sides of the portion of the semiconductor layer away from the gate, leading to an increase in the electric field strength at this location. This makes the portion of the semiconductor layer away from the gate more susceptible to quantum tunneling, affecting the device stability of the TFT.

[0004] Therefore, it is necessary to propose a new technical solution to solve the above-mentioned technical problems. Summary of the Invention

[0005] The purpose of this application is to provide a driving substrate and a display panel that can improve the device stability of thin-film transistors, increase the switching speed of thin-film transistors, and improve the refresh rate of the display panel.

[0006] To solve the above problems, the technical solution of this application is as follows: In a first aspect, this application proposes a driving substrate, comprising: Includes a substrate and a first transistor disposed on one side of the substrate, the first transistor comprising: The first electrode is disposed on one side of the substrate; A first semiconductor layer is disposed on the side of the first electrode away from the substrate, and includes a main body portion and a first active portion connected to one side of the main body portion; A first insulating layer is disposed on the side of the main body away from the substrate; A second electrode, at least a portion of which is disposed on the side of the first active portion away from the substrate; A second insulating layer covers at least the side surface of the first electrode, the side surface of the first active portion, and the second electrode; and The first gate is disposed on the side of the second insulating layer away from the first active portion and overlaps with the side of the first active portion.

[0007] In one embodiment of this application, the width of the first active portion in the direction parallel to the substrate is in the range of 5 nanometers to 30 nanometers.

[0008] In one embodiment of this application, the first active part includes: A first connecting portion is located between the first electrode and the second electrode, and the first connecting portion is connected to one side of the main body; and A first channel portion is located between the first electrode and the second electrode. The first channel portion is connected to the side of the first connection portion away from the main body portion. The second insulating layer covers the side of the first channel portion away from the first connection portion. The first gate overlaps with the side of the first channel portion. When the first transistor is turned on, the first channel portion electrically connects the first electrode and the second electrode, and the first electrode and the second electrode are respectively insulated from the first connection portion.

[0009] In one embodiment of this application, the width of the first channel portion in the direction parallel to the substrate is in the range of 5 nanometers to 30 nanometers.

[0010] In one embodiment of this application, the first semiconductor layer further includes a second active portion, which is disposed on the side of the first electrode away from the substrate. The two sides of the main body are respectively connected to the first active portion and the second active portion, and a portion of the second electrode is disposed on the side of the second active portion away from the substrate. The second insulating layer also covers the side of the second active part; The first gate includes a first sub-gate and a second sub-gate; The first sub-gate is disposed on the side of the second insulating layer away from the first active portion and overlaps with the side of the first active portion; The second sub-gate is disposed on the side of the second insulating layer away from the second active portion and overlaps with the side of the second active portion.

[0011] In one embodiment of this application, the width of the second active portion in the direction parallel to the substrate is in the range of 5 nanometers to 30 nanometers.

[0012] In one embodiment of this application, the second active part includes: A second connecting portion is located between the first electrode and the second electrode, and the second connecting portion is connected to the other side of the main body; and The second channel portion is located between the first electrode and the second electrode. The second channel portion is connected to the side of the second connection portion away from the main body portion. The second insulating layer covers the side of the second channel portion away from the second connection portion. The second sub-gate overlaps with the side of the second channel portion. When the first transistor is turned on, the second channel portion electrically connects the first electrode and the second electrode, and the first electrode and the second electrode are respectively insulated from the second connection portion.

[0013] In one embodiment of this application, the first sub-gate is electrically connected to the second sub-gate.

[0014] In one embodiment of this application, the second electrode continuously covers the side of the first active portion away from the substrate, the side of the first insulating layer away from the substrate, and the side of the second active portion away from the substrate.

[0015] In one embodiment of this application, the second electrode includes: The first sub-electrode is disposed on the side of the first active portion away from the substrate; and The second sub-electrode is disposed on the side of the second active portion away from the substrate. The second sub-electrode is spaced apart from the first sub-electrode to form a gap, and the gap exposes the first insulating layer.

[0016] In one embodiment of this application, the driving substrate further includes a connection trace. In a plan view of the driving substrate, the connection trace is located outside the first semiconductor layer, and the connection trace electrically connects the first sub-electrode and the second sub-electrode.

[0017] In one embodiment of this application, in a plan view of the driving substrate, the first active portion extends around the periphery of the main body portion, and the orthographic projection of the first gate on the substrate extends around the periphery of the orthographic projection of the first semiconductor layer on the substrate.

[0018] In one embodiment of this application, the thickness of the first insulating layer is in the range of 4000 angstroms to 8000 angstroms; The thickness of the first semiconductor layer is in the range of 5 nanometers to 500 nanometers.

[0019] In one embodiment of this application, the driving substrate further includes: The adapter structure is located on one side of the first transistor and is electrically connected to one of the first electrode and the second electrode. A passivation layer covers the first transistor and the transition structure; and The third electrode is disposed on the side of the passivation layer away from the substrate and is electrically connected to the transition structure; The switching structure includes at least one switching electrode, each switching electrode being disposed on the same layer as one of the first electrode, the second electrode, and the first gate, and different switching electrodes being disposed on different layers.

[0020] In one embodiment of this application, the driving substrate includes a pixel setting area and a non-pixel setting area located on at least one side of the pixel setting area, and the first transistor is disposed in the non-pixel setting area; The driving substrate further includes a second transistor located in the pixel setting area, the second transistor comprising: A fourth electrode is disposed on one side of the substrate, and the fourth electrode is disposed in the same layer as the first electrode; The second semiconductor layer is disposed on the side of the fourth electrode away from the substrate. The second semiconductor layer is disposed in the same layer as the first semiconductor layer. The second semiconductor layer includes a third channel portion and a third connection portion and a fourth connection portion connected to both sides of the third channel portion. The first insulating layer is also disposed on the side of the third channel portion away from the substrate; The second gate is disposed on the side of the first insulating layer away from the third channel portion, and the second gate is disposed in the same layer as the second electrode; The second insulating layer also covers the second electrode, the second semiconductor layer, and the fourth electrode; The fifth electrode is disposed on the side of the second insulating layer away from the substrate. The fifth electrode is disposed on the same layer as the first gate electrode. The fifth electrode includes a third sub-electrode and a fourth sub-electrode. The third sub-electrode is electrically connected to the third connection portion, and the fourth sub-electrode is electrically connected to the fourth connection portion. The driving substrate further includes: A passivation layer covers the first transistor and the second transistor; The sixth electrode is disposed on the side of the passivation layer away from the substrate, and the sixth electrode is electrically connected to one of the third sub-electrode and the fourth sub-electrode.

[0021] Secondly, this application proposes a display panel, the display panel including a driving substrate, the driving substrate including a substrate and a first transistor disposed on one side of the substrate, the first transistor including: The first electrode is disposed on one side of the substrate; A first semiconductor layer is disposed on the side of the first electrode away from the substrate, and includes a main body portion and a first active portion connected to one side of the main body portion; A first insulating layer is disposed on the side of the main body away from the substrate; A second electrode, at least a portion of which is disposed on the side of the first active portion away from the substrate; A second insulating layer covers at least the side surface of the first electrode, the side surface of the first active portion, and the second electrode; and The first gate is disposed on the side of the second insulating layer away from the first active portion and overlaps with the side of the first active portion.

[0022] In the embodiments of this application, when the first transistor is turned on, the first active portion can electrically connect the first electrode and the second electrode to form a vertical channel. Charge carriers can transfer between the first electrode and the second electrode through the first active portion. There is a voltage difference between the first electrode and the second electrode. By providing a first insulating layer on the main body, the contact area between the second electrode and the main body is reduced, thereby reducing the probability of quantum tunneling in the main body, improving the device stability of the first transistor, increasing the switching speed of the first transistor, and increasing the refresh rate of the display panel. Attached Figure Description

[0023] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0024] To gain a more complete understanding of this application and its beneficial effects, the following description will be provided in conjunction with the accompanying drawings, wherein the same reference numerals in the following description denote the same parts.

[0025] Figure 1 This is a schematic diagram of a driving substrate; Figure 2 This is a schematic diagram of a driving substrate according to the first embodiment of this application; Figure 3 This is a plan view of the driving substrate according to the first embodiment of this application; Figure 4 This is another plan view of the driving substrate of the first embodiment of this application; Figure 5 This is yet another plan view of the driving substrate according to the first embodiment of this application; Figure 6This is another plan view of the driving substrate of the first embodiment of this application; Figure 7 This is a plan view of the driving substrate according to the first embodiment of this application; Figure 8 This is another plan view of the driving substrate of the first embodiment of this application; Figure 9 This is a schematic diagram of a driving substrate according to a second embodiment of this application; Figure 10 This is a schematic diagram of a driving substrate according to a third embodiment of this application; Figure 11 This is a plan view of the driving substrate according to the third embodiment of this application; Figure 12 This is a schematic diagram of a driving substrate according to the fourth embodiment of this application; Figure 13 This is a plan view of the driving substrate according to the fourth embodiment of this application; Figure 14 This is a schematic diagram of a driving substrate according to the fifth embodiment of this application; Figure 15 This is a schematic diagram of a driving substrate according to the sixth embodiment of this application; Figure 16 This is another schematic diagram of the driving substrate according to the sixth embodiment of this application; Figure 17 This is another schematic diagram of the driving substrate according to the seventh embodiment of this application.

[0026] Explanation of reference numerals in the attached figures: 100, driving substrate; AA, pixel setting area; NA, non-pixel setting area; D1, board surface direction parallel to the substrate; 10. Substrate; T1, First transistor; T2, Second transistor; G, Notch; 21. First electrode; 22. Fourth electrode; 30. First semiconductor layer; 31. Main body portion; 32. First active portion; 321. First connecting portion; 322. First channel portion; 33. Second active portion; 331. Second connecting portion; 332. Second channel portion; 34. Second semiconductor layer; 341. Third channel portion; 342. Third connecting portion; 343. Fourth connecting portion; 40. First insulating layer; 50. Second electrode; 51. First sub-electrode; 52. Second sub-electrode; 53. Connecting trace; 54. Second gate electrode; 60. Second insulating layer; 70. First gate electrode; 71. First sub-gate electrode; 72. Second sub-gate electrode; 73. Fifth electrode; 731. Third sub-electrode; 732. Fourth sub-electrode; 81. Adapter structure; 811. Adapter electrode; 82. Passivation layer; 83. Third electrode; 84. Sixth electrode. Detailed Implementation

[0027] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the protection scope of this application.

[0028] Please see Figure 1 In a thin-film transistor with a vertical channel formed by stacking a source 21', a semiconductor layer 30', and a drain 50', a gate 70' is disposed on the side of the semiconductor layer 30'. When the thin-film transistor is turned on, a portion 32' of the semiconductor layer 30' near the gate 70' forms a vertical channel that can conduct the source 21' and the drain 50'. Charge carriers transfer between the source 21' and the drain 50 through the vertical channel, resulting in a voltage difference between the source 21' and the drain 50'. A portion 31' of the semiconductor layer 30' away from the gate 70' cannot conduct the source 21' and the drain 50'. At this time, the source 21', the portion 31' of the semiconductor layer 30' away from the gate 70', and the drain 50' form a stacked structure. Because there is a voltage difference between the source 21' and the drain 50', the portion 31' of the semiconductor layer 30' away from the gate 70' is located in an electric field.

[0029] To further improve the refresh rate of the display panel, the switching speed of the thin-film transistor (TFT) needs to be increased. Increasing the switching speed can be achieved by shortening the channel length, thereby reducing the carrier migration time from the source 21' to the drain 50'. In the aforementioned TFT with a vertical channel, the length of the vertical channel is equal to the thickness of the semiconductor layer 30'. To improve the switching speed of the TFT, the thickness of the semiconductor layer 30' needs to be reduced. However, after reducing the thickness of the semiconductor layer 30', the thickness of the portion 31' of the semiconductor layer 30' away from the gate 70' is also reduced. This reduces the distance between the source 21' and drain 50' on both sides of this portion 31', leading to an increase in the electric field strength at this location. This makes the portion 31' of the semiconductor layer 30' away from the gate 70' more susceptible to quantum tunneling, affecting the device stability of the TFT.

[0030] It's important to understand that the reason quantum tunneling occurs in a portion 31' of the semiconductor layer 30' away from the gate 70' in an electric field is that the semiconductor layer 30' is formed through deposition, and from a microscopic perspective, its surface contains defects. The larger the surface area of ​​the semiconductor layer 30', the more surface defects it contains. When these surface defects are located in an electric field, the probability of quantum tunneling occurring at these defects is relatively high. When the surface area of ​​the semiconductor layer 30' in the electric field is relatively large, the relatively large number of defects on its surface will also be located in the electric field, thus increasing the probability of quantum tunneling occurring on the surface of the semiconductor layer 30'.

[0031] This application discloses a display panel that can be applied to display devices such as tablet computers, e-readers, electronic display screens, laptops, mobile phones, augmented reality (AR) / virtual reality (VR) devices, media players, wearable devices, digital cameras, and car navigation systems. The display panel includes a driving substrate 100.

[0032] The display panel can be one of the following: organic light-emitting diode display panel, micro light-emitting diode display panel, sub-millimeter light-emitting diode display panel, or liquid crystal display panel.

[0033] Please see Figure 2 This application proposes a driving substrate 100, including a substrate 10 and a first transistor T1 disposed on one side of the substrate 10.

[0034] The first transistor T1 includes a first electrode 21, a first semiconductor layer 30, a first insulating layer 40, a second electrode 50, a second insulating layer 60, and a first gate 70.

[0035] The first electrode 21 is disposed on one side of the substrate 10.

[0036] The first semiconductor layer 30 is disposed on the side of the first electrode 21 away from the substrate 10. The first semiconductor layer 30 includes a main body portion 31 and a first active portion 32 connected to one side of the main body portion 31.

[0037] The first insulating layer 40 is disposed on the side of the main body 31 away from the substrate 10.

[0038] At least a portion of the second electrode 50 is disposed on the side of the first active portion 32 away from the substrate 10.

[0039] The second insulating layer 60 at least covers the side of the first electrode 21, the side of the first active portion 32, and the second electrode 50.

[0040] The first gate 70 is disposed on the side of the second insulating layer 60 away from the first active portion 32. The first gate 70 overlaps with the side surface of the first active portion 32.

[0041] In the embodiments of this application, when the first transistor T1 is turned on, the first active portion 32 can electrically conduct the first electrode 21 and the second electrode 50, forming a vertical channel. Charge carriers can transfer between the first electrode 21 and the second electrode 50 through the first active portion 32, and a voltage difference exists between the first electrode 21 and the second electrode 50. By providing a first insulating layer 40 on the main body 31, the embodiment of this application reduces the contact area between the second electrode 50 and the main body 31, thereby reducing the probability of quantum tunneling in the main body 31, improving the device stability of the first transistor T1, increasing the switching speed of the first transistor T1, and improving the refresh rate of the display panel.

[0042] It is important to understand that a voltage difference exists between the first electrode 21 and the second electrode 50, forming a first electric field. The strength of the first electric field also depends on the distance between the first electrode 21 and the second electrode 50; when the thickness of the first semiconductor layer 30 is small, the strength of the first electric field is large. The main body 31 is located on the side of the first active part 32 away from the gate. When the first transistor T1 is turned on, the main body 31 is still in a high-resistivity state. Due to the thinness of the main body 31 and the presence of defects on its surface, if the surface area of ​​the main body 31 in the first electric field is large, quantum tunneling is likely to occur, causing the first transistor T1 to fail. This embodiment reduces the surface area of ​​the main body 31 in the first electric field, thereby reducing the probability of quantum tunneling in the main body 31 and improving the device stability of the first transistor T1.

[0043] It should be understood that in the first transistor T1, the first electrode 21 can be used as either the source or the drain, and the second electrode 50 can be used as either the source or the drain; these are not limited here.

[0044] Optionally, the material of the first semiconductor layer 30 can be a metal oxide semiconductor layer. The metal oxide semiconductor can be indium gallium zinc oxide (IGZO), indium gallium zinc tin oxide (IGZTO), indium zinc oxide (IZO), indium gallium oxide (IGO), etc. The metal oxide semiconductor layer can suppress excessive oxygen vacancy generation, improve bias stability, and reduce off-state leakage current.

[0045] Optionally, the first semiconductor layer 30 may be made of low-temperature polycrystalline silicon (LTPS). LTPS has a high mobility, which can improve the switching speed of the first transistor T1 and increase the refresh rate of the display panel.

[0046] Optionally, the material of the first insulating layer 40 can be an organic insulating material or an inorganic insulating material. The inorganic insulating material can be at least one of silicon oxide, silicon nitride, and silicon oxynitride. Optionally, the material of the first insulating layer 40 has good dielectric insulation properties and withstand voltage properties.

[0047] Optionally, the first semiconductor layer 30 is a single-layer film.

[0048] In this embodiment, the thickness of the single-layer first semiconductor layer 30 is relatively thin compared to a semiconductor layer formed by multiple film layers. Since the channel length of the first active portion 32 is related to the thickness of the first semiconductor layer 30, the thinner the first semiconductor layer 30, the shorter the channel length of the first active portion 32, thereby increasing the switching speed of the first transistor T1 and improving the refresh rate of the display panel.

[0049] Optionally, the thickness of the first semiconductor layer 30 is in the range of 5 nanometers to 500 nanometers.

[0050] Since the channel length of the first active portion 32 is related to the thickness of the first semiconductor layer 30, the thinner the first semiconductor layer 30, the shorter the channel length of the first active portion 32, thereby improving the switching speed of the first transistor T1 and increasing the refresh rate of the display panel. Furthermore, because the first semiconductor layer 30 is nanometer-thick, it is relatively thin. When the first semiconductor layer 30 is disposed alone between the first electrode 21 and the second electrode 50, the thinner main body portion 31 will experience quantum tunneling in the electric field between the first electrode 21 and the second electrode 50, affecting the device stability of the first transistor T1. Therefore, a first insulating layer 40 needs to be disposed on the first semiconductor layer 30 to protect the main body portion 31.

[0051] The thickness of the first semiconductor layer 30 can be 5 nm, 10 nm, 15 nm, 20 nm, 25 nm, 30 nm, 35 nm, 40 nm, 45 nm, 50 nm, 55 nm, 60 nm, 65 nm, 70 nm, 75 nm, 80 nm, 85 nm, 90 nm, 95 nm, 100 nm, 110 nm, 120 nm, 130 nm, 140 nm, 150 nm, 160 nm, 170 nm, 180 nm, 190 nm, 200 nm, 21 nm, etc. The thicknesses range from 0 nm, 220 nm, 230 nm, 240 nm, 250 nm, 260 nm, 270 nm, 280 nm, 290 nm, 300 nm, 310 nm, 320 nm, 330 nm, 340 nm, 350 nm, 360 nm, 370 nm, 380 nm, 390 nm, 400 nm, 410 nm, 420 nm, 430 nm, 440 nm, 450 nm, 460 nm, 470 nm, 480 nm, 490 nm, to 500 nm. As the thickness of the first semiconductor layer 30 decreases, the thickness of the main body 31 and the first active portion 32 also decrease accordingly. The thickness of the first active portion 32 is related to the channel length of the first semiconductor layer 30, and the thickness of the main body 31 is related to the spacing between the first electrode 21 and the second electrode 50.

[0052] Optionally, the thickness of the first insulating layer 40 is in the range of 4,000 angstroms to 8,000 angstroms.

[0053] In this embodiment, during the process of thinning the thickness of the first semiconductor layer 30 to improve the switching speed of the first transistor T1, when a portion of the second electrode 50 is disposed on the surface of the first insulating layer 40, a main body portion 31 and the first insulating layer 40 are disposed between the first electrode 21 and the second electrode 50. The distance between the first electrode 21 and the second electrode 50 also depends on the thickness of the main body portion 31 and the thickness of the first insulating layer 40. Since the first insulating layer 40 itself has a certain thickness, it can be ensured that the distance between the first electrode 21 and the second electrode 50 is greater than the thickness of the first insulating layer 40 itself, thereby reducing the risk of quantum tunneling in the main body portion 31, improving the device stability of the first transistor T1, increasing the switching speed of the first transistor T1, and improving the refresh rate of the display panel.

[0054] Optionally, as the thickness of the first semiconductor layer 30 decreases, the thickness of the first insulating layer 40 increases accordingly.

[0055] Optionally, the thickness of the first insulating layer 40 can be 4000 angstroms, 4100 angstroms, 4200 angstroms, 4300 angstroms, 4400 angstroms, 4500 angstroms, 4600 angstroms, 4700 angstroms, 4800 angstroms, 4900 angstroms, 5000 angstroms, 5100 angstroms, 5200 angstroms, 5300 angstroms, 5400 angstroms, 5500 angstroms, 5600 angstroms, 5700 angstroms, 5800 angstroms, 5 900 angstroms, 6000 angstroms, 6100 angstroms, 6200 angstroms, 6300 angstroms, 6400 angstroms, 6500 angstroms, 6600 angstroms, 6700 angstroms, 6800 angstroms, 6900 angstroms, 7000 angstroms, 7100 angstroms, 7200 angstroms, 7300 angstroms, 7400 angstroms, 7500 angstroms, 7600 angstroms, 7700 angstroms, 7800 angstroms, 7900 angstroms, 8000 angstroms, etc.

[0056] In the first embodiment of this application: Please see Figure 2 Optionally, the width M1 of the first active portion 32 in the direction D1 parallel to the substrate 10 is in the range of 5 nanometers to 30 nanometers.

[0057] In the first embodiment, the second electrode 50 is disposed on the first active portion 32. When the first transistor T1 is turned on, the first gate 70 is subjected to voltage, and the first active portion 32 forms a vertical conductive channel.

[0058] Since the voltage of the first gate 70 only establishes an electric field on the side surface of the first semiconductor layer 30, when the voltage of the first gate 70 remains constant, the length of the width M1 of the first active portion 32 in the direction D1 parallel to the substrate 10 depends on the thickness of the gate insulating layer. The thinner the gate insulating layer, the longer the width M1 of the first active portion 32 in the direction D1 parallel to the substrate 10. The thicker the gate insulating layer, the shorter the width M1 of the first active portion 32 in the direction D1 parallel to the substrate 10.

[0059] In the first embodiment, the first active portion 32 is the region in the first semiconductor layer 30 where a vertical conductive channel is formed when the first transistor T1 is turned on. The main body portion 31 is the region in the first semiconductor layer 30 where no vertical conductive channel is formed when the first transistor T1 is turned on. The first embodiment contacts the second electrode 50 with the region in the first semiconductor layer 30 where a channel is formed, reducing the contact area between the second electrode 50 and the region in the first semiconductor layer 30 where no channel is formed. This reduces the surface area of ​​the region in the first semiconductor layer 30 where no channel is formed in the first electric field, lowers the probability of quantum tunneling in the region, improves the device stability of the first transistor, increases the switching speed of the first transistor, and increases the refresh rate of the display panel.

[0060] The width M1 of the first active portion 32 in the direction D1 parallel to the substrate 10 can be 5 nm, 6 nm, 7 nm, 8 nm, 9 nm, 10 nm, 11 nm, 12 nm, 13 nm, 14 nm, 15 nm, 16 nm, 17 nm, 18 nm, 19 nm, 20 nm, 21 nm, 22 nm, 23 nm, 24 nm, 25 nm, 26 nm, 27 nm, 28 nm, 29 nm, 30 nm, etc. As the gate insulating layer becomes thinner, the width M1 of the first active portion 32 in the direction D1 parallel to the substrate 10 becomes longer, the contact area between the second electrode 50 and the first active portion 32 becomes larger, and the contact effect between the second electrode 50 and the first active portion 32 becomes better. However, the gate insulating layer cannot be too thin, otherwise there is a risk of gate insulating layer breakdown.

[0061] Optionally, in a plan view of the drive substrate 100, the first active portion 32 extends around the periphery of the main body portion 31.

[0062] Optionally, the orthographic projection of the first gate 70 on the substrate 10 extends around the periphery of the orthographic projection of the first semiconductor layer 30 on the substrate 10.

[0063] In this embodiment, the extension length of the first active portion 32 around the periphery of the main body portion 31 is equal to the channel width of the first semiconductor layer 30. The longer the extension length of the first active portion 32, the wider the channel width of the first semiconductor layer 30. When the thickness of the first semiconductor layer 30 remains constant, the aspect ratio of the channel of the first semiconductor layer 30 can be increased, thereby reducing the on-resistance and increasing the on-current. This allows the first transistor T1 to charge more current to the pixel capacitor or the light-emitting sub-pixel, thus improving the charging speed.

[0064] Please see Figure 3 In one embodiment, in a plan view of the driving substrate 100, the orthographic projection of the first active portion 32 on the substrate 10 is located on one side of the orthographic projection of the main body portion 31 on the substrate 10.

[0065] In this embodiment, the extension length of the first active portion 32 around the periphery of the main body portion 31 is relatively short, the channel width of the first semiconductor layer 30 is relatively small, and the charging speed of the first transistor T1 is relatively slow.

[0066] Please see Figure 4 In another embodiment, in a plan view of the driving substrate 100, the orthographic projection of the first active portion 32 on the substrate 10 is located on both sides adjacent to the orthographic projection of the main body portion 31 on the substrate 10.

[0067] In this embodiment, the first active portion 32 extends longer around the periphery of the main body portion 31 than in the previous embodiment, the channel width of the first semiconductor layer 30 is wider than in the previous embodiment, and the charging speed of the first transistor T1 is improved compared to the previous embodiment.

[0068] Please see Figure 5 In another embodiment, in a plan view of the driving substrate 100, the orthographic projection of the first active portion 32 on the substrate 10 is located on three adjacent sides of the orthographic projection of the main body portion 31 on the substrate 10.

[0069] In this embodiment, the first active portion 32 extends longer around the periphery of the main body portion 31 than in the previous embodiment, the channel width of the first semiconductor layer 30 is wider than in the previous embodiment, and the charging speed of the first transistor T1 is improved compared to the previous embodiment.

[0070] Please see Figure 6 In another embodiment, in a plan view of the drive substrate 100, the orthographic projection of the first active portion 32 on the substrate 10 surrounds the orthographic projection of the main body portion 31 on the substrate 10.

[0071] In this embodiment, the first active portion 32 extends longer around the periphery of the main body portion 31 than in the previous embodiment, the channel width of the first semiconductor layer 30 is wider than in the previous embodiment, and the charging speed of the first transistor T1 is improved compared to the previous embodiment.

[0072] Please see Figure 7 The shape of the orthographic projection of the first semiconductor layer 30 onto the substrate 10 can be circular. (See also...) Figure 8 The shape of the orthographic projection of the first semiconductor layer 30 onto the substrate 10 can also be a semicircle. Here, the shape of the orthographic projection of the first semiconductor layer 30 onto the substrate 10 is not limited.

[0073] In the second embodiment of this application: To avoid redundancy, the second embodiment of this application only describes the differences from the first embodiment of this application.

[0074] The second embodiment of this application differs from the first embodiment of this application in that: Please see Figure 9 Optionally, the first active part 32 includes a first connecting part 321 and a first channel part 322.

[0075] The first connecting portion 321 is located between the first electrode 21 and the second electrode 50. The first connecting portion 321 is connected to one side of the main body portion 31.

[0076] The first channel portion 322 is located between the first electrode 21 and the second electrode 50. The first channel portion 322 is connected to the side of the first connection portion 321 away from the main body portion 31. The second insulating layer 60 covers the side of the first channel portion 322 away from the first connection portion 321. The first gate 70 overlaps with the side of the first channel portion 322.

[0077] When the first transistor T1 is turned on, the first channel portion 322 electrically connects the first electrode 21 and the second electrode 50, and the first electrode 21 and the second electrode 50 are respectively insulated from the first connection portion 321.

[0078] In the second embodiment of this application, the second electrode 50 is disposed on the first connecting portion 321 and the first channel portion 322. When the first transistor T1 is turned on, a voltage is applied to the first gate 70, and the first channel portion 322 forms a vertical conductive channel. The first connecting portion 321 is insulated from the first electrode 21 and the second electrode 50, respectively. The arrangement of the first connecting portion 321 ensures that the upper surface of the first channel portion 322 is in full contact with the second electrode 50, improving the contact effect between the first channel portion 322 and the second electrode 50 and reducing the contact resistance between the first channel portion 322 and the second electrode 50. In the first embodiment, the contact area between the first active portion 32 and the second electrode 50 is small, which poses a risk of insufficient contact and high contact resistance affecting the performance of the first transistor T1. The second embodiment can solve this problem.

[0079] Secondly, the first insulating layer 40 is fabricated using a photolithography process, resulting in an angle of less than 90 degrees between its side surface and bottom surface. Since the thickness of the first insulating layer 40 is between 4000 and 8000 angstroms, a step difference exists between its upper surface and the upper surface of the first active portion 32. This step difference can be understood as a height difference between their upper surfaces. Consequently, the second electrode 50, which continuously covers the upper surface of the first active portion 32, the side surface of the first insulating layer 40, and the upper surface of the first insulating layer 40, may not make sufficient contact at the junction of the side surface of the first insulating layer 40 and the upper surface of the first active portion 32. This phenomenon is caused by the angle and thickness of the first insulating layer 40 itself. If a conductive channel forms at the location where the second electrode 50 does not make sufficient contact with the first active portion 32, the switching speed of the first transistor T1 will be reduced. Therefore, in the second embodiment, the first connection portion 321, which cannot form a channel, is placed at the position where the contact is insufficient, and the first channel portion 322 is placed at the position where it can make sufficient contact with the second electrode 50, thereby ensuring the switching speed of the first transistor T1 and improving the refresh rate of the display panel.

[0080] Optionally, the angle between the side of the first insulating layer 40 and the side of the first insulating layer 40 near the substrate 10 is in the range of 60 degrees to 80 degrees.

[0081] The angle between the side of the first insulating layer 40 and the side of the first insulating layer 40 near the substrate 10 can be 60 degrees, 65 degrees, 70 degrees, 75 degrees, 80 degrees, etc.

[0082] Optionally, the width M2 of the first channel portion 322 in the direction D1 parallel to the substrate 10 is in the range of 5 nanometers to 30 nanometers.

[0083] In this embodiment, since the voltage of the first gate 70 only establishes an electric field on the side surface of the first semiconductor layer 30, when the voltage of the first gate 70 remains constant, the length of the width M2 of the first channel portion 322 in the direction D1 parallel to the substrate 10 depends on the thickness of the gate insulating layer. The thinner the gate insulating layer, the longer the width M2 of the first channel portion 322 in the direction D1 parallel to the substrate 10. The thicker the gate insulating layer, the shorter the width M2 of the first channel portion 322 in the direction D1 parallel to the substrate 10.

[0084] The width M2 of the first channel portion 322 in the direction D1 parallel to the substrate 10 can be 5 nm, 6 nm, 7 nm, 8 nm, 9 nm, 10 nm, 11 nm, 12 nm, 13 nm, 14 nm, 15 nm, 16 nm, 17 nm, 18 nm, 19 nm, 20 nm, 21 nm, 22 nm, 23 nm, 24 nm, 25 nm, 26 nm, 27 nm, 28 nm, 29 nm, 30 nm, etc. As the gate insulating layer becomes thinner, the width M2 of the first channel portion 322 in the direction D1 parallel to the substrate 10 becomes longer, the contact area between the second electrode 50 and the first channel portion 322 becomes larger, and the contact effect between the second electrode 50 and the first channel portion 322 becomes better. However, the gate insulating layer thickness cannot be too thin, otherwise there is a risk of gate insulating layer breakdown.

[0085] In the third embodiment of this application: To avoid redundancy, the third embodiment of this application only describes the differences from the first embodiment of this application.

[0086] The third embodiment of this application differs from the first embodiment in that: Please see Figure 10 Optionally, the first semiconductor layer 30 further includes a second active portion 33. The second active portion 33 is disposed on the side of the first electrode 21 away from the substrate 10. The two sides of the main body 31 are respectively connected to the first active portion 32 and the second active portion 33. A portion of the second electrode 50 is disposed on the side of the second active portion 33 away from the substrate 10.

[0087] The second insulating layer 60 also covers the side of the second active part 33.

[0088] The first gate 70 includes a first sub-gate 71 and a second sub-gate 72.

[0089] The first sub-gate 71 is disposed on the side of the second insulating layer 60 away from the first active portion 32 and overlaps with the side of the first active portion 32.

[0090] The second sub-gate 72 is disposed on the side of the second insulating layer 60 away from the second active portion 33 and overlaps with the side of the second active portion 33.

[0091] Please see Figure 11 In the third embodiment, the first transistor T1 has a double-sided channel structure. When the first transistor T1 is turned on, both the first active part 32 and the second active part 33 can form a vertical conductive channel, which further improves the switching speed of the first transistor T1 and increases the refresh rate of the display panel.

[0092] Please see Figure 10 Optionally, the width of the second active portion 33 in the direction D1 parallel to the substrate 10 is in the range of 5 nanometers to 30 nanometers.

[0093] In this embodiment, since the voltage of the second sub-gate 72 only establishes an electric field on the side surface of the first semiconductor layer 30, when the voltage of the second sub-gate 72 remains constant, the length of the width M3 of the second active portion 33 in the direction D1 parallel to the substrate 10 depends on the thickness of the gate insulating layer. The thinner the gate insulating layer, the longer the width M3 of the second active portion 33 in the direction D1 parallel to the substrate 10. The thicker the gate insulating layer, the shorter the width M3 of the second active portion 33 in the direction D1 parallel to the substrate 10.

[0094] The width M3 of the second active portion 33 in the direction D1 parallel to the substrate 10 can be 5 nm, 6 nm, 7 nm, 8 nm, 9 nm, 10 nm, 11 nm, 12 nm, 13 nm, 14 nm, 15 nm, 16 nm, 17 nm, 18 nm, 19 nm, 20 nm, 21 nm, 22 nm, 23 nm, 24 nm, 25 nm, 26 nm, 27 nm, 28 nm, 29 nm, 30 nm, etc. As the gate insulating layer becomes thinner, the width M3 of the second active portion 33 in the direction D1 parallel to the substrate 10 becomes longer, the contact area between the second electrode 50 and the second active portion 33 becomes larger, and the contact effect between the second electrode 50 and the second active portion 33 becomes better. However, the gate insulating layer cannot be too thin, otherwise there is a risk of gate insulating layer breakdown.

[0095] Optionally, the first sub-gate 71 is electrically connected to the second sub-gate 72.

[0096] In this embodiment, since the first active portion 32 and the second active portion 33 are both channels of the first transistor T1, the first sub-gate 71 and the second sub-gate 72 are electrically connected, which can ensure that the first active portion 32 and the second active portion 33 are turned on or off at the same time, thus ensuring the device performance of the first transistor T1, avoiding the adverse phenomenon of secondary turn-on of the device turn-on characteristics of the first transistor T1, and optimizing the circuit structure of the first transistor T1.

[0097] Optionally, the second electrode 50 continuously covers the side of the first active portion 32 away from the substrate 10, the side of the first insulating layer 40 away from the substrate 10, and the side of the second active portion 33 away from the substrate 10.

[0098] In this embodiment, the charge carriers between the first electrode 21 and the second electrode 50 can migrate through the first channel portion 322 and the second channel portion 332. The continuous coverage of the second electrode 50 ensures that the first channel portion 322 and the second channel portion 332 can be turned on or off simultaneously, realizing a dual-channel design, optimizing the circuit structure of the first transistor T1, improving the switching speed of the first transistor T1, and increasing the refresh rate of the display panel.

[0099] In the fourth embodiment of this application: To avoid redundancy, the fourth embodiment of this application only describes the differences from the third embodiment of this application.

[0100] The fourth embodiment of this application differs from the third embodiment in that: Please see Figure 12 Optionally, the second electrode 50 includes a first sub-electrode 51 and a second sub-electrode 52.

[0101] The first sub-electrode 51 is disposed on the side of the first active portion 32 away from the substrate 10.

[0102] The second sub-electrode 52 is disposed on the side of the second active portion 33 away from the substrate 10. The second sub-electrode 52 is disposed at a distance from the first sub-electrode 51, forming a notch G. The notch G exposes the first insulating layer 40.

[0103] In the fourth embodiment, the second electrode 50 is not continuously disposed, but rather a notch G is formed in the first insulating layer 40. The notch G reduces the formation of parasitic channels within the main body 31 for the following reasons: In the third embodiment, when the first transistor T1 is turned on, the second electrode 50 disposed on the upper surface of the first insulating layer 40 becomes an equivalent gate, inducing a charge on the surface of the main body 31 and forming a parasitic channel. When the thickness of the main body 31 is thin, the parasitic channel can conduct the first electrode 21 and the second electrode 50 on the upper and lower sides of the main body 31. However, the conduction effect of the parasitic channel is weaker than that of the first channel portion 322 and the second channel portion 332. During the use of the first transistor T1, the formation of the parasitic channel will affect the device turn-on characteristics of the first transistor T1, causing the device turn-on characteristics of the first transistor T1 to undergo secondary turn-on, making the device turn-on characteristics of the first transistor T1 uneven and affecting the stability of the device performance of the first transistor T1.

[0104] In the fourth embodiment, in order to solve this problem, a notch G is formed in the second electrode 50, thereby reducing the portion of the second electrode 50 located above the first insulating layer 40 and reducing the parasitic channel formed by the second electrode 50 in the main body 31. This reduces the influence of the parasitic channel on the device turn-on characteristics of the first transistor T1, making the device turn-on characteristics of the first transistor T1 smoother and improving the stability of the device performance of the first transistor T1.

[0105] Please see Figure 13 Optionally, the driving substrate 100 also includes a connection trace 53. In a plan view of the driving substrate 100, the connection trace 53 is located outside the first semiconductor layer 30, and the connection trace 53 is electrically connected to the first sub-electrode 51 and the second sub-electrode 52.

[0106] In this embodiment, in order to reduce the impact of parasitic channels on the device turn-on characteristics of the first transistor T1, the connection trace 53 is disposed on the outside of the first semiconductor layer 30, thereby reducing the charge induced by the connection trace 53 on the surface of the main body 31, making the device turn-on characteristics of the first transistor T1 smoother and improving the stability of the device performance of the first transistor T1.

[0107] In the fifth embodiment of this application: To avoid redundancy, the fifth embodiment of this application only describes the differences from the third embodiment of this application.

[0108] The fifth embodiment of this application differs from the third embodiment in that: Please see Figure 14 Optionally, the second active part 33 includes a second connecting part 331 and a second channel part 332.

[0109] The second connecting part 331 is located between the first electrode 21 and the second electrode 50. The second connecting part 331 is connected to the other side of the main body part 31.

[0110] The second channel portion 332 is located between the first electrode 21 and the second electrode 50. The second channel portion 332 is connected to the side of the second connection portion 331 away from the main body portion 31. The second insulating layer 60 covers the side of the second channel portion 332 away from the second connection portion 331. The second sub-gate 72 overlaps with the side of the second channel portion 332.

[0111] When the first transistor T1 is turned on, the second channel portion 332 electrically connects the first electrode 21 and the second electrode 50, and the first electrode 21 and the second electrode 50 are respectively insulated from the second connection portion 331.

[0112] In the fifth embodiment of this application, the second electrode 50 is further disposed on the second connection portion 331 and the second channel portion 332. When the first transistor T1 is turned on, a voltage is applied to the first gate 70, and the second channel portion 332 forms a vertical conductive channel. The second connection portion 331 is insulated from the first electrode 21 and the second electrode 50, respectively. The provision of the second connection portion 331 can ensure that the upper surface of the second channel portion 332 is in full contact with the second electrode 50, improve the contact effect between the second channel portion 332 and the second electrode 50, and reduce the contact resistance between the second channel portion 332 and the second electrode 50.

[0113] Secondly, the first insulating layer 40 is fabricated using a photolithography process, resulting in an angle of less than 90 degrees between its side surface and bottom surface. Since the thickness of the first insulating layer 40 is between 4000 and 8000 angstroms, a step difference exists between its upper surface and the upper surface of the second active portion 33. This step difference can be understood as a height difference between their upper surfaces. Consequently, the second electrode 50, which continuously covers the upper surface of the second active portion 33, the side surface of the first insulating layer 40, and the upper surface of the first insulating layer 40, may not make sufficient contact at the junction of the side surface of the first insulating layer 40 and the upper surface of the second active portion 33. This phenomenon is caused by the angle and thickness of the first insulating layer 40 itself. If a conductive channel forms at the location where the second electrode 50 does not make sufficient contact with the second active portion 33, the switching speed of the first transistor T1 will be reduced. Therefore, in the fifth embodiment, the second connection portion 331, which cannot form a channel, is placed at the position where the contact is insufficient, and the second channel portion 332 is placed at the position where it can make sufficient contact with the second electrode 50, thereby ensuring the switching speed of the first transistor T1 and improving the refresh rate of the display panel.

[0114] Optionally, the width M4 of the second channel portion 332 in the direction D1 parallel to the substrate 10 is in the range of 5 nanometers to 30 nanometers.

[0115] In this embodiment, since the voltage of the first gate 70 only establishes an electric field on the side surface of the first semiconductor layer 30, when the voltage of the first gate 70 remains constant, the length of the width M4 of the second channel portion 332 in the direction D1 parallel to the substrate 10 depends on the thickness of the gate insulating layer. The thinner the gate insulating layer, the longer the width M4 of the second channel portion 332 in the direction D1 parallel to the substrate 10. The thicker the gate insulating layer, the shorter the width M4 of the second channel portion 332 in the direction D1 parallel to the substrate 10.

[0116] The width M4 of the second channel portion 332 in the direction D1 parallel to the substrate 10 can be 5 nm, 6 nm, 7 nm, 8 nm, 9 nm, 10 nm, 11 nm, 12 nm, 13 nm, 14 nm, 15 nm, 16 nm, 17 nm, 18 nm, 19 nm, 20 nm, 21 nm, 22 nm, 23 nm, 24 nm, 25 nm, 26 nm, 27 nm, 28 nm, 29 nm, 30 nm, etc. As the gate insulating layer becomes thinner, the width M4 of the second channel portion 332 in the direction D1 parallel to the substrate 10 becomes longer, the contact area between the second electrode 50 and the second channel portion 332 becomes larger, and the contact effect between the second electrode 50 and the second channel portion 332 becomes better. However, the gate insulating layer thickness cannot be too thin, otherwise there is a risk of gate insulating layer breakdown.

[0117] In the sixth embodiment of this application: Please see Figure 15 The driving substrate 100 also includes a transition structure 81, a passivation layer 82, and a third electrode 83.

[0118] The adapter structure 81 is located on one side of the first transistor T1 and is electrically connected to one of the first electrode 21 and the second electrode 50.

[0119] The passivation layer 82 covers the first transistor T1 and the transition structure 81.

[0120] The third electrode 83 is disposed on the side of the passivation layer 82 away from the substrate 10 and is electrically connected to the transition structure 81.

[0121] The transition structure 81 includes at least one transition electrode 811. Each transition electrode 811 is disposed on the same layer as one of the first electrode 21, the second electrode 50, and the first gate 70. Different transition electrodes 811 are disposed on different layers.

[0122] In the sixth embodiment of this application, "same-layer arrangement" means that the transition electrode 811 and one of the first electrode 21, the second electrode 50, and the first gate 70 are formed simultaneously through the same mask, and the materials are the same. This can reduce the additional mask used to form the transition electrode 811 separately, reduce the production cost of the driving substrate 100, and improve the production efficiency of the driving substrate 100.

[0123] Please see Figure 15 In one embodiment, the transition structure 81 includes two transition electrodes 811. One transition electrode 811 is disposed on the same layer as the first gate 70, and the other transition electrode 811 is disposed on the same layer as the second electrode 50. The transition structure 81 is electrically connected to the second electrode 50. This embodiment can reduce the number of photomasks, reduce the production cost of the driving substrate 100, and improve the production efficiency of the driving substrate 100.

[0124] Please see Figure 16 In another embodiment, the transition structure 81 includes three transition electrodes 811. One transition electrode 811 is disposed on the same layer as the first gate 70, one transition electrode 811 is disposed on the same layer as the second electrode 50, and one transition electrode 811 is disposed on the same layer as the first electrode 21. The transition structure 81 is electrically connected to the first electrode 21. This embodiment can reduce the number of photomasks, reduce the production cost of the driving substrate 100, and improve the production efficiency of the driving substrate 100.

[0125] In the sixth embodiment of this application, the first transistor T1 can be used as a pixel driving transistor and disposed in the pixel setting area AA to drive sub-pixels. The first transistor T1 can also be disposed in a non-pixel setting area NA, and this is not limited here.

[0126] Optionally, the driving substrate 100 is applied to an organic light-emitting diode display panel, and the third electrode 83 is configured as the anode.

[0127] In this embodiment, after the third electrode 83 is configured as the anode, an organic light-emitting layer and a cathode layer can be disposed on the third electrode 83 to form an organic light-emitting device.

[0128] Optionally, the driving substrate 100 is applied to a micro LED display panel or a sub-millimeter LED display panel, and the third electrode 83 is configured as a bonding pad.

[0129] In this embodiment, after the third electrode 83 is configured as a bonding pad, a micro LED or a sub-millimeter LED can be bonded to the third electrode 83.

[0130] Optionally, the driving substrate 100 is applied to a liquid crystal display panel, and the third electrode 83 is configured as a pixel electrode.

[0131] In this embodiment, after the third electrode 83 is configured as a pixel electrode, since the liquid crystal display panel is a passive light-emitting display panel, there is no need to attach light-emitting devices to the third electrode 83. The pixel electrode can work with the common electrode to deflect the liquid crystal layer of the liquid crystal display panel, thereby controlling the light emitted by the backlight module to pass through the liquid crystal display panel.

[0132] In the seventh embodiment of this application: To avoid redundancy, the seventh embodiment of this application only describes the differences from the sixth embodiment of this application.

[0133] The seventh embodiment of this application differs from the sixth embodiment in that: Please see Figure 17 The driving substrate 100 includes a pixel setting area AA and a non-pixel setting area NA located on at least one side of the pixel setting area AA. A first transistor T1 is disposed in the non-pixel setting area NA. The driving substrate 100 also includes a second transistor T2 located in the pixel setting area AA. The second transistor T2 includes a fourth electrode 22, a second semiconductor layer 34, a second gate 54, and a fifth electrode 73.

[0134] The fourth electrode 22 is disposed on one side of the substrate 10. The fourth electrode 22 is disposed in the same layer as the first electrode 21.

[0135] The second semiconductor layer 34 is disposed on the side of the fourth electrode 22 away from the substrate 10. The second semiconductor layer 34 is disposed in the same layer as the first semiconductor layer 30. The second semiconductor layer 34 includes a third channel portion 341 and a third connection portion 342 and a fourth connection portion 343 connected to both sides of the third channel portion 341.

[0136] The first insulating layer 40 is also provided on the side of the third channel portion 341 away from the substrate 10.

[0137] The second gate 54 is disposed on the side of the first insulating layer 40 away from the third channel portion 341. The second gate 54 is disposed in the same layer as the second electrode 50.

[0138] The second insulating layer 60 also covers the second electrode 50, the second semiconductor layer 34, and the fourth electrode 22.

[0139] The fifth electrode 73 is disposed on the side of the second insulating layer 60 away from the substrate 10. The fifth electrode 73 is disposed in the same layer as the first gate electrode 70. The fifth electrode 73 includes a third sub-electrode 731 and a fourth sub-electrode 732. The third sub-electrode 731 is electrically connected to the third connection portion 342, and the fourth sub-electrode 732 is electrically connected to the fourth connection portion 343.

[0140] In the seventh embodiment of this application, the fourth electrode 22 and the first electrode 21 being disposed in the same layer means that the first electrode 21 of the first transistor T1 and the fourth electrode 22 of the second transistor T2 are formed simultaneously through the same photomask, and the materials of the two can be the same.

[0141] The co-location of the second semiconductor layer 34 and the first semiconductor layer 30 means that the first semiconductor layer 30 of the first transistor T1 and the second semiconductor layer 34 of the second transistor T2 are formed simultaneously using the same photomask. The materials of the two layers can be the same or different, depending on the specific requirements.

[0142] It should be understood that the portion of the first insulating layer 40 located in the first transistor T1 and the portion of the first insulating layer 40 located in the second transistor T2 can be formed simultaneously using the same photomask. The materials of the two can be the same, and they can be disconnected from each other.

[0143] The second gate 54 and the second electrode 50 being arranged in the same layer means that the second electrode 50 of the first transistor T1 and the second gate 54 of the second transistor T2 are formed simultaneously through the same photomask, and the materials of the two can be the same.

[0144] It should be understood that the portion of the second insulating layer 60 located in the first transistor T1 and the portion of the second insulating layer 60 located in the second transistor T2 can be formed simultaneously using the same photomask. The two layers are made of the same material and can be continuous.

[0145] The fifth electrode 73 and the first gate 70 are arranged in the same layer, which means that the first gate 70 of the first transistor T1 and the fifth electrode 73 of the second transistor T2 are formed simultaneously through the same mask, and the materials of the two can be the same.

[0146] This embodiment can reduce the additional mask used to form the second transistor T2 separately, reduce the production cost of the driving substrate 100, and improve the production efficiency of the driving substrate 100.

[0147] Since the first transistor T1 has a vertical channel and the second transistor T2 has a horizontal channel, the size of the first transistor T1 is smaller than that of the second transistor T2 under the same switching performance. Therefore, the first transistor T1 can be placed in the non-pixel setting area NA, thereby reducing the area of ​​the non-pixel setting area NA, realizing the narrow bezel design of the driving substrate 100, and improving the visual effect of the driving substrate 100.

[0148] Optionally, the driving substrate 100 further includes a passivation layer 82 and a sixth electrode 84.

[0149] Passivation layer 82 covers the first transistor T1 and the second transistor T2.

[0150] The sixth electrode 84 is disposed on the side of the passivation layer 82 away from the substrate 10. The sixth electrode 84 is electrically connected to one of the third sub-electrode 731 and the fourth sub-electrode 732.

[0151] Optionally, the driving substrate 100 is applied to an organic light-emitting diode display panel, and the sixth electrode 84 is configured as the anode.

[0152] In this embodiment, after the sixth electrode 84 is configured as the anode, an organic light-emitting layer and a cathode layer can be disposed on the sixth electrode 84 to form an organic light-emitting device.

[0153] Optionally, the driving substrate 100 is applied to a micro LED display panel or a sub-millimeter LED display panel, and the sixth electrode 84 is configured as a bonding pad.

[0154] In this embodiment, after the sixth electrode 84 is configured as a bonding pad, a micro LED or a sub-millimeter LED can be bonded to the sixth electrode 84.

[0155] Optionally, the driving substrate 100 is applied to a liquid crystal display panel, and the sixth electrode 84 is configured as a pixel electrode.

[0156] In this embodiment, after the sixth electrode 84 is configured as a pixel electrode, since the liquid crystal display panel is a passive light-emitting display panel, there is no need to attach a light-emitting device to the sixth electrode 84. The pixel electrode can work with the common electrode to deflect the liquid crystal layer of the liquid crystal display panel, thereby controlling the light emitted by the backlight module to pass through the liquid crystal display panel.

[0157] In the description of this application, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more features. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0158] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.

[0159] The embodiments, implementation methods, and related technical features of this application can be combined and substituted for each other without conflict.

[0160] The above are merely preferred embodiments of this application and are not intended to limit this application in any way. Any simple modifications, equivalent changes, and alterations made to the above embodiments based on the technical essence of this application without departing from the scope of the technical solution of this application shall still fall within the scope of the technical solution of this application.

Claims

1. A driving substrate, characterized in that, Includes a substrate and a first transistor disposed on one side of the substrate, the first transistor comprising: The first electrode is disposed on one side of the substrate; A first semiconductor layer is disposed on the side of the first electrode away from the substrate, and includes a main body portion and a first active portion connected to one side of the main body portion; A first insulating layer is disposed on the side of the main body away from the substrate; A second electrode, at least a portion of which is disposed on the side of the first active portion away from the substrate; A second insulating layer covers at least the side surface of the first electrode, the side surface of the first active portion, and the second electrode; and The first gate is disposed on the side of the second insulating layer away from the first active portion and overlaps with the side of the first active portion.

2. The driving substrate as described in claim 1, characterized in that, The width of the first active portion in the direction parallel to the substrate is in the range of 5 nanometers to 30 nanometers.

3. The driving substrate as described in claim 1, characterized in that, The first active part includes: A first connecting portion is located between the first electrode and the second electrode, and the first connecting portion is connected to one side of the main body; and A first channel portion is located between the first electrode and the second electrode. The first channel portion is connected to the side of the first connection portion away from the main body portion. The second insulating layer covers the side of the first channel portion away from the first connection portion. The first gate overlaps with the side of the first channel portion. When the first transistor is turned on, the first channel portion electrically connects the first electrode and the second electrode, and the first electrode and the second electrode are respectively insulated from the first connection portion.

4. The driving substrate as described in claim 3, characterized in that, The width of the first channel portion in the direction parallel to the substrate is in the range of 5 nanometers to 30 nanometers.

5. The driving substrate as described in claim 1, characterized in that, The first semiconductor layer further includes a second active portion, which is disposed on the side of the first electrode away from the substrate. The two sides of the main body are respectively connected to the first active portion and the second active portion. A portion of the second electrode is disposed on the side of the second active portion away from the substrate. The second insulating layer also covers the side of the second active part; The first gate includes a first sub-gate and a second sub-gate; The first sub-gate is disposed on the side of the second insulating layer away from the first active portion and overlaps with the side of the first active portion; The second sub-gate is disposed on the side of the second insulating layer away from the second active portion and overlaps with the side of the second active portion.

6. The driving substrate as described in claim 5, characterized in that, The width of the second active portion in the direction parallel to the substrate is in the range of 5 nanometers to 30 nanometers.

7. The driving substrate as described in claim 5, characterized in that, The second active part includes: A second connecting portion is located between the first electrode and the second electrode, and the second connecting portion is connected to the other side of the main body; and The second channel portion is located between the first electrode and the second electrode. The second channel portion is connected to the side of the second connection portion away from the main body portion. The second insulating layer covers the side of the second channel portion away from the second connection portion. The second sub-gate overlaps with the side of the second channel portion. When the first transistor is turned on, the second channel portion electrically connects the first electrode and the second electrode, and the first electrode and the second electrode are respectively insulated from the second connection portion.

8. The driving substrate as described in claim 5, characterized in that, The first sub-gate is electrically connected to the second sub-gate.

9. The driving substrate as described in claim 8, characterized in that, The second electrode continuously covers the side of the first active portion away from the substrate, the side of the first insulating layer away from the substrate, and the side of the second active portion away from the substrate.

10. The driving substrate as claimed in claim 8, characterized in that, The second electrode includes: The first sub-electrode is disposed on the side of the first active portion away from the substrate; and The second sub-electrode is disposed on the side of the second active portion away from the substrate. The second sub-electrode is spaced apart from the first sub-electrode to form a gap, and the gap exposes the first insulating layer.

11. The driving substrate as claimed in claim 10, characterized in that, The driving substrate also includes connection traces. In a plan view of the driving substrate, the connection traces are located outside the first semiconductor layer and electrically connect the first sub-electrode and the second sub-electrode.

12. The driving substrate as claimed in claim 1, characterized in that, In a plan view of the driving substrate, the first active portion extends around the periphery of the main body portion, and the orthographic projection of the first gate on the substrate extends around the periphery of the orthographic projection of the first semiconductor layer on the substrate.

13. The driving substrate as described in any one of claims 1-12, characterized in that, The thickness of the first insulating layer is in the range of 4000 angstroms to 8000 angstroms; The thickness of the first semiconductor layer is in the range of 5 nanometers to 500 nanometers.

14. The driving substrate as described in any one of claims 1-12, characterized in that, The driving substrate further includes: The adapter structure is located on one side of the first transistor and is electrically connected to one of the first electrode and the second electrode. A passivation layer covers the first transistor and the transition structure; and The third electrode is disposed on the side of the passivation layer away from the substrate and is electrically connected to the transition structure; The switching structure includes at least one switching electrode, each switching electrode being disposed on the same layer as one of the first electrode, the second electrode, and the first gate, and different switching electrodes being disposed on different layers.

15. The driving substrate as described in any one of claims 1-12, characterized in that, The driving substrate includes a pixel setting area and a non-pixel setting area located on at least one side of the pixel setting area, and the first transistor is disposed in the non-pixel setting area; The driving substrate further includes a second transistor located in the pixel setting area, the second transistor comprising: A fourth electrode is disposed on one side of the substrate, and the fourth electrode is disposed in the same layer as the first electrode; The second semiconductor layer is disposed on the side of the fourth electrode away from the substrate. The second semiconductor layer is disposed in the same layer as the first semiconductor layer. The second semiconductor layer includes a third channel portion and a third connection portion and a fourth connection portion connected to both sides of the third channel portion. The first insulating layer is also disposed on the side of the third channel portion away from the substrate; The second gate is disposed on the side of the first insulating layer away from the third channel portion, and the second gate is disposed in the same layer as the second electrode; The second insulating layer also covers the second electrode, the second semiconductor layer, and the fourth electrode; The fifth electrode is disposed on the side of the second insulating layer away from the substrate. The fifth electrode is disposed on the same layer as the first gate electrode. The fifth electrode includes a third sub-electrode and a fourth sub-electrode. The third sub-electrode is electrically connected to the third connection portion, and the fourth sub-electrode is electrically connected to the fourth connection portion. The driving substrate further includes: A passivation layer covers the first transistor and the second transistor; The sixth electrode is disposed on the side of the passivation layer away from the substrate, and the sixth electrode is electrically connected to one of the third sub-electrode and the fourth sub-electrode.

16. A display panel, characterized in that, Includes the driving substrate as described in any one of claims 1-15.

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