A tgv glass-based reconfigurable integrated passive device with parasitic parameter balancing structure and a preparation method thereof

Abstract

The application discloses a TGV glass-based reconfigurable integrated passive device with a parasitic parameter balancing structure and a preparation method thereof, and is applied to the technical field of glass-based three-dimensional semiconductor integrated passive devices, and the technical solution points of the application are as follows: the device comprises a glass substrate, an integrated passive device layer, a thin film switch layer and a via hole interconnection structure penetrating through the glass substrate; the integrated passive device layer comprises a common passive element and at least two passive branches, each branch is connected with a corresponding thin film switch device through a radio frequency via hole; the number of thin film switch devices, the number of radio frequency via holes and the number of RDL redistribution layer interconversion times of each passive branch are the same, and the non-functional connection sections outside the passive units in each passive branch are equal in length or the length difference is not more than 10%; and the device has the technical effect that the connection state of the passive device is changed, and the parasitic parameter consistency under different working states is improved.

Description

Technical Field

[0001] This invention relates to the field of glass-based three-dimensional semiconductor integrated passive device technology, and in particular to a TGV glass-based reconfigurable integrated passive device with a parasitic parameter balance structure and its fabrication method. Background Technology

[0002] As wireless communication systems evolve towards multi-band, multi-standard, and miniaturized designs, RF front-ends need to integrate more filtering, resonant, and impedance matching functions within limited package space. Integrated passive devices (IPDs) can integrate passive units such as capacitors, inductors, and resistors on the same substrate, significantly shortening signal transmission paths and reducing device size, leading to wider application development. However, in existing glass-based IPDs, the capacitance, inductance, and connection topology of conventional IPDs are fixed after manufacturing. This often necessitates multiple IPD chips arranged in parallel or additional RF switches incorporated into the package to cover multiple operating frequency bands, resulting in increased device quantity, larger package area, and increased interconnect parasitic parameters.

[0003] Currently, Chinese invention patent CN115241163A discloses an adjustable filter and its fabrication method. This prior art uses switching transistors to change the connection state of the resonant unit. However, when the thin-film switching devices and glass-based passive devices are compactly arranged in three dimensions, the on-resistance and off-resistance of the thin-film switching devices, the parasitic inductance of the TGV and the parasitic capacitance of the pads, and the interlayer transition parasitic parameters of the RDL redistribution layer all affect the actual resonant characteristics. When the number of thin-film switching devices, the number of TGVs, the number of RDL interlayer transitions, or the length of non-functional connection segments traversed by different switching states are inconsistent, the actual center frequency, insertion loss, and quality factor of each operating position will be affected by different additional parasitic parameters, causing the actual response to deviate from the ideal design result. Therefore, it is necessary to improve the vertical interconnection path and redistribution path of different passive branches to improve the consistency of parasitic parameters in each operating state. Summary of the Invention

[0004] The first objective of this invention is to provide a TGV glass-based reconfigurable integrated passive device with a parasitic parameter balancing structure. Its advantage is that it can improve the consistency of parasitic parameters under different operating conditions while changing the connection state of the passive device.

[0005] The above-mentioned technical objective of this invention is achieved through the following technical solution: a TGV glass-based reconfigurable integrated passive device with a parasitic parameter balancing structure, comprising: A glass substrate, including a first surface side and a second surface side disposed opposite to each other; An integrated passive device layer is disposed on the first surface side of the glass substrate, including a radio frequency input terminal, a radio frequency output terminal, a common node, a common passive unit, at least two passive branches, and an RDL redistribution layer for realizing electrical connections. The common passive unit is connected between the radio frequency input terminal and the common node, and the passive branches are respectively connected between the common node and the radio frequency output terminal. Each passive branch includes at least one branch passive unit. A thin-film switching layer is disposed on the second surface side of the glass substrate. The thin-film switching layer includes switching units corresponding to the passive branches and control lines connected to the switching units. The switching unit includes at least one thin-film switching device, and the thin-film switching device has a control electrode, a first electrode, and a second electrode. The through-hole interconnect structure extends through the glass substrate and includes radio frequency (RF) vias and control vias. Each passive branch is provided with at least one pair of RF vias. The first and second electrodes of the thin-film switch are connected in series in the corresponding passive branch through the corresponding pair of RF vias. The control electrode of the thin-film switch is electrically connected to the control via through the control line. Each passive branch has the same number of thin-film switching devices in its corresponding switching unit, and each passive branch has the same number of RF vias and the same number of RDL interlayer transitions in its RF signal path. Furthermore, the equivalent connection lengths of the non-functional connection segments located outside the passive units of each passive branch are the same or differ by no more than 10%, so that when different passive branches are selected, the switching parasitic parameters, vertical interconnect parasitic parameters, and interlayer transition parasitic parameters in the RF signal path are balanced.

[0006] The present invention is further configured such that: the common passive unit and the branch passive unit are one or more of the following: capacitor unit, inductor unit, and resistor unit; When the common passive unit is a capacitor unit, each branch passive unit includes an inductor unit with different inductance values ​​and / or a resistor unit with different resistance values; or, when the common passive unit is an inductor unit, each branch passive unit includes a capacitor unit with different capacitance values ​​and / or a resistor unit with different resistance values. When the branch passive unit includes multiple passive elements, the multiple passive elements are connected in series, in parallel, or in a series-parallel combination.

[0007] The present invention is further configured such that: the integrated passive device includes a MIM capacitor composed of a first electrode, an insulating dielectric layer and a second electrode stacked in sequence, wherein the pattern boundary of the second electrode is located within the pattern boundary of the insulating dielectric layer, so as to form an edge insulation margin on the outer periphery of the second electrode.

[0008] The present invention is further configured such that: each pair of radio frequency vias corresponding to the passive branch has the same aperture, the same internal conductive layer structure, and the same glass penetration length; The rewiring structures corresponding to different passive branches have the same number of wiring layers and the same number of interlayer conductive vias, and at least two of the passive branches are arranged in a mirror image with respect to a preset symmetry plane passing through the common node.

[0009] The present invention is further configured such that when at least two of the passive branches cannot be arranged in a completely mirrored manner, a compensation connection segment that does not participate in the formation of the main passive parameters of the branch is set in the passive branch with the shorter connection path, and / or the same number of dummy interlayer transformation structures as the other passive branch are set, so that the number of RDL level transformations, the number of interlayer conductive vias and the equivalent connection length of the non-functional connection segments of the two passive branches are the same or differ by no more than 10%.

[0010] The present invention is further configured such that: the thin-film switching device is a bottom-gate thin-film transistor or a top-gate thin-film transistor, the thin-film transistor includes a gate, a gate insulating layer, a semiconductor active layer, a source / drain electrode layer and a passivation layer arranged in sequence, the material of the semiconductor active layer is selected from one of hydrogenated amorphous silicon, low-temperature polycrystalline silicon and oxide semiconductor; the integrated passive device layer also includes a bump terminal that is electrically connected to the RF input terminal, the RF output terminal and the control via respectively.

[0011] The second objective of this invention is to provide a method for fabricating a TGV glass-based reconfigurable integrated passive device with a parasitic parameter balancing structure. Its advantage is that it can achieve the goal of changing the connection state of the passive device while taking into account the requirements of radio frequency isolation and parasitic parameter consistency.

[0012] The above-mentioned technical objective of this invention is achieved through the following technical solution: a method for fabricating a TGV glass-based reconfigurable integrated passive device with a parasitic parameter balancing structure, used to manufacture a TGV glass-based reconfigurable integrated passive device with a parasitic parameter balancing structure as described in any of the above technical solutions; comprising: S1. Provide a glass substrate, and form radio frequency vias and control vias through the first surface side and the second surface side respectively on the glass substrate based on a preset interconnect pattern, and form a conductive interconnect structure inside each via; S2. A thin-film switch layer is formed on the second surface side of the glass substrate to form at least two switch units and their control lines. The first connection terminal and the second connection terminal of each switch unit are respectively connected to the lower end of the corresponding radio frequency via. Each switch unit includes at least one thin-film switch device with a control electrode, a first electrode and a second electrode. The control electrode of each thin-film switch device is electrically connected to the corresponding control via through the control line. S3. An integrated passive device layer is formed on the first surface side. The integrated passive device layer includes a radio frequency input terminal, a radio frequency output terminal, a common node, a common passive unit connected between the radio frequency input terminal and the common node, and at least two passive branches respectively connected between the common node and the radio frequency output terminal. S4. Connect the passive unit of each passive branch in series with the corresponding switching unit through a pair of corresponding radio frequency vias, and ensure that the number of thin film switching devices, the number of radio frequency vias and the number of RDL redistribution layer transitions contained in all passive branches are the same, and make the non-functional connection segments outside the passive unit in each passive branch equal in length or with a length difference of no more than 10%.

[0013] The present invention is further configured such that, in S1, the method for preparing the conductive interconnect structure is as follows: S1.1 The glass substrate is subjected to laser modification treatment to form a modified area at the preset through-hole position; S1.2. Selective wet etching is performed on the modified area using a fluorine-containing etching solution or an alkaline etching solution to form a through-hole penetrating the glass substrate. S1.3 Deposit a barrier layer and a conductive seed layer on the hole wall, the first surface side, and the second surface side of the through hole; S1.4. Electrochemically plate copper onto the via based on the conductive seed layer to form a copper interconnect filling the via; S1.5. Perform chemical mechanical polishing on the first and second surface sides of the glass substrate to make the end face of the copper interconnect flush with the corresponding glass surface.

[0014] The present invention is further configured as follows: In S3, the method for fabricating the integrated passive device layer is as follows: S3.1 Deposit and pattern a first metal layer on the first surface side to form the first electrode of the MIM capacitor; S3.2. An insulating dielectric layer is formed on the first electrode, and a second electrode is formed on the insulating dielectric layer to form a MIM capacitor formed by sequentially stacking the first electrode, the insulating dielectric layer and the second electrode. S3.3 Form a photosensitive polyimide insulating layer on the MIM capacitor, and pattern the photosensitive polyimide insulating layer to form interlayer vias that expose the electrical connection area; S3.4 At least two RDL redistribution layers and a polyimide insulating layer located between adjacent RDL redistribution layers are sequentially formed using a semi-additive method to form the common passive unit, the branch passive unit and their electrical connection lines.

[0015] The present invention is further configured as follows: After forming the conductive interconnect structure, at least three non-collinear conductive interconnect structure end faces are selected as double-sided alignment marks. When forming the thin-film switching layer, the position of each thin-film switching device relative to the corresponding radio frequency via is determined according to the double-sided alignment mark; When forming the integrated passive device layer, the position of each passive branch is determined according to the same set of double-sided alignment marks, so that the corresponding branch passive units, radio frequency vias and thin-film switching devices are aligned in the thickness direction of the glass substrate.

[0016] In summary, the present invention has the following beneficial effects: 1. This invention achieves vertical interconnection by placing the integrated passive device layer and the thin-film switch layer on both sides of the glass substrate and using TGV to transfer the switch area that originally needed to be arranged side by side to the back of the glass substrate, reducing the planar occupation of the passive device area on the front side, and enabling the same glass substrate IPD to form two or more discrete working positions. 2. Set different passive branches to use the same number of thin-film switching devices, RF TGV and RDL redistribution layers to ensure high consistency of switch on-resistance, TGV parasitic inductance, pad parasitic capacitance and interlayer interconnect parasitic parameters in each working position, and reduce the frequency offset and insertion loss differences caused by branch path asymmetry. 3. By arranging at least two passive branches in a mirrored manner, or by setting up a compensation connection segment and a virtual interlayer conversion structure when a complete mirroring is not possible, the parasitic parameter differences of non-functional connection paths are further reduced, making the actual RF response of different operating levels closer to the preset value. Attached Figure Description

[0017] Figure 1 This is a schematic cross-sectional view of the TGV glass-based reconfigurable integrated passive device in Example 1, where the common passive unit is a MIM capacitor and the first passive branch and the second passive branch are inductor units or resistor units. Figure 2 This is a cross-sectional schematic diagram of the TGV glass-based reconfigurable integrated passive device in Example 2, where the common passive unit is an inductor unit or a resistor unit, and the first passive branch and the second passive branch are MIM capacitor units. Figure 3 This is a cross-sectional view of the common passive unit in Example 3, where the first passive branch and the second passive branch are selectively connected via the first membrane switch and the second membrane switch, respectively. Figure 4 This is a cross-sectional structural diagram of the common inductor unit or common resistor unit combined with different capacitor branches to form multiple operating states in Example 4. Figure 5 This is a schematic diagram of the fabrication process of the thin-film switching layer in this invention; Figure 6 This is a schematic diagram of the fabrication process of the glass substrate, through-hole interconnect structure, and MIM capacitor in Example 5; Figure 7 This is a schematic diagram of the fabrication process of the RDL redistribution layer and the integrated passive device layer in Example 5.

[0018] Reference numerals: 1. Glass substrate; 2. Integrated passive device layer; 21. RF input terminal; 22. RF output terminal; 23. Common node; 24. Common passive unit; 25. First passive branch; 251. First branch passive unit; 26. Second passive branch; 261. Second branch passive unit; 27. RDL redistribution layer; 28. Bump terminal; 3. Thin-film switch layer; 31. First thin-film switch device; 32. Second thin-film switch device; 33. Control circuit; 4. Through-hole interconnect structure; 41. RF through-hole; 42. Control through-hole; 6. MIM capacitor; 61. First electrode; 62. Dielectric layer; 63. Second electrode. Detailed Implementation

[0019] The present invention will be further described in detail below with reference to the accompanying drawings.

[0020] The first surface side and the second surface side referred to in this invention are only used to distinguish the two opposing surfaces of the glass substrate 1, and do not limit the up and down direction when the device is in use. For ease of understanding, the first surface side will be referred to as the passive device side and the second surface side as the thin-film switch side.

[0021] The same number of RDL redistribution layers 27 referred to in this invention means that the number of metal layer transitions traversed by the RF signal from the common node 23 to the RF output terminal 22 is the same under different effective operating states, without requiring that each metal pattern be exactly the same.

[0022] Thin-film switching devices are not ideal switches. In the on-state, they primarily exhibit on-resistance Ron and parasitic inductance of the source-drain connection structure; in the off-state, they primarily exhibit turn-off capacitance Coff and leakage resistance. TGV also introduces parasitic inductance, via wall resistance, and pad parasitic capacitance. Therefore, the actual impedance when a branch is selected can be approximately expressed as the sum of the branch's passive unit impedance, the thin-film switching device's on-resistance, the RF TGV impedance, and the RDL impedance. By ensuring that the number of switches, RF TGVs, and interlayer transitions in different branches are consistent, the aforementioned additional impedances can be made to correspond substantially across different branches.

[0023] When the common capacitor C0 and the gate inductor Li form an LC resonant network, its theoretical resonant frequency can be estimated by the following formula, neglecting losses and higher-order parasitic parameters: f i =1 / [2π(C0·Li)(1 / 2)] When the first inductor L1 and the second inductor L2 are connected to the same two nodes and are simultaneously selected, if the mutual inductance between them can be ignored, then the equivalent inductance is: L eq =L1·L2 / (L1+L2) When the first capacitor C1 and the second capacitor C2 are connected to the same two nodes, their parallel equivalent capacitance is C. eq =C1+C2; When the first capacitor C1 and the second capacitor C2 are connected end to end, their series equivalent capacitance is C. eq =C1·C2 / (C1+C2). The specific series or parallel connection should be determined by the RDL node connection method, not just by the spatial position of the two capacitors.

[0024] Example 1: refer to Figure 1 A TGV glass-based reconfigurable integrated passive device with a parasitic parameter balance structure includes a glass substrate 1, an integrated passive device layer 2, a thin-film switch layer 3, and a through-hole interconnect structure 4. The glass substrate 1 has a first surface side and a second surface side arranged opposite to each other. Multiple sets of TGV through holes are formed in the glass substrate 1, and copper is filled in the TGV through holes to form the through-hole interconnect structure 4. In this embodiment, the glass substrate 11 is BF33 borosilicate glass, but other borosilicate glass, alkali-free glass, fused silica, or glass materials that meet the requirements of low dielectric loss and TGV processing can also be used.

[0025] The TGV through-holes in the via interconnect structure 4 include RF through-holes 41 for carrying RF signals between the common node 23, the branch passive unit, and the thin-film switching device, and control through-holes 42 for inputting control voltage to the control electrode of the thin-film switching device. In this embodiment, the opening diameter of the first surface of each TGV through-hole is 50-100 μm, preferably 70 μm; the center-to-center distance between adjacent TGVs is 200-300 μm, preferably 250 μm. A titanium barrier / adhesion layer and a copper seed layer are provided on the inner wall of the TGV through-hole to form an electroplated copper interconnect inside the TGV through-hole.

[0026] An integrated passive device layer 2 is disposed on the first surface side, including an RF input terminal 21, an RF output terminal 22, a common node 233, a common passive unit 24, a first passive branch, a second passive branch, a multilayer RDL redistribution layer 27, and a bump terminal 28. In this embodiment, the common passive unit 24 is a common MIM capacitor 6C0, the first branch passive unit 251 is a planar spiral inductor L1, and the second branch passive unit 261 is a planar spiral inductor L2. Specifically, the common MIM capacitor 6C0 includes a first electrode 61, a dielectric layer 62, and a second electrode 63. The first electrode 61 is formed on one side of the first surface, the dielectric layer 62 covers the first electrode 61, and the second electrode 63 is formed on the dielectric layer 62. The dielectric layer 62 can be made of SiNx, SiOx, Al2O3, or a stack thereof. The electrode materials of the first electrode 61 and the second electrode 63 can be Cu, Al, Mo, Ti, TiN, or a stack thereof. In this embodiment, a SiNx with a thickness of 100 nm is used. The pattern boundary of the second electrode 63 is located within the pattern boundary of the dielectric layer 62, with a single-sided indentation of 3–7 μm, preferably 5 μm, to reduce the risk of short circuits at the electrode edge. The first inductor L1 and the second inductor L2 are formed using RDL copper wires. The thickness of the copper wires is 5-20 μm, the line width is 10-50 μm, the line spacing is 10-40 μm, and the number of turns is 1.5-5.5. By changing the outer diameter, inner diameter, number of turns, line width, and line spacing of the copper wires, L1 and L2 can have different inductance values. The RDLs are insulated by a photosensitive polyimide layer, and an interlayer conductive via is formed in the photosensitive polyimide layer.

[0027] The thin-film switching layer 3 is disposed on the second surface side and includes a first thin-film switching device 31, a second thin-film switching device 32, a control circuit 33, and a passivation protection structure. The first thin-film switching device 31 corresponds to the first passive branch 25, and the second thin-film switching device 32 corresponds to the second passive branch 26. In this embodiment, the thin-film switching device adopts a bottom-gate type multi-finger oxide thin-film transistor. The gate adopts a Mo / Al / Mo stack, the gate insulating layer adopts SiNx with a thickness of 150-350nm, the semiconductor active layer adopts IGZO with a thickness of 20-60nm, the source and drain electrodes adopt a Mo / Al / Mo stack, and the passivation layer adopts a composite layer of SiNx and organic resin. To reduce the on-resistance, the source and drain electrodes are formed with multiple staggered finger electrodes respectively. The length of a single finger channel is 2-8μm, and the total channel width is selected in the range of 0.5-10mm according to the target on-resistance. The specific size of the thin-film transistor is determined by the target frequency band, the allowable insertion loss, and the driving voltage. Specifically, the first passive branch 25 is provided with a first pair of RF vias 41, the first electrode of the first thin-film switch 31 is connected to one end of the first inductor L1 through one of the RF vias 41, and the second electrode is connected to the RF output terminal 22 through the other RF via 41; the second passive branch 26 is provided with a second pair of RF vias 41, and the second thin-film switch 32 is connected in series between the second inductor L2 and the RF output terminal 22 in the same manner; the control electrodes of the first thin-film switch 31 and the second thin-film switch 32 are respectively connected to the corresponding control vias 42 through the control lines 33; The first pair of RF vias 41 and the second pair of RF vias 41 have the same aperture and the same pad size; the first thin-film switch device 31 and the second thin-film switch device 32 have the same channel structure and the same index; the first inductor L1 branch and the second inductor L2 branch both cross two RF vias 41 and the same number of RDL interlayer conductive vias from the common node 23 to the RF output terminal 22; the total length difference of the non-inductor connection lines of the two branches is no greater than 5%; When in the first working state, a turn-on control voltage is applied to the first thin-film switch device 31 and a cut-off control voltage is applied to the second thin-film switch device 32. The radio frequency signal passes from the radio frequency input terminal 21 through the common capacitor C0, the common node 23, the first inductor L1, the first pair of radio frequency vias 41 and the first thin-film switch device 31 to reach the radio frequency output terminal 22. At this time, the first working frequency is mainly determined by C0 and L1. When in the second operating state, the first thin-film switch 31 is off, and the second thin-film switch 32 is on. The radio frequency signal passes through the common capacitor C0, the second inductor L2, the second pair of radio frequency vias 41, and the second thin-film switch 32. At this time, the second operating frequency is mainly determined by C0 and L2. When in the third working state, both the first thin-film switch device 31 and the second thin-film switch device 32 are turned on. When the two ends of L1 and L2 are connected to the common node 23 and the RF output terminal 22 respectively, L1 and L2 form a parallel combination, and the third working frequency is formed by C0 and the parallel equivalent inductance. When in isolation, both the first membrane switch 31 and the second membrane switch 32 are turned off, and there is no main RF branch connected between the common node 23 and the RF output terminal 22. The device is in isolation or standby state.

[0028] Example 2: refer to Figure 2 Compared to Embodiment 1, the difference in this embodiment is that the common passive unit 24 is a common inductor L0, the first branch passive unit 251 is a first MIM capacitor 6C1, and the second branch passive unit 261 is a second MIM capacitor 6C2. The first MIM capacitor 6C1 is connected in series between the common node 23 and the RF output terminal 22 through the first pair of RF vias 41 and the first thin film switch device 31; the second MIM capacitor 6C2 is connected in series between the common node 23 and the RF output terminal 22 through the second pair of RF vias 41 and the second thin film switch device 32. When the first membrane switch 31 is turned on and the second membrane switch 32 is turned off, L0 and C1 form a first working state; when the first membrane switch 31 is turned off and the second membrane switch 32 is turned on, L0 and C2 form a second working state; when both membrane switches are turned on, if C1 and C2 are connected between the same two nodes, then C1 and C2 are connected in parallel, and the equivalent capacitance is C1+C2; if a series capacitor is required, C1 and C2 should be connected end to end through another RDL node, and the equivalent series capacitance is C1·C2 / (C1+C2), thus avoiding the problem of judging the series and parallel relationship based solely on the spatial position of the devices. The actual combination relationship of the capacitors is determined by the electrical connection relationship between the first electrode 61, the second electrode 63, and the RDL node.

[0029] Example 3: refer to Figure 3 Based on Embodiments 1 and 2, at least one passive branch can be replaced with a resistor unit. The resistor unit can be formed of nickel-chromium, tantalum nitride or other thin film resistor materials, or a predetermined resistance value can be obtained by extending the RDL metal trace and reducing its cross-sectional area.

[0030] When a resistor branch is selected, the damping, bandwidth, or port impedance of the resonant network can be changed. For example, in a resonant network formed by a common capacitor and an inductor, by connecting resistor branches in parallel or series to corresponding nodes, the resonant peak value and bandwidth can be adjusted in stages. The resistor branch still uses the same number of thin-film switching devices and RF vias 41 as other branches to maintain the correspondence between the switching and vertical interconnect parasitic parameters.

[0031] Example 4: refer to Figure 4 The first passive branch 25 and the second passive branch 26 are symmetrically arranged around the location of the common node 23. By setting the two branches as mirror images of the preset symmetry plane passing through the common node 23, the planar path lengths from the two sets of RF vias 41 to the common node 23 are basically the same, and the connection path lengths from the two sets of RF vias 41 to the second surface side of the corresponding thin-film switching device are basically the same. The length difference between the two sets of branches on the corresponding paths is controlled within 10%, thereby minimizing the parasitic parameter differences between the two branches on the connection path and enabling different branches to have a closer RF transmission environment when selected. If the passive unit 251 of the first branch and the passive unit 261 of the second branch need to adopt different body sizes due to different target inductance, capacitance or resistance values, the part bearing the parameter difference can be concentrated on the passive unit body, while the connection part in the branch that does not directly determine the target parameters is designed to be of equal or approximately equal length, thereby ensuring that the two branches are as consistent as possible in terms of connection parasitic effects.

[0032] Example 5: refer to Figures 5 to 7 A method for fabricating a TGV glass-based reconfigurable integrated passive device with a parasitic parameter balance structure, used to manufacture a TGV glass-based reconfigurable integrated passive device with a parasitic parameter balance structure as shown in any of Examples 1-4 above; comprising: S1. A glass substrate 1 is provided with plate-level or wafer-level glass, and radio frequency vias 41 and control vias 42 are formed on the glass substrate 1 based on a preset interconnect pattern, respectively penetrating the first surface side and the second surface side, and conductive interconnect structures are formed inside each via. S1.1 The glass substrate 1 is subjected to laser modification treatment to form a modified area at the preset through hole position, and the center distance between adjacent laser modification trajectories is greater than 100μm, preferably 200-300μm; S1.2. Selective wet etching is performed on the modified area using a fluorine-containing etching solution or an alkaline NaOH etching solution to form a through hole penetrating the glass substrate 1. The opening size of the first surface side of the through hole can be 50 to 100 μm. S1.3 After cleaning and activating the glass substrate 1, a barrier / adhesion layer and a conductive seed layer are deposited on the hole wall of the through hole and on the first surface side and the second surface side. The barrier / adhesion layer can be Ti, TiW, Cr or a combination thereof, and the conductive seed layer can be Cu. S1.4 Electrochemical copper plating is performed on the via based on the conductive seed layer, so that copper grows from the hole wall into the hole and fills the via to form a copper interconnect filled in the via. S1.5 Perform chemical mechanical polishing (CMP) on the first and second surface sides of the glass substrate 1 to make the end face of the copper interconnect flush with the corresponding glass surface; S2. A thin-film switching layer 3 is fabricated on the second surface side of the glass substrate 1. Gate metal is deposited and patterned on the second surface side to form the gates and control lines 33 of the first thin-film switching device 31 and the second thin-film switching device 32. Subsequently, a gate insulating layer is deposited sequentially to form a semiconductor active layer and pattern it. Then, a source and drain electrode layer is formed so that the source and drain of each thin-film switching device are connected to the lower end of the corresponding radio frequency via 41 through contact openings. This connects the first connection terminal and the second connection terminal of each switching unit to the lower end of the corresponding radio frequency via 41. Subsequently, a passivation layer is formed, and contact windows required for the control terminal, ground terminal or test terminal are opened on the passivation layer. The control electrode of each thin-film switching device is electrically connected to the corresponding control via 42 through the control line 33. The fabrication temperature of the aforementioned thin-film transistors must be compatible with the glass substrate 1 and the formed TGV structure. When amorphous silicon or IGZO is used as the active layer material, the maximum process temperature is preferably controlled below 300°C. If low-temperature polycrystalline silicon is used, the temperature and steps can be adjusted accordingly based on the laser crystallization or solid-state crystallization process. After the fabrication of the thin-film switching layer 3 is completed, each thin-film switching device is subjected to DC electrical testing to eliminate abnormal devices with gate-source short circuits, gate-drain short circuits, or on-resistance exceeding the design range. Then, a temporary protective layer is formed on the second surface, and the second surface is temporarily bonded to a temporary carrier to protect the thin-film switching layer 3 and provide mechanical support for the subsequent processes on the first surface. The temporary bonding material should be selected to be stable at the highest process temperature of the subsequent RDL redistribution layer 27 and to be debonded by thermal release, laser release, or solvent release. S3. A MIM capacitor 6 is formed on the first surface side of the glass substrate 1. First, a first metal layer is deposited and patterned on the first surface side to form the first electrode 61 of the MIM capacitor 6. Then, an insulating dielectric layer 62 is deposited on the first electrode 61. The insulating dielectric layer 62 can be SiNx, SiOx, Al2O3 or a multilayer dielectric. Next, a second metal layer is deposited and patterned on the insulating dielectric layer 62 to form the second electrode 63 of the MIM capacitor 6. The pattern boundary of the second electrode 63 is smaller than the pattern boundary of the insulating dielectric layer 62 to retain edge insulation margin, thereby completing the fabrication of the MIM capacitor 6. S4. An integrated passive device layer 2 is formed on the first surface side. First, photosensitive polyimide is spin-coated or laminated, exposed, developed and cured to form a first polyimide insulating layer and its interlayer vias. Then, a first RDL redistribution layer 27 is fabricated using a semi-additive method. First, a titanium-copper seed layer is formed by physical vapor deposition, then photoresist is coated, exposed and developed, copper is electroplated in the development opening, then the photoresist is removed and the seed layer in the non-circuit area is etched. The above polyimide patterning and semi-additive copper wiring steps are repeated to sequentially form multiple RDL redistribution layers 27 and polyimide insulating layers located between adjacent RDL redistribution layers 27. The planar spiral inductor is formed in one or more RDL redistribution layers 27 and the coil segments in different RDL redistribution layers 27 are connected through interlayer vias.

[0033] During the above process, an RF input terminal 21, an RF output terminal 22, a common node 23, a common passive unit 24 connecting the RF input terminal 21 and the common node 23, and at least two passive branches respectively connected between the common node 23 and the RF output terminal 22 are simultaneously formed. Each passive branch is connected to the corresponding RF via 41 according to a preset equivalent circuit. During the fabrication process, at least three non-collinear glass via copper end faces are used as double-sided alignment marks to ensure that each passive branch on the first surface and the thin-film switching device on the second surface are aligned in the glass thickness direction, thereby completing the fabrication of the integrated passive device layer 2. S5. Connect the passive unit of each passive branch in series with the corresponding switching unit through a pair of corresponding RF vias 41, and ensure that the number of thin film switching devices, the number of RF vias 41 and the number of transitions between the RDL redistribution layers 27 are the same in all passive branches. Then, form each functional bump terminal 28 on the top RDL redistribution layer 27, debond the glass substrate 1 from the temporary carrier, perform RF performance tests on each working state, and correct the passive component parameters according to the test results. Make the non-functional connection segments located outside the passive unit of each selectable passive branch equal in length or with a length difference of no more than 10%.

[0034] This specific embodiment is merely an explanation of the present invention and is not intended to limit the invention. After reading this specification, those skilled in the art can make inventive modifications to this embodiment as needed, but as long as they are within the scope of the claims of the present invention, they are protected by patent law.

Claims

1. A TGV glass-based reconfigurable integrated passive device with a parasitic parameter balancing structure, characterized in that, include: A glass substrate (1) includes a first surface side and a second surface side disposed opposite to each other; An integrated passive device layer (2) is disposed on the first surface side of the glass substrate (1), including a radio frequency input terminal (21), a radio frequency output terminal (22), a common node (23), a common passive unit (24), at least two passive branches, and an RDL redistribution layer (27) for realizing electrical connections. The common passive unit (24) is connected between the radio frequency input terminal (21) and the common node (23). The passive branches are respectively connected between the common node (23) and the radio frequency output terminal (22). Each passive branch includes at least one branch passive unit. A thin-film switching layer (3) is disposed on the second surface side of the glass substrate (1). The thin-film switching layer (3) includes a switching unit corresponding to the passive branch and a control line (33) connected to the switching unit. The switching unit includes at least one thin-film switching device, and the thin-film switching device has a control electrode, a first electrode and a second electrode. The through-hole interconnect structure (4) is disposed through the glass substrate (1) and includes radio frequency through-holes (41) and control through-holes (42). Each passive branch is provided with at least one pair of radio frequency through-holes (41). The first and second electrodes of the thin film switch device are connected in series in the corresponding passive branch through the corresponding pair of radio frequency through-holes (41). The control electrode of the thin film switch device is electrically connected to the control through-hole (42) through the control line (33). Each passive branch has the same number of thin-film switching devices in its corresponding switching unit, and each passive branch has the same number of radio frequency vias (41) and the same number of RDL interlayer transitions in its radio frequency signal path. Furthermore, the equivalent connection lengths of the non-functional connection segments located outside the passive unit of each passive branch are the same or differ by no more than 10%, so that when different passive branches are selected, the switching parasitic parameters, vertical interconnect parasitic parameters, and interlayer transition parasitic parameters in the radio frequency signal path are balanced.

2. The TGV glass-based reconfigurable integrated passive device with a parasitic parameter balancing structure according to claim 1, characterized in that, The common passive unit (24) and the branch passive unit are one or more of the following: capacitor unit, inductor unit and resistor unit; When the common passive unit (24) is a capacitor unit, each branch passive unit includes an inductor unit with different inductance values ​​and / or a resistor unit with different resistance values; or, when the common passive unit (24) is an inductor unit, each branch passive unit includes a capacitor unit with different capacitance values ​​and / or a resistor unit with different resistance values. When the branch passive unit includes multiple passive elements, the multiple passive elements are connected in series, in parallel, or in a series-parallel combination.

3. A TGV glass-based reconfigurable integrated passive device with a parasitic parameter balancing structure according to claim 1 or 2, characterized in that, The integrated passive device includes a MIM capacitor (6) consisting of a first electrode (61), an insulating dielectric layer (62), and a second electrode (63) stacked sequentially. The pattern boundary of the second electrode (63) is located within the pattern boundary of the insulating dielectric layer (62) to form an edge insulation margin on the outer periphery of the second electrode (63).

4. The TGV glass-based reconfigurable integrated passive device with a parasitic parameter balancing structure according to claim 3, characterized in that, Each pair of radio frequency vias (41) corresponding to each passive branch has the same aperture, the same conductive layer structure inside the via, and the same glass penetration length. The rewiring structures corresponding to different passive branches have the same number of wiring layers and the same number of interlayer conductive vias, and at least two of the passive branches are arranged in a mirror image relative to the preset symmetry plane passing through the common node (23).

5. A TGV glass-based reconfigurable integrated passive device with a parasitic parameter balancing structure according to claim 4, characterized in that, When at least two of the passive branches cannot be perfectly mirrored, a compensation connection segment that does not participate in the formation of the main passive parameters of the branch is set in the passive branch with the shorter connection path, and / or the same number of dummy interlayer transformation structures as the other passive branch are set, so that the number of RDL level transformations, the number of interlayer conductive vias and the equivalent connection length of the non-functional connection segments of the two passive branches are the same or differ by no more than 10%.

6. A TGV glass-based reconfigurable integrated passive device with a parasitic parameter balancing structure according to claim 5, characterized in that, The thin-film switching device is a bottom-gate thin-film transistor or a top-gate thin-film transistor. The thin-film transistor includes a gate, a gate insulating layer, a semiconductor active layer, a source drain electrode layer and a passivation layer arranged in sequence. The material of the semiconductor active layer is selected from hydrogenated amorphous silicon, low-temperature polycrystalline silicon and oxide semiconductor. The integrated passive device layer (2) also includes a bump terminal (28) that is electrically connected to the RF input terminal (21), the RF output terminal (22) and the control via (42) respectively.

7. A method for fabricating a TGV glass-based reconfigurable integrated passive device with a parasitic parameter balancing structure, used to manufacture a TGV glass-based reconfigurable integrated passive device with a parasitic parameter balancing structure as described in any one of claims 1-6; characterized in that, include: S1. Provide a glass substrate (1), and form radio frequency vias (41) and control vias (42) through the first surface side and the second surface side respectively on the glass substrate (1) based on a preset interconnect pattern, and form a conductive interconnect structure inside each via; S2. A thin film switch layer (3) is formed on the second surface side of the glass substrate (1) to form at least two switch units and their control lines (33). The first connection end and the second connection end of each switch unit are respectively connected to the lower end of the corresponding radio frequency via (41). Each switch unit includes at least one thin film switch device with a control electrode, a first electrode and a second electrode. The control electrode of each thin film switch device is electrically connected to the corresponding control via (42) through the control line (33). S3. An integrated passive device layer (2) is formed on the first surface side. The integrated passive device layer (2) includes a radio frequency input terminal (21), a radio frequency output terminal (22), a common node (23), a common passive unit (24) connected between the radio frequency input terminal (21) and the common node (23), and at least two passive branches respectively connected between the common node (23) and the radio frequency output terminal (22). S4. Connect the passive unit of each passive branch in series with the corresponding switching unit through a pair of corresponding radio frequency vias (41), and ensure that the number of thin film switching devices, the number of radio frequency vias and the number of transitions between the RDL redistribution layers (27) contained in all passive branches are the same, and make the non-functional connection segments outside the passive unit in each passive branch equal in length or have a length difference of no more than 10%.

8. The method for fabricating a TGV glass-based reconfigurable integrated passive device with a parasitic parameter balance structure according to claim 7, characterized in that, In S1, the method for fabricating the conductive interconnect structure is as follows: S1.1 The glass substrate (1) is subjected to laser modification treatment to form a modified area at the preset through hole position; S1.

2. Selective wet etching is performed on the modified area using a fluorine-containing etching solution or an alkaline etching solution to form a through hole penetrating the glass substrate (1); S1.3 Deposit a barrier layer and a conductive seed layer on the hole wall, the first surface side, and the second surface side of the through hole; S1.

4. Electrochemically plate copper onto the via based on the conductive seed layer to form a copper interconnect filling the via; S1.

5. Perform chemical mechanical polishing on the first and second surface sides of the glass substrate (1) so that the end face of the copper interconnect is flush with the corresponding glass surface.

9. The method for fabricating a TGV glass-based reconfigurable integrated passive device with a parasitic parameter balance structure according to claim 8, characterized in that, In S3, the method for fabricating the integrated passive device layer (2) is as follows: S3.1 Deposit and pattern a first metal layer on the first surface side to form the first electrode of the MIM capacitor; S3.

2. An insulating dielectric layer is formed on the first electrode, and a second electrode is formed on the insulating dielectric layer to form a MIM capacitor formed by sequentially stacking the first electrode, the insulating dielectric layer and the second electrode. S3.3 Form a photosensitive polyimide insulating layer on the MIM capacitor, and pattern the photosensitive polyimide insulating layer to form interlayer vias that expose the electrical connection area; S3.4 At least two RDL redistribution layers and a polyimide insulating layer located between adjacent RDL redistribution layers are sequentially formed using a semi-additive method to form the common passive unit, the branch passive unit and their electrical connection lines.

10. The method for fabricating a TGV glass-based reconfigurable integrated passive device with a parasitic parameter balance structure according to claim 9, characterized in that, After forming the conductive interconnect structure, at least three non-collinear conductive interconnect structure end faces are selected as double-sided alignment marks. When forming the thin film switch layer (3), the position of each thin film switch device relative to the corresponding radio frequency via (41) is determined according to the double-sided alignment mark; When forming the integrated passive device layer (2), the position of each passive branch is determined according to the same set of double-sided alignment marks so that the corresponding branch passive unit, radio frequency via (41) and thin film switching device are aligned in the thickness direction of the glass substrate (1).

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