Array substrate and display panel

Abstract

The application relates to an array substrate and a display panel. The array substrate comprises a substrate, an array film layer structure arranged on one side of the substrate, a first transistor film layer structure and a second transistor film layer structure; the first transistor is a data writing transistor, and the second transistor is a threshold compensation transistor; the first transistor film layer structure comprises a first active layer, a first gate layer and a first source-drain layer; the second transistor film layer structure comprises a first top gate layer, a second active layer, a first bottom gate layer and a second source-drain layer; the orthographic projection of the first active layer on the substrate at least partially overlaps the orthographic projection of the second active layer on the substrate; the first source-drain layer and the second source-drain layer are arranged on the side of the first top gate layer away from the substrate, the first source-drain layer is connected with the first active layer through a first via, and the second source-drain layer is connected with the second active layer through a second via. The resolution of the display panel can be improved by adopting the scheme.

Description

Technical Field

[0001] This application relates to the field of display panel technology, and in particular to an array substrate and a display panel. Background Technology

[0002] Display panels are widely used in various consumer electronics products such as mobile phones, televisions, laptops, and desktop computers. High-resolution display panels, due to their superior visual effects, have gradually become a development trend in the display industry.

[0003] Therefore, improving the resolution of display panels has become an urgent problem to be solved. Summary of the Invention

[0004] Therefore, it is necessary to provide an array substrate and display panel that can improve resolution in response to the above-mentioned technical problems.

[0005] In a first aspect, this application provides an array substrate, the array substrate comprising:

[0006] substrate;

[0007] An array of film layers is disposed on one side of the substrate, including a film layer structure of a first transistor and a film layer structure of a second transistor; the first transistor is a data writing transistor, and the second transistor is a threshold compensation transistor.

[0008] The first transistor has a film structure comprising a first active layer, a first gate layer, and a first source / drain layer; the second transistor has a film structure comprising a first top gate layer, a second active layer, a first bottom gate layer, and a second source / drain layer; the first active layer, the first gate layer, the first bottom gate layer, the second active layer, and the first top gate layer are sequentially stacked along a direction away from the substrate, wherein the orthographic projection of the first active layer on the substrate and the orthographic projection of the second active layer on the substrate at least partially overlap; the first source / drain layer and the second source / drain layer are both disposed on the side of the first top gate layer away from the substrate, the first source / drain layer is connected to the first active layer through a first via, and the second source / drain layer is connected to the second active layer through a second via.

[0009] In one embodiment, the material of the first active layer includes polycrystalline silicon; the material of the second active layer includes metal oxide.

[0010] In one embodiment, the first gate layer and the first bottom gate layer form a storage capacitor.

[0011] In one embodiment, the array film structure further includes a film structure of a third transistor, wherein the third transistor is a driving transistor;

[0012] The film structure of the third transistor includes a third active layer, a third gate layer, and a third source-drain layer; the third active layer, the third gate layer, and the third source-drain layer are stacked sequentially along the direction away from the substrate, and the third source-drain layer is connected to the third active layer through a third via.

[0013] The third active layer is disposed on the same layer as the first active layer; the third gate layer is disposed on the same layer as the first gate layer; and the third source-drain layer is disposed on the same layer as the first source-drain layer.

[0014] In one embodiment, the array film structure further includes a film structure of a fourth transistor, wherein the fourth transistor is a gate reset transistor;

[0015] The film structure of the fourth transistor includes a second bottom gate layer, a fourth active layer, a second top gate layer, and a fourth source-drain layer; the second bottom gate layer, the fourth active layer, the second top gate layer, and the fourth source-drain layer are stacked sequentially along the direction away from the substrate, and the fourth source-drain layer is connected to the fourth active layer through a fourth via.

[0016] The fourth active layer is disposed on the same layer as the second active layer; the second top gate layer is disposed on the same layer as the first top gate layer; the second bottom gate layer is disposed on the same layer as the first bottom gate layer; and the fourth source-drain layer is disposed on the same layer as the second source-drain layer.

[0017] In one embodiment, the array film structure further includes a film structure of a fifth transistor, wherein the fifth transistor is a light-emitting control transistor;

[0018] The film structure of the fifth transistor includes a fifth active layer, a fifth gate layer, and a fifth source-drain layer; the fifth active layer, the fifth gate layer, and the fifth source-drain layer are stacked sequentially along the direction away from the substrate, and the fifth source-drain layer is connected to the fifth active layer through a fifth via.

[0019] The fifth active layer is disposed on the same layer as the first active layer; the fifth gate layer is disposed on the same layer as the first gate layer; and the fifth source-drain layer is disposed on the same layer as the first source-drain layer.

[0020] In one embodiment, the array film structure further includes a film structure of a sixth transistor, wherein the sixth transistor is a light-emitting control transistor;

[0021] The film structure of the sixth transistor includes a sixth active layer, a sixth gate layer, and a sixth source-drain layer; the sixth active layer, the sixth gate layer, and the sixth source-drain layer are stacked sequentially along the direction away from the substrate, and the sixth source-drain layer is connected to the sixth active layer through a sixth via.

[0022] The sixth active layer is disposed on the same layer as the first active layer; the sixth gate layer is disposed on the same layer as the first gate layer; and the sixth source-drain layer is disposed on the same layer as the first source-drain layer.

[0023] In one embodiment, the array film structure further includes a film structure of a seventh transistor, which is an anode reset transistor;

[0024] The film structure of the seventh transistor includes a seventh active layer, a seventh gate layer, and a seventh source-drain layer; the seventh active layer, the seventh gate layer, and the seventh source-drain layer are stacked sequentially along the direction away from the substrate, and the seventh source-drain layer is connected to the seventh active layer through a seventh via;

[0025] The seventh active layer is disposed on the same layer as the first active layer; the seventh gate layer is disposed on the same layer as the first gate layer; and the seventh source-drain layer is disposed on the same layer as the first source-drain layer.

[0026] In one embodiment, the gate layer of each transistor includes the gate of the transistor, and the source-drain layer of each transistor includes the first electrode and the second electrode of the transistor.

[0027] The gate of the first transistor is connected to the first scan signal line, the first terminal of the first transistor is connected to the data signal line, and the second terminal of the first transistor is connected to the first terminal of the third transistor.

[0028] The gate of the second transistor is connected to the second scan signal line, the first terminal of the second transistor is connected to the first terminal of the storage capacitor, and the second terminal of the second transistor is connected to the second terminal of the third transistor.

[0029] The gate of the third transistor is connected to the first terminal of the storage capacitor;

[0030] The gate of the fourth transistor is connected to the third scan signal line, the first terminal of the fourth transistor is connected to the first terminal of the second transistor or the second terminal of the second transistor, and the second terminal of the fourth transistor is connected to the first reset signal line;

[0031] The gate of the fifth transistor is connected to the light-emitting control signal line, the first terminal of the fifth transistor is connected to the second terminal of the storage capacitor and the power supply signal line, and the second terminal of the fifth transistor is connected to the first terminal of the third transistor.

[0032] The gate of the sixth transistor is connected to the light-emitting control signal line, the first terminal of the sixth transistor is connected to the second terminal of the third transistor, and the second terminal of the sixth transistor is connected to the light-emitting device.

[0033] The gate of the seventh transistor is connected to the fourth scan signal line, the first electrode of the seventh transistor is connected to the second reset signal line, and the second electrode of the seventh transistor is connected to the light-emitting device.

[0034] Secondly, this application also provides a display panel, the display panel comprising the array substrate described in any one of the first aspects above.

[0035] In the aforementioned array substrate, the orthographic projection of the first active layer of the first transistor (i.e., the data write transistor) onto the substrate at least partially overlaps with the orthographic projection of the second active layer of the second transistor (i.e., the threshold compensation transistor) onto the substrate. This achieves a stacked arrangement of the data write transistor and the threshold compensation transistor, thereby saving space, reducing the size of the pixel circuit, and thus increasing the number of pixels distributed per unit area, thereby improving the resolution of the display panel. Furthermore, the stacked arrangement of the first gate layer and the first bottom gate layer can form a storage capacitor; therefore, there is no need to additionally set a storage capacitor, further saving space and further improving the resolution of the display panel. Attached Figure Description

[0036] Figure 1 A cross-sectional view of the array substrate in one embodiment;

[0037] Figure 2 This is a cross-sectional view of the display panel in one embodiment;

[0038] Figure 3 Here is a pixel circuit diagram from one embodiment;

[0039] Figure 4 A pixel circuit diagram in another embodiment;

[0040] Figure 5 This is a layout of the pixel circuitry in one embodiment;

[0041] Figure 6 This is a layout of the first metal layer M1 and the active layer in one embodiment;

[0042] Figure 7A This is a layout of the second metal layer M2 and the third metal layer M3 with the active layer in one embodiment;

[0043] Figure 7B This is a layout of the third metal layer M3 and the active layer in one embodiment;

[0044] Figure 7C This is a layout of the second metal layer M2 and the active layer in one embodiment. Detailed Implementation

[0045] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0046] It should be understood that although the terms “first,” “second,” etc., may be used herein to describe various elements, this does not indicate any order, quantity, or importance, but is merely used to distinguish different components. These terms are used only to distinguish one element from another. For example, without departing from the scope of this application, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element. Words such as “comprising” or “including” mean that the element or object preceding the word covers the element or object listed following the word and its equivalents, without excluding other elements or objects.

[0047] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the specification of this application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0048] In one embodiment, such as Figure 1 As shown, a cross-sectional view of an array substrate is provided. The array substrate 1 includes a substrate 10 and an array film structure 20 disposed on one side of the substrate 10. The array film structure 20 includes a film structure of a first transistor T2 and a film structure of a second transistor T3; the first transistor T2 is a data writing transistor, and the second transistor T3 is a threshold compensation transistor. It should be noted that, in order to enable those skilled in the art to understand this application by referring to the figures, the marking symbols of each transistor in this application are consistent with the marking symbols of each transistor in the 7T1C pixel circuit.

[0049] The first transistor T2 has a film structure including a first active layer 201a, a first gate layer 201b, and a first source-drain layer 201c; the second transistor T3 has a film structure including a second active layer 202a, a first top gate layer 202b, a second source-drain layer 202c, and a first bottom gate layer 202d. The first transistor T2 and the second transistor T3 are stacked, that is, along the direction away from the substrate 10, the first active layer 201a, the first gate layer 201b, the first bottom gate layer 202d, the second active layer 202a, and the first top gate layer 202b are stacked sequentially, wherein the orthographic projection of the first active layer 201a on the substrate 10 at least partially overlaps with the orthographic projection of the second active layer 202a on the substrate 10. The first source-drain layer 201c and the second source-drain layer 202c are both disposed on the side of the first top gate layer 202b away from the substrate 20. The first source-drain layer 201c is connected to the first active layer 201a through a first via (not marked in the figure), and the second source-drain layer 202c is connected to the second active layer 202a through a second via (not marked in the figure).

[0050] The substrate 10 may include a first PI substrate layer 101a, a first barrier layer 102a, a second PI substrate layer 101b, and a second barrier layer 102b, which are sequentially stacked. The first PI substrate layer 101a and the second PI substrate layer 101b are collectively referred to as substrate layer 101. Exemplarily, the substrate 10 is a flexible material, allowing the display panel to be bent, thereby enabling the display panel to achieve functions such as curved display, foldable display, or rollable display. For example, the material of the flexible substrate 10 can be any one of PI (Polyimide), PC (polycarbonate), or PVC (polyvinyl chloride). The substrate 10 can also be a rigid material, such as glass or plastic.

[0051] The array substrate 1 also includes a light-shielding layer 30, a third blocking layer 102c, and a first buffer layer 40 located between the substrate 10 and the first active layer 201a. The light-shielding layer 30 is located on the side of the second blocking layer 102b away from the substrate layer 101. The light-shielding layer 30 is used to block light emitted from the outside toward the substrate 10, so as to avoid the influence of external light on the active layer in the array film structure 20. The light-shielding layer 30 can be composed of a black matrix, and its own material can block light.

[0052] The third barrier layer 102c is located on the side of the light-shielding layer 30 away from the substrate layer 101. The first barrier layer 102a, the second barrier layer 102b, and the third barrier layer 102c are collectively referred to as barrier layer 102. The materials of the first barrier layer 102a, the second barrier layer 102b, and the third barrier layer 102c include SiOx (Silicon Oxide).

[0053] The first buffer layer 40 is located on the side of the third barrier layer 102c away from the substrate layer 101. The first buffer layer 40 includes an inorganic layer or an organic layer. Exemplarily, the first buffer layer 40 may be formed from an inorganic material selected from silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, or aluminum nitride, or an organic material selected from acrylic, polyimide, or polyester. The first buffer layer 40 may include a single layer or multiple layers. The first buffer layer 40 serves to block oxygen and moisture, prevent moisture or impurities from diffusing through the substrate 10, and provide a flat surface on the upper surface of the substrate 10, thereby facilitating the fabrication of the first active layer 201a. For example, in this embodiment, the material of the first buffer layer 40 includes SiNx (Silicon Nitride).

[0054] It can be understood that the first active layer 201a includes the channel layer of the first transistor T2 and the source and drain regions located on both sides of the channel layer of the first transistor T2; the second active layer 202a includes the channel layer of the second transistor T3 and the source and drain regions located on both sides of the channel layer of the second transistor T3. The material of the first active layer 201a includes polysilicon, that is, the material of the channel layer of the first transistor T2 includes polysilicon, such as PSI (Polysiloxane); the material of the second active layer 202a includes metal oxide, that is, the material of the channel layer of the second transistor T3 includes metal oxide, such as IGZO (Indium Gallium Zinc Oxide).

[0055] The first gate layer 201b includes the gate of the first transistor T2, and the first top gate layer 202b includes the gate of the second transistor T3. The materials of the first gate layer 201b, the first top gate layer 202b, and the first bottom gate layer 202d can be the same or different. In one example, both the first gate layer 201b and the first bottom gate layer 202d can include a metal material, such as at least one of aluminum, molybdenum, copper, titanium, or ITO (Indium Tin Oxides); the material of the first top gate layer 202b includes a metal oxide, such as GATO (Gallium Tin Oxide).

[0056] The first source-drain layer 201c includes a first electrode and a second electrode of the first transistor T2, wherein the first electrode of the first transistor T2 is one of the source and the drain, and correspondingly, the second electrode of the first transistor T2 is the other of the drain and the source. The second source-drain layer 202c includes a first electrode and a second electrode of the second transistor T3, wherein the first electrode of the second transistor T3 is one of the source and the drain, and correspondingly, the second electrode of the second transistor T3 is the other of the drain and the source. The first source-drain layer 201c and the second source-drain layer 202c are disposed in the same layer, and the first source-drain layer 201c and the second source-drain layer 202c are made of the same material, both of which may include a metallic material, such as at least one of aluminum, molybdenum, copper, titanium, or ITO.

[0057] The first source-drain layer 201c is connected to the first active layer 201a through a first via. Specifically, there can be two first vias. The first and second terminals of the first transistor T2 in the first source-drain layer 201c are connected to the source and drain regions of the first active layer 201a through the two first vias. The second source-drain layer 202c is connected to the second active layer 202a through a second via. Specifically, there can be two second vias. The first and second terminals of the second transistor T3 in the second source-drain layer 202c are connected to the source and drain regions of the second active layer 202a through the two second vias.

[0058] In one example, the projection relationship between the film structure of the first transistor T2 and the film structure of the second transistor T3 is as follows: the orthographic projection of the first active layer 201a on the substrate 10 at least partially overlaps with the orthographic projection of the second active layer 202a on the substrate 10; the orthographic projection of the first gate layer 201b on the substrate 10 at least partially overlaps with the orthographic projection of the first top gate layer 202b on the substrate 10; and the orthographic projection of the first gate layer 201b on the substrate 10 at least partially overlaps with the orthographic projection of the first bottom gate layer 202d on the substrate 10.

[0059] It is understood that a first gate insulator (GI) 301 exists between the first active layer 201a and the first gate layer 201b, and the material of the first gate insulator 301 includes SiOx. A capacitance insulator (CI) 302 exists between the first gate layer 201b and the first bottom gate layer 202d, and the material of the capacitance insulator 302 includes SiNx. A second buffer layer 303 exists between the first bottom gate layer 202d and the second active layer 202a, and the material of the second buffer layer 303 includes SiNx. A second gate insulator 304 exists between the second active layer 202a and the first top gate layer 202b, and the material of the second gate insulator 304 includes SiOx. An interlayer dielectric (ILD) 305 exists between the first gate layer 201b and the first source-drain layer 201c, and between the first top gate layer 202b and the second source-drain layer 202c. The material of the interlayer dielectric 305 includes SiOx.

[0060] As can be seen from the arrangement relationship of the film layer structure of the first transistor T2 and the film layer structure of the second transistor T3, the first gate layer 201b and the first bottom gate layer 202d can form a storage capacitor C1. The first terminal of the storage capacitor C1 can be located in the first gate layer 201b or the first bottom gate layer 202d. Correspondingly, the second terminal of the storage capacitor C1 can be located in the first bottom gate layer 202d or the first gate layer 201b.

[0061] It should be noted that the array film structure 20 includes a first metal layer M1, a second metal layer M2, a third metal layer M3 and a fourth metal layer M4 stacked sequentially along the direction away from the substrate 10. The first gate layer 201b is located in the first metal layer M1, the first bottom gate layer 202d is located in the second metal layer M2, and the first top gate layer 202b is located in the third metal layer M3.

[0062] In this embodiment, the orthographic projection of the first active layer 201a of the first transistor T2 (i.e., the data writing transistor) onto the substrate 10 at least partially overlaps with the orthographic projection of the second active layer 202a of the second transistor T3 (i.e., the threshold compensation transistor) onto the substrate 10. This achieves a stacked configuration of the data writing transistor and the threshold compensation transistor, thereby saving space, reducing the size of the pixel circuit, and thus increasing the number of pixels distributed per unit area, thereby improving the resolution of the display panel. Furthermore, the stacked configuration of the first gate layer and the first bottom gate layer can form a storage capacitor; therefore, no additional storage capacitor is required, further saving space and further improving the resolution of the display panel.

[0063] In one embodiment, such as Figure 2The diagram shows a cross-sectional view of a display panel. The display panel includes an array substrate 1, a pixel definition layer 50, a light-emitting device 60, and a support member 70. The array film structure 20 of the array substrate 1 also includes a film structure of a third transistor T1, which is a driving transistor. The film structure of the third transistor T1 includes a third active layer 203a, a third gate layer 203b, and a third source-drain layer 203c. Along the direction away from the substrate 10, the third active layer 203a, the third gate layer 203b, and the third source-drain layer 203c are stacked sequentially, and the third source-drain layer 203c is connected to the third active layer 203a through a third via (not marked in the figure). The third active layer 203a is disposed on the same layer as the first active layer 201a; the third gate layer 203b is disposed on the same layer as the first gate layer 201b; and the third source-drain layer 203c is disposed on the same layer as the first source-drain layer 201c.

[0064] It is understandable that setting two film layers in the same layer means that the two film layers are formed simultaneously during the patterning process in the preparation process.

[0065] The third active layer 203a includes the channel layer of the third transistor T1 and source and drain regions located on both sides of the channel layer of the third transistor T1. The material of the first active layer 201a is the same as that of the third active layer 201a, including polysilicon, that is, the material of the channel layer of the third transistor T1 includes polysilicon, such as PSI.

[0066] The third gate layer 203b includes the gate of the third transistor T1. The material of the third gate layer 203b is the same as that of the first gate layer 201b, including a metallic material, such as at least one of aluminum, molybdenum, copper, titanium or ITO (Indium Tin Oxides).

[0067] The third source-drain layer 203c includes a first electrode and a second electrode of the third transistor T1, wherein the first electrode of the third transistor T1 is one of the source and the drain, and correspondingly, the second electrode of the third transistor T1 is the other of the drain and the source.

[0068] The third source-drain layer 203c is connected to the third active layer 203a through a third via. Specifically, there can be two third vias. The first and second terminals of the third transistor T1 in the third source-drain layer 203c are connected to the source and drain regions in the third active layer 203a through two third vias.

[0069] The third transistor T1 is a driving transistor and is connected to the light-emitting device 60 in the display panel. Specifically, the array film structure 20 also includes a first planarization layer 401, a bridging layer 402, and a second planarization layer 403, which are sequentially stacked along the direction away from the substrate 10. The first planarization layer 401 is disposed on the side of the third source-drain layer 203c away from the substrate 10, and the bridging layer 402 is located in the fourth metal layer M4 in the array film structure 20. Both the first planarization layer 401 and the second planarization layer 403 are provided with vias (not marked in the figure) so that the third source-drain layer 203c is connected to the bridging layer 402 through the vias on the first planarization layer 401, and the bridging layer 402 is connected to the light-emitting device 60 through the vias on the second planarization layer 403.

[0070] Reference Figure 2 As shown, the light-emitting device 60 includes a first electrode 601, which can be an anode; the third transistor T1 is connected to the light-emitting device 60 in the display panel, which can refer to the third transistor T1 being connected to the first electrode 601.

[0071] The light-emitting device 60 also includes a light-emitting layer and a second electrode, wherein the first electrode 601, the light-emitting layer and the second electrode are stacked sequentially along the direction away from the substrate 10. Figure 2 The light-emitting layer and second electrode of the light-emitting device 60 are not shown in the diagram. The second electrode may be a cathode; the light-emitting layer includes at least a light-emitting functional material, and may also include one or more of the following: a hole injection layer (HIL), a hole transport layer (HTL), an electron injection layer (EIL), an electron transport layer (ETL), a hole block layer (HBL), and an electron block layer (EBL). Alternatively, the light-emitting layer may be a stacked light-emitting layer, that is, it includes at least two light-emitting layers and a charge generation layer (CGL) located between each adjacent light-emitting layer.

[0072] The first electrode 601 is disposed on one side of the array substrate 1, and the pixel definition layer 50 is disposed on the side of the first electrode 601 away from the array substrate 1. A pixel opening (not marked in the figure) is provided on the pixel definition layer 50, and part of the surface of the first electrode 601 is exposed from the pixel opening.

[0073] The fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 in the array film structure 20 will be described in detail below. Since the film structures of the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 are similar to those of the first transistor T2, the second transistor T3, and the third transistor T1, the film structures of the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 are not shown in cross-sectional views in this application.

[0074] In one embodiment, the array film structure 20 further includes a film structure of a fourth transistor T4, which is a gate reset transistor. The film structure of the fourth transistor T4 includes a second bottom gate layer, a fourth active layer, a second top gate layer, and a fourth source-drain layer. Along the direction away from the substrate 10, the second bottom gate layer, the fourth active layer, the second top gate layer, and the fourth source-drain layer are stacked sequentially, and the fourth source-drain layer is connected to the fourth active layer through a fourth via. The fourth active layer is disposed on the same layer as the second active layer 202a; the second top gate layer is disposed on the same layer as the first top gate layer 202b; the second bottom gate layer is disposed on the same layer as the first bottom gate layer 202d; and the fourth source-drain layer and the second source-drain layer 202c are disposed on the same layer.

[0075] The fourth active layer includes the channel layer of the fourth transistor T4 and the source and drain regions located on both sides of the channel layer of the fourth transistor T4; the material of the fourth active layer is the same as the material of the second active layer 202a, including metal oxide, that is, the material of the channel layer of the fourth transistor T4 includes metal oxide, such as IGZO.

[0076] The second top gate layer includes the gate of the fourth transistor T4. The material of the second bottom gate layer is the same as that of the first bottom gate layer 202d, including a metallic material, such as at least one of aluminum, molybdenum, copper, titanium or ITO; the material of the second top gate layer is the same as that of the first top gate layer 202b, including a metal oxide, such as GATO (Gallium Tin Oxide).

[0077] The fourth source-drain layer includes a first electrode and a second electrode of the fourth transistor T4, wherein the first electrode of the fourth transistor T4 is one of the source and the drain, and correspondingly, the second electrode of the fourth transistor T4 is the other of the drain and the source. The fourth source-drain layer and the second source-drain layer 202c are made of the same material, including a metallic material, such as at least one of aluminum, molybdenum, copper, titanium, or ITO.

[0078] The fourth source-drain layer is connected to the fourth active layer through a fourth via. Specifically, there can be two fourth vias. The first and second terminals of the fourth transistor T4 in the fourth source-drain layer are connected to the source and drain regions in the fourth active layer through two fourth vias.

[0079] In one embodiment, the array film structure 20 further includes a film structure of a fifth transistor T5, which is a light-emitting control transistor. The film structure of the fifth transistor T5 includes a fifth active layer, a fifth gate layer, and a fifth source-drain layer. The fifth active layer, the fifth gate layer, and the fifth source-drain layer are stacked sequentially along the direction away from the substrate 10, and the fifth source-drain layer is connected to the fifth active layer through a fifth via. The fifth active layer is disposed on the same layer as the first active layer 201a; the fifth gate layer is disposed on the same layer as the first gate layer 201b; and the fifth source-drain layer is disposed on the same layer as the first source-drain layer 201c.

[0080] The fifth active layer includes the channel layer of the fifth transistor T5 and the source and drain regions located on both sides of the channel layer of the fifth transistor T5. The material of the fifth active layer is the same as that of the first active layer 201a, including polysilicon, that is, the material of the channel layer of the fifth transistor T5 includes polysilicon, such as PSI.

[0081] The fifth gate layer includes the gate of the fifth transistor T5. The material of the fifth gate layer is the same as that of the first gate layer 201b, including a metallic material, such as at least one of aluminum, molybdenum, copper, titanium or ITO.

[0082] The fifth source-drain layer includes a first electrode and a second electrode of the fifth transistor T5, wherein the first electrode of the fifth transistor T5 is one of the source and the drain, and correspondingly, the second electrode of the fifth transistor T5 is the other of the drain and the source. The material of the fifth source-drain layer is the same as the material of the first source-drain layer 201c, including a metallic material, such as at least one of aluminum, molybdenum, copper, titanium, or ITO.

[0083] The fifth source-drain layer is connected to the fifth active layer through a fifth via. Specifically, there can be two fifth vias. The first and second terminals of the fifth transistor T5 in the fifth source-drain layer are connected to the source and drain regions in the fifth active layer through two fifth vias.

[0084] In one embodiment, the array film structure 20 further includes a film structure of a sixth transistor T6, which is a light-emitting control transistor. The film structure of the sixth transistor T6 includes a sixth active layer, a sixth gate layer, and a sixth source-drain layer. The sixth active layer, the sixth gate layer, and the sixth source-drain layer are stacked sequentially along the direction away from the substrate 10, and the sixth source-drain layer is connected to the sixth active layer through a sixth via. The sixth active layer is disposed on the same layer as the first active layer 201a; the sixth gate layer is disposed on the same layer as the first gate layer 201b; and the sixth source-drain layer is disposed on the same layer as the first source-drain layer 201c.

[0085] The sixth active layer includes the channel layer of the sixth transistor T6 and the source and drain regions located on both sides of the channel layer of the sixth transistor T6. The material of the sixth active layer is the same as that of the first active layer 201a, including polysilicon, that is, the material of the channel layer of the sixth transistor T6 includes polysilicon, such as PSI.

[0086] The sixth gate layer includes the gate of the sixth transistor T6. The material of the sixth gate layer is the same as that of the first gate layer 201b, including a metallic material, such as at least one of aluminum, molybdenum, copper, titanium or ITO.

[0087] The sixth source-drain layer includes a first electrode and a second electrode of the sixth transistor T6, wherein the first electrode of the sixth transistor T6 is one of the source and the drain, and correspondingly, the second electrode of the sixth transistor T6 is the other of the drain and the source. The material of the sixth source-drain layer is the same as that of the first source-drain layer 201c, including a metallic material, such as at least one of aluminum, molybdenum, copper, titanium, or ITO.

[0088] The sixth source-drain layer is connected to the sixth active layer through a sixth via. Specifically, there can be two sixth vias. The first and second terminals of the sixth transistor T6 in the sixth source-drain layer are connected to the source and drain regions in the sixth active layer through two sixth vias.

[0089] In one embodiment, the array film structure 20 further includes a film structure of a seventh transistor T7, which is an anode reset transistor. The film structure of the seventh transistor T7 includes a seventh active layer, a seventh gate layer, and a seventh source-drain layer. The seventh active layer, the seventh gate layer, and the seventh source-drain layer are stacked sequentially along the direction away from the substrate 10, and the seventh source-drain layer is connected to the seventh active layer through a seventh via. The seventh active layer is disposed on the same layer as the first active layer 201a; the seventh gate layer is disposed on the same layer as the first gate layer 201b; and the seventh source-drain layer is disposed on the same layer as the first source-drain layer 201c.

[0090] The seventh active layer includes the channel layer of the seventh transistor T7 and the source and drain regions located on both sides of the channel layer of the seventh transistor T7. The material of the seventh active layer is the same as that of the first active layer 201a, which includes polysilicon, that is, the material of the channel layer of the seventh transistor T7 includes polysilicon, such as PSI.

[0091] The seventh gate layer includes the gate of the seventh transistor T7. The material of the seventh gate layer is the same as that of the first gate layer 201b, including a metallic material, such as at least one of aluminum, molybdenum, copper, titanium or ITO.

[0092] The seventh source-drain layer includes a first electrode and a second electrode of the seventh transistor T7, wherein the first electrode of the seventh transistor T7 is one of the source and the drain, and correspondingly, the second electrode of the seventh transistor T7 is the other of the drain and the source. The material of the seventh source-drain layer is the same as that of the first source-drain layer 201c, including a metallic material, such as at least one of aluminum, molybdenum, copper, titanium, or ITO.

[0093] The seventh source-drain layer is connected to the seventh active layer through a seventh via. Specifically, there can be two seventh vias. The first and second terminals of the seventh transistor T7 in the seventh source-drain layer are connected to the source and drain regions in the seventh active layer through two seventh vias.

[0094] In one embodiment, such as Figure 3 and Figure 4 As shown, two pixel circuits are provided, in which the fourth transistor T4 is connected in different ways. The gate layer of each transistor includes the gate of the transistor, and the source-drain layer of each transistor includes the first and second terminals of the transistor; the top gate layer of each transistor includes the gate of the transistor.

[0095] The gate of the first transistor T2 is connected to the first scan signal line S2, the first terminal of the first transistor T2 is connected to the data signal line data, and the second terminal of the first transistor T2 is connected to the first terminal of the third transistor T1. The gate of the second transistor T3 is connected to the second scan signal line S3, the first terminal of the second transistor T3 is connected to the first terminal of the storage capacitor C1, and the second terminal of the second transistor T3 is connected to the second terminal of the third transistor T1; the gate of the third transistor T1 is connected to the first terminal of the storage capacitor C1.

[0096] The gate of the fourth transistor T4 is connected to the third scan signal line S1, and the second terminal of the fourth transistor T4 is connected to the first reset signal line Vref1; the first terminal of the fourth transistor T4 is connected to the first terminal of the second transistor T3, as shown below. Figure 3 As shown, or the first terminal of the fourth transistor T4 is connected to the second terminal of the second transistor T3, as... Figure 4 As shown.

[0097] The gate of the fifth transistor T5 is connected to the light-emitting control signal line EM. The first terminal of the fifth transistor T5 is connected to the second terminal of the storage capacitor C1 and the power supply signal line VDD. The second terminal of the fifth transistor T5 is connected to the first terminal of the third transistor T1. The gate of the sixth transistor T6 is connected to the light-emitting control signal line EM. The first terminal of the sixth transistor T6 is connected to the second terminal of the third transistor T1. The second terminal of the sixth transistor T6 is connected to the first electrode 601 of the light-emitting device 60. The second electrode of the light-emitting device 60 is connected to the power supply signal line VSS.

[0098] The gate of the seventh transistor T7 is connected to the fourth scan signal line S4, the first electrode of the seventh transistor is connected to the second reset signal line Vref1, and the second electrode of the seventh transistor T7 is connected to the first electrode of the light-emitting device.

[0099] The second transistor T3 and the fourth transistor T4 are P-type transistors, while the third transistor T1, the first transistor T2, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 are N-type transistors.

[0100] The layouts of the two pixel circuits mentioned above are as follows: Figure 5 As shown, the layout of the first metal layer M1 and the active layers (PSI layers) of the third transistor T1, the first transistor T2, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 is as follows. Figure 6 As shown. The layout of the second metal layer M2 and the third metal layer M3 (GATO layer) and the active layer (IGZO layer) of the second transistor T3 and the fourth transistor T4 is as follows. Figure 7A As shown, due to Figure 7A In the diagram, the M2 layer and the GATO layer are stacked. To make them easier to see, [the following text is missing]. Figure 7A Split into Figure 7B and Figure 7C .

[0101] by Figure 3 Taking the pixel circuit shown as an example, the operation flow of the pixel circuit includes a reset stage, a threshold voltage compensation stage, and a light-emitting stage. In the reset stage, the fourth transistor T4 is turned on, and the first transistor T2, second transistor T3, fifth transistor T5, sixth transistor T6, and seventh transistor T7 are turned off. In the threshold voltage compensation stage, the third transistor T1, first transistor T2, second transistor T3, and seventh transistor T7 are turned on, and the fourth transistor T4, fifth transistor T5, and sixth transistor T6 are turned off. In the light-emitting stage, the third transistor T1, fifth transistor T5, and sixth transistor T6 are turned on, and the first transistor T2, second transistor T3, fourth transistor T4, and seventh transistor T7 are turned off.

[0102] In one embodiment, this application also provides a display panel, referring to Figure 2 As shown, the display panel includes the array substrate, pixel definition layer, light-emitting device, and support member described in any of the above-mentioned embodiments.

[0103] In one embodiment, this application also provides a display device, which includes the display panel described in the above-described display panel embodiments. The display device can be a laptop computer, mobile phone, wireless device, personal digital assistant (PDA), handheld or portable computer, GPS receiver / navigator, camera, MP4 video player, camcorder, game console, watch, clock, calculator, television monitor, flat panel display, computer monitor, automotive display (e.g., odometer display), navigator, cockpit controller and / or display, camera view display (e.g., display of a rearview camera in a vehicle), electronic photograph, electronic billboard or sign, projector, etc.

[0104] The above embodiments are merely illustrative of several implementation methods of this application, and their descriptions are relatively specific and detailed. However, they should not be construed as limiting the scope of this application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this application should be determined by the appended claims.

Claims

1. An array substrate, characterized in that, The array substrate includes: substrate; An array of film layers is disposed on one side of the substrate, including a film layer structure of a first transistor and a film layer structure of a second transistor; the first transistor is a data writing transistor, and the second transistor is a threshold compensation transistor. The first transistor has a film structure comprising a first active layer, a first gate layer, and a first source / drain layer; the second transistor has a film structure comprising a first top gate layer, a second active layer, a first bottom gate layer, and a second source / drain layer; the first active layer, the first gate layer, the first bottom gate layer, the second active layer, and the first top gate layer are sequentially stacked along a direction away from the substrate, wherein the orthographic projection of the first active layer on the substrate and the orthographic projection of the second active layer on the substrate at least partially overlap; the first source / drain layer and the second source / drain layer are both disposed on the side of the first top gate layer away from the substrate, the first source / drain layer is connected to the first active layer through a first via, and the second source / drain layer is connected to the second active layer through a second via.

2. The array substrate according to claim 1, characterized in that, The material of the first active layer includes polycrystalline silicon; the material of the second active layer includes metal oxide.

3. The array substrate according to claim 1, characterized in that, The first gate layer and the first bottom gate layer form a storage capacitor.

4. The array substrate according to claim 3, characterized in that, The array film structure also includes a third transistor film structure, wherein the third transistor is a driving transistor; The film structure of the third transistor includes a third active layer, a third gate layer, and a third source-drain layer; the third active layer, the third gate layer, and the third source-drain layer are stacked sequentially along the direction away from the substrate, and the third source-drain layer is connected to the third active layer through a third via. The third active layer is disposed on the same layer as the first active layer; the third gate layer is disposed on the same layer as the first gate layer; and the third source-drain layer is disposed on the same layer as the first source-drain layer.

5. The array substrate according to claim 4, characterized in that, The array film structure also includes a fourth transistor film structure, wherein the fourth transistor is a gate reset transistor; The film structure of the fourth transistor includes a second bottom gate layer, a fourth active layer, a second top gate layer, and a fourth source / drain layer; Along a direction away from the substrate, the second bottom gate layer, the fourth active layer, the second top gate layer, and the fourth source-drain layer are stacked sequentially, and the fourth source-drain layer is connected to the fourth active layer through a fourth via. The fourth active layer is disposed on the same layer as the second active layer; the second top gate layer is disposed on the same layer as the first top gate layer; the second bottom gate layer is disposed on the same layer as the first bottom gate layer; and the fourth source-drain layer is disposed on the same layer as the second source-drain layer.

6. The array substrate according to claim 5, characterized in that, The array film structure also includes a fifth transistor film structure, wherein the fifth transistor is a light-emitting control transistor; The film structure of the fifth transistor includes a fifth active layer, a fifth gate layer, and a fifth source / drain layer; Along a direction away from the substrate, the fifth active layer, the fifth gate layer, and the fifth source-drain layer are stacked sequentially, and the fifth source-drain layer is connected to the fifth active layer through a fifth via. The fifth active layer is disposed on the same layer as the first active layer; the fifth gate layer is disposed on the same layer as the first gate layer; and the fifth source-drain layer is disposed on the same layer as the first source-drain layer.

7. The array substrate according to claim 6, characterized in that, The array film structure also includes a sixth transistor film structure, wherein the sixth transistor is a light-emitting control transistor; The film structure of the sixth transistor includes a sixth active layer, a sixth gate layer, and a sixth source-drain layer; the sixth active layer, the sixth gate layer, and the sixth source-drain layer are stacked sequentially along the direction away from the substrate, and the sixth source-drain layer is connected to the sixth active layer through a sixth via. The sixth active layer is disposed on the same layer as the first active layer; the sixth gate layer is disposed on the same layer as the first gate layer; and the sixth source-drain layer is disposed on the same layer as the first source-drain layer.

8. The array substrate according to claim 7, characterized in that, The array film structure also includes a film structure of a seventh transistor, which is an anode reset transistor; The film structure of the seventh transistor includes a seventh active layer, a seventh gate layer, and a seventh source / drain layer. Along a direction away from the substrate, the seventh active layer, the seventh gate layer, and the seventh source-drain layer are stacked sequentially, and the seventh source-drain layer is connected to the seventh active layer through a seventh via. The seventh active layer is disposed on the same layer as the first active layer; the seventh gate layer is disposed on the same layer as the first gate layer; and the seventh source-drain layer is disposed on the same layer as the first source-drain layer.

9. The array substrate according to claim 8, characterized in that, The gate layer of each transistor includes the gate of the transistor, and the source and drain layers of each transistor include the first and second terminals of the transistor. The gate of the first transistor is connected to the first scan signal line, the first terminal of the first transistor is connected to the data signal line, and the second terminal of the first transistor is connected to the first terminal of the third transistor. The gate of the second transistor is connected to the second scan signal line, the first terminal of the second transistor is connected to the first terminal of the storage capacitor, and the second terminal of the second transistor is connected to the second terminal of the third transistor. The gate of the third transistor is connected to the first terminal of the storage capacitor; The gate of the fourth transistor is connected to the third scan signal line, the first terminal of the fourth transistor is connected to the first terminal of the second transistor or the second terminal of the second transistor, and the second terminal of the fourth transistor is connected to the first reset signal line; The gate of the fifth transistor is connected to the light-emitting control signal line, the first terminal of the fifth transistor is connected to the second terminal of the storage capacitor and the power supply signal line, and the second terminal of the fifth transistor is connected to the first terminal of the third transistor. The gate of the sixth transistor is connected to the light-emitting control signal line, the first terminal of the sixth transistor is connected to the second terminal of the third transistor, and the second terminal of the sixth transistor is connected to the light-emitting device. The gate of the seventh transistor is connected to the fourth scan signal line, the first electrode of the seventh transistor is connected to the second reset signal line, and the second electrode of the seventh transistor is connected to the light-emitting device.

10. A display panel, characterized in that, The display panel includes an array substrate as described in any one of claims 1 to 9.

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