Array substrate, method for manufacturing array substrate, and display panel

Abstract

Embodiments of the present application provide an array substrate, a preparation method of the array substrate and a display panel. The array substrate comprises a substrate and a plurality of first transistors. The plurality of first transistors are arranged on the substrate. The first transistor comprises an active layer, a first gate, a first insulating layer and a second insulating layer. The active layer comprises a first surface, a second surface and a first side surface. The first surface is located on a side of the second surface close to the substrate. The first side surface connects the first surface and the second surface. The first gate is arranged on a side of the active layer away from the substrate. The first insulating layer is at least partially located between the active layer and the first gate. The first insulating layer is stacked on the second surface and between the insulating layer and the first gate. Part of the second insulating layer covers the first side surface. In the present application, the performance and reliability of the first transistor in the array substrate are improved by arranging the first insulating layer and the second insulating layer.

Description

Technical Field

[0001] This application relates to the field of display device technology, and in particular to an array substrate, a method for preparing the array substrate, and a display panel. Background Technology

[0002] The array substrate is an important component of the display panel. Multiple thin-film transistors (TFTs) are disposed in the array substrate. The light emission of the light-emitting devices in the display panel is controlled by controlling the current flowing through the thin-film transistors.

[0003] In related technologies, the active layer of the thin-film transistor (TFT) is fabricated first, followed by the gate insulating layer. During the fabrication of the active layer, the surface of the active layer that contacts the gate insulating layer is easily contaminated, thereby reducing the carrier concentration distribution during TFT operation and resulting in uneven brightness of the display panel. Summary of the Invention

[0004] This application provides an array substrate, a method for fabricating the array substrate, and a display panel, aiming to improve the technical problem of uneven light emission brightness in the display panel when the array substrate is applied to the display panel.

[0005] An embodiment of the first aspect of this application provides an array substrate, including a substrate and a plurality of first transistors, wherein the plurality of first transistors are disposed on the substrate, and the first transistors include:

[0006] An active layer is disposed on one side of a substrate. The active layer includes a first surface, a second surface, and a first side surface. The first surface is located on the side of the second surface closer to the substrate, and the first side surface connects the first surface and the second surface.

[0007] The first gate is disposed on the side of the active layer away from the substrate;

[0008] A first insulating layer is located at least partially between the active layer and the first gate, and the first insulating layer is stacked on the second surface, wherein the orthographic projection of the second surface onto the substrate is located within the orthographic projection of the first insulating layer onto the substrate.

[0009] A second insulating layer is disposed on the side of the active layer away from the substrate, a portion of the second insulating layer is located between the first insulating layer and the first gate, and a portion of the second insulating layer covers the first side surface.

[0010] According to any of the foregoing embodiments of the first aspect of this application, the first insulating layer includes a third surface, a fourth surface, and a second side surface, the third surface is in contact with the second surface, the fourth surface is located on the side of the third surface away from the substrate, the second side surface connects the third surface and the fourth surface, and a portion of the second insulating layer covers the second side surface.

[0011] According to any of the foregoing embodiments of the first aspect of this application, the orthographic projection of the first insulating layer onto the substrate is located within the orthographic projection of the active layer onto the substrate;

[0012] According to any of the foregoing embodiments of the first aspect of this application, the first side and the second side are smoothly connected.

[0013] According to any of the foregoing embodiments of the first aspect of this application, the second insulating layer includes a first insulating portion and a second insulating portion connected to each other, a fourth surface, a first insulating portion and a first gate are stacked in sequence, and the second insulating portion covers the first side surface and the second side surface.

[0014] According to any of the foregoing embodiments of the first aspect of this application, the active layer includes a channel region disposed opposite to the first gate, and the orthogonal projection of the channel region onto the substrate is located within the orthogonal projection of the second insulating layer onto the substrate.

[0015] According to any of the foregoing embodiments of the first aspect of this application, the array substrate further includes a buffer layer disposed between the substrate and the active layer, and the second insulating layer further includes a third insulating portion connected to the second insulating portion, the third insulating portion being in contact with the surface of the buffer layer away from the substrate.

[0016] According to any of the foregoing embodiments of the first aspect of this application, the thickness of the first insulating layer is H1, and the thickness of the second insulating layer is H2, where H1 < H2;

[0017] According to any of the foregoing embodiments of the first aspect of this application, 5nm≤H1≤50nm;

[0018] According to any of the foregoing embodiments of the first aspect of this application, the total thickness of the first insulating layer and the second insulating layer stacked between the first gate and the active layer is H3, 50nm≤H3≤200nm;

[0019] According to any of the foregoing embodiments of the first aspect of this application, the material used to prepare the first insulating layer is different from the material used to prepare the second insulating layer.

[0020] According to any of the foregoing embodiments of the first aspect of this application, the first transistor has a first via and a second via penetrating the first insulating layer and the second insulating layer;

[0021] The first transistor also includes:

[0022] The source-drain conductive layer includes a source electrode and a drain electrode spaced apart. The source electrode is connected to the source region of the active layer through a first via, and the drain electrode is connected to the drain region of the active layer through a first via.

[0023] According to any of the foregoing embodiments of the first aspect of this application, the active layer is an oxide;

[0024] According to any of the foregoing embodiments of the first aspect of this application, the active layer is prepared using one or more of indium oxide, zinc oxide, indium gallium zinc oxide, indium zinc oxide, gallium indium zinc tin oxide, and aluminum indium zinc oxide.

[0025] According to any of the foregoing embodiments of the first aspect of this application, the array substrate includes a pixel driving circuit, the pixel driving circuit includes a plurality of thin film transistors, the plurality of thin film transistors includes a driving transistor, and the driving transistor is a first transistor.

[0026] According to any of the foregoing embodiments of the first aspect of this application, the driving transistor further includes:

[0027] The source-drain conductive layer includes a source electrode and a drain electrode spaced apart, wherein the source electrode is connected to the source region of the active layer and the drain electrode is connected to the drain region of the active layer.

[0028] A shielding metal layer is located between the active layer and the substrate, and the source electrode is connected to the shielding metal layer via a via.

[0029] According to any of the foregoing embodiments of the first aspect of this application, a plurality of thin-film transistors include a switching transistor, wherein the first transistor is a switching transistor;

[0030] According to any of the foregoing embodiments of the first aspect of this application, the switching transistor further includes:

[0031] The second gate is located between the active layer and the substrate.

[0032] An embodiment of the second aspect of this application also provides a method for fabricating an array substrate, comprising:

[0033] Take a substrate and sequentially form an active material layer and a first insulating material layer on the substrate;

[0034] The active material layer and the first insulating material layer are patterned to obtain the active layer and the first insulating layer;

[0035] A second insulating layer is formed on the substrate, the second insulating layer covering the active layer and the first insulating layer;

[0036] A first gate material layer is formed on the second insulating layer, and the first gate material layer is patterned to obtain the first gate.

[0037] According to any of the foregoing embodiments of the second aspect of this application, patterning the active material layer and the first insulating material layer to obtain the active layer and the first insulating layer includes:

[0038] A patterned first mask layer is formed on a first insulating material layer, the first mask layer covering a portion of the first insulating material layer;

[0039] Using the first mask layer as a mask, the first insulating material layer is etched to form the first insulating layer;

[0040] Using the first mask layer as a mask, the active material layer is etched to form the active layer;

[0041] Remove the first mask layer.

[0042] According to any of the foregoing embodiments of the second aspect of this application, after forming a first gate material layer on a second insulating layer, patterning the first gate layer to obtain a first gate, the process includes:

[0043] The second insulating layer and the first insulating layer are made to form a first via and a second via that penetrate the second insulating layer and the first insulating layer, and the first via and the second via expose the active layer.

[0044] A source-drain conductive layer is formed, which includes a source electrode and a drain electrode spaced apart. The source electrode is connected to the active layer through a first via, and the drain electrode is connected to the active layer through a first via.

[0045] The third aspect of this application also provides a display panel, including an array substrate of any of the first aspects described above, or an array substrate prepared by the preparation method of the array substrate of any of the first aspects described above.

[0046] In the array substrate, array substrate fabrication method, and display panel provided in this application embodiment, a first insulating layer is stacked on a second surface, and the orthographic projection of the second surface onto the substrate lies within the orthographic projection of the first insulating layer onto the substrate. This allows the pre-stacked active material layer and the first insulating material layer to be patterned together to obtain the first insulating layer and the active layer. This reduces or avoids damage to the second surface of the active layer when fabricating the active layer separately, and also reduces or avoids residual impurities on the second surface, improving the carrier concentration distribution when the first transistor is working, and improving the uniformity of the light emission brightness of the display panel using the thin-film crystal light. By setting a portion of the second insulating layer between the first insulating layer and the first gate, the thickness of the insulating layer distributed between the active layer and the first gate is increased, avoiding leakage current between the active layer and the first gate. By setting a portion of the second insulating layer to cover the first side, carrier crosstalk between the active layer and adjacent structures is reduced or avoided. Attached Figure Description

[0047] To more clearly illustrate the technical solutions of the embodiments of this application, the drawings used in the embodiments of this application will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0048] Figure 1 This is a partial cross-sectional structural diagram of a display panel provided in some embodiments of this application;

[0049] Figure 2 This is a partial cross-sectional structural diagram of the array substrate provided in some embodiments of this application;

[0050] Figure 3 This is a partial cross-sectional structural diagram of the array substrate provided in some embodiments of this application;

[0051] Figure 4 This is a partial cross-sectional structural diagram of the array substrate provided in some embodiments of this application;

[0052] Figure 5 This is a partial cross-sectional structural diagram of the array substrate provided in some embodiments of this application;

[0053] Figure 6 This is a schematic diagram of a portion of the process flow of the array substrate fabrication method provided in some embodiments of this application;

[0054] Figure 7 This is a schematic diagram of a portion of the process flow of the array substrate fabrication method provided in some embodiments of this application.

[0055] Explanation of reference numerals in the attached figures:

[0056] 100. Array substrate; 200. Light-emitting device;

[0057] 1. Substrate; 2. First transistor; 21. Active layer; 211. First surface; 212. Second surface; 213. First side surface; 214. Source region; 215. Drain region; 216. Channel region; 22. First gate; 23. First insulating layer; 231. Third surface; 232. Fourth surface; 233. Second side surface; 24. Second insulating layer; 241. First insulating portion; 242. Second insulating portion; 243. Third insulating portion; 25. First via; 26. Second via; 27. Source / drain conductive layer; 271. Source; 272. Drain; 28. Planarization layer; 29. ​​Buffer layer; 30. Interlayer dielectric layer; 31. Shielding metal layer; 32. Second gate; 33. Third via;

[0058] X, the first direction. Detailed Implementation

[0059] The features and exemplary embodiments of various aspects of this application will now be described in detail. To make the objectives, technical solutions, and advantages of this application clearer, the application will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are only configured to explain this application and are not configured to limit this application. For those skilled in the art, this application can be implemented without some of these specific details. The following description of the embodiments is merely to provide a better understanding of this application by illustrating examples of this application.

[0060] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising..." does not exclude the presence of additional identical elements in the process, method, article, or apparatus that includes the element.

[0061] It should be understood that when describing the structure of a component, when referring to a layer or region as being "above" or "on top of" another layer or region, it can mean that it is directly above the other layer or region, or that it contains other layers or regions between it and the other layer or region. Furthermore, if the component is flipped over, that layer or region will be located "below" or "under" the other layer or region.

[0062] The array substrate is an important component of the display panel. Multiple thin-film transistors are disposed in the array substrate, and the light-emitting devices in the display panel are controlled by controlling the current flowing through the thin-film transistors.

[0063] In related technologies, the active layer of the thin-film transistor (TFT) is fabricated first, followed by the gate insulating layer. During the fabrication of the active layer, the surface of the active layer that contacts the gate insulating layer is easily contaminated, thereby reducing the carrier concentration distribution during TFT operation and resulting in uneven brightness of the display panel.

[0064] For example, the process of fabricating an active layer includes: first, setting up a semiconductor material; then, coating the semiconductor material with photoresist; finally, etching the semiconductor material with patterned photoresist to form the active layer; and then removing the photoresist. Both coating and removing the photoresist on the semiconductor material can cause surface damage or residual contaminants in the active layer, thereby reducing the carrier concentration distribution during thin-film transistor operation.

[0065] To address the aforementioned issues, this application provides an array substrate, a method for fabricating the array substrate, and a display panel. The following description, in conjunction with the accompanying drawings, will illustrate various embodiments of the array substrate, the method for fabricating the array substrate, and the display panel.

[0066] The first aspect of this application provides an array substrate 100, such as... Figure 1 and Figure 2 As shown, an array substrate 100 includes a substrate 1 and a plurality of first transistors 2. The plurality of first transistors 2 are disposed on the substrate 1. Each first transistor 2 includes an active layer 21, a first gate 22, a first insulating layer 23, and a second insulating layer 24. The active layer 21 is disposed on one side of the substrate 1. The active layer 21 includes a first surface 211, a second surface 212, and a first side surface 213. The first surface 211 is located on the side of the second surface 212 that is close to the substrate 1. The first side surface 213 connects the first surface 211 and the second surface 212. The first gate 22 is disposed on the side of the active layer 21 away from the substrate 1; the first insulating layer 23 is at least partially located between the active layer 21 and the first gate 22, the first insulating layer 23 is stacked on the second surface 212, and the orthographic projection of the second surface 212 onto the substrate 1 is located within the orthographic projection of the first insulating layer 23 onto the substrate 1; the second insulating layer 24 is disposed on the side of the active layer 21 away from the substrate 1, a portion of the second insulating layer 24 is located between the first insulating layer 23 and the first gate 22, and a portion of the second insulating layer 24 covers the first side surface 213.

[0067] This application provides an array substrate 100 that can be used in a display panel, which can be an organic light-emitting diode (OLED) based display panel, a light-emitting diode (LED) based display panel, etc. The display panel also includes multiple light-emitting devices 200, each capable of emitting different colors of light to achieve light emission and display. The light-emitting devices 200 can be red light-emitting devices 200, blue light-emitting devices 200, and green light-emitting devices 200. The array substrate 100 and the device layer on which the multiple light-emitting devices 200 are disposed are stacked along a first direction X.

[0068] The substrate 1 can be a flexible or inflexible plate. The substrate 1 is used to support the first transistor 2. The substrate 1 can be one of polyimide (PI), polyamide (PA), polycarbonate (PC), polyethersulfone (PES), polyethylene terephthalate (PET), polyethylene naphthalate (PEN), polymethyl methacrylate (PMMA), or cycloolelin copolymer (COC).

[0069] The array substrate 100 has patterned conductive layers, patterned semiconductor layers, insulating layers, etc., formed on the substrate 1. Multiple conductive and semiconductor layers are interconnected to form a pixel driving circuit. The pixel driving circuit includes thin-film transistors, storage capacitors, etc. The thin-film transistor can be a first transistor. The storage capacitor includes a first electrode and a second electrode. The pixel driving circuit is electrically connected to the light-emitting device 200, and controls the light-emitting device 200 to emit light.

[0070] The active layer 21 is fabricated using a semiconductor material. The active layer 21 includes a source region 214 and a drain region 215 disposed at its two ends, and a channel region 216 disposed between the source region 214 and the drain region 215. The channel region 216 and the first gate 22 are disposed at a distance from each other. A first insulating layer 23 and a second insulating layer 24 can be stacked between the channel region 216 and the first gate 22. The orthographic projection of the second surface 212 onto the substrate 1 lies within the orthographic projection of the first insulating layer 23 onto the substrate 1, meaning the first insulating layer 23 shields one side of the source region 214, the drain region 215, and the channel region 216.

[0071] In this embodiment, the first transistor 2 further includes a source 271 and a drain 272. The first transistor 2 can be a top-gate transistor, that is, the source 271 and the drain are disposed on the same side of the first gate 22 opposite to the active layer 21. The source 271 and the drain 272 are electrically connected to the source region 214 and the drain region 215 of the active layer 21, respectively.

[0072] When preparing the array substrate 100 provided in this application, an active material layer and a first insulating material layer can be sequentially formed on the substrate 1. Photoresist is then applied to the side of the first insulating material layer away from the active material layer. The active material layer and the first insulating material layer are patterned together using the photoresist to obtain the active layer 21 and the first insulating layer 23.

[0073] Remove photoresist. Since the active layer 21 and the first insulating layer 23 are stacked, the process of removing photoresist reduces or avoids damage to the contact surface between the active layer 21 and the first insulating layer 23, and also reduces or avoids the presence of impurities on the contact surface between the active layer 21 and the first insulating layer 23.

[0074] A second insulating layer 24 is then formed on substrate 1, covering the active layer 21 and the first insulating layer 23. This allows the second insulating layer 24 to be disposed between the first insulating layer 23 and the first gate 22, thereby improving the insulation between the first gate 22 and the active layer 21. The second insulating layer 24 also covers the first side 213 of the active layer 21, thereby reducing or preventing carrier crosstalk between the active layer 21 and adjacent structures. Finally, the first gate 22, source 271, drain 272, etc., are formed on the second insulating layer 24. Adjacent structures can be other thin-film crystal optical components, storage capacitors, signal lines, etc.

[0075] In the embodiments provided in this application, by stacking the first insulating layer 23 on the second surface 212, the pre-stacked active material layer and the first insulating material layer can be patterned together to obtain the first insulating layer 23 and the active layer 21. This reduces or avoids damage to the second surface 212 of the active layer 21 when the active layer 21 is fabricated separately, and also reduces or avoids residual impurities on the second surface 212, improving the carrier concentration distribution when the first transistor 2 is working and improving the uniformity of the light emission brightness of the display panel using the first transistor 2. By setting a portion of the second insulating layer 24 between the first insulating layer 23 and the first gate 22, the thickness of the insulating layer distributed between the active layer 21 and the first gate 22 is increased, avoiding leakage current between the active layer 21 and the first gate 22. By setting a portion of the second insulating layer 24 to cover the first side surface 213, carrier crosstalk between the active layer 21 and adjacent structures is reduced or avoided.

[0076] Please refer to the following: Figure 3 In some embodiments, the first insulating layer 23 includes a third surface 231, a fourth surface 232, and a second side surface 233. The third surface 231 is in contact with the second surface 212, the fourth surface 232 is located on the side of the third surface 231 away from the substrate 1, the second side surface 233 connects the third surface 231 and the fourth surface 232, and a portion of the second insulating layer 24 covers the second side surface 233.

[0077] A first insulating layer 23 is stacked on the active layer 21, and the third surface 231 of the first insulating layer 23 is in contact with the second surface 212 of the active layer 21. During the fabrication of the active layer 21 and the first insulating layer 23, after etching the pre-stacked active material layer and the first insulating material layer, the portion of the active material layer facing away from the first insulating material layer is retained, forming the first surface 211; the portion of the active material layer close to the first insulating material layer is retained, forming the second surface 212; the portion of the first insulating material layer close to the active material layer is retained, forming the third surface 231; and the portion of the first insulating material layer facing away from the active material layer is retained, forming the fourth surface 232. Etching is performed on the active material layer and the first insulating layer to form the first side surface 213 and the second side surface 233.

[0078] After the active layer 21 and the first insulating layer 23 are fabricated, a second insulating material is provided to cover the active layer 21 and the first insulating layer 23, such that a portion of the second insulating layer 24 covers the second side surface 233, thereby improving the uniformity of the light emission brightness of the display panel using the first transistor 2; by providing a portion of the second insulating layer 24 between the first insulating layer 23 and the first gate 22, the thickness of the insulating layer distributed between the active layer 21 and the first gate 22 is increased, avoiding leakage current between the active layer 21 and the first gate 22; by providing a portion of the second insulating layer 24 to cover the first side surface 213, carrier crosstalk between the active layer 21 and adjacent structures through the second surface 212 is reduced or avoided.

[0079] In some embodiments, the orthographic projection of the first insulating layer 23 onto the substrate 1 lies within the orthographic projection of the active layer 21 onto the substrate 1.

[0080] Dry etching can be performed on the pre-stacked active material layer and the first insulating material layer to prepare the active layer 21 and the first insulating layer 23, such that the orthographic projection of the prepared first insulating layer 23 onto the substrate 1 lies within the orthographic projection of the active layer 21 onto the substrate 1. Optionally, the orthographic projection of the edge of the first insulating layer 23 onto the substrate 1 overlaps with the orthographic projection of the edge of the active layer 21 onto the substrate 1, that is, the active layer 21 and the first insulating layer 23 have the same shape and the same outer contour size.

[0081] In some embodiments, the first side 213 and the second side 233 are smoothly connected.

[0082] Since the first side 213 and the second side 233 are obtained through patterning, after the pre-stacked active material layer and the first insulating material layer are dry-etched together with the same photoresist, the first side 213 and the second side 233 are smoothly connected, which is beneficial for the subsequent fabrication of the second insulating layer 24 to cover the first side 213 and the second side 233.

[0083] Optionally, the surface formed by connecting the first side surface 213 and the second side surface 233 is arranged perpendicularly or obliquely relative to the substrate 1. When the surface formed by connecting the first side surface 213 and the second side surface 233 is obliquely arranged relative to the substrate 1, the orthographic projection of the second surface 212 on the substrate 1 is located within the orthographic projection of the first surface 211 on the substrate 1, and the orthographic projection of the fourth surface 232 on the substrate 1 is located within the orthographic projection of the third surface 231 on the substrate 1.

[0084] In some embodiments, the second insulating layer 24 includes a first insulating portion 241 and a second insulating portion 242 connected to each other, the fourth surface 232, the first insulating portion 241 and the first gate 22 are stacked in sequence, and the second insulating portion 242 covers the first side surface 213 and the second side surface 233.

[0085] The first insulating portion 241 is stacked on the fourth surface 232, and the second insulating portion 242 covers the second side surface 233, so that the second insulating layer 24 can cover the stacked active layer 21 and the first insulating layer 23.

[0086] Please refer to the following: Figure 4 In some embodiments, the active layer 21 includes a channel region 216 disposed opposite to the first gate 22, and the orthographic projection of the channel region 216 onto the substrate 1 lies within the orthographic projection of the second insulating layer 24 onto the substrate 1.

[0087] The orthographic projection of the channel region 216 onto the substrate 1 lies within the orthographic projection of the second insulating layer 24 onto the substrate 1, ensuring that the second insulating layer 24 covers the channel region 216. The orthographic projection of the first insulating layer 23 onto the substrate 1 lies within the orthographic projection of the second insulating layer 24 onto the substrate 1, ensuring that the second insulating layer 24 can cover the first insulating layer 23.

[0088] In some embodiments, the array substrate 100 further includes a buffer layer 29 disposed between the substrate 1 and the active layer 21, and the second insulating layer 24 further includes a third insulating portion 243 connected to the second insulating portion 242, the third insulating portion 243 being in contact with the surface of the buffer layer 29 away from the substrate 1.

[0089] The buffer layer 29 can serve as a transition layer to alleviate the physical and chemical differences between the substrate 1 and the active layer 21, thereby reducing the interface state density. The buffer layer 29 can block the diffusion or leakage of charge carriers, thereby reducing the leakage current of the first transistor 2, improving the reliability and power consumption performance of the first transistor 2, and extending the lifespan of the first transistor 2.

[0090] The first insulating portion 241, the second insulating portion 242, and the third insulating portion 243 can be disposed together to form a second insulating layer 24 covering the entire surface. The second insulating layer 24 can be formed on an intermediate material used to fabricate the array substrate 100 using a chemical vapor deposition (CVD) process. Part of the second insulating material falls on the fourth surface 232 to form the first insulating portion 241; part of the second insulating material falls on the first side surface 213 and the second side surface 233 to form the second insulating portion 242; and part of the second insulating material falls on the surface of the buffer layer 29 not shielded by the active layer 21 to form the third insulating portion 243. The third insulating portion 243 is fabricated to facilitate the continued fabrication of other first transistor 2 structures or storage capacitor structures on the third insulating portion 243.

[0091] In some embodiments, the thickness of the first insulating layer 23 is H1, the thickness of the second insulating layer 24 is H2, and H1 < H2.

[0092] The total thickness of the stacked first insulating layer 23 and the second insulating layer 24 is the sum of H1 and H2, meaning that there is at least an insulating material thickness of H1 + H2 between the first gate 22 and the active layer 21. When fabricating the active layer 21 and the first insulating layer 23, the pre-stacked active material layer and the first insulating material layer are etched together, so that the thickness of the layer structure to be etched is the sum of the thicknesses of the active material layer and the first insulating layer. Maintaining a constant thickness of the active material layer ensures that the thickness of the fabricated active layer 21 remains constant. Reducing the thickness of the first insulating material layer reduces the thickness of the pre-stacked active material layer and the first insulating layer, reducing the difficulty of etching the active layer 21 and the first insulating layer 23 and improving the consistency of the etching process.

[0093] While ensuring sufficient insulating material between the first gate 22 and the active layer 21, the thickness of the first insulating layer 23 is reduced, the thickness of the second insulating layer 24 is increased, and H1 < H2 is set, thereby reducing the difficulty of etching to form the active layer 21 and the first insulating layer 23.

[0094] In some embodiments, 5nm ≤ H1 ≤ 50nm.

[0095] A smaller H1 indicates uneven distribution of the first insulating material layer used to prepare the first insulating layer 23 on the active material layer. This can easily lead to parts of the active material layer not being covered by the first insulating material layer, causing damage to the uncovered portions of the active material layer during the fabrication process. A larger H1 increases the total thickness of the first insulating material layer and the active material layer, making it more difficult to etch and form the active layer 21 and the first insulating layer 23. Setting H1 to 5nm ≤ H1 ≤ 50nm balances the uniform coverage of the active material layer by the first insulating material layer with reducing the difficulty of etching and forming the active layer 21 and the first insulating layer 23.

[0096] Optionally, H1 can be 5nm, 10nm, 25nm, 40nm, or 50nm.

[0097] In some embodiments, the total thickness of the first insulating layer 23 and the second insulating layer 24 stacked between the first gate 22 and the active layer 21 is H3, where 50nm≤H3≤200nm.

[0098] When only a first insulating layer 23 and a second insulating layer 24 are stacked between the first gate 22 and the active layer 21, H3 is equal to the spacing between the first gate 22 and the active layer 21. If H3 is too small, the insulating material distributed between the first gate 22 and the active layer 21 will be reduced, making it easier to break down the first insulating layer 23 and the second insulating layer 24, forming a conductive channel from the first gate 22 to the active layer 21, resulting in permanent damage to the first transistor 2. If H3 is too large, the voltage driving the first transistor 2 will increase, affecting the signal amplification capability of the first transistor 2, resulting in a decrease in gain during signal amplification. Setting 50nm≤H3≤200nm ensures that an insulating material of appropriate thickness is distributed between the first gate 22 and the active layer 21.

[0099] In some embodiments, the material used to prepare the first insulating layer 23 is the same as the material used to prepare the second insulating layer 24, in order to simplify the materials required to prepare the array substrate 100.

[0100] In some other embodiments, the material used to prepare the first insulating layer 23 is different from the material used to prepare the second insulating layer 24.

[0101] By setting the materials used to prepare the first insulating layer 23 and the second insulating layer 24 to be different, the different insulation properties, dielectric constants, and carrier blocking capabilities of the materials used to prepare the first insulating layer 23 and the second insulating layer 24 can be utilized to obtain different effects when the first insulating layer 23 and the second insulating layer 24 are distributed between the first gate 22 and the active layer 21.

[0102] In one embodiment, the materials used to prepare the first insulating layer 23 and the second insulating layer 24 are zirconium oxide (ZrO2) and silicon nitride (Si3N4), respectively. Zirconia has a high dielectric constant, which helps maintain good insulation properties. Silicon nitride has a high breakdown electric field strength, enabling it to withstand large electric fields without breakdown. By stacking silicon nitride and zirconium oxide, silicon nitride can provide good anti-breakdown properties, preventing the insulation material from failing under high voltage and ensuring the long-term stable operation of the first transistor 2.

[0103] In one embodiment, one of the materials used to prepare the first insulating layer 23 is hafnium oxide (HfO2), and the other is silicon dioxide (SiO2). Silicon dioxide has a lower dielectric constant than zirconium oxide. When hafnium oxide and silicon dioxide are stacked, the equivalent dielectric constant of the stacked first insulating layer 23 and second insulating layer 24 can be adjusted to different values ​​by changing the thickness ratio of silicon dioxide to zirconium oxide. When the first insulating layer 23 is made of silicon dioxide and the second insulating layer 24 is made of hafnium oxide, growing a thin layer of silicon dioxide on the active layer 21 followed by the growth of hafnium oxide can improve the interface states.

[0104] In some embodiments, the material used to prepare the first insulating layer 23 includes one or more of silicon oxide, silicon carbide, hafnium oxide, aluminum oxide, and zirconium oxide.

[0105] In some embodiments, the material used to prepare the second insulating layer 24 includes one or more of silicon oxide, silicon carbide, hafnium oxide, aluminum oxide, and zirconium oxide.

[0106] Hafnium-based oxides include, but are not limited to, HfO2, HfSiO, and HfSiON; aluminum-based oxides can be Al2O3; and zirconium-based oxides can be ZrO2.

[0107] In some implementations, the first transistor 2 has a first via 25 and a second via 26 penetrating the first insulating layer 23 and the second insulating layer 24; the first transistor 2 also includes a source-drain conductive layer 27, which includes a source 271 and a drain 272 spaced apart, the source 271 being connected to the source region 214 of the active layer 21 through the first via 25, and the drain 272 being connected to the drain region 215 of the active layer 21 through the first via 25.

[0108] After dry etching of the pre-stacked active material layer and the first insulating material layer to prepare the active layer 21 and the first insulating layer 23, a second insulating layer 24 and a first gate 22 are formed on the first insulating layer 23. Then, the first insulating layer 23 and the second insulating layer 24 are opened together to obtain the first via 25 that exposes the source region 214 and the second via 26 that exposes the drain region 215.

[0109] Through the first via 25 and the second via 26, the source and drain conductive layers 27 distributed on one side of the active layer 21 can be electrically connected to the source region 214 and the drain region 215.

[0110] In some embodiments, the first transistor 2 further includes an interlayer dielectric layer 30, which is located on the side of the second insulating layer 24 away from the substrate 1. The first gate 22 is located between the second insulating layer 24 and the interlayer dielectric layer 30, and the orthogonal projection of the first gate 22 onto the substrate 1 is located within the orthogonal projection of the interlayer dielectric layer 30 onto the substrate 1.

[0111] Before forming the interlayer dielectric layer 30, the source region 214 and the drain region 215 are doped with plasma. The portion between the source region 214 and the drain region 215 forms a channel region 216. The interlayer dielectric layer 30 (ILD) is disposed between the first gate 22 and the source / drain conductive layer, and can electrically insulate the first gate 22 and the source / drain conductive layer 27 to prevent short circuits between the first gate 22 and the source / drain conductive layer.

[0112] The source and drain conductive layers 27 are located on the side of the interlayer dielectric layer 30 away from the substrate 1. The first via 25 and the second via 26 penetrate the interlayer dielectric layer 30 respectively, so that the source 271 is connected to the source region 214 of the active layer 21 through the first via 25, and the drain 272 is connected to the drain region 215 of the active layer 21 through the first via 25.

[0113] In some embodiments, the array substrate 100 further includes a planarization layer 28 located on the side of the interlayer dielectric layer 30 away from the substrate, the planarization layer 28 covering the source / drain conductive layer 27 to planarize the source / drain conductive layer 27.

[0114] In some embodiments, the active layer 21 is an oxide layer, i.e., the first transistor 2 is an oxide transistor, in order to improve the electron mobility of the first transistor 2.

[0115] In some embodiments, the active layer 21 is prepared from one or more of indium oxide (In2O3), zinc oxide (ZnO), indium gallium zinc oxide (IGZO), indium zinc oxide (IZO), gallium indium zinc tin oxide (GIZTO), and aluminum indium zinc oxide (AIZO). Optionally, the active layer 21 is prepared from indium gallium zinc oxide.

[0116] In some embodiments, the array substrate 100 includes a pixel driving circuit, which includes a plurality of thin-film transistors, the plurality of thin-film transistors including a driving transistor, and the driving transistor being a first transistor 2.

[0117] In some embodiments of this application, the pixel driving circuit can be a 7T1C, 8T1C, or 9T1C circuit, where T represents the first transistor 2, the number preceding T indicates the number of first transistors 2, and C represents the storage capacitor, the number preceding C indicates the number of storage capacitors. For example, 7T1C represents 7 first transistors 2 and 1 storage capacitor. The multiple thin-film transistors in the pixel driving circuit include at least one driving transistor, the drain 272 of which is electrically connected to the anode 201 of the light-emitting device 200. The multiple thin-film transistors in the pixel driving circuit also include at least one switching transistor. When the driving transistor is the aforementioned first transistor 2, the switching transistor can be a polysilicon transistor.

[0118] The driving transistor also includes a source-drain conductive layer 27 and a shielding metal layer 31. The source-drain conductive layer 27 includes a source 271 and a drain 272 spaced apart. The source 271 is connected to the source region 214 of the active layer 21, and the drain 272 is connected to the drain region 215 of the active layer 21. The shielding metal layer 31 is located between the active layer 21 and the substrate 1, and the source 271 is connected to the shielding metal layer 31 via a via.

[0119] The shielding metal layer 31 can help adjust the electric field, thereby improving the migration efficiency of carriers in the active layer 21 and improving the electrical performance of the thin film transistor.

[0120] Please see Figure 5 In some embodiments, the plurality of thin-film transistors include a switching transistor, wherein the switching transistor is a first transistor 2.

[0121] The switching transistor and the driving transistor can be configured together as oxide transistors to improve the electrical performance of the array substrate 100.

[0122] In some embodiments, the switching transistor further includes a second gate 32 located between the active layer 21 and the substrate 1.

[0123] The carriers in the active layer 21 can be controlled by the first gate 22 and the second gate 32 together. The two gates can apply electric fields to the carriers in the active layer 21 from different directions, which enhances the control capability of the carriers, thereby improving the carrier mobility and reducing leakage current. Optionally, the active layer 21 and the second gate 32 are located on opposite sides of the buffer layer 29.

[0124] An embodiment of the second aspect of this application also provides a method for fabricating an array substrate, comprising:

[0125] S100, Take a substrate and sequentially form an active material layer and a first insulating material layer on the substrate;

[0126] S200, The active material layer and the first insulating material layer are patterned to obtain the active layer and the first insulating layer;

[0127] S300, a second insulating layer is formed on the substrate, the second insulating layer covering the active layer and the first insulating layer;

[0128] S400, a first gate material layer is formed on the second insulating layer, and the first gate material layer is patterned to obtain the first gate.

[0129] The array substrate 100 of any of the first aspects embodiments can be prepared using this array substrate preparation method.

[0130] The active material layer is used to prepare the active layer. It can be formed on the substrate using physical vapor deposition (PVD) technology. The active material layer can be an oxide such as IGZO or IZO. The first insulating material layer is used to prepare the first insulating layer. It can be formed on the active material layer using chemical vapor deposition technology. The first insulating material layer can be an insulating material such as silicon oxide or silicon nitride.

[0131] In S200, the stacked active material layer and the first insulating material layer can be patterned by wet etching, dry etching, etc., to obtain the active layer and the first insulating layer of the desired shape. It is also possible to simultaneously fabricate the active layer and the first insulating layer in multiple first transistors.

[0132] In S300, the second insulating layer is used to prepare the second insulating layer. It can be formed on the substrate using chemical vapor deposition (CVD) technology. The second insulating layer can be an insulating material such as silicon oxide or silicon nitride. The formed second insulating layer partially falls on the first insulating layer, partially on the second side of the first insulating layer and the first side of the active layer, and partially on the substrate not covered by the active layer. If a buffer layer has already been prepared on the substrate, the formed second insulating layer partially falls on the buffer layer not covered by the active layer. Because the second insulating layer 24 covers both the active layer and the first insulating layer, a portion of the second insulating layer is located between the first insulating layer and the first gate, and a portion of the second insulating layer covers the first side.

[0133] In S400, a first gate material layer is used to form a first gate. The first gate material layer can be a metal material such as Mo, Al, or Cu. The first gate material layer can be patterned by wet etching, dry etching, or other methods to obtain a first gate positioned opposite to the active layer.

[0134] In the embodiments provided in this application, by sequentially forming an active material layer and a first insulating material layer on a substrate, and then patterning the active material layer and the first insulating material layer to obtain an active layer and a first insulating layer, damage to the second surface of the active layer is reduced or avoided when the active layer is fabricated separately. This also reduces or avoids residual impurities on the second surface, improves the carrier concentration distribution when the first transistor is working, and improves the uniformity of the light emission brightness of the display panel using the thin-film crystal light. By forming a second insulating layer on the substrate, which covers the active layer and the first insulating layer 23, the thickness of the insulating layer distributed between the active layer and the first gate is increased, leakage current is avoided between the active layer and the first gate, and the second insulating layer partially covers the first side, thereby reducing or avoiding carrier crosstalk between the active layer and adjacent structures.

[0135] In some embodiments, S200 includes:

[0136] S210, a patterned first mask layer is formed on the first insulating material layer, the first mask layer covering a portion of the first insulating material layer;

[0137] S220, using the first mask layer as a mask, the first insulating material layer is etched to form the first insulating layer;

[0138] S230, using the first mask layer as a mask, the active material layer is etched to form the active layer 21;

[0139] S240, Remove the first mask layer.

[0140] A patterned first mask layer can be formed using photoresist, which can be either positive or negative. The following description uses a positive photoresist as an example.

[0141] In step S210, photoresist is applied to the first insulating material layer, and the area corresponding to the pre-prepared first insulating layer is exposed and developed to obtain a patterned first mask layer.

[0142] In S220 and S230, the area of ​​the first insulating material layer that is not covered by the first mask layer is first etched away until the active material layer is exposed, and then the exposed active material layer is etched away to obtain the first insulating layer and the active layer.

[0143] In S240, since the second surface of the active layer that contacts the first insulating layer is blocked by the first insulating layer, the operation of removing the first mask layer will not affect the second surface, nor will it leave any impurities on the second surface.

[0144] In some embodiments, after S400, the following is included:

[0145] S500, the second insulating layer and the first insulating layer are opened to obtain a first via and a second via that penetrate the second insulating layer and the first insulating layer, and the first via and the second via expose the active layer.

[0146] S600, forming a source-drain conductive layer, the source-drain conductive layer includes a source electrode and a source electrode spaced apart, the source electrode is connected to the active layer through a first via, and the source electrode is connected to the active layer through a first via.

[0147] Before or after S500, it also includes:

[0148] An interlayer dielectric layer is formed on the second insulating layer, and the interlayer dielectric layer covers the first gate.

[0149] In S500, the second insulating layer, the first insulating layer, and the interlayer dielectric layer can be simultaneously perforated to obtain a first via and a second via that penetrate the second insulating layer, the first insulating layer, and the interlayer dielectric layer.

[0150] In S500, the second insulating layer and the first insulating layer can also be perforated together to obtain a first via and a second via penetrating the second insulating layer and the first insulating layer. After the interlayer dielectric layer is prepared, the interlayer dielectric layer 30 is perforated to obtain a first via and a second via penetrating the interlayer dielectric layer.

[0151] In S600, a source-drain conductive layer can be set on the prepared interlayer dielectric layer. The source electrode is connected to the active layer through a first via.

[0152] Please see Figure 6 .like Figure 6 As shown in (a), a substrate 1 is taken, and a shielding metal layer 31 and a buffer layer 29 are pre-prepared on the substrate 1; an active material layer 21M and a first insulating material layer 23M are sequentially formed on the buffer layer 29, and photoresist 300 is disposed on the first insulating layer 23M. The first region of the photoresist 300 is exposed and developed; as shown in (a), a shielding metal layer 31 and a buffer layer 29 are pre-prepared on the substrate 1; an active material layer 21M and a first insulating material layer 23M are sequentially formed on the buffer layer 29, and a photoresist 300 is disposed on the first insulating layer 23M. The first region of the photoresist 300 is exposed and developed. Figure 6 As shown in (b), photoresist 300 retaining the first region was prepared; Figure 6 As shown in (c), the first insulating material layer 23M and the active material layer 21M are etched to remove the portions not covered by the photoresist 300, resulting in the first insulating layer 23 and the active layer 21; Figure 6 As shown in (d), the photoresist 300 is removed, so that the surface of the first insulating layer 23 facing away from the active layer 21 is exposed.

[0153] Please see Figure 7 .like Figure 7 As shown in (a), a second insulating layer 24 is formed on the buffer layer 29, and the second insulating layer 24 covers the active layer 21 and the first insulating layer 23; as Figure 7 As shown in (b), a first gate 22 is formed on the second insulating layer 24, and an interlayer dielectric layer 30 is formed on the second insulating layer 24, covering the first gate 22. Figure 7 As shown in (c), the interlayer dielectric layer 30, the second insulating layer 24, the first insulating layer 23, and a via are made to obtain a first via 25, a second via 26, and a third via 33 penetrating the interlayer dielectric layer 30, the second insulating layer 24, and the first insulating layer 23. The first via 25 exposes the source region 214, the second via 26 exposes the drain region 215, and the third via 33 exposes the shielding metal layer 31; as shown in (c), the interlayer dielectric layer 30, the second insulating layer 24, the first insulating layer 23, and a third via 33 expose the shielding metal layer 31. Figure 7 As shown in (d), a source electrode 271 and a drain electrode 272 are provided on the interlayer dielectric layer 30. The source electrode 271 is connected to the source region 214 via a first via 25 and to the shielding metal layer 31 via a third via 33. The drain electrode 272 is connected to the drain region 215 via a second via 26.

[0154] An embodiment of the third aspect of this application also provides a display panel, including the array substrate 100 of any of the first aspect embodiments described above, or the array substrate 100 prepared in any of the second aspect embodiments described above. Since the display panel provided by the third aspect embodiment of this application includes the array substrate 100 of any of the first aspect embodiments described above, or the array substrate 100 prepared in any of the second aspect embodiments described above, the display panel provided by the third aspect embodiment of this application has the beneficial effects of the array substrate 100 of any of the first aspect embodiments described above, or the array substrate 100 prepared in any of the second aspect embodiments described above, which will not be elaborated further here.

[0155] The display panel in this application embodiment includes, but is not limited to, devices with display functions such as mobile phones, personal digital assistants (PDAs), tablet computers, e-books, televisions, access control systems, smart landline phones, and control consoles.

[0156] The embodiments described above are not exhaustive and do not limit the invention to specific examples. Clearly, many modifications and variations can be made based on the above description. These embodiments are selected and specifically described in this specification to better explain the principles and practical applications of this application, thereby enabling those skilled in the art to effectively utilize this application and its modifications. This application is limited only by the claims and their full scope and equivalents.

Claims

1. An array substrate, characterized in that, The system includes a substrate and a plurality of first transistors disposed on the substrate. Each first transistor includes: An active layer is disposed on one side of the substrate. The active layer includes a first surface, a second surface, and a first side surface. The first surface is located on the side of the second surface closer to the substrate, and the first side surface connects the first surface and the second surface. A first gate is disposed on the side of the active layer opposite to the substrate; A first insulating layer is located at least partially between the active layer and the first gate, the first insulating layer is stacked on the second surface, and the orthographic projection of the second surface on the substrate is located within the orthographic projection of the first insulating layer on the substrate; A second insulating layer is disposed on the side of the active layer away from the substrate, a portion of the second insulating layer is located between the first insulating layer and the first gate, and a portion of the second insulating layer covers the first side surface.

2. The array substrate according to claim 1, characterized in that, The first insulating layer includes a third surface, a fourth surface, and a second side surface. The third surface is in contact with the second surface, the fourth surface is located on the side of the third surface away from the substrate, the second side surface connects the third surface and the fourth surface, and a portion of the second insulating layer covers the second side surface. Preferably, the orthographic projection of the first insulating layer onto the substrate lies within the orthographic projection of the active layer onto the substrate; Preferably, the first side and the second side are smoothly connected.

3. The array substrate according to claim 2, characterized in that, The second insulating layer includes a first insulating portion and a second insulating portion connected to each other, the fourth surface, the first insulating portion and the first gate are stacked in sequence, and the second insulating portion covers the first side surface and the second side surface; Preferably, the active layer includes a channel region disposed opposite to the first gate, and the orthographic projection of the channel region onto the substrate lies within the orthographic projection of the second insulating layer onto the substrate; Preferably, the array substrate further includes a buffer layer disposed between the substrate and the active layer, and the second insulating layer further includes a third insulating portion connected to the second insulating portion, the third insulating portion being in contact with the surface of the buffer layer opposite to the substrate.

4. The array substrate according to claim 1, characterized in that, The thickness of the first insulating layer is H1, and the thickness of the second insulating layer is H2, where H1 < H2; Preferably, 5nm ≤ H1 ≤ 50nm; Preferably, the total thickness of the first insulating layer and the second insulating layer stacked between the first gate and the active layer is H3, where 50nm≤H3≤200nm; Preferably, the material used to prepare the first insulating layer is different from the material used to prepare the second insulating layer.

5. The array substrate according to claim 1, characterized in that, The first transistor has a first via and a second via penetrating the first insulating layer and the second insulating layer; The first transistor further includes: The source-drain conductive layer includes a source electrode and a drain electrode spaced apart. The source electrode is connected to the source region of the active layer through the first via, and the drain electrode is connected to the drain region of the active layer through the first via.

6. The array substrate according to claim 1, characterized in that, The active layer is an oxide; Preferably, the active layer is prepared from one or more of indium oxide, zinc oxide, indium gallium zinc oxide, indium zinc oxide, gallium indium zinc tin oxide, and aluminum indium zinc oxide. Preferably, the array substrate includes a pixel driving circuit, the pixel driving circuit includes a plurality of thin-film transistors, the plurality of thin-film transistors includes a driving transistor, and the driving transistor is the first transistor; Preferably, the driving transistor further includes: A source-drain conductive layer includes a source electrode and a drain electrode spaced apart, wherein the source electrode is connected to the source region of the active layer, and the drain electrode is connected to the drain region of the active layer; A shielding metal layer is located between the active layer and the substrate, and the source electrode is connected to the shielding metal layer via a via. Preferably, the plurality of thin-film transistors include a switching transistor, wherein the first transistor is the switching transistor; Preferably, the switching transistor further includes: The second gate is located between the active layer and the substrate.

7. A method for fabricating an array substrate, characterized in that, include: Take a substrate, and sequentially form an active material layer and a first insulating material layer on the substrate; The active material layer and the first insulating material layer are patterned to obtain the active layer and the first insulating layer; A second insulating layer is formed on the substrate, the second insulating layer covering the active layer and the first insulating layer; A first gate material layer is formed on the second insulating layer, and the first gate material layer is patterned to obtain the first gate.

8. The method for fabricating an array substrate according to claim 7, characterized in that, The step of patterning the active material layer and the first insulating material layer to obtain the active layer and the first insulating layer includes: A patterned first mask layer is formed on the first insulating material layer, the first mask layer covering a portion of the first insulating material layer; Using the first mask layer as a mask, the first insulating material layer is etched to form the first insulating layer; Using the first mask layer as a mask, the active material layer is etched to form the active layer; Remove the first mask layer.

9. The method for fabricating an array substrate according to claim 8, characterized in that, The process of forming a first gate material layer on the second insulating layer, and then patterning the first gate layer to obtain the first gate includes: The second insulating layer and the first insulating layer are subjected to an opening process to obtain a first via and a second via penetrating the second insulating layer and the first insulating layer, and the first via and the second via expose the active layer; A source-drain conductive layer is formed, the source-drain conductive layer including a source electrode and a drain electrode arranged at intervals, the source electrode being connected to the active layer through the first via, and the drain electrode being connected to the active layer through the first via.

10. A display panel, characterized in that, The array substrate includes the array substrate as described in any one of claims 1-6, or the array substrate prepared by the method described in any one of claims 7-9.

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