Array substrate and display panel

Abstract

The application discloses an array substrate and a display panel. The array substrate comprises a substrate, an array layer, a pixel circuit and a target initialization signal line. The pixel circuit comprises a first thin film transistor and a capacitor. The first thin film transistor comprises a first semiconductor part, a first gate, a first source and a first drain. The capacitor comprises a first plate and a second plate. The first gate and the first plate are formed in a first metal layer. The second plate is formed in a second metal layer. The first source and the first drain are formed in a third metal layer. The target initialization signal line comprises at least a first wire segment and a second wire segment in series. The first wire segment comprises a first wire part and a second wire part in parallel. The first wire part is formed in the first metal layer. The second wire part is formed in the second metal layer. The second wire segment is formed in the third metal layer. The application can avoid the corrosion problem caused by the signal line breakage and ensure the uniformity of the display panel.

Description

Technical Field

[0001] This application relates to the field of display technology, and in particular to an array substrate and a display panel. Background Technology

[0002] In recent years, with the development and widespread adoption of display technology, display panels have been applied to various electronic devices, such as mobile phones, tablets, or other portable electronic devices.

[0003] However, the inventors of this application have discovered that current display panels still have defects such as easily broken signal lines and uneven display, and the display quality needs to be further improved. Summary of the Invention

[0004] This application provides an array substrate and a display panel that can avoid corrosion problems caused by broken signal lines and ensure the uniformity of the display panel.

[0005] A first aspect of this application provides an array substrate, the array substrate including a central region and a peripheral region located around the central region, the peripheral region including an arc-shaped region, the array substrate including: a substrate; an array layer disposed on one side of the substrate, including a pixel circuit located in the central region and a target initialization signal line located in the arc-shaped region and electrically connected to the pixel circuit, the pixel circuit including a first thin-film transistor and a capacitor, the first thin-film transistor including a first semiconductor portion, a first gate, a first source, and a first drain, the capacitor including a first electrode plate and a second electrode plate, the array layer including a first metal layer, a second metal layer, and a third metal layer sequentially stacked in a direction away from the substrate, the first gate... The first electrode is formed in the first metal layer, the second electrode is formed in the second metal layer, the first source electrode and the first drain electrode are formed in the third metal layer, wherein the target initialization signal line includes at least a first trace segment and a second trace segment connected in series, the first trace segment and the second trace segment are arranged in the extension direction of the target initialization signal line, the first trace segment includes a first trace portion and a second trace portion connected in parallel, the first trace portion is formed in the first metal layer, the second trace portion is formed in the second metal layer, the second trace segment is formed in the third metal layer, and the sheet resistance value of the third metal layer is less than the sheet resistance values ​​of the first metal layer and the second metal layer.

[0006] The sheet resistance of the third metal layer is in the range of 0.02 Ω / m. 2 ~0.05Ω / m 2 ;

[0007] Furthermore, the sheet resistance values ​​of the first metal layer and the second metal layer are in the range of 0.1Ω / m.2 ~0.5Ω / m 2 .

[0008] The third metal layer is a stacked structure, comprising a first sub-metal layer, a second sub-metal layer and a third sub-metal layer sequentially disposed in the direction away from the substrate. The first sub-metal layer and the third sub-metal layer are made of titanium, and the second sub-metal layer is made of aluminum.

[0009] Both the first metal layer and the second metal layer are single-layer structures, and both are made of molybdenum.

[0010] The width of the first trace portion ranges from 20 micrometers to 40 micrometers; the width of the second trace portion ranges from 20 micrometers to 40 micrometers; and the width of the second trace segment ranges from 20 micrometers to 40 micrometers.

[0011] The widths of the first wiring section, the second wiring section, and the second wiring segment are equal.

[0012] The first trace and the second trace have their orthographic projections on the substrate coincide.

[0013] The pixel circuit includes: a driving module, a data writing module, a first initialization module, a second initialization module, a third initialization module, and a light emission control module;

[0014] The first initialization module is electrically connected to the control terminal and the first initialization signal line of the drive module, and is used to write the first initial voltage on the first initialization signal line to the control terminal of the drive module during the first initialization phase.

[0015] The second initialization module is electrically connected to the first end of the light-emitting element and the second initialization signal line, and is used to write the second initial voltage on the second initialization signal line into the first end of the light-emitting element during the second initialization phase;

[0016] The third initialization module is electrically connected to the second terminal and the third initialization signal line of the driving module, and is used to write the third initial voltage on the third initialization signal line into the second terminal of the driving module during the third initialization phase;

[0017] The data writing module is electrically connected to the first terminal of the driving module and is used to write data voltage into the driving module during the data writing stage.

[0018] The light-emitting control module, the driving module, and the light-emitting element are connected in series to form a driving branch. The light-emitting control module is used to turn on the driving branch during the light-emitting stage to make the light-emitting element light up.

[0019] The target initialization signal line is the first initialization signal line, the second initialization signal line, or the third initialization signal line.

[0020] The array substrate further includes a fourth metal layer located between the second and third metal layers. The pixel circuit includes a second thin-film transistor, and the first thin-film transistor includes a second semiconductor portion, a second gate, a third gate, a second source, and a second drain.

[0021] The second gate is formed in the second metal layer, the third gate is formed in the fourth metal layer, and the second source and the second drain are formed in the third metal layer.

[0022] The array substrate further includes a fifth metal layer, which is disposed on the side of the third metal layer away from the substrate. Connection traces that electrically connect the pixel circuit and the light-emitting element are formed in the fifth metal layer.

[0023] The fifth metal layer is a stacked structure, comprising a fourth sub-metal layer, a fifth sub-metal layer and a sixth sub-metal layer sequentially disposed in the direction away from the substrate. The materials of the fourth sub-metal layer and the sixth sub-metal layer include titanium, and the material of the fifth sub-metal layer includes aluminum.

[0024] A second aspect of this application provides a display panel including an array substrate of any of the above; and a light-emitting element disposed on the side of the array layer away from the substrate and electrically connected to the pixel circuit.

[0025] It also includes: a pixel definition layer disposed on the side of the array layer away from the substrate, the pixel definition layer having a pixel opening, and the light-emitting element formed in the pixel opening; an isolation structure disposed on the side of the pixel definition layer away from the substrate, the isolation structure having an isolation opening communicating with the pixel opening, the isolation structure including a first end near the substrate and a second end away from the substrate, the orthographic projection of the first end on the substrate being located within the orthographic projection of the second end on the substrate.

[0026] The isolation structure includes an isolation pillar and a crown arranged sequentially in a direction away from the substrate, wherein the orthographic projection of the isolation pillar on the substrate is located within the orthographic projection of the crown on the substrate.

[0027] The beneficial effects are as follows: The target initialization signal line of this application adopts a segmented design. Some traces are formed by two metal layers connected in parallel. At the same time, in order to avoid reducing impedance, a portion of the traces of the target initialization signal line is formed by a third metal layer with a relatively small sheet resistance value. This avoids the target initialization signal line from being formed by stacking too many metal layers and also ensures that the target initialization signal line has low impedance. This reduces the risk of breakage of the target initialization signal line, ensures the uniformity of the display panel, and improves the display quality of the display panel. Attached Figure Description

[0028] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort, wherein:

[0029] Figure 1 This is a top view of one embodiment of the array substrate of this application;

[0030] Figure 2 yes Figure 1 A cross-sectional structural schematic diagram of one embodiment of the array substrate;

[0031] Figure 3 This is a cross-sectional structural diagram of the target initialization signal line in one embodiment of this application;

[0032] Figure 4 yes Figure 1 A cross-sectional structural schematic diagram of another embodiment of the array substrate;

[0033] Figure 5 yes Figure 2 , Figure 4 A schematic diagram of the specific structure of the third metal layer in the middle;

[0034] Figure 6 This is a schematic diagram of one embodiment of the pixel circuit of this application;

[0035] Figure 7 This is a schematic diagram of the structure of one embodiment of the display panel of this application. Detailed Implementation

[0036] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of the embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.

[0037] It should be noted that the terms "first" and "second" in this application are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this application, "multiple" means at least two, such as two, three, etc., unless otherwise explicitly specified. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or apparatus that includes a series of steps or units is not limited to the listed steps or units, but may optionally include steps or units not listed, or may optionally include other steps or units inherent to these processes, methods, products, or apparatuses.

[0038] See Figure 1 as well as Figure 2 The array substrate 100 includes a central region AA and a peripheral region NA located around the central region AA. The peripheral region NA includes an arc-shaped region 10, specifically the lower arc-shaped region, which is located at the lower edge of the array substrate 100. The central region AA typically forms a pixel circuit 121 for driving the light-emitting elements to emit light, and the peripheral region NA forms a peripheral circuit (not shown). The peripheral circuit may include at least one of the following: a GIP (Gate In Panel) circuit, an ESD (Electrostatic Discharge) circuit, a Demultiplexer circuit, an AT (Array Test) circuit, and a CT (Cell Test) circuit. The GIP circuit includes cascaded driving units. The GIP circuit outputs driving signals line-by-line to the control terminal of the pixel circuit 121 to drive the light-emitting elements electrically connected to the pixel circuit 121 to emit light or not emit light. The ESD circuit releases static electricity present in the array substrate 100 to prevent static electricity accumulation from damaging the array substrate 100. The Demux circuit distributes a single signal to multiple output channels according to control logic to reduce wiring space. The AT circuit is used for functional testing of the array substrate 100 during the array process stage, including at least one of electrical and optical testing. The CT circuit is used in subsequent processes after the array substrate 100 is fabricated, such as in the stage of further fabricating display panels or display modules based on the array substrate 100, to perform functional testing on the display products, which also includes at least one of electrical and optical testing. The pixel circuit 121 directly drives the light-emitting elements in the display panel to emit light or not emit light.

[0039] See also Figure 2 as well as Figure 3 The array substrate 100 includes a substrate 110 and an array layer 120.

[0040] The substrate 110 serves a supporting function in the array substrate 100. It can be a flexible substrate or a rigid substrate. When the substrate 110 is a flexible substrate, its material can be polyimide (PI), or it can be a multilayer structure with alternating organic and inorganic layers. For example, the substrate 110 includes inorganic layers, organic layers, and inorganic layers stacked sequentially. In this case, the multilayer structure with alternating organic and inorganic layers can balance the flexibility and strength of the substrate 110, making the array substrate 100 bendable and resistant to breakage and deformation. When the substrate 110 is a rigid substrate, its material can be glass or metal. This application does not limit the structure of the substrate 110.

[0041] The array layer 120 is disposed on one side of the substrate 110. The array layer 120 mainly contains circuits and traces. Specifically, it includes a pixel circuit 121 located in the central region AA and a target initialization signal line 122 located in the arc corner region 10 and electrically connected to the pixel circuit 121. The pixel circuit 121 includes a first thin film transistor 1211 and a capacitor 1212. The first thin film transistor 1211 includes a first gate 12111, a first source 12112, a first drain 12113 and a first semiconductor part 12114. The capacitor 1212 includes a first electrode 12121 and a second electrode 12122.

[0042] Meanwhile, the array layer 120 includes multiple metal layers sequentially stacked on the substrate 110, with an insulating layer formed between any two adjacent metal layers. In one embodiment, the material of the insulating layer formed between two adjacent metal layers includes an inorganic material, such as at least one of silicon nitride (SiNx) and silicon oxide (SiOx). Electrical connections between different metal layers can be formed through vias.

[0043] Meanwhile, the multilayer metal layer includes a first metal layer 1201, a second metal layer 1202, and a third metal layer 1203 sequentially stacked in the direction away from the substrate 110. A first gate 12111 and a first electrode 12121 are formed in the first metal layer 1201, a second electrode 12122 is formed in the second metal layer 1202, and a first source 12112 and a first drain 12113 are formed in the third metal layer 1203. In one embodiment, the first thin-film transistor 1211 is a low-temperature polycrystalline silicon thin-film transistor.

[0044] See Figure 4In one embodiment, the array substrate 100 further includes a fourth metal layer 1204, which is located between the second metal layer 1202 and the third metal layer 1203. The pixel circuit 121 further includes a second thin-film transistor 1213, which includes a second semiconductor portion 12131, a second gate 12132, a third gate 12133, a second source 12134, and a second drain 12135. The second gate 12132 is formed in the second metal layer 1202, the third gate 12133 is formed in the fourth metal layer 1204, and the second source 12134 and the second drain 12135 are formed in the third metal layer 1203. In one embodiment, the second thin-film transistor 1213 is a metal-oxide-slim thin-film transistor.

[0045] Continue reading Figure 2 as well as Figure 4 The array layer 120 may further include a fifth metal layer 1205 and a planarization layer 1206. The fifth metal layer 1205 is provided with a connection trace 12051, which electrically connects the pixel circuit 121 and the light-emitting element. The planarization layer 1206 is used for planarization to ensure the flatness of the array substrate 100, and its material may specifically be an organic adhesive. In one embodiment, the fifth metal layer 1205 located in the arc corner region 10 is provided with a through hole, which facilitates venting of the planarization layer 1206. In one embodiment, when the light-emitting element is further fabricated on the array substrate 100, the first electrode layer (used to form the first electrode of the light-emitting element) located in the arc corner region 10 is also provided with a through hole, which is also for venting of the planarization layer 1206.

[0046] The pixel circuit 121 can be, for example, a 2T1C circuit, a 7T1C circuit, a 7T2C circuit, or a 9T1C circuit, and this application does not limit its specific structure. The "2T1C circuit" refers to a pixel circuit that includes two thin-film transistors (T) and one capacitor (C), and so on for "7T1C circuit", "7T2C circuit", "9T1C circuit", etc.

[0047] The target initialization signal line 122 is used to transmit the initial voltage to the pixel circuit 121 to initialize the voltage at a certain node in the pixel circuit 121. It affects the uniformity of the display panel. If the target initialization signal line 122 is broken, it will affect the uniformity of the display panel and cause corrosion of the array substrate 100, which will also affect the lifespan of the display panel.

[0048] Continue reading Figure 3In this application, the target initialization signal line 122 adopts a segmented design. Specifically, the target initialization signal line 122 includes at least a first trace segment 1221 and a second trace segment 1222 connected in series. The orthographic projections of the first trace segment 1221 and the second trace segment 1222 on the substrate 110 do not overlap at least partially. The first trace segment 1221 and the second trace segment 1222 are arranged in the extension direction of the target initialization signal line 122. The first trace segment 1221 includes a first trace portion 12211 and a second trace portion 12212 connected in parallel. The first trace portion 12211 is formed in the first metal layer 1201, the second trace portion 12212 is formed in the second metal layer 1202, and the second trace segment 1222 is formed in the third metal layer 1203. The sheet resistance of the third metal layer 1203 is less than the sheet resistance of the first metal layer 1201 and the second metal layer 1202.

[0049] In this embodiment, the first trace portion 12211 and the second trace portion 12212 are connected in parallel through at least two vias, for example, see [reference needed]. Figure 3 The first end of the first trace 12211 is electrically connected to the first end of the second trace 12212 through a via, and the second end of the first trace 12211 is electrically connected to the second end of the second trace 12212 through another via. At the same time, the first trace segment 1221 and the second trace segment 1222 are connected in series through vias, so that the signal transmitted by the first trace segment 1221 is transmitted to the second trace segment 1222 through the vias.

[0050] The sheet resistance of the third metal layer 1203 being less than that of the first metal layer 1201 and the second metal layer 1202 specifically means that, within the same volume, the impedance of the third metal layer 1203 is less than that of the first metal layer 1201 and the second metal layer 1202. The impedances of the first metal layer 1201 and the second metal layer 1202 may be the same or different.

[0051] In related technologies, the target initialization signal line 122 located in the arc corner region 10 is formed by stacking and connecting at least three metal layers (an insulating layer is formed between any two adjacent metal layers in the at least three metal layers) in parallel. (That is, the target initialization signal line 122 in the prior art generally includes at least three parts stacked and connected in parallel, which are formed in three metal layers respectively. In one application scenario, the target initialization signal line 122 is formed by a first metal layer 1201, a second metal layer 1202, and a third metal layer 1203, that is, the target initialization signal line 122 includes three parts connected in parallel, which are formed in the first metal layer 1201, the second metal layer 1202, and the third metal layer 1203 respectively.) However, this method of stacking multiple metal layers makes the target initialization signal line 122 prone to breakage in high temperature and high humidity environments, which causes corrosion in the arc corner region 10, resulting in unevenness of the display panel and affecting the lifespan of the display panel.

[0052] To avoid the aforementioned problems, this application adopts a segmented design for the target initialization signal line 122. Some segments are formed by two metal layers connected in parallel. At the same time, to avoid reducing impedance, a portion of the target initialization signal line 122 is formed by a third metal layer 1203 with a relatively low sheet resistance. This avoids the target initialization signal line 122 from being formed by stacking too many metal layers and ensures that the target initialization signal line 122 has low impedance. This reduces the risk of breakage of the target initialization signal line 122, ensures the uniformity of the display panel, and improves the display quality of the display panel.

[0053] In one embodiment, the target initialization signal line 122 may include only the first trace segment 1221 and the second trace segment 1222 described above.

[0054] In one embodiment, the first wiring segment 1221 may include only the first wiring portion 12211 and the second wiring portion 12212 described above.

[0055] In one embodiment, the target initialization signal line 122 may be further configured to include more routing segments, such as a third routing segment and a fourth routing segment, which are connected in series with the first routing segment 1221 and the second routing segment 1222.

[0056] In one embodiment, the sheet resistance of the third metal layer 1203 is in the range of 0.02 Ω / m. 2 ~0.05Ω / m 2 For example, the sheet resistance of the third metal layer 1203 is 0.02 Ω / m. 2 0.03Ω / m 2 0.04Ω / m 2 0.043Ω / m2 Or 0.05Ω / m 2 The specific settings can be customized according to your needs.

[0057] In one embodiment, the sheet resistance values ​​of the first metal layer 1201 and the second metal layer 1202 are in the range of 0.1 Ω / m. 2 ~0.5Ω / m 2 For example, the sheet resistance of the first metal layer 1201 and the second metal layer 1202 is 0.1Ω / m. 2 0.2Ω / m 2 0.3Ω / m 2 0.4Ω / m 2 0.44Ω / m 2 Or 0.5Ω / m 2 The specific settings can be customized according to your needs.

[0058] In a specific example, the sheet resistance values ​​of the first metal layer 1201 and the second metal layer 1202 are equal. This can be achieved by making the materials of the first metal layer 1201 and the second metal layer 1202 the same.

[0059] In one embodiment, see Figure 5 The third metal layer 1203 has a stacked structure, including a first sub-metal layer 12031, a second sub-metal layer 12032, and a third sub-metal layer 12033 sequentially disposed in the direction away from the substrate 110. The first sub-metal layer 12031 and the third sub-metal layer 12033 are made of titanium, and the second sub-metal layer 12032 is made of aluminum. That is, the third metal layer 1203 is a titanium-aluminum-titanium stacked structure. In this titanium-aluminum-titanium stacked structure, on the one hand, the upper and lower titanium layers can protect the middle aluminum layer; on the other hand, experiments have verified that this combination has a low impedance value. It should be noted that in other embodiments, the materials of the first sub-metal layer 12031, the second sub-metal layer 12032, and the third sub-metal layer 12033 can be set to other materials as needed.

[0060] In one embodiment, the fifth metal layer 1205 has the same structure as the third metal layer 1203, that is, the fifth metal layer 1205 is a stacked structure, including a fourth sub-metal layer (not shown), a fifth sub-metal layer (not shown), and a sixth sub-metal layer (not shown) sequentially disposed in the direction away from the substrate 110. The materials of the fourth sub-metal layer and the sixth sub-metal layer include titanium, and the material of the fifth sub-metal layer includes aluminum. That is, the fifth metal layer 1205 is also a titanium-aluminum-titanium stacked structure.

[0061] In one embodiment, the materials of the first metal layer 1201 and the second metal layer 1202 both include molybdenum (MO), that is, the materials of the first metal layer 1201 and the second metal layer 1202 are the same.

[0062] In one embodiment, the material of the fourth metal layer 1204 includes a titanium layer and a molybdenum layer sequentially stacked on the substrate 110 away from it.

[0063] It should be noted that this application does not impose any restrictions on the specific materials of the first metal layer 1201, the second metal layer 1202, the third metal layer 1203, the fourth metal layer 1204, and the fifth metal layer 1205. The materials can be set according to actual needs, as long as the sheet resistance of the third metal layer 1203 is less than that of the first metal layer 1201 and the second metal layer 1202.

[0064] In one embodiment, the width of the first trace portion 12211 is in the range of 20 micrometers to 40 micrometers. For example, the width of the first trace portion 12211 is 20 micrometers, 30 micrometers, or 40 micrometers.

[0065] In one embodiment, the width of the second trace portion 12212 is in the range of 20 micrometers to 40 micrometers. For example, the width of the second trace portion 12212 is 20 micrometers, 30 micrometers, or 40 micrometers.

[0066] In one embodiment, the width of the second trace segment 1222 is in the range of 20 micrometers to 40 micrometers. For example, the width of the second trace segment 1222 is 20 micrometers, 30 micrometers, or 40 micrometers.

[0067] The above-mentioned width range setting can avoid the first trace 12211, the second trace 12212, and the second trace segment 1222 being too small, which would result in the impedance of the target initialization signal line 122 being too small. It can also avoid the first trace 12211, the second trace 12212, and the second trace segment 1222 being too large, which would result in a short circuit with other signal lines.

[0068] It should be noted that, in other embodiments, the widths of the first wiring section 12211, the second wiring section 12212, and the second wiring segment 1222 can be set according to actual needs.

[0069] In one embodiment, the widths of the first wiring portion 12211, the second wiring portion 12212, and the second wiring segment 1222 are equal, but they can also be set to be unequal, depending on actual needs.

[0070] In one embodiment, the orthographic projections of the first trace 12211 and the second trace 12212 on the substrate 110 overlap to reduce the space occupied by the target initialization signal line 122. Of course, in other embodiments, the orthographic projections of the first trace 12211 and the second trace 12212 on the substrate 110 may partially overlap or partially not overlap, and the specific configuration can be adjusted according to actual needs.

[0071] See Figure 6 The pixel circuit 121 includes a driving module 221, a data writing module 222, a first initialization module 223, a second initialization module 224, a third initialization module 225, an emissive control module 226, a storage module 227, and a compensation module 228.

[0072] The first initialization module 223 is electrically connected to the control terminal and the first initialization signal line Vref1 of the drive module 221, and is used to write the first initial voltage on the first initialization signal line Vref1 to the control terminal of the drive module 221 during the first initialization phase. The drive module 221 includes a drive transistor T1, and the first initialization module 223 includes a thin-film transistor T4. The first terminal of the thin-film transistor T4 is electrically connected to the control terminal of the drive transistor T1, the second terminal of the thin-film transistor T4 is electrically connected to the first initialization signal line Vref1, and the control terminal of the thin-film transistor T4 is electrically connected to the scan line S1. During the first initialization phase, the signal on the scan line S1 turns on the thin-film transistor T4, thereby writing the first initial voltage on the first initialization signal line Vref1 to the control terminal of the drive transistor T1.

[0073] The second initialization module 224 is electrically connected to the first terminal of the light-emitting element 210 and the second initialization signal line Vref2, and is used to write the second initial voltage on the second initialization signal line Vref2 to the first terminal of the light-emitting element 210 during the second initialization phase. The second initialization module 224 includes a thin-film transistor T7, the first terminal of which is electrically connected to the first terminal of the light-emitting element 210, the second terminal of which is electrically connected to the second initialization signal line Vref2, and the control terminal of which is electrically connected to the scan line S4. During the second initialization phase, the signal on the scan line S4 turns on the thin-film transistor T7, thereby writing the second initial voltage on the second initialization signal line Vref2 to the first terminal of the light-emitting element 210.

[0074] The third initialization module 225 is electrically connected to the second terminal of the driving module 221 and the third initialization signal line Vref3. It is used to write the third initial voltage on the third initialization signal line Vref3 to the second terminal of the driving module 221 during the third initialization phase. The third initialization module 225 includes a thin-film transistor T8. The first terminal of the thin-film transistor T8 is electrically connected to the second terminal of the driving transistor T1, and the second terminal of the thin-film transistor T8 is electrically connected to the third initialization signal line Vref3. The control terminal of the thin-film transistor T8 is electrically connected to the scan line S4. During the third initialization phase, the signal on the scan line S4 turns on the thin-film transistor T8, thereby writing the third initial voltage on the third initialization signal line Vref3 to the second terminal of the driving transistor T1. Since the control terminals of both the thin-film transistors T7 and T8 are electrically connected to the scan line S4, the thin-film transistors T7 and T8 can be turned on or off simultaneously, meaning the second and third initialization phases are the same.

[0075] The data writing module 222 is electrically connected to the first terminal of the driving module 221 and is used to write the data voltage to the driving module 221 during the data writing phase. The data writing module 222 includes a thin-film transistor T2, the first terminal of which is electrically connected to the data signal line, the second terminal of which is electrically connected to the first terminal of the driving transistor T1, and the control terminal of which is electrically connected to the scan line S2. During the data writing phase, the signal on the scan line S2 turns on the thin-film transistor T2, thereby writing the data voltage on the data signal line to the driving transistor T1.

[0076] The light-emitting control module 226, the driving module 221, and the light-emitting element 210 are connected in series to form a driving branch. The light-emitting control module 226 is used to turn on during the light-emitting stage to connect the driving branch, thereby causing the light-emitting element 210 to emit light. In one embodiment, the light-emitting control module 226 includes a first light-emitting control unit 2261 and a second light-emitting control unit 2262. The first light-emitting control unit 2261 is connected between the first power supply voltage input terminal ELVDD and the first terminal of the driving module 221. The second light-emitting control unit 2262 is connected between the second terminal of the driving module 221 and the first terminal of the light-emitting element 210. The control terminals of the first light-emitting control unit 2261 and the second light-emitting control unit 2262 are simultaneously connected to the light-emitting control signal EM, thereby turning on or off the first light-emitting control unit 2261 and the second light-emitting control unit 2262 simultaneously. The first light-emitting control unit 2261 includes a thin-film transistor T5, and the second light-emitting control unit 2262 includes a thin-film transistor T6. The first terminal of the thin-film transistor T5 is electrically connected to the first power supply voltage input terminal ELVDD, and the second terminal is electrically connected to the first terminal of the driving transistor T1. The first terminal of the thin-film transistor T6 is electrically connected to the second terminal of the driving transistor T1, and the second terminal of the thin-film transistor T6 is electrically connected to the first terminal of the light-emitting element 210. The control terminals of the thin-film transistors T5 and T6 are both connected to the light-emitting control signal EM.

[0077] The first terminal of the storage module 227 is electrically connected to the control terminal of the drive module 221, and the second terminal of the storage module 227 is electrically connected to the first power supply voltage input terminal ELVDD, for storing the voltage of the control terminal of the drive module 221. The storage module 227 includes a capacitor C1, which is connected between the first power supply voltage input terminal ELVDD and the control terminal of the drive transistor T1.

[0078] The compensation module 228 is connected between the second terminal and the control terminal of the drive module 221. The compensation module 228 is used to compensate the threshold voltage of the drive module 221. The compensation module 228 includes a thin-film transistor T3, which is connected between the second terminal and the control terminal of the drive transistor T1, and the control terminal is electrically connected to the scan line S3.

[0079] Among them, the target initialization signal line 122 is the first initialization signal line Vref1, the second initialization signal line Vref2, or the third initialization signal line Vref3.

[0080] Specifically, the first initialization signal line Vref1, the second initialization signal line Vref2, and the third initialization signal line Vref3 all affect the uniformity of the display panel, therefore, these three signal lines all have impedance requirements. In one embodiment, one of the first initialization signal line Vref1, the second initialization signal line Vref2, and the third initialization signal line Vref3 can adopt the design of the target initialization signal line 122 of this application; in another embodiment, two or three of the first initialization signal line Vref1, the second initialization signal line Vref2, and the third initialization signal line Vref3 can adopt the design of the target initialization signal line 122 of this application, thereby avoiding the breakage of the first initialization signal line Vref1, the second initialization signal line Vref2, and the third initialization signal line Vref3 and ensuring the uniformity of the display panel.

[0081] Among them, the driving transistor T1, thin film transistor T2, thin film transistor T3, thin film transistor T4, thin film transistor T5, thin film transistor T6, thin film transistor T7 and thin film transistor T8 can be configured as the structure of the first thin film transistor 1211 or the second thin film transistor 1213 as required.

[0082] See Figure 7 In one embodiment of this application, the display panel includes the array substrate 100 and the light-emitting element 210 as described in any of the above embodiments.

[0083] The light-emitting element 210 is disposed on the side of the array layer 120 facing away from the substrate 110 and is electrically connected to the pixel circuit 121. The light-emitting element 210 includes a first electrode 211, a light-emitting material layer 212, and a second electrode 213, which are sequentially stacked in the direction facing away from the substrate 110. One of the first electrode 211 and the second electrode 213 is an anode, and the other is a cathode. For ease of explanation, the following description will use the first electrode 211 as the anode and the second electrode 213 as the cathode. There are multiple light-emitting elements 210; some emit red light, some emit green light, and some emit blue light.

[0084] The display panel can be an OLED display panel (Liquid Crystal Display), a liquid crystal display panel (LCD), a Micro-LED display panel (Micro Light Emitting Diode), or other types of display panels. This application does not limit the specific type of display panel.

[0085] Continue reading Figure 7 The display panel includes a pixel definition layer 220 and an isolation structure 230.

[0086] A pixel definition layer 220 is disposed on the side of the array layer 120 facing away from the substrate 110. The pixel definition layer 220 has pixel openings, and light-emitting elements 210 are formed in the pixel openings (not shown in the figure). The pixel definition layer 220 is used to define the position of the light-emitting elements 210. The pixel definition layer 220 can be formed of organic materials such as polyimide (PI), polyamide, benzocyclobutene (BCB), acrylic resin, or phenolic resin, or of inorganic materials such as SiNx. In one embodiment, the material of the pixel definition layer 220 includes a light-absorbing material, which can prevent crosstalk between light emitted from adjacent light-emitting elements. Different light-emitting elements 210 are formed in different pixel openings.

[0087] An isolation structure 230 is disposed on the side of the pixel definition layer 220 away from the substrate 110. The isolation structure 230 has an isolation opening that communicates with the pixel opening. The isolation structure 230 includes a first end 2301 close to the substrate 110 and a second end 2302 away from the substrate 110. The orthographic projection of the first end 2301 on the substrate 110 is located within the orthographic projection of the second end 2302 on the substrate 110.

[0088] Specifically, the isolation structure 230 is generally wider at the top and narrower at the bottom. In this way, during the fabrication process, the light-emitting functional layers (including the light-emitting material layer 212, electron transport layer, hole transport layer, etc.) and the second electrode 213 in the light-emitting element 210 can be deposited on the entire surface first. At the edge of the isolation structure 230, due to the existence of the step difference, the film layer deposited on the entire surface will be broken at the edge of the isolation structure 230, so that the film layer of the light-emitting element 210 can be completely in the isolation opening. This allows the fabrication of the film layer to be made without the need for a precision mask for alignment, which can reduce costs.

[0089] Continue reading Figure 7 In one embodiment, the isolation structure 230 includes isolation pillars 231 and a crown 232 sequentially stacked in a direction away from the substrate 110. The orthographic projection of the side of the isolation pillars 231 away from the substrate 110 onto the substrate 110 lies within the orthographic projection of the crown 232 onto the substrate 110. That is, in a direction parallel to the substrate 110, the isolation pillars 231 are recessed relative to the crown 232, resulting in the isolation structure 230 generally having a shape that is wider at the top and narrower at the bottom. The second electrode 213 overlaps with the isolation pillars 231. The orthographic projection area of ​​the side of the isolation pillars 231 away from the substrate 110 onto the substrate 110 is smaller than the orthographic projection area of ​​the crown 232 onto the substrate 110. The cross-section of the isolation structure 230 perpendicular to the substrate 110 may be T-shaped.

[0090] In one embodiment, the material of the isolation pillar 231 includes a conductive material, such as a metallic material, like aluminum, and the material of the crown 232 includes a conductive material, such as a metallic material, like titanium. See also Figure 7 In other embodiments, to reduce the transmission impedance of the isolation structure 230, the isolation structure 230 may further include an isolation layer 233 located between the isolation pillar 231 and the substrate 110. In one embodiment, the orthographic projection of the isolation pillar 231 on the substrate 110 lies within the orthographic projection of the isolation layer 233 on the substrate 110; that is, in a direction parallel to the substrate 110, the isolation pillar 231 is recessed relative to the isolation layer 233. The orthographic projection area of ​​the isolation pillar 231 on the substrate 110 is smaller than the orthographic projection area of ​​the isolation layer 233 on the substrate 110. The cross-section of the isolation structure 230 perpendicular to the substrate 110 may be I-shaped.

[0091] In one embodiment, the material of the isolation layer 233 includes a conductive material, such as a metallic material, such as molybdenum. In this case, the isolation structure 230 is a combination of a molybdenum layer, an aluminum layer, and a titanium layer. This combination can ensure that the impedance of the isolation structure 230 is the lowest, and the titanium layer can also protect the aluminum layer and prevent the aluminum layer from being etched.

[0092] In one embodiment, the display panel further includes an encapsulation layer 240 for the light-emitting element 210.

[0093] For ease of explanation, the fabrication process of the display panel is illustrated using an example of multiple light-emitting elements 210, including red light-emitting elements 210, green light-emitting elements 210, and blue light-emitting elements 210:

[0094] After forming the isolation structure 230, the light-emitting material layer 212, the second electrode 213, and the encapsulation layer 240 of the light-emitting element 210 with a red light-emitting color are first vapor-deposited across the entire surface. Then, the entire surface of the encapsulation layer 240, the second electrode 213, and the light-emitting material layer 212 is patterned, leaving only the light-emitting material layer 212, the second electrode 213, and the encapsulation layer 240 in some pixel openings. Next, the entire surface of the light-emitting material layer 212, the second electrode 213, and the encapsulation layer 240 with a green light-emitting color is vapor-deposited, and the entire surface of the light-emitting material layer 212, the second electrode 213, and the encapsulation layer 240 is patterned. Finally, the entire surface of the light-emitting material layer 212, the second electrode 213, and the encapsulation layer 240 with a blue light-emitting color is vapor-deposited, and the entire surface of the light-emitting material layer 212, the second electrode 213, and the encapsulation layer 240 is patterned.

[0095] The composition and preparation of the isolation structure 230 are further described in patents CN118251982A, 202410864269.8, PCT / CN2024 / 098407, PCT / CN2024 / 102783, PCT / CN2024 / 098217, PCT / CN2024 / 099419, and PCT / CN2024 / 099072, the contents of which are incorporated herein by reference.

[0096] The above description is merely an embodiment of this application and does not limit the patent scope of this application. Any equivalent structural or procedural transformations made using the content of this application's specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of this application.

Claims

1. An array substrate, characterized in that, The array substrate includes a central region and a peripheral region located around the central region, the peripheral region including an arc-shaped area, and the array substrate includes: Substrate; An array layer, disposed on one side of the substrate, includes a pixel circuit located in the central region and a target initialization signal line located in the arc-angle region and electrically connected to the pixel circuit. The pixel circuit includes a first thin-film transistor and a capacitor. The first thin-film transistor includes a first semiconductor portion, a first gate, a first source, and a first drain. The capacitor includes a first electrode and a second electrode. The array layer includes a first metal layer, a second metal layer, and a third metal layer sequentially stacked in a direction away from the substrate. The first gate and the first electrode are formed in the first metal layer, the second electrode is formed in the second metal layer, and the first source and the first drain are formed in the third metal layer. The target initialization signal line includes at least a first trace segment and a second trace segment connected in series. The first trace segment and the second trace segment are arranged in the extension direction of the target initialization signal line. The first trace segment includes a first trace portion and a second trace portion connected in parallel. The first trace portion is formed in the first metal layer, the second trace portion is formed in the second metal layer, and the second trace segment is formed in the third metal layer. The sheet resistance of the third metal layer is less than the sheet resistance of the first metal layer and the second metal layer.

2. The array substrate according to claim 1, characterized in that, The sheet resistance of the third metal layer is in the range of 0.02Ω / m. 2 ~0.05Ω / m 2 ; Furthermore, the sheet resistance values ​​of the first metal layer and the second metal layer are in the range of 0.1Ω / m. 2 ~0.5Ω / m 2 .

3. The array substrate according to claim 1, characterized in that, The third metal layer is a stacked structure, comprising a first sub-metal layer, a second sub-metal layer and a third sub-metal layer sequentially disposed in the direction away from the substrate. The first sub-metal layer and the third sub-metal layer are made of titanium, and the second sub-metal layer is made of aluminum. Preferably, both the first metal layer and the second metal layer are single-layer structures, and both are made of molybdenum.

4. The array substrate according to claim 1, characterized in that, The width of the first trace ranges from 20 micrometers to 40 micrometers. The width of the second trace ranges from 20 micrometers to 40 micrometers; The width of the second trace segment ranges from 20 micrometers to 40 micrometers; Preferably, the widths of the first wiring section, the second wiring section, and the second wiring segment are equal.

5. The array substrate according to claim 1, characterized in that, The orthographic projections of the first trace and the second trace on the substrate coincide.

6. The array substrate according to claim 1, characterized in that, The pixel circuit includes: a driving module, a data writing module, a first initialization module, a second initialization module, a third initialization module, and a light emission control module; The first initialization module is electrically connected to the control terminal and the first initialization signal line of the drive module, and is used to write the first initial voltage on the first initialization signal line to the control terminal of the drive module during the first initialization phase. The second initialization module is electrically connected to the first end of the light-emitting element and the second initialization signal line, and is used to write the second initial voltage on the second initialization signal line into the first end of the light-emitting element during the second initialization phase; The third initialization module is electrically connected to the second terminal and the third initialization signal line of the driving module, and is used to write the third initial voltage on the third initialization signal line into the second terminal of the driving module during the third initialization phase; The data writing module is electrically connected to the first terminal of the driving module and is used to write data voltage into the driving module during the data writing stage. The light-emitting control module, the driving module, and the light-emitting element are connected in series to form a driving branch. The light-emitting control module is used to turn on the driving branch during the light-emitting stage to make the light-emitting element light up. The target initialization signal line is the first initialization signal line, the second initialization signal line, or the third initialization signal line.

7. The array substrate according to claim 1, characterized in that, The array substrate further includes a fourth metal layer located between the second and third metal layers. The pixel circuit includes a second thin-film transistor, and the first thin-film transistor includes a second semiconductor portion, a second gate, a third gate, a second source, and a second drain. The second gate is formed in the second metal layer, the third gate is formed in the fourth metal layer, and the second source and the second drain are formed in the third metal layer; Preferably, the array substrate further includes a fifth metal layer, which is disposed on the side of the third metal layer away from the substrate, and connection traces electrically connecting the pixel circuit and the light-emitting element are formed in the fifth metal layer; Preferably, the fifth metal layer is a stacked structure, including a fourth sub-metal layer, a fifth sub-metal layer and a sixth sub-metal layer disposed sequentially in the direction away from the substrate, wherein the fourth sub-metal layer and the sixth sub-metal layer are made of titanium and the fifth sub-metal layer is made of aluminum.

8. A display panel, characterized in that, include: The array substrate as described in any one of claims 1 to 7; The light-emitting element is disposed on the side of the array layer opposite to the substrate and is electrically connected to the pixel circuit.

9. The display panel according to claim 8, characterized in that, Also includes: A pixel definition layer is disposed on the side of the array layer opposite to the substrate, the pixel definition layer has pixel openings, and the light-emitting element is formed in the pixel openings; An isolation structure is disposed on the side of the pixel definition layer away from the substrate. The isolation structure has an isolation opening that communicates with the pixel opening. The isolation structure includes a first end near the substrate and a second end away from the substrate. The orthographic projection of the first end on the substrate is located within the orthographic projection of the second end on the substrate.

10. The display panel according to claim 9, characterized in that, The isolation structure includes an isolation pillar and a crown arranged sequentially in a direction away from the substrate, wherein the orthographic projection of the isolation pillar on the substrate is located within the orthographic projection of the crown on the substrate.

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