Solar cell, method for manufacturing solar cell, and photovoltaic module

Abstract

The embodiment of the present application relates to the photovoltaic field, and provides a solar cell, a preparation method of the solar cell and a photovoltaic module, the solar cell comprises: a substrate, the substrate has oppositely arranged first and second surfaces, the first surface is divided into a first region and a second region arranged along a first direction, and the first direction intersects with the thickness direction of the substrate; a first tunneling oxide layer is located on the first surface, the first tunneling oxide layer comprises a first part and a second part, the first part is located on the first region, and the second part is located on the second region, and the thickness of the first part is less than the thickness of the second part; a first doped conductive layer is located on the side, away from the substrate, of the first part; a first electrode is located on the side, away from the substrate, of the first doped conductive layer, and the first electrode forms electrical connection with the first doped conductive layer. The solar cell provided by the embodiment of the present application is at least beneficial to improving the electrical performance of the solar cell.

Description

Technical Field

[0001] This application relates to the field of photovoltaics, and in particular to a solar cell, a method for preparing a solar cell, and a photovoltaic module. Background Technology

[0002] Tunnel oxide passivating contact (TOPCon) solar cells use N-type silicon as the substrate material and consist of an ultrathin silicon oxide layer and a highly doped polycrystalline silicon layer forming the passivation contact structure. By fabricating an ultrathin tunnel oxide layer and a highly doped polycrystalline silicon film in the metal electrode contact region, carrier recombination between the metal electrode and silicon can be effectively suppressed. Therefore, electrons can tunnel and be collected more easily, achieving excellent passivation and selective carrier transport. Currently, the photoelectric conversion efficiency of TOPCon cells has exceeded 26.5%, with a theoretical efficiency of up to 28.7%, making it the most likely next-generation high-efficiency battery technology to achieve mass production. However, with the further development of TOPCon cell technology, traditional tunnel oxide layers struggle to simultaneously achieve both tunneling performance and interface passivation performance, resulting in poor electrical performance of the solar cells. Summary of the Invention

[0003] This application provides a solar cell, a method for preparing a solar cell, and a photovoltaic module, which at least help improve the electrical performance of the solar cell.

[0004] According to some embodiments of this application, one aspect of this application provides a solar cell, comprising: a substrate having a first surface and a second surface disposed opposite to each other, the first surface dividing a first region and a second region arranged along a first direction, the first direction intersecting the thickness direction of the substrate; a first tunneling oxide layer located on the first surface, the first tunneling oxide layer comprising a first portion and a second portion, the first portion being located on the first region and the second portion being located on the second region, the thickness of the first portion being less than the thickness of the second portion; a first doped conductive layer located at least on the side of the first portion opposite to the substrate; and a first electrode located on the side of the first doped conductive layer opposite to the substrate, the first electrode forming an electrical connection with the first doped conductive layer.

[0005] In some embodiments, the first surface is further divided into a third region, the third region being located between the first region and the second region; the first tunneling oxide layer further includes a third portion, the third portion being located between the first portion and the second portion, the third portion being connected to the first portion and the second portion respectively, and the third portion being located on the third region; wherein, the thickness of the third portion increases in the direction from the first region to the second region.

[0006] In some embodiments, the doping concentration of the first doped conductive layer first decreases and then increases in the direction along the first surface toward the second surface.

[0007] In some embodiments, the difference between the thickness of the second portion and the thickness of the first portion is less than or equal to 0.8 nm.

[0008] In some embodiments, the thickness of the first portion is 1.0 nm to 1.5 nm, and the thickness of the second portion is 1.5 nm to 2.0 nm.

[0009] According to some embodiments of this application, another aspect of this application provides a method for fabricating a solar cell. The method is used to fabricate any of the aforementioned solar cells. The method includes: providing a substrate having a first surface and a second surface disposed opposite to each other; the first surface dividing a first region and a second region arranged along a first direction, the first direction intersecting the thickness direction of the substrate; forming a preliminary tunneling oxide layer on the first surface; and treating the preliminary tunneling oxide layer using a laser irradiation process to remove a portion of the preliminary tunneling oxide layer to obtain a first tunneling oxide layer. The first tunneling oxide layer includes a first portion and a second portion, the first portion being located on the first region and the second portion being located on the second region, the thickness of the first portion being less than the thickness of the second portion; forming a first doped conductive layer at least on the side of the first portion facing away from the substrate; and forming a first electrode on the side of the first doped conductive layer facing away from the substrate, the first electrode being electrically connected to the first doped conductive layer.

[0010] In some embodiments, the laser power in the laser irradiation process is 0.5W to 5W, and the scanning speed is 10mm / s to 100mm / s.

[0011] In some embodiments, forming a first doped conductive layer at least on the side of the first portion away from the substrate includes: forming an intrinsic amorphous silicon layer at least on the side of the first portion away from the substrate; doping the intrinsic amorphous silicon layer using a diffusion process to obtain a doped amorphous silicon layer, wherein the flow rate of the dopant gas first decreases and then increases during the diffusion process; and annealing the doped amorphous silicon layer to form the first doped conductive layer.

[0012] In some embodiments, the diffusion process includes a starting stage, an intermediate stage, and a final stage performed sequentially. The duration of the starting stage is 20-40 minutes, the duration of the intermediate stage is 30-60 minutes, and the duration of the final stage is 30-60 minutes. The flow rate of the dopant gas introduced in the starting stage is 100-300 sccm, the flow rate of the dopant gas introduced in the intermediate stage is reduced to 20-80 sccm, and the flow rate of the dopant gas introduced in the final stage is increased to 150-350 sccm.

[0013] According to some embodiments of this application, another aspect of this application provides a photovoltaic module, including: a battery string, formed by connecting a plurality of solar cells of any one of the above; an encapsulating film for covering the surface of the battery string; and a cover plate for covering the surface of the encapsulating film opposite to the battery string.

[0014] The technical solution provided in this application has at least the following advantages:

[0015] A solar cell includes a stacked substrate, a first tunneling oxide layer, a first doped conductive layer, and a first electrode. The substrate includes a first surface divided into a first region and a second region. The first tunneling oxide layer includes a first portion located in the first region and a second portion located in the second region. The first doped conductive layer is located at least in the first portion. The first electrode is electrically connected to the first doped conductive layer. The thickness of the first portion is less than the thickness of the second portion. This application divides the first surface of the substrate into a first region and a second region. The thickness of the first portion of the first tunneling oxide layer located in the first region is less than the thickness of the second portion located in the second region. This difference in thickness directly adjusts the tunneling and passivation performance of the first tunneling oxide layer in different regions. A thinner first tunneling oxide layer is used in the metal contact region (i.e., the first region corresponding to the first electrode) to reduce contact resistance and improve carrier tunneling efficiency. A thicker first tunneling oxide layer is used in the non-metal contact region (i.e., the second region) to enhance interface passivation. This reduces metal contact resistance while optimizing interface passivation performance, thereby improving the overall conversion efficiency of the solar cell and enhancing its electrical performance. Attached Figure Description

[0016] One or more embodiments are illustrated by way of example with reference to the accompanying drawings. These illustrations do not constitute a limitation on the embodiments. Unless otherwise stated, the drawings in the accompanying drawings do not constitute a limitation on scale. In order to more clearly illustrate the technical solutions in the embodiments of this application or in the conventional art, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0017] Figure 1 A cross-sectional structural schematic diagram of a solar cell provided according to an embodiment of this application is shown;

[0018] Figure 2 A cross-sectional structural schematic diagram of another solar cell provided according to an embodiment of this application is shown;

[0019] Figure 3 A schematic diagram showing the thickness distribution of a first tunneling oxide layer in a solar cell according to an embodiment of this application is illustrated.

[0020] Figure 4 A graph showing the variation of phosphorus doping concentration along the thickness direction in the first doped conductive layer of a solar cell according to an embodiment of this application is shown.

[0021] Figure 5 A graph showing the phosphine flow rate variation in a variable flow rate phosphorus diffusion process according to an embodiment of this application is illustrated.

[0022] The above figures include the following reference numerals:

[0023] 10. Substrate; 11. First region; 12. Second region; 13. First tunneling oxide layer; 14. First part; 15. Second part; 16. First doped conductive layer; 17. First electrode; 18. Back passivation antireflection layer; 19. Front emitter structure; 20. Front passivation antireflection layer; 21. Second electrode; 22. Second tunneling oxide layer; 23. Second doped conductive layer; 24. Third region; 25. Third part. Detailed Implementation

[0024] As is known from the background art, the electrical performance of existing solar cells is poor. To solve the above problems, this application provides a solar cell, a method for preparing a solar cell, and a photovoltaic module.

[0025] In the description of the embodiments of this application, technical terms such as "first" and "second" are used only to distinguish different objects and should not be construed as indicating or implying relative importance or implicitly specifying the number, specific order, or primary and secondary relationship of the indicated technical features. In the description of the embodiments of this application, "multiple" means two or more, unless otherwise explicitly defined.

[0026] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0027] In the description of the embodiments in this application, the term "and / or" is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent three cases: A exists, A and B exist simultaneously, and B exists. In addition, the character " / " in this document generally indicates that the related objects before and after it have an "or" relationship.

[0028] In the description of the embodiments of this application, the term "multiple" refers to two or more (including two), similarly, "multiple sets" refers to two or more (including two sets), and "multiple pieces" refers to two or more (including two pieces).

[0029] In the description of the embodiments of this application, the technical terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", "axial", "radial", "circumferential", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing the embodiments of this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on the embodiments of this application.

[0030] In the description of the embodiments of this application, unless otherwise expressly specified and limited, the technical terms such as "installation," "connection," "joining," and "fixing" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. For those skilled in the art, the specific meaning of the above terms in the embodiments of this application can be understood according to the specific circumstances.

[0031] In the accompanying drawings corresponding to the embodiments of this application, the thickness and area of ​​the layers are enlarged for better understanding and ease of description. When describing a component (such as a layer, film, region, or substrate) on or on the surface of another component, the component may be "directly" located on the surface of the other component, or there may be a third component between the two components. Conversely, when describing a component on the surface of another component, or when another component is formed or disposed on the surface of a component, it indicates that there is no third component between the two components. Furthermore, when describing a component as being "generally" formed on another component, it means that the component is not formed on the entire surface (or front surface) of the other component, nor is it formed on a portion of the edge of the entire surface.

[0032] In the description of the embodiments of this application, when a component "includes" another component, other components are not excluded unless otherwise stated, and other components may be further included. Furthermore, when a component such as a layer, film, region, or plate is referred to as being "on / located" on another component, it can be "directly on" the other component (i.e., located on the surface of the other component with no other components between them), or another component may be present therein. Moreover, when a component such as a layer, film, region, or plate is "directly located" on another component, or when a component such as a layer, film, region, or plate is located on the surface of another component, it indicates that no other components are located therein.

[0033] The terminology used in the description of the various embodiments described herein is for the purpose of describing particular embodiments only and is not intended to be limiting. As used in the description of the various embodiments and the appended claims, the term "foreword" is also intended to include the plural form unless the context clearly indicates otherwise. Components include layers, films, regions, or plates, etc.

[0034] The embodiments of this application will now be described in detail with reference to the accompanying drawings. However, those skilled in the art will understand that many technical details have been provided in the embodiments of this application to facilitate a better understanding of the application. However, the technical solutions claimed in this application can be implemented even without these technical details and various variations and modifications based on the following embodiments.

[0035] This application provides a solar cell, such as... Figure 1 and Figure 2 As shown, it includes:

[0036] The substrate 10 has a first surface (not shown in the figure) and a second surface (not shown in the figure) disposed opposite to each other. The first surface divides a first region 11 and a second region 12 arranged along a first direction, which intersects with the thickness direction of the substrate 10.

[0037] In one embodiment, the first direction is perpendicular to the thickness direction of the substrate.

[0038] In one embodiment, the first region is a metal contact region, and the second region is a non-metal contact region.

[0039] It should be noted that the substrate material can be at least one of monocrystalline silicon, polycrystalline silicon, amorphous silicon, or microcrystalline silicon; the substrate can be an N-type semiconductor substrate or a P-type semiconductor substrate. The N-type semiconductor substrate is doped with an N-type dopant element, which can be at least one of group V elements such as phosphorus (P), bismuth (Bi), antimony (Sb), or arsenic (As). The P-type semiconductor substrate is doped with a P-type dopant element, which can be at least one of group III elements such as boron (B), aluminum (Al), gallium (Ga), or indium (In).

[0040] In one embodiment, the substrate is an N-type silicon substrate.

[0041] A first tunneling oxide layer 13 is located on the first surface. The first tunneling oxide layer 13 includes a first part 14 and a second part 15. The first part 14 is located on the first region 11, and the second part 15 is located on the second region 12. The thickness of the first part 14 is less than the thickness of the second part 15.

[0042] In one embodiment, the material of the first tunneling oxide layer includes SiO2. x , of which 1 <x≤2。

[0043] The first doped conductive layer 16 is located at least on the side of the first portion 14 opposite to the substrate 10.

[0044] In one embodiment, the first doped conductive layer is doped polycrystalline silicon.

[0045] The first electrode 17 is located on the side of the first doped conductive layer 16 away from the substrate 10, and the first electrode 17 is electrically connected to the first doped conductive layer 16.

[0046] It should be noted that, along the thickness direction of the substrate, the first electrode overlaps with the first portion; the first electrode and the first doped conductive layer form an ohmic contact.

[0047] In the above embodiments, the solar cell includes a stacked substrate, a first tunneling oxide layer, a first doped conductive layer, and a first electrode. The substrate includes a first surface divided into a first region and a second region. The first tunneling oxide layer includes a first portion located on the first region and a second portion located on the second region. The first doped conductive layer is located at least on the first portion. The first electrode is electrically connected to the first doped conductive layer. The thickness of the first portion is less than the thickness of the second portion. This application divides the first surface of the substrate into a first region and a second region, and sets the thickness of the first portion of the first tunneling oxide layer located on the first region to be less than the thickness of the second portion located on the second region. This allows for direct adjustment of the tunneling and passivation performance of the first tunneling oxide layer in different regions by utilizing the thickness difference. A thinner first tunneling oxide layer is used in the metal contact region (i.e., the first region corresponding to the first electrode) to reduce contact resistance and improve carrier tunneling efficiency. A thicker first tunneling oxide layer is used in the non-metal contact region (i.e., the second region) to enhance the interface passivation effect. This reduces metal contact resistance while optimizing interface passivation performance, thereby improving the overall conversion efficiency of the solar cell and enhancing its electrical performance.

[0048] It should be noted that the first tunneling oxide layer is divided into several functional zones (such as the first zone and the second zone) according to the metal contact area, and different functional zones have different tunneling oxide layer thickness distributions.

[0049] In one embodiment, the surface of the first part closest to the substrate is the third surface, and the surface of the first part away from the substrate is the fourth surface. The thickness of the first part can be measured by using a 3D microscope or an electron microscope to measure the distance between the third and fourth surfaces at different locations along the first direction multiple times, and then taking the average value as the thickness of the first part. Of course, other methods can also be used to measure the thickness of the first part, and this application does not impose specific limitations on this.

[0050] In one embodiment, the surface of the second part near the substrate is the fifth surface, and the surface of the first part away from the substrate is the sixth surface. The thickness of the second part can be measured by using a 3D microscope or an electron microscope to measure the distance between the fifth and sixth surfaces at different locations along the first direction multiple times, and then taking the average value as the thickness of the second part. Of course, other methods can also be used to measure the thickness of the second part, and this application does not impose specific limitations on this.

[0051] In one embodiment, the first doped conductive layer is located on the side of the first tunneling oxide layer opposite to the substrate.

[0052] In one embodiment, the first tunneling oxide layer is located on the back side of the substrate (i.e., the first surface is the back side of the substrate, and the second surface is the front side of the substrate), such as Figure 1 and Figure 2 As shown, the solar cell further includes: a back passivation antireflection layer 18 located between the first tunneling oxide layer 13 and the first electrode 17; a front emitter structure 19 located on the second surface; a front passivation antireflection layer 20 located on the side of the front emitter structure 19 facing away from the substrate 10; and a second electrode 21 located on the side of the front passivation antireflection layer 20 facing away from the substrate 10.

[0053] In one embodiment, such as Figure 1 and Figure 2 As shown, the aforementioned front emitter structure 19 includes: a second tunneling oxide layer 22 located on the aforementioned second surface; and a second doped conductive layer 23 located on the surface of the aforementioned second tunneling oxide layer 22 facing away from the aforementioned substrate 10.

[0054] In one embodiment, the second doped conductive layer is doped polycrystalline silicon; the thickness of the second tunneling oxide layer is 1.0~2.0 nm, the thickness of the second doped conductive layer is 50~100 nm, and the doping element of the second doped conductive layer includes boron with a doping concentration of 1×10⁻⁶. 19 ~1×10 20 atoms / cm³.

[0055] It should be noted that the second electrode forms an ohmic contact with the front emitter structure.

[0056] In one alternative, such as Figure 2As shown, the first surface is further divided into a third region 24, which is located between the first region 11 and the second region 12; the first tunneling oxide layer 13 also includes a third part 25, which is located between the first part 14 and the second part 15, and is connected to the first part 14 and the second part 15 respectively, and is located on the third region 24; wherein, the thickness of the third part 25 increases in the direction from the first region 11 to the second region 12. In this embodiment, the first surface is divided into a third region and a third part is provided between the first region and the second region, aiming to construct a transition zone with a gradually varying thickness. The third part refers to the intermediate layer structure connecting the first part and the second part. The oxide layer thickness of the third part shows a continuous and smooth increasing trend from the side closer to the first part to the side closer to the second part. By introducing this third part with a gradually varying thickness, the first tunneling oxide layer no longer experiences a sudden jump or abrupt change in thickness at the connection between the first part and the second part, but instead forms a continuous sloping interface. This structure effectively disperses the local stress caused by the thickness difference and avoids the microcracks or interface defects that are easily caused by traditional right-angle step-shaped interfaces. This improves the structural integrity and electrical stability of the tunneling oxide layer under thermal cycling or mechanical stress, and ensures the reliability of the solar cell in long-term operation.

[0057] In one embodiment, the thickness of the third portion varies with the first direction at a rate of 0.1 nm / μm to 0.5 nm / μm.

[0058] It should be noted that, along the direction from the first region to the second region, the thickness difference between any two locations with a distance of 1 μm in the third part is 0.1 nm to 0.5 nm.

[0059] In another alternative embodiment, the doping concentration of the first doped conductive layer first decreases and then increases along the direction from the first surface to the second surface. In this embodiment, in the thickness direction from the substrate interface side outward to the electrode contact side, the doping concentration inside the first doped conductive layer exhibits a distribution pattern of low concentration in the middle and high concentration at both ends. The lower doping concentration region in the middle can effectively suppress the Auger recombination effect caused by excessively high carrier density inside the polycrystalline silicon layer, thereby reducing internal recombination loss and improving carrier lifetime. Meanwhile, the higher doping concentration region on the surface forms a good ohmic contact interface, significantly reducing the contact resistance between the first electrode and the first doped conductive layer. Through this concentration distribution of low concentration inside and high concentration outside, the first doped conductive layer can ensure both efficient carrier transport inside and low-resistance connection with the electrode, thereby achieving a synergistic improvement in reducing internal recombination loss and optimizing contact resistance. This solves the technical problem of difficulty in simultaneously addressing internal recombination and contact resistance in traditional uniform doped structures.

[0060] In one embodiment, a secondary ion mass spectrometry (SIMS) can be used to measure the doping concentration at different depths (i.e., different positions in the thickness direction) of the first doped conductive layer. For example, to measure the doping concentration at a predetermined position in the thickness direction of the first doped conductive layer, the secondary ion mass spectrometry can be used to measure the doping concentration at different positions in the first direction corresponding to the predetermined position several times, and then the average value can be taken as the doping concentration of the first doped conductive layer at the predetermined position. Of course, other methods can also be used to measure the doping concentration at different depths of the first doped conductive layer, and this application does not impose specific limitations on this.

[0061] In one embodiment, the first doped conductive layer has a doping concentration gradient distribution along its thickness direction. The doping element in the first doped conductive layer includes phosphorus. The phosphorus doping concentration in the first doped conductive layer varies as follows: at the interface adjacent to the first tunneling oxide layer, the phosphorus doping concentration is 1×10⁻⁶. 20 ~8×10 20 atoms / cm³; in the middle of the first doped conductive layer, the phosphorus doping concentration decreases to 1×10⁻⁶ atoms / cm³. 19 ~5×10 19 atoms / cm³; at the surface of the first doped conductive layer away from the substrate, the phosphorus doping concentration increases to 2×10⁻⁶ atoms / cm³. 20 ~9×10 20 atoms / cm³; the total thickness of the first doped conductive layer is 60~150nm, and the lowest point of phosphorus doping concentration in the first doped conductive layer is located at a position of 30~70nm from the interface adjacent to the first tunneling oxide layer.

[0062] According to some exemplary embodiments of this application, the difference between the thickness of the second portion and the thickness of the first portion is less than or equal to 0.8 nm. In this embodiment, the second tunneling oxide layer located in the second region and the first tunneling oxide layer located in the first region have a step-like difference in thickness. However, this thickness jump is strictly limited to the microscale. For example, when the first region is used to form an ohmic contact and requires a thinner oxide layer to reduce resistance, and the second region is used to provide surface passivation and requires a thicker oxide layer, the difference in thickness between the two is controlled within 0.8 nm, avoiding drastic changes in thickness. This fine thickness control aims to solve the problem of interface stress concentration caused by the functional requirements of partitioning (such as the separation of contact and passivation). By limiting the magnitude of thickness changes, the accumulation of mechanical stress at the junction of different functional partitions is reduced, thereby improving the mechanical stability and electrical reliability of the overall structure of the solar cell and ensuring the structural integrity of the cell during long-term operation or thermal cycling.

[0063] In one embodiment, the thickness difference between the second part and the first part is not less than 0.04 nm. This minimum thickness difference (≥0.04 nm) ensures that the laser local processing technology has sufficient physical differentiation and electrical effectiveness to clearly define the performance boundary between the first and second parts. If the difference is too small, it means that the laser thinning effect is weak, and the first part cannot form a sufficiently low tunneling barrier to reduce the contact resistance, resulting in the inability to realize the advantages of the partitioned design, and even the possibility of local passivation failure due to process fluctuations. Setting a difference of not less than 0.04 nm ensures that the first tunneling oxide layer in the metal contact area is significantly thinner than the first tunneling oxide layer in the non-metal contact area, thereby maintaining the high passivation quality of the non-metal contact area while effectively reducing the tunneling resistance of the metal contact area, achieving effective decoupling of passivation and contact performance.

[0064] According to some other exemplary embodiments of this application, the thickness of the first part is 1.0 nm to 1.5 nm, and the thickness of the second part is 1.5 nm to 2.0 nm. In this embodiment, the thickness of the first part of 1.0 to 1.5 nm is within the efficient tunneling window. If it is too thin, it is easy to increase the recombination of pinhole defects; if it is too thick, it is easy to cause a sharp increase in tunneling resistance. Therefore, this range is limited to reduce contact resistance. The thickness of the second part is set to 1.5 to 2.0 nm. This thickness range can ensure that the oxide layer has sufficient density to effectively saturate the dangling bonds on the silicon surface, suppress the interface state density, and block the diffusion of impurities. If it is less than 1.5 nm, the oxide layer may have pinholes or incomplete structure, resulting in interface passivation failure and increased leakage current. If it is greater than 2.0 nm, although the passivation effect is saturated, it will further increase the tunneling resistance or introduce additional thermal stress and fabrication time cost. Therefore, this range can ensure a better interface passivation effect while taking into account process stability and material density, avoiding defect leakage caused by excessive thinness or unnecessary performance redundancy caused by excessive thickness.

[0065] It should be noted that, with the further development of TOPCon battery technology, the existing technology still faces the following technical challenges: Regarding the contradiction between the thickness of the tunneling oxide layer and passivation / contact performance, the ultrathin silicon oxide layer needs to simultaneously achieve two functions: on the one hand, it must be thin enough to allow electron tunneling through; on the other hand, it must have sufficient thickness and density to achieve good interface passivation and block hole transport. Traditional uniform thickness silicon oxide layers struggle to simultaneously meet these two requirements. When the thickness is too thin, the blocking ability for interface states and impurity diffusion is insufficient; when the thickness is too thick, the tunneling resistance increases, affecting carrier collection efficiency. Secondly, there is the issue of doping concentration distribution in the polycrystalline silicon layer. In the fabrication of TOPCon cells, a high-temperature diffusion furnace is typically used to achieve full-surface phosphorus diffusion doping on the back of the cell, resulting in a high phosphorus doping concentration in the polycrystalline silicon layer. However, high doping concentration can cause some phosphorus atoms to tunnel through the oxide layer from the polycrystalline silicon layer into the N-type silicon substrate. This increases the impurity concentration in the silicon substrate, leading to increased Auger recombination and consequently reducing the cell's open-circuit voltage and short-circuit current density. Furthermore, research indicates that improper phosphine flow rate settings are a significant cause of dark spots in PL (Polymer Diode) cells, affecting cell yield. The study also addresses the contradiction between the doping concentration gradient distribution in the polycrystalline silicon layer and Auger recombination and parasitic absorption. Research shows that when the polycrystalline silicon layer is designed to be 100 nm thick and the doping concentration is (2~3) × 10⁻⁶, the doping concentration can reach a certain level. 20 / cm 3 While it can achieve good overall performance, a uniform doping distribution along the thickness of the polycrystalline silicon layer makes it difficult to simultaneously meet the requirements of interface passivation, bulk transport, and surface metal contact. Specifically, a high doping concentration is required at the interface to enhance field-effect passivation, a moderate doping concentration is needed inside the polycrystalline silicon layer to reduce Auger recombination and parasitic absorption, and a high doping concentration is needed at the surface to reduce metal contact resistance. The doping distribution formed by the traditional whole-surface diffusion process is relatively uniform, making it difficult to achieve such a gradient doping distribution, thus limiting further improvement in battery performance.

[0066] It should be noted that in the solar cell of this application, 1) by setting a partitioned gradient tunneling oxide layer (i.e., the first tunneling oxide layer) on the back of the cell, a thinner oxide layer (1.0~1.5nm) is used in the metal contact area (i.e., the first region) to reduce tunneling resistance and improve electron collection efficiency, while a thicker oxide layer (1.5~2.0nm) is used in the non-metal contact area to enhance interface passivation, suppress hole recombination and impurity diffusion. This partitioned thickness design achieves spatial decoupling of tunneling performance and passivation performance. Compared with the traditional uniform thickness tunneling oxide layer, it can simultaneously obtain lower contact resistance and better interface passivation effect. At the same time, the gradient design of oxide layer thickness between different functional partitions (change rate 0.1~0.5nm / μm) avoids stress concentration and interface defect problems caused by abrupt thickness changes, ensuring the mechanical stability and electrical reliability of the device structure; 2) by introducing a gradient doping distribution in the gradient-doped polycrystalline silicon layer (i.e., the first doped conductive layer), a high doping concentration is set at the interface adjacent to the first tunneling oxide layer to enhance the field. The effect passivation and promote electron tunneling collection are achieved by setting a lower doping concentration in the middle of the gradient-doped polycrystalline silicon layer to reduce Auger recombination and parasitic absorption, and setting a high doping concentration again on the surface of the gradient-doped polycrystalline silicon layer away from the substrate to reduce the contact resistance with the metal electrode. This high-low-high gradient doping distribution pattern effectively solves the contradiction that high concentration leads to increased Auger recombination and low concentration leads to increased contact resistance in traditional uniform doping, and achieves synergistic optimization of passivation quality, carrier transport efficiency and metal contact performance; 3) The partitioned gradient tunneling oxide layer and the gradient-doped polycrystalline silicon layer work together to form an optimized back passivation contact structure; the thicker oxide layer in the non-metallic contact area combined with the lower doping concentration in the middle of the polycrystalline silicon layer effectively suppresses carrier recombination in the non-metallic contact area; the thinner oxide layer in the metallic contact area combined with the higher surface doping concentration ensures efficient carrier collection and low contact resistance in the metallic contact area; this multi-dimensional structural design that combines spatial partitioning and thickness gradient achieves a better balance between passivation quality and contact performance of the battery.

[0067] This application also provides a method for preparing a solar cell, the method being used to prepare any of the above-mentioned solar cells, the method comprising:

[0068] Step S101: Provide a substrate having a first surface and a second surface disposed opposite to each other, the first surface dividing a first region and a second region arranged along a first direction, the first direction intersecting the thickness direction of the substrate;

[0069] In one embodiment, an N-type monocrystalline silicon substrate is provided and then cleaned and texturized on its front side.

[0070] Step S102: A preliminary tunneling oxide layer is formed on the first surface, and the preliminary tunneling oxide layer is treated by laser irradiation to remove part of the preliminary tunneling oxide layer, thereby obtaining a first tunneling oxide layer. The first tunneling oxide layer includes a first part and a second part. The first part is located on the first region, and the second part is located on the second region. The thickness of the first part is less than the thickness of the second part.

[0071] Step S103: A first doped conductive layer is formed at least on the side of the first portion facing away from the substrate.

[0072] In step S104, a first electrode is formed on the side of the first doped conductive layer away from the substrate, and the first electrode is electrically connected to the first doped conductive layer.

[0073] In the above embodiments, a substrate having a first surface and a second surface is first provided, a pre-tunneling oxide layer is then formed on the first surface, and the pre-tunneling oxide layer is treated by laser irradiation to obtain a first tunneling oxide layer including a first part and a second part. The first surface is divided into a first region and a second region, and the first part and the second part are respectively located on the first region and the second region. A first doped conductive layer is then formed on the side of the first part away from the substrate, and finally a first electrode electrically connected to the first doped conductive layer is formed on the side of the first doped conductive layer away from the substrate. This application divides a first region and a second region on a first surface of a substrate. The thickness of the first portion of the first tunneling oxide layer in the first region is less than the thickness of the second portion in the second region. This difference in thickness allows for direct adjustment of the tunneling and passivation performance of the first tunneling oxide layer in different regions. A thinner first tunneling oxide layer is used in the metal contact region (i.e., the first region corresponding to the first electrode) to reduce contact resistance and improve carrier tunneling efficiency. A thicker first tunneling oxide layer is used in the non-metal contact region (i.e., the second region) to enhance the interface passivation effect. This reduces metal contact resistance while optimizing interface passivation performance, thereby improving the overall conversion efficiency of the solar cell and enhancing its electrical performance.

[0074] Furthermore, by first growing a preliminary tunneling oxide layer on the substrate surface, and then using laser irradiation to locally process the preliminary tunneling oxide layer, the thickness of the tunneling oxide layer corresponding to the first and second regions can be precisely controlled. This method of selectively removing material by laser eliminates the need for additional photoresist masks or complex mask alignment processes, and can directly form a structural difference in the thickness of the first region being smaller than that of the second region on the preliminary oxide layer. This step effectively achieves precise regional control of the thickness of the first tunneling oxide layer, ensuring that the tunneling oxide layer in the first region is thin enough to facilitate carrier tunneling and reduce contact resistance, while retaining a thicker tunneling oxide layer in the second region to provide excellent surface passivation. At the same time, it avoids the increased cost and process complexity brought about by traditional photolithography processes, achieving a balance between low cost, high precision passivation and tunneling performance.

[0075] In one embodiment, after providing the substrate and before forming a pre-tunneling oxide layer on the first surface, the method further includes: preparing a front-side emitter structure on the front side of the substrate.

[0076] In one embodiment, the fabrication of the front-side emitter structure specifically includes: preparing a first tunneling oxide layer with a thickness of 1.0~2.0 nm on the front side of the substrate by thermal oxidation; depositing an intrinsic amorphous silicon layer with a thickness of 50~100 nm on the front side by LPCVD (Low Pressure Chemical Vapor Deposition) or PECVD (Plasma Enhanced Chemical Vapor Deposition); boron doping the intrinsic amorphous silicon layer on the front side by boron diffusion process, with boron tribromide (BBr3) or boron trichloride (BCl3) as the boron source, a diffusion temperature of 850~950℃, and a diffusion time of 30~90 min; and annealing to crystallize the amorphous silicon layer into a polycrystalline silicon layer to obtain a second doped conductive layer.

[0077] In one embodiment, after forming a first doped conductive layer on at least the side of the first portion facing away from the substrate, and before forming a first electrode on the side of the first doped conductive layer facing away from the substrate, the method further includes: removing the wrap-around layers on the front and side surfaces of the substrate; depositing a front passivation antireflection layer on the front surface of the substrate, and depositing a back passivation antireflection layer on the back surface of the substrate. Forming a first electrode on the side of the first doped conductive layer facing away from the substrate includes: screen printing a metal electrode and sintering it into an ohmic contact to form a first electrode on the side of the first doped conductive layer facing away from the substrate, and forming a second electrode on the side of the second doped conductive layer facing away from the substrate, wherein both the first electrode and the second electrode are metal electrodes.

[0078] In another alternative, the laser power in the aforementioned laser irradiation process is 0.5W to 5W, and the scanning speed is 10mm / s to 100mm / s. In this embodiment, the laser power is limited to 0.5W~5W and the scanning speed is 10mm / s~100mm / s. The aim is to achieve precise control of the energy density and duration of the laser beam to achieve fine regulation of the removal process of the pre-tunneling oxide layer. Specifically, the lower laser power (0.5W~5W) can avoid the oxide layer cracking or substrate damage caused by the instantaneous ablation of high-energy laser, while the moderate scanning speed (10mm / s~100mm / s) ensures the uniformity of laser energy distribution on the substrate surface, preventing incomplete removal due to excessively fast scanning or local overheating due to excessively slow scanning. This combination of parameter ranges allows the laser irradiation to gradually vaporize or peel off the oxide layer in the designated area with controllable energy input, thereby accurately thinning the pre-tunneling oxide layer in the first area to a thickness less than the preset thickness in the second area. This effectively solves the problems of low oxide layer thickness control accuracy, unstable interface quality, and difficulty in balancing passivation and tunneling performance caused by fuzzy laser parameters. Ultimately, it achieves the precise construction of the oxide layer thickness difference between the contact area and the non-contact area of ​​the solar cell electrode, improving the consistency of the device's electrical performance.

[0079] In one embodiment, the pre-tunneling oxide layer with a thickness of 1.5~2.0 nm is deposited on the back side of the substrate by thermal oxidation or ozone phase oxidation. The pre-tunneling oxide layer corresponding to the first region is locally treated by laser irradiation to reduce the thickness of the pre-tunneling oxide layer corresponding to the first region to 1.0~1.5 nm, thereby obtaining the first tunneling oxide layer. The laser parameters are: wavelength 355 nm or 532 nm, power 0.5~5 W, and scanning speed 10~100 mm / s.

[0080] In one embodiment, the scanning path of the laser irradiation is matched with the grid pattern of the subsequent metal electrodes.

[0081] According to some exemplary embodiments of this application, forming a first doped conductive layer at least on the side of the first portion away from the substrate includes: forming an intrinsic amorphous silicon layer at least on the side of the first portion away from the substrate; doping the intrinsic amorphous silicon layer using a diffusion process to obtain a doped amorphous silicon layer, wherein the flow rate of the dopant gas first decreases and then increases during the diffusion process; and annealing the doped amorphous silicon layer to form the first doped conductive layer. In this embodiment, the doping concentration is dynamically controlled by first decreasing and then increasing the flow rate of the dopant gas during the diffusion process. Specifically, the high flow rate in the initial stage of diffusion allows phosphorus atoms to rapidly penetrate into the near-interface region, forming a highly doped layer to enhance surface passivation and promote electron tunneling. Subsequently, the flow rate is reduced, decreasing the supply of phosphorus source to the depth of the intrinsic layer, forcing the doping concentration to gradually decrease within the layer, thereby constructing a low-doped inner layer region, effectively suppressing Auger recombination and reducing the risk of phosphorus atoms penetrating the tunneling oxide layer into the substrate. Finally, the flow rate is increased to form a highly doped region on the surface again to reduce contact resistance. Then, annealing is used to crystallize the doped amorphous silicon layer and activate impurities, ultimately forming a first doped conductive layer with a high-low-high doping concentration gradient. By using the above techniques and optimizing the doping distribution within the first doped conductive layer, the excellent passivation effect of the tunneling oxide layer is maintained while significantly reducing carrier recombination loss and ensuring good ohmic contact performance, thereby improving the photoelectric conversion efficiency of the solar cell.

[0082] According to some other exemplary embodiments of this application, the diffusion process includes a starting stage, an intermediate stage, and a final stage performed sequentially. The duration of the starting stage is 20 min to 40 min, the duration of the intermediate stage is 30 min to 60 min, and the duration of the final stage is 30 min to 60 min. The flow rate of the dopant gas introduced in the starting stage is 100 sccm to 300 sccm, the flow rate of the dopant gas introduced in the intermediate stage is reduced to 20 sccm to 80 sccm, and the flow rate of the dopant gas introduced in the final stage is increased to 150 sccm to 350 sccm. In this embodiment, the diffusion process is refined into three consecutive stages: initiation, intermediate, and final. The initiation stage lasts 20-40 minutes with a flow rate of 100-300 sccm; the intermediate stage lasts 30-60 minutes with the flow rate decreasing to 20-80 sccm; and the final stage lasts 30-60 minutes with the flow rate increasing back to 150-350 sccm. Specifically, the high flow rate and rapid implantation in the initiation stage cause the dopant to rapidly accumulate in the near-surface region, forming a high-concentration layer to facilitate the subsequent formation of good ohmic contacts. Subsequently, the intermediate stage involves low-flow diffusion, where the doping rate slows down, prompting the dopant to penetrate deeper into the layer at a relatively low concentration, thereby constructing a low-doping concentration layer within the layer. The buffer zone effectively reduces the carrier recombination center density in this region, suppressing nonradiative recombination losses within the bulk. The flow rate recovery in the final stage further replenishes the doping concentration near the surface and interface, maintaining a stable field-effect passivation effect and preventing passivation failure caused by low concentrations in the intermediate stages. Through this high-low-high flow rate timing control, combined with precise limitation of the duration of each stage, the doped amorphous silicon layer can naturally form a first doped conductive layer with a specific gradient distribution after annealing. This provides sufficient field effect at the interface to achieve high-quality passivation, reduces recombination losses within the layer, and maintains low contact resistance on the surface. Thus, the contradiction between passivation performance, recombination suppression, and contact resistance is balanced in a single process step, improving the photoelectric conversion efficiency of the solar cell.

[0083] In one embodiment, an intrinsic amorphous silicon layer with a thickness of 60-150 nm is deposited on the substrate-away surface of the first tunneling oxide layer using low-pressure chemical vapor deposition (LPCVD) or plasma-enhanced chemical vapor deposition (PECVD). The intrinsic amorphous silicon layer is doped using a variable-flow phosphorus diffusion process, in which a mixture of phosphine (PH3) and oxygen is introduced. The phosphine flow rate decreases and then increases according to a preset curve during the diffusion process. The diffusion temperature is 800-950 °C, and the total diffusion time is 30-120 min, forming a gradient doping distribution. Annealing is performed at 850-950 °C to crystallize the amorphous silicon layer into a polycrystalline silicon layer and activate the phosphorus doping source to obtain the first doped conductive layer.

[0084] In one embodiment, the phosphine flow rate variation curve is as follows: the phosphine flow rate is 100~300 sccm in the initial stage, decreases linearly to 20~80 sccm within 30~60 min, and then increases linearly to 150~350 sccm within 30~60 min; the oxygen flow rate remains constant at 200~600 sccm.

[0085] It should be noted that during the initial stage with a constant flow rate (0~30min, 200sccm), the phosphorus source is continuously fed in and diffuses into the interior at high temperature, ultimately forming a high-concentration region at the interface (near the first tunneling oxide layer). The intermediate stage of decreasing flow rate results in a low-concentration region in the middle; and the final stage of increasing flow rate results in a high-concentration region at the surface (away from the first tunneling oxide layer). The constant flow rate in the initial stage does not mean it is constant, but rather that the feed is continuous, allowing phosphorus atoms sufficient time to penetrate the entire thickness of the polycrystalline silicon layer. The change in doping concentration from the surface to the interior is not due to flow rate changes, but rather to diffusion kinetics. Phosphorus atoms advance from the surface to the interior, accumulating the most at the interface and the least in the middle, thus forming a high-low-high gradient distribution.

[0086] In one embodiment, the variable flow phosphorus diffusion process uses a tubular diffusion furnace with a diffusion temperature of 850~900℃ and a total diffusion time of 60~90min.

[0087] It should be noted that in the solar cell fabrication method of this application, 1) a partitioned gradient tunneling oxide layer (i.e., the first tunneling oxide layer) is prepared using laser local oxide layer thinning technology. This is achieved by precisely controlling the oxide layer thickness in the metal contact area to the target value through laser irradiation with a wavelength of 355nm or 532nm, a power of 0.5~5W, and a scanning speed of 10~100mm / s. This process is highly compatible with existing screen printing and metallization processes, requiring no additional mask or photolithography steps, and has the advantages of low cost and good scalability, making it suitable for large-scale industrial production; 2) a gradient-doped polycrystalline silicon layer (i.e., the first doped conductive layer) is prepared using a variable-flow phosphorus diffusion process. By designing a curve where the phosphine flow rate first decreases and then increases during diffusion, a layer is formed in the amorphous silicon layer from the interface to the surface. The doping concentration gradient distribution is such that, since the diffusion rate of phosphorus atoms at high temperatures is affected by the concentration of phosphorus source in the gas phase, the doping depth and concentration distribution of phosphorus atoms in the thickness direction of the amorphous silicon layer can be effectively controlled by controlling the timing and amplitude of the change in phosphine flow rate, thereby accurately achieving the required high, low, and high doping gradients; 3) The gradient doping polycrystalline silicon layer design also effectively suppresses the problem of phosphorus atoms penetrating the tunnel oxide layer into the silicon substrate. By setting a lower doping concentration region in the middle of the polycrystalline silicon layer, the excessive supply of phosphorus source during diffusion is reduced, thereby reducing the driving force for phosphorus atoms to diffuse to the interface of the first tunnel oxide layer. Compared with the traditional uniform doping process, the gradient doping design of this application can reduce the amount of phosphorus atoms penetrating by more than 40%, significantly reduce Auger recombination loss, and improve minority carrier lifetime and open circuit voltage.

[0088] The solar cells described above in this application will be specifically described below with reference to specific embodiments and comparative examples.

[0089] Example 1

[0090] The solar cell comprises: an N-type monocrystalline silicon substrate, the front side of which is texturized to form a textured surface; and a front-side emitter structure located on the front side of the N-type monocrystalline silicon substrate. The front-side emitter structure includes a second tunneling oxide layer and a second doped conductive layer. The thickness of the second tunneling oxide layer is 1.5 nm, and the thickness of the second doped conductive layer (which is polycrystalline silicon) is 80 nm. The doping element of the second doped polycrystalline silicon layer includes boron, with a boron doping concentration of 5 × 10⁻⁶. 19 atoms / cm 3 The front passivation antireflection layer, located above the front emitter structure, is an aluminum oxide / silicon nitride stacked structure; the first tunneling oxide layer, located on the back side of the N-type single-crystal silicon substrate, has the following thickness distribution. Figure 3As shown, the thickness of the first tunneling oxide layer in the first region is approximately 1.2 nm, and the thickness of the first tunneling oxide layer in the second region is approximately 1.8 nm. The thickness of the first tunneling oxide layer gradually transitions between the two regions, with a change rate of 0.3 nm / μm. The first region is located in the metal contact region, the second region is located in the non-metal contact region, and the transition region between the two regions (i.e., the third region) is located in the metal contact region and / or the non-metal contact region. Figure 3 In the diagram, the horizontal axis represents the lateral position parallel to the battery surface, and the vertical axis represents the thickness of the first tunneling oxide layer. The first doped conductive layer (polycrystalline silicon) located above the first tunneling oxide layer has a thickness of 100 nm, and its phosphorus doping concentration varies along the thickness direction as shown in the diagram. Figure 4 As shown: The doping concentration at the interface adjacent to the first tunneling oxide layer is 5 × 10⁻⁶. 20 atoms / cm 3 The doping concentration in the middle of the first doped conductive layer (approximately 50 nm from the interface) is reduced to 3 × 10⁻⁶. 19 atoms / cm 3 The doping concentration at the surface of the first doped conductive layer away from the substrate increases to 6 × 10⁻⁶. 20 atoms / cm 3 ,in, Figure 4 In the diagram, the horizontal axis represents the distance from the back surface of the polycrystalline silicon layer (i.e., the surface facing away from the substrate), and the vertical axis represents the phosphorus doping concentration. The back passivation antireflection layer located above the first doped conductive layer is an aluminum oxide / silicon nitride stacked structure. The first electrode forms an ohmic contact with the first doped conductive layer, and the second electrode forms an ohmic contact with the second doped conductive layer in the front emitter structure.

[0091] Methods for preparing solar cells include:

[0092] Step S1: Silicon substrate preparation. Provide an N-type single-crystal silicon substrate with a resistivity of 1.0~3.0 Ω·cm and a thickness of 130~150 μm. Perform standard RCA cleaning on the silicon substrate to remove surface organic matter and metallic impurities. Then, perform front-side texturing in a 2%~5% potassium hydroxide solution at a temperature of 75~85℃ to form a pyramid-shaped textured surface structure. The texturing time is 15~25 min, and the pyramid size is controlled at 2~5 μm. The formation of the textured surface structure helps to reduce the front-side light reflectivity and increase light absorption.

[0093] Step S2: Fabrication of the front-side emitter structure. A second tunneling oxide layer and a second doped conductive layer are sequentially fabricated on the front side of an N-type single-crystal silicon substrate. The second doped conductive layer is boron-doped polycrystalline silicon. Fabrication of the second tunneling oxide layer: A thermal oxidation method is used. The silicon substrate is placed in a high-temperature tube furnace and oxidized at 600-700℃ for 10-30 minutes in an O2 atmosphere to form a SiO2 tunneling oxide layer with a thickness of 1.0-2.0 nm. In this embodiment, a thickness of 1.5 nm is preferred. Fabrication of the second doped conductive layer: 1) Deposition of the intrinsic amorphous silicon layer: LPCVD is used. Silane (SiH4) gas is introduced at a temperature of 550-650℃ with a flow rate of 500-1500 sccm to deposit the intrinsic amorphous silicon layer on the front side. 1) Crystalline silicon layer: deposition time is 30-90 min, thickness is 50-100 nm, preferably 80 nm in this embodiment; 2) Boron diffusion doping: Boron doping is performed on the front intrinsic amorphous silicon layer using a tube diffusion furnace. The silicon substrate is placed in the diffusion furnace and heated to 850-950℃ (preferably 900℃ in this embodiment). Boron source gas BBr3 (flow rate 100-300 sccm) and O2 (flow rate 500-1000 sccm) are introduced. The diffusion time is 30-90 min (preferably 60 min in this embodiment). After boron diffusion is completed, N2 is introduced at 900℃ for annealing for 30 min to crystallize the amorphous silicon layer into a polycrystalline silicon layer and activate the boron doping source, forming a boron doping concentration of 5×10⁻⁶. 19 atoms / cm 3 The second doped conductive layer;

[0094] Step S3: Preparation of the first tunneling oxide layer: 1) Deposition of the pre-tunneling oxide layer: Using ozone gas phase oxidation (OGO), the back side of the silicon substrate is exposed to an ozone / O2 mixed atmosphere and oxidized at 150~300℃ for 5~15 min to form a SiO2 pre-tunneling oxide layer with a thickness of 1.5~2.0nm. In this embodiment, the preferred thickness is 1.8nm. Compared with thermal oxidation, ozone gas phase oxidation can form a dense silicon oxide film at a lower temperature and has better coverage of textured structures, making it suitable for industrial production; 2) Laser local thinning treatment: The metal contact area (i.e., the first region) is irradiated with a nanosecond pulsed laser with a wavelength of 532nm. The laser power is 2W, the scanning speed is 50mm / s, and the scanning path matches the pattern of the back metal grid line (i.e. the first electrode) printed by the screen. The laser irradiation causes the local temperature of the pre-tunneling oxide layer in the metal contact area to rise, and the silicon oxide undergoes pyrolysis and recombination, reducing the thickness to 1.2nm. The pre-tunneling oxide layer in the non-metal contact area (i.e. the second region) of the non-laser irradiated area maintains the original thickness of 1.8nm. Between the two regions (i.e. the third region), due to the Gaussian distribution of the laser spot energy density, the thickness of the pre-tunneling oxide layer shows a gradual transition of 0.3nm / μm, thus obtaining the first tunneling oxide layer.

[0095] Step S4: Preparation of the first doped conductive layer: 1) Deposition of intrinsic amorphous silicon layer: Using LPCVD, silane (SiH4) gas is introduced at a temperature of 550~650℃ at a flow rate of 1000~2000 sccm to deposit an intrinsic amorphous silicon layer on the first tunneling oxide layer. The deposition time is 60~120 min, and the thickness is 60~150 nm. In this embodiment, the thickness is preferably 100 nm. 2) Variable flow rate phosphorus diffusion doping: Phosphorus doping of the intrinsic amorphous silicon layer is performed using a tube diffusion furnace. The silicon substrate is placed in the diffusion furnace and heated to 850~900℃ (preferably 870℃ in this embodiment). A mixed gas of PH3 and O2 is introduced, wherein the flow rate of O2 is kept constant at 400 sccm. The curve of the change in the flow rate of PH3 is shown in the figure. Figure 5 As shown, the initial PH3 flow rate was 200 sccm, which linearly decreased to 50 sccm within 45 min, and then linearly increased to 250 sccm within another 45 min. The total diffusion time was 90 min. Figure 5 In the diagram, the horizontal axis represents diffusion time, and the vertical axis represents the PH3 flow rate. In the first half of the diffusion process (PH3 flow rate gradually decreases), the phosphorus source forms initial doping on the surface and near-surface region of the amorphous silicon layer. As the PH3 flow rate continues to decrease, the phosphorus source supply decreases, and the diffusion depth of phosphorus atoms into the interior of the amorphous silicon layer is limited, forming a low-doped region in the middle of the polycrystalline silicon layer. In the second half of the diffusion process (PH3 flow rate gradually increases), the phosphorus source supply increases again, and phosphorus atoms form a high concentration enrichment on the partially doped surface of the amorphous silicon layer, which is then further enriched by subsequent heat treatment. Further diffusion into the depth direction was limited, and by precisely controlling the timing and amplitude of the PH3 flow rate change, a high, low, and high gradient doping distribution was formed in the thickness direction of the amorphous silicon layer; 3) Annealing and crystallization: After diffusion, the temperature was raised to 900℃ and annealed for 60 min in a N2 atmosphere to crystallize the amorphous silicon layer into a polycrystalline silicon layer and fully activate the phosphorus doping source, thus obtaining the first doped conductive layer. Electrochemical capacitance-voltage profile analysis showed that the doping concentration distribution of the first doped conductive layer was 5×10 at the interface adjacent to the first tunneling oxide layer. 20 atoms / cm 3 The first doped conductive layer has a density of 3 × 10⁻⁶ at its center (50 nm from the interface). 19 atoms / cm 3 The surface of the first doped conductive layer facing away from the substrate is 6×10 20 atoms / cm 3 ;

[0096] Step S5: Remove the winding layer. Using a wet etching process, the winding polysilicon layer, the winding tunneling oxide layer, the borosilicate glass layer (BSG) on the front side and the side side of the silicon substrate are removed sequentially. Specifically, the PSG and BSG are first removed by soaking in a 5% HF solution for 3 minutes. Then, the winding layer is etched at 70-80°C with a mixed solution containing KOH (potassium hydroxide) and additives (such as IPA (isopropyl alcohol)) for 5-10 minutes to ensure that the passivated contact structure on the back side remains intact and the surface of the second doped conductive layer on the front side is exposed.

[0097] Step S6: Deposition of passivation and antireflection layer, 1) Deposition of front passivation and antireflection layer: Using PECVD, an aluminum oxide layer and a silicon nitride layer are deposited sequentially on the front side; the deposition process of the aluminum oxide layer is: using trimethylaluminum (TMA) and N2O as precursors, it is deposited at a temperature of 200~350℃, with a thickness of 5~10nm; the deposition process of the silicon nitride layer is: using SiH4 and NH3 as reactant gases, it is deposited at a temperature of 350~450℃, with a thickness of 70~90nm and a refractive index of 2.0~2.1; the aluminum oxide layer provides excellent field-effect passivation, and the silicon nitride layer has both antireflection and bulk passivation functions; 2) Deposition of back passivation and antireflection layer: Using a similar process to the front side, an aluminum oxide layer and a silicon nitride layer are deposited sequentially on the first doped conductive layer, with an aluminum oxide layer thickness of 5~10nm and a silicon nitride layer thickness of 90~110nm;

[0098] Step S7: Fabrication of metal electrodes (i.e., the first and second electrodes). Silver paste is printed on both the front and back sides using screen printing. The front grid pattern corresponds to the contact area of ​​the second doped conductive layer, and the back grid pattern corresponds to the metal contact area after laser thinning. After printing, ohmic contacts are rapidly formed at 750-800℃ for 2-5 seconds.

[0099] Example 2

[0100] The difference between this embodiment and Embodiment 1 is that the preparation parameters of the second doped conductive layer are different, while the other steps are the same.

[0101] In the intrinsic amorphous silicon layer deposition, the thickness of the intrinsic amorphous silicon layer was 70 nm. In the variable-flow phosphorus diffusion doping, the diffusion temperature was 880℃, and the total diffusion time was 80 min. The PH3 flow rate change curve was as follows: initially, the PH3 flow rate was 250 sccm, then linearly decreased to 60 sccm within 40 min, and then linearly increased to 280 sccm within 40 min. The O2 flow rate remained constant at 500 sccm. In the annealing crystallization and activation, the annealing temperature was 920℃, and the annealing time was 50 min. The doping concentration distribution of the obtained first doped conductive layer was measured to be 6 × 10⁻⁶ at the interface adjacent to the first tunneling oxide layer. 20 atoms / cm 3 The first doped conductive layer has a density of 2 × 10⁻⁶ in the middle (35 nm from the interface). 19 atoms / cm 3 The surface of the first doped conductive layer facing away from the substrate is 7×10 20 atoms / cm 3 .

[0102] Example 3

[0103] The difference between this embodiment and Embodiment 1 is that the preparation parameters of the first tunneling oxide layer and the first doped conductive layer are different, while the other steps are the same.

[0104] In the pre-tunneling oxide layer deposition, the pre-tunneling oxide layer was prepared by thermal oxidation at 650℃ in an O2 atmosphere for 15 min, with a thickness of 2.0 nm. In the laser local thinning treatment, the laser irradiation used a 355 nm wavelength ultraviolet nanosecond pulsed laser with a laser power of 3 W and a scanning speed of 40 mm / s, which reduced the thickness of the pre-tunneling oxide layer in the metal contact area to 1.3 nm. The thickness of the pre-tunneling oxide layer between the two regions gradually transitioned, with a change rate of 0.4 nm / μm.

[0105] In the intrinsic amorphous silicon layer deposition, the deposition thickness of the intrinsic amorphous silicon layer is 120 nm; in the variable flow rate phosphorus diffusion doping, the PH3 flow rate change curve is as follows: the initial PH3 flow rate is 150 sccm, which decreases linearly to 40 sccm within 50 min, and then increases linearly to 200 sccm within 50 min, with a total diffusion time of 100 min.

[0106] Comparative Example 1

[0107] The differences between this comparative example and Example 1 are: 1) The first tunneling oxide layer has a uniform thickness (1.5 nm) and is not subjected to laser partitioning; 2) The first doped conductive layer (100 nm thick) is produced using a conventional constant-flow phosphorus diffusion process, and the doping concentration is basically uniform along the thickness direction of the first doped conductive layer, approximately 3 × 10⁻⁶. 20 atoms / cm 3Everything else is the same as in Example 1.

[0108] Comparative Example 2

[0109] The differences between this comparative example and Example 1 are: 1) The first tunneling oxide layer has a uniform thickness (1.5 nm) and is not subjected to laser zoning; 2) The first doped conductive layer uses a conventional constant flow phosphorus diffusion process (PH3 flow rate is constant at 180 sccm, diffusion time is 90 min), and the doping concentration is basically uniform in the thickness direction of the first doped conductive layer, approximately 4 × 10⁻⁶. 20 atoms / cm 3 Everything else is the same as in Example 1.

[0110] The solar cells of Examples 1, 2, 3, Comparative Example 1, and Comparative Example 2 were subjected to electrical performance tests. IV characteristics were tested under standard AM1.5G illumination conditions (1000 W / m², 25°C). The test results for Example 1 were: open-circuit voltage (Voc) of 728 mV and short-circuit current density (Jsc) of 42.5 mA / cm². 2 The fill factor (FF) was 84.2%, and the photoelectric conversion efficiency (η) was 26.0%. The test results for Example 2 were: open-circuit voltage 724 mV, and short-circuit current density 42.3 mA / cm². 2 The fill factor was 83.9%, and the photoelectric conversion efficiency was 25.7%. The test results for Example 3 were: open-circuit voltage 726mV, and short-circuit current density 42.2mA / cm². 2 The fill factor was 84.0%, and the photoelectric conversion efficiency was 25.8%. The test results for Comparative Example 1 were: open-circuit voltage 715mV, short-circuit current density 41.2mA / cm². 2 The fill factor was 82.8%, and the photoelectric conversion efficiency was 24.8%. The test results for Comparative Example 2 were: open-circuit voltage 712mV, short-circuit current density 41.0mA / cm². 2 The fill factor is 82.5% and the photoelectric conversion efficiency is 24.5%.

[0111] Compared to the conventional battery structure of Comparative Example 1, Example 1 showed an increase of 13mV in open-circuit voltage, 1.3mA / cm² in short-circuit current density, 1.4 percentage points in fill factor, and 1.2 percentage points in absolute photoelectric conversion efficiency. Examples 1-3, compared to Comparative Examples 1 and 2, all showed improvements in open-circuit voltage, short-circuit current density, fill factor, and photoelectric conversion efficiency. Furthermore, the dark-state saturation current density, back surface dark-state saturation current density, and metal contact resistivity of the batteries in Example 1 and Comparative Example 1 were simultaneously tested; the dark-state saturation current density of the battery in Example 1 was 2.8fA / cm². 2The dark saturation current density on the back surface is 7.5 fA / cm. 2 The resistivity of the metal contact is 2.5 mΩ·cm. 2 The dark-state saturation current density of the battery in Comparative Example 1 is 3.5 fA / cm². 2 The dark saturation current density on the back surface is 15.2 fA / cm². 2 The metal contact resistivity is 3.8 mΩ·cm. 2 The above results demonstrate that the solar cell of this application has significant advantages in passivation quality, contact performance, and photoelectric conversion efficiency.

[0112] This application also provides a photovoltaic module, including: a battery string, which is formed by connecting multiple solar cells of any of the above types; an encapsulating film for covering the surface of the battery string; and a cover plate for covering the surface of the encapsulating film facing away from the battery string.

[0113] In one embodiment, the connection between batteries can be achieved through technologies such as welding and laser connection, with the aim of converging the current generated by the batteries to form a larger output power; the encapsulating film is an important component inside the photovoltaic module, playing a role in sealing and bonding. The encapsulating film can be EVA (ethylene vinyl acetate copolymer), POE (polyolefin elastomer), or other special materials, which can effectively block the influence of external factors such as moisture and dust on the batteries, while maintaining the physical stability of the batteries; the cover plate is usually transparent tempered glass, located on the outermost layer of the photovoltaic module, directly exposed to the external environment. It not only needs to have good light transmittance and mechanical strength, but also needs to have properties such as UV protection, high temperature resistance, and impact resistance to protect the internal batteries from damage.

[0114] Those skilled in the art will understand that the above embodiments are specific examples of implementing this application, and in practical applications, various changes in form and detail can be made without departing from the spirit and scope of this application. Any person skilled in the art can make various alterations and modifications without departing from the spirit and scope of this application; therefore, the scope of protection of this application should be determined by the scope defined in the claims.

Claims

1. A solar cell, characterized in that, include: The substrate has a first surface and a second surface disposed opposite to each other, the first surface dividing a first region and a second region arranged along a first direction, the first direction intersecting the thickness direction of the substrate; A first tunneling oxide layer is located on the first surface. The first tunneling oxide layer includes a first part and a second part. The first part is located on the first region, and the second part is located on the second region. The thickness of the first part is less than the thickness of the second part. A first doped conductive layer is located at least on the side of the first portion facing away from the substrate; The first electrode is located on the side of the first doped conductive layer opposite to the substrate, and the first electrode is electrically connected to the first doped conductive layer.

2. The solar cell according to claim 1, characterized in that, The first surface is further divided into a third region, which is located between the first region and the second region; the first tunneling oxide layer further includes a third part, which is located between the first part and the second part, and is connected to the first part and the second part respectively, and is located on the third region; The thickness of the third part increases in the direction from the first region to the second region.

3. The solar cell according to claim 1, characterized in that, In the direction from the first surface to the second surface, the doping concentration of the first doped conductive layer first decreases and then increases.

4. The solar cell according to claim 1, characterized in that, The difference between the thickness of the second part and the thickness of the first part is less than or equal to 0.8 nm.

5. The solar cell according to claim 1, characterized in that, The thickness of the first part is 1.0 nm to 1.5 nm, and the thickness of the second part is 1.5 nm to 2.0 nm.

6. A method for preparing a solar cell, characterized in that, The method is used to prepare the solar cell according to any one of claims 1 to 5, and the method includes: A substrate is provided, the substrate having a first surface and a second surface disposed opposite to each other, the first surface dividing a first region and a second region arranged along a first direction, the first direction intersecting the thickness direction of the substrate; A preliminary tunneling oxide layer is formed on the first surface, and the preliminary tunneling oxide layer is treated by laser irradiation to remove part of the preliminary tunneling oxide layer, thereby obtaining a first tunneling oxide layer. The first tunneling oxide layer includes a first part and a second part. The first part is located on the first region, and the second part is located on the second region. The thickness of the first part is less than the thickness of the second part. A first doped conductive layer is formed at least on the side of the first portion facing away from the substrate; A first electrode is formed on the side of the first doped conductive layer opposite to the substrate, and the first electrode is electrically connected to the first doped conductive layer.

7. The method for preparing a solar cell according to claim 6, characterized in that, In the laser irradiation process, the laser power is 0.5W~5W and the scanning speed is 10mm / s~100mm / s.

8. The method for preparing a solar cell according to claim 6, characterized in that, A first doped conductive layer is formed at least on the side of the first portion facing away from the substrate, comprising: An intrinsic amorphous silicon layer is formed at least on the side of the first portion facing away from the substrate; The intrinsic amorphous silicon layer is doped using a diffusion process to obtain a doped amorphous silicon layer. In the diffusion process, the flow rate of the dopant gas first decreases and then increases during the diffusion process. The doped amorphous silicon layer is annealed, and the annealed doped amorphous silicon layer forms the first doped conductive layer.

9. The method for preparing a solar cell according to claim 8, characterized in that, The diffusion process includes a starting stage, an intermediate stage, and a final stage performed sequentially. The duration of the starting stage is 20-40 minutes, the duration of the intermediate stage is 30-60 minutes, and the duration of the final stage is 30-60 minutes. The flow rate of the doping gas introduced in the initial stage is 100 sccm to 300 sccm, the flow rate of the doping gas introduced in the intermediate stage is reduced to 20 sccm to 80 sccm, and the flow rate of the doping gas introduced in the final stage is increased to 150 sccm to 350 sccm.

10. A photovoltaic module, characterized in that, include: A battery string, comprising a plurality of solar cells connected together as described in any one of claims 1 to 5; An encapsulating film is used to cover the surface of the battery string; A cover plate is used to cover the surface of the encapsulating film that faces away from the battery string.

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