Semiconductor optoelectronic device

Abstract

The application relates to a semiconductor photoelectric device. The semiconductor photoelectric device comprises a substrate, an epitaxial layer, an epitaxial layer, an emitting region, a passivation layer and a metal layer. The epitaxial layer is arranged on the upper surface of the substrate. The epitaxial layer has grooves arranged at intervals along a first direction and extending along a second direction. The first direction and the second direction intersect. The epitaxial layer is formed in the epitaxial layer on the side wall of the groove. The emitting region is formed in the epitaxial layer on the side wall of the groove and is located in the base region. The passivation layer covers the side wall and the bottom of the groove. The metal layer is arranged on the side of the epitaxial layer away from the substrate and is connected with the emitting region. The application can improve the current transmission ratio of the device, widen the response wavelength width and reduce the power consumption of the device.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to a semiconductor optoelectronic device. Background Technology

[0002] As a core branch of semiconductor optoelectronic devices, phototransistors are key devices for converting optical signals into electrical signals. Their development and application have always kept pace with the upgrading of semiconductor technology and emerging industries. They have become an indispensable basic component in modern optoelectronic systems and are key components for forming optocouplers.

[0003] However, traditional phototransistors suffer from the following technical bottlenecks: severe surface recombination and low photoelectric conversion efficiency: the highly doped base and emitter regions on the front side contain a large number of recombination centers, which makes it easy for photogenerated carriers on the surface to be consumed by recombination, significantly reducing the device's photoresponsivity and current transfer ratio (CTR); limited depletion layer distribution and narrow response spectrum: photogenerated carriers and the depletion layer are mainly distributed parallel to the chip surface, resulting in poor compatibility with light wavelengths at different penetration depths and a narrow response band; and poor electrical performance: the device has a high on-state voltage drop and high power consumption, which restricts the overall performance and long-term reliability.

[0004] Therefore, improving the current transfer ratio of phototransistors, broadening the wavelength of the response light, and reducing device power consumption are urgent problems to be solved. Summary of the Invention

[0005] Based on this, this application provides a semiconductor optoelectronic device that can improve the current transfer ratio, broaden the wavelength of the response light, and reduce the power consumption of the device.

[0006] According to some embodiments of this application, a semiconductor optoelectronic device is provided, comprising: a substrate, an epitaxial layer, an emitter region, a passivation layer, and a metal layer. The epitaxial layer is disposed on the upper surface of the substrate. The epitaxial layer has trenches spaced apart along a first direction and extending along a second direction, wherein the first and second directions intersect. The epitaxial layer is formed within the epitaxial layer of the trench sidewalls. The emitter region is formed within the epitaxial layer of the trench sidewalls and is located within the base region. The passivation layer covers the sidewalls and bottom of the trenches. The metal layer is disposed on the side of the epitaxial layer opposite to the substrate and is connected to the emitter region.

[0007] In some embodiments of this application, the junction depth of the base region is less than 10 μm.

[0008] In some embodiments of this application, the trench has a first dimension along a first direction and a second dimension along the substrate thickness direction, and the ratio of the first dimension to the second dimension is greater than 0.08.

[0009] In some embodiments of this application, the second dimension is greater than 21 μm.

[0010] In some embodiments of this application, the dimension along the first direction between two adjacent base regions located in two adjacent trenches is greater than 30 μm and less than 120 μm.

[0011] In some embodiments of this application, the dimension between two adjacent metal layers along the first direction is greater than 30 μm.

[0012] In some embodiments of this application, the base region is also formed within the epitaxial layer at the bottom of the trench.

[0013] In some embodiments of this application, the passivation layer also covers the upper surface of the epitaxial layer; the passivation layer located on the upper surface of the epitaxial layer has an opening that exposes the emission region.

[0014] In some embodiments of this application, the metal layer fills the opening and is in contact with the emission region.

[0015] In some embodiments of this application, the semiconductor optoelectronic device further includes a back metal layer disposed on the lower surface of the substrate.

[0016] The semiconductor optoelectronic device provided in this application may have, or at least has, the following advantages:

[0017] In this embodiment, the base region and emitter region are formed within the sidewalls of the trench, maximizing the generation of photogenerated carriers near the depletion region of the base region, thereby generating an effective photocurrent and significantly improving the current transfer ratio (CTR). Since the trench sidewalls serve as the light-receiving surface, light enters the base and emitter regions from the side. This lateral light-receiving structure is better compatible with various light wavelengths at different penetration depths, broadening the response wavelength range of the device. Furthermore, the trench structure provides more area for the emitter and base regions, enabling better conduction modulation of the substrate, reducing the on-state voltage drop, and thus reducing device power consumption. Because the light-receiving surface is a stepped structure, the epitaxial thickness from the bottom of the step to the substrate layer is not affected by substrate doping, further reducing the on-state voltage drop and thus further reducing device power consumption. Attached Figure Description

[0018] To more clearly illustrate the technical solutions in the embodiments of this application or the conventional technology, the drawings used in the description of the embodiments or the conventional technology will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0019] Figure 1 This is a cross-sectional structural diagram of a semiconductor optoelectronic device provided in an embodiment of this application;

[0020] Figure 2A cross-sectional structural schematic diagram of another semiconductor optoelectronic device provided in an embodiment of this application;

[0021] Figure 3 A cross-sectional structural schematic diagram of another semiconductor optoelectronic device provided in an embodiment of this application;

[0022] Figure 4 This is a schematic cross-sectional view of the structure obtained in step S1 of a method for fabricating a semiconductor optoelectronic device according to an embodiment of this application.

[0023] Figure 5 This is a schematic cross-sectional view of the structure obtained in step S2 of a method for fabricating a semiconductor optoelectronic device according to an embodiment of this application.

[0024] Figure 6 This is a cross-sectional structural diagram of the structure obtained in step S3 of a method for fabricating a semiconductor optoelectronic device according to an embodiment of this application.

[0025] Figure 7 This is a schematic cross-sectional view of the structure obtained in step S4 of a method for fabricating a semiconductor optoelectronic device according to an embodiment of this application.

[0026] Figure 8 This is a schematic cross-sectional view of the structure obtained in step S5 of a method for fabricating a semiconductor optoelectronic device according to an embodiment of this application.

[0027] Figure 9 This is a cross-sectional structural diagram of the structure obtained in step S6 of a method for fabricating a semiconductor optoelectronic device according to an embodiment of this application.

[0028] Explanation of reference numerals in the attached figures:

[0029] 10-Substrate; 11-Epipolar layer; 12-Trench; 2-Base region; 3-Emitter region; 4-Passivation layer; 5-Metal layer; 6-Back metal layer. Detailed Implementation

[0030] To facilitate understanding of the present invention, a more complete description will be given below with reference to the accompanying drawings. Preferred embodiments of the invention are shown in the drawings. However, the invention can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to provide a thorough and complete understanding of the disclosure of the invention.

[0031] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. The terminology used herein in the description of the invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0032] When using the terms “including,” “having,” and “comprising” as described herein, another component may be added unless explicitly qualifying terms such as “only,” “consisting of,” etc. are used. Unless otherwise stated, singular terms may include plural forms and should not be construed as having a quantity of one.

[0033] It should be understood that although the terms “first,” “second,” etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used only to distinguish one element from another. For example, without departing from the scope of this application, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element. It should be understood that, in addition to the orientations shown in the figures, spatial relation terms also include different orientations of the device in use and operation. For example, if the device in the figures is flipped, an element or feature described as “below” or “under” or “beneath” will be oriented “above” the other element or feature. Thus, the exemplary terms “below” and “under” can include both upper and lower orientations. Furthermore, the device may also include other orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptive terms used herein are interpreted accordingly.

[0034] When used herein, the singular forms of “a,” “an,” and “the” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that when the terms “comprise” and / or “comprising” are used in this specification, the presence of the stated feature, integer, step, operation, element, and / or part is established, but the presence or addition of one or more other features, integers, steps, operations, elements, parts, and / or groups is not excluded. Meanwhile, when used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0035] In this application, unless otherwise expressly specified and limited, the terms "connected" and "linked" should be interpreted broadly. For example, they can refer to a direct connection or an indirect connection through an intermediate medium, or they can refer to the internal connection of two elements or the interaction between two elements. Those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances.

[0036] It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of this disclosure. Although the illustrations only show components related to this disclosure and are not drawn according to the actual number, shape and size of the components, the form, quantity and proportion of each component can be arbitrarily changed in actual implementation, and the layout of the components may also be more complex.

[0037] As a core branch of semiconductor optoelectronic devices, phototransistors are key devices for converting optical signals into electrical signals. Their development and application have always kept pace with the upgrading of semiconductor technology and emerging industries. They have become an indispensable basic component in modern optoelectronic systems and are key components for forming optocouplers.

[0038] Research on phototransistors began in the 1950s, emerging alongside the development of semiconductor technology. Initially, they were primarily used in detection and control systems in the military and aerospace fields. Their core working principle utilizes the photoelectric effect: when light shines on the base region, the resulting electron-hole pairs are amplified by the transistor to form a significant photocurrent. Compared to photodiodes, they possess higher sensitivity and built-in signal amplification capabilities, allowing them to respond to weak light signals without the need for additional amplification circuitry.

[0039] Phototransistors possess outstanding characteristics such as high gain, fast response speed, good linearity, and simple structure. Based on their response wavelength, they can be divided into three categories: ultraviolet, visible, and infrared, adaptable to different application scenarios. Their application areas have expanded comprehensively from traditional industries to emerging industries, covering multiple key fields: in industrial automation, they serve as core components of photoelectric switches and counters for object detection, position positioning, and speed measurement; in the communications field, they undertake the tasks of optical signal reception and amplification; in medical equipment, they are used in biological detection scenarios such as blood analysis and cell counting; and in emerging industries, they are used for light sensing in smart homes, infrared detection in security monitoring, and environmental perception systems for new energy vehicles.

[0040] A phototransistor, also known as a photodiode, is a transistor that essentially has a photodiode connected between the base and collector of a transistor. The current in the photodiode is equivalent to the base current of the transistor. Because of its current amplification capability, a phototransistor is much more sensitive than a photodiode, and can output a large photocurrent at its collector. In the absence of light, the phototransistor is in the off state, with no electrical signal output. When light shines on the base of the phototransistor, it conducts. First, the photoelectric conversion occurs through the photodiode, then the photocurrent is amplified by the transistor, and finally, the amplified electrical signal is output from either the emitter or collector.

[0041] Current transfer ratio (CTR) is an important parameter in optocouplers, defined as the percentage of output current (Ic) to input current (If). The formula is: CTR = (Ic / If) × 100%. A high CTR directly affects the performance of the optocoupler and the stability of signal transmission. For example, a high CTR (e.g., 100%) means that when the input current is 10mA, the output current is also 10mA, indicating a strong signal; while a low CTR (e.g., 20%) may lead to signal attenuation, affecting the recognition capability of subsequent circuits.

[0042] Different wavelengths of light penetrate silicon to varying depths, resulting in different distributions of photogenerated carriers. Photogenerated carriers require a reverse-biased electric field in the CB junction (collector-base junction) of a phototransistor to generate photocurrent. The depletion layer width of traditional photosensitive devices cannot cover the generation range of photogenerated carriers, causing most photogenerated carriers to fail to generate photocurrent, thus reducing photoresponsivity.

[0043] Traditional phototransistors typically employ a planar structure, where the base and emitter regions are formed on the upper surface of the epitaxial layer. This planar structure has the following drawbacks: In a traditional planar structure, the base and emitter regions are located on the front side of the chip (i.e., the upper surface of the epitaxial layer), which is covered by highly doped base and emitter regions. Highly doped silicon contains numerous recombination centers. When light enters from the front of the chip, photogenerated carriers generated on the surface of the base and emitter regions are easily consumed by these recombination centers, failing to effectively participate in photocurrent generation, leading to reduced photoresponsivity and a decrease in CTR parameters. In a traditional planar structure, photogenerated carriers are mainly generated parallel to the chip surface, and the depletion layer is also distributed parallel to the chip surface. This structure has poor compatibility with light wavelengths at different penetration depths, resulting in a narrow response wavelength range. Devices with traditional planar structures have higher power consumption and higher on-state voltage drop, affecting the overall performance and reliability of the device.

[0044] Therefore, improving the CTR parameter of phototransistors, broadening the wavelength of the response light, and reducing device power consumption are technical problems that urgently need to be solved in this field.

[0045] Please see Figure 1 This application provides a semiconductor optoelectronic device, including: a substrate 10, an epitaxial layer 11, a base region 2, an emitter region 3, a passivation layer 4, and a metal layer 5. The epitaxial layer 11 is disposed on the upper surface of the substrate 10. The epitaxial layer 11 has trenches 12 spaced apart along a first direction and extending along a second direction, wherein the first and second directions intersect. The base region 2 is formed within the epitaxial layer 11 on the sidewalls of the trenches 12. The emitter region 3 is formed within the epitaxial layer 11 on the sidewalls of the trenches 12 and is located within the base region 2. The passivation layer 4 covers the sidewalls and bottom of the trenches 12. The metal layer 5 is disposed on the side of the epitaxial layer 11 opposite to the substrate 10 and is connected to the emitter region 3.

[0046] It should be noted here that the first direction refers to the arrangement direction of the grooves 12 (i.e., the spacing direction between adjacent grooves 12), and the second direction refers to the extension direction of the grooves 12 (i.e., the length direction of the grooves 12). The first direction and the second direction intersect, and preferably, the first direction and the second direction are perpendicular to each other.

[0047] This application embodiment adopts a trench-type side base region structure, in which the base region 2 and the emitter region 3 are formed within the sidewall of the trench 12, rather than on the upper surface of the epitaxial layer 11, which has the following technical effects:

[0048] First, it maximizes the generation of photogenerated carriers near the depletion region of base region 2. In traditional planar structures, photogenerated carriers are mainly generated in a direction parallel to the chip surface, with some carriers generated far from the depletion region, unable to effectively participate in the generation of photocurrent. However, in the trench-type side-mounted base structure, light enters from the trench opening and illuminates the sidewall of trench 12, allowing photogenerated carriers to be generated directly within the depletion region of base region 2. This significantly improves carrier collection efficiency, thereby generating effective photocurrent and significantly improving the current transfer ratio (CTR).

[0049] Secondly, the flat area on the front side of the chip (i.e., the upper surface of the epitaxial layer 11) is not largely covered by the base region 2 and the emitter region 3, thus avoiding the recombination consumption effect of recombination centers in highly doped silicon on photogenerated carriers. In traditional planar structures, the front side of the chip is covered by highly doped base region 2 and emitter region 3. Highly doped silicon contains numerous defects and recombination centers. When light strikes these areas, photogenerated carriers generated on the surface are easily consumed by recombination centers. However, in this embodiment, the base region 2 and emitter region 3 are formed within the sidewalls of the trench 12, and the flat area on the front side of the chip remains the original epitaxial layer surface. There are no recombination centers introduced by the highly doped region, effectively reducing the ineffective recombination loss of photogenerated carriers.

[0050] Third, the sidewalls of trench 12, serving as lateral light-receiving surfaces, can better accommodate multiple wavelengths of light. Different wavelengths of light penetrate silicon to varying depths. Short-wavelength light penetrates shallowly, primarily generating photogenerated carriers near the surface; long-wavelength light penetrates deeply, generating photogenerated carriers in deeper regions. Traditional planar structures have a fixed depletion layer width, making it difficult to simultaneously accommodate wavelengths with different penetration depths. However, in the trench-type side-base region structure, light enters the sidewall obliquely from the opening of trench 12. Different wavelengths of light are absorbed at different depths on the sidewall, and the base region 2 on the sidewall has a large distribution range in the longitudinal direction (along the trench depth direction), capable of covering the photogenerated carrier regions generated by light wavelengths with different penetration depths, thereby broadening the response light wavelength width of the device.

[0051] Fourth, the trench 12 structure provides more area for the emitter region 3 and the base region 2. With the same chip planar area, the sidewall area of ​​the trench 12 is much larger than the surface area of ​​the planar structure, thus allowing for a larger emitter region 3 and base region 2. Larger emitter regions 3 and base regions 2 enable better conduction modulation of the substrate, reducing the on-state voltage drop of the device.

[0052] Fifth, since the light-receiving surface is a stepped structure (i.e., the sidewall of trench 12), the thickness of the epitaxial layer 11 from the bottom of the step to the substrate 10 is not affected by the doping of the substrate 10. In conventional structures, the thickness design of the epitaxial layer 11 needs to consider the impact of the doping of the substrate 10 on the effective thickness of the epitaxial layer, and sufficient margin needs to be reserved. However, in the trench structure of this application, the trench 12 extends downward from the upper surface of the epitaxial layer 11, and the effective thickness of the epitaxial layer at the sidewall is directly determined by the depth of the trench 12, and is not affected by the doping of the substrate 10. Therefore, the thickness design of the epitaxial layer 11 can be further optimized, and the on-state voltage drop can be further reduced.

[0053] In some embodiments, substrate 10 provides mechanical support for the device. Substrate 10 may be a silicon substrate, and its doping type and concentration may be selected according to the device type.

[0054] In some embodiments, the epitaxial layer 11 is disposed on the upper surface of the substrate 10. The epitaxial layer 11 is formed on the substrate 10 by an epitaxial growth process and has a predetermined doping concentration and thickness. The epitaxial layer 11 is the core functional layer of the device, and both the base region 2 and the emitter region 3 are formed within the epitaxial layer 11.

[0055] In some embodiments, the epitaxial layer 11 has trenches 12. The trenches 12 extend from the upper surface of the epitaxial layer 11 toward the substrate 1. A plurality of trenches 12 are spaced apart along a first direction, and each trench 12 extends along a second direction. The first and second directions intersect, and preferably, the first and second directions are perpendicular to each other.

[0056] In some embodiments, the base region 2 is formed within the epitaxial layer 11 on the sidewall of the trench 12. For example, the base region 2 is formed in the sidewall region of the trench 12 by an ion implantation process. The doping type of the base region 2 is opposite to that of the epitaxial layer 11, thereby forming a PN junction at the sidewall of the trench 12.

[0057] In some embodiments, the emitter region 3 is formed within the epitaxial layer 11 on the sidewall of the trench 12 and is located within the base region 2. The emitter region 3 is formed within the base region 2 by an ion implantation process, and its doping type is opposite to that of the base region 2, with a higher doping concentration. The emitter region 3 and the base region 2 together constitute the emitter junction (EB junction) of the transistor.

[0058] In some embodiments, the passivation layer 4 covers the sidewalls and bottom of the trench 12 to protect the device surface and prevent surface leakage and contamination.

[0059] In some embodiments, the metal layer 5 is disposed on the side of the epitaxial layer 11 opposite to the substrate 10 and is connected to the emitter region 3. The metal layer 5 electrically connects all the emitter regions 3 together, serving as the emitter lead of the device.

[0060] In some embodiments, the junction depth of base region 2 is less than 10 μm. For example, the junction depth of base region 2 can be 10 μm, 8 μm, 6 μm, 4 μm, 2 μm, or 1 μm, etc.

[0061] In some examples, the junction depth of base region 2 refers to the depth at which the doping concentration of base region 2 is equal to the background doping concentration of epitaxial layer 11, extending from the surface of the trench 12 sidewall into the epitaxial layer 11. Base region 2 is formed within the sidewall of trench 12 via ion implantation, with the implanted ion type selected based on the device type. For NPN phototransistors, epitaxial layer 11 is N-type, and base region 2 is P-type doped (e.g., boron ion implantation).

[0062] In some examples, the junction depth of base region 2 is controlled to be less than 10 μm based on the following technical considerations: Excessive junction depth in base region 2 leads to increased parasitic resistance and capacitance, thus affecting the device's operating frequency and switching speed. Controlling the junction depth to less than 10 μm ensures sufficient photogenerated carrier collection efficiency while keeping parasitic resistance and capacitance within acceptable ranges, thus guaranteeing good high-frequency response characteristics of the device.

[0063] In some embodiments, the trench 12 has a first dimension (i.e., the width A of the trench 12) along a first direction, and a second dimension (i.e., the depth B of the trench 12) along the thickness direction of the substrate, and the ratio of the first dimension to the second dimension is greater than 0.08. That is, the ratio of the width A to the depth B of the trench 12 is greater than 0.08.

[0064] In some examples, the ratio A / B of the width A to the depth B of the trench 12 is a key geometric parameter that directly affects the illumination effect of incident light on the sidewalls of the trench 12. When the ratio A / B is small, the trench 12 is relatively deep and narrow, and the obliquely incident light is more likely to illuminate the sidewalls of the trench 12 rather than directly illuminating the bottom of the trench 12.

[0065] In some examples, the A / B ratio is less than 0.087, i.e., less than tan(5°). The physical meaning of this value is that when light is incident at an angle greater than 5°, because the ratio of the width A to the depth B of the trench 12 satisfies A / B < tan(5°), the light will illuminate the sidewalls of the trench 12 instead of its bottom. This allows more light to generate photogenerated carriers in the base region 2 and emitter region 3 at the sidewalls, thus utilizing the photocurrent generated by the light more effectively and improving the current transfer ratio (CTR).

[0066] It is understandable that the smaller the A / B ratio, the deeper and narrower the trench 12, and the wider the range of angles from which the oblique incident light can be received. However, if the A / B ratio is too small, the etching difficulty of the trench 12 increases, and the uniformity of ion implantation inside the trench 12 may be affected. Therefore, the A / B ratio can be optimized according to the actual process capability and device performance requirements. For example, A / B can be 0.087, 0.1, 0.2, 0.5, or 1.

[0067] In some embodiments, the second dimension is greater than 21 μm. That is, the depth B of the trench 21 is greater than 21 μm.

[0068] In some examples, the depth B of the trench 21 can be 21 μm, 25 μm, 30 μm, 35 μm or 40 μm, etc.

[0069] In some examples, the lower limit of the trench 12 depth B is determined based on considerations of the light incident depth.

[0070] For example, the incident depth of light in silicon is approximately 30 μm. When the light is incident at a 45° angle, the projected path length of the light on the sidewall of trench 12 is approximately 30 μm / cos(45°) ≈ 42.4 μm. To ensure sufficient absorption of the light on the sidewall, the depth B of trench 12 needs to be sufficiently large. Using 30 μm / 1.414 ≈ 21.2 μm as a reference, setting the depth B of trench 12 to be greater than 21 μm ensures that light incident at a 45° angle is completely attenuated and absorbed on the sidewall of trench 12, maximizing the generation efficiency of photogenerated carriers.

[0071] In some embodiments, the dimension C (i.e., the spacing C) between two adjacent base regions located within two adjacent trenches 12 and along the first direction is greater than 30 μm and less than 120 μm. For example, the spacing C can be 30 μm, 40 μm, 50 μm, 60 μm, 80 μm, 100 μm, or 120 μm, etc.

[0072] In some examples, the spacing C is the distance along the first direction (the arrangement direction of the trenches 12) between the two closest base regions 2 in two adjacent trenches 12. The size of the spacing C directly affects the collection efficiency of photogenerated carriers and the electrical performance of the device.

[0073] In some examples, when the spacing C is greater than 30 μm, the epitaxial layer 11 between adjacent trenches 12 has sufficient thickness and volume, allowing photogenerated carriers generated in the epitaxial layer 2 enough time and space to diffuse into the depletion region of the base region 2 and be collected by the reverse bias electric field to form an effective photocurrent. If the spacing C is too small, the volume of the epitaxial layer 11 between adjacent trenches 12 is insufficient, and some photogenerated carriers may be recombinated and consumed before reaching the depletion region, reducing the carrier collection efficiency.

[0074] In some examples, when the spacing C is less than 120 μm, it can be ensured that photogenerated carriers between adjacent trenches 12 can effectively enter the depletion region. Assuming the width of the CB junction depletion layer of base region 2 is approximately 20 μm on each side, the maximum distance that the depletion layers of the two base regions 2 can cover in the region between adjacent trenches 12 is approximately (20 μm + 20 μm) × 3 = 120 μm. By controlling the spacing C within 120 μm, it can be ensured that most of the photogenerated carriers generated within this range can be collected by the depletion region, thereby guaranteeing a high current conversion efficiency.

[0075] In some embodiments, the dimension D between two adjacent metal layers 5 along the first direction is greater than 30 μm. For example, the dimension D can be 30 μm, 35 μm, 40 μm, 50 μm, or 60 μm, etc.

[0076] In some examples, the metal layer 5 is disposed on the side of the epitaxial layer 11 facing away from the substrate 10, and is used to connect the emitter region 3. The spacing D between two adjacent metal layers 5 needs to be greater than 30 μm to ensure sufficient electrical isolation between adjacent metal layers 5 and prevent short circuits or leakage between metal layers 5. At the same time, sufficient spacing D also facilitates light to enter the trench 12 from the gap between the metal layers 5 without being blocked by the metal layers 5, ensuring that the light can fully illuminate the sidewalls of the trench 12.

[0077] In some embodiments, the base region 2 is also formed within the epitaxial layer 11 at the bottom of the trench 12.

[0078] In this embodiment, the base region 2 is formed not only within the sidewall of the trench 12 but also within the bottom of the trench 12. For example, in the ion implantation process, the implantation direction is perpendicular to both the sidewall and the bottom of the trench 12; therefore, the base region 2 is formed simultaneously on both the sidewall and the bottom of the trench 12. The base region 2 at the bottom of the trench 12 can also collect photogenerated carriers, increasing the total area of ​​the base region 2 and further improving the collection efficiency of photogenerated carriers.

[0079] In some examples, forming a base region 2 at the bottom of the trench 12 can enhance the PN junction area between the base region 2 and the epitaxial layer 11, which is beneficial to improving the current amplification factor of the device. At the same time, the base region 2 at the bottom can serve as an electric field modulation region, optimizing the electric field distribution inside the trench 12 and reducing the electric field concentration effect.

[0080] In some embodiments, the passivation layer 4 also covers the upper surface of the epitaxial layer 11. The passivation layer 4 located on the upper surface of the epitaxial layer 11 has an opening that exposes the emission region 3.

[0081] In some examples, the passivation layer 4 covers the sidewalls and bottom of the trench 12 and extends to the upper surface of the epitaxial layer 11, providing protection for the entire device surface. The material of the passivation layer 4 can be silicon oxide (SiO2), silicon nitride (Si3N4), or other suitable insulating dielectric materials. The passivation layer 4 is formed by thermal oxidation, chemical vapor deposition (CVD), or other deposition processes.

[0082] In some examples, an opening is formed in the passivation layer 4 located on the upper surface of the epitaxial layer 11 by photolithography and etching processes, exposing the emitter region 3. For example, at the sidewall of the trench 12, a portion of the emitter region 3 is close to the upper surface region of the epitaxial layer 11, and the opening in the passivation layer 4 exposes this portion of the emitter region 3 so that the subsequent metal layer 5 can form an electrical connection with the emitter region 3.

[0083] In some examples, the design of the passivation layer 4 covering the upper surface of the epitaxial layer 11 has the following technical effects: on the one hand, the passivation layer 4 protects the upper surface of the epitaxial layer 11, preventing surface contamination and oxidation, and improving the long-term reliability of the device; on the other hand, since the flat area of ​​the upper surface of the epitaxial layer 11 remains the original epitaxial layer surface (not covered by the base region 2 and the emitter region 3), the passivation layer 4 directly covers the original epitaxial layer surface, avoiding defects and interface states at the interface between the highly doped region and the passivation layer 4, which is beneficial to reducing the surface recombination rate.

[0084] In some embodiments, the metal layer 5 fills the opening and is in contact with the emission region 3.

[0085] In some examples, the metal layer 5 is deposited on the passivation layer 4 by processes such as sputtering, evaporation, or electroplating, and fills the openings in the passivation layer 4, forming a direct metal-semiconductor contact with the exposed emission region 3. The material of the metal layer 5 can be aluminum (Al), gold (Au), copper (Cu), or other metals with good electrical conductivity.

[0086] In some examples, the design of metal layer 5 filling the openings and directly contacting the emitter region 3 ensures low contact resistance and reliable electrical connection between metal layer 5 and emitter region 3. Metal layer 5 electrically connects the emitter regions 3 at all the sidewalls of trench 12 together, serving as the common emitter lead of the device. After depositing metal layer 5, it is patterned using photolithography and etching processes to maintain an appropriate spacing D (greater than 30 μm) between adjacent trenches 12, ensuring electrical isolation.

[0087] In some embodiments, the semiconductor optoelectronic device further includes a back metal layer 6 disposed on the lower surface of the substrate 10.

[0088] In some examples, the back metal layer 6 is used to form an electrical connection with the external electrode, serving as the collector lead of the device. The material of the back metal layer 6 can be a metal such as titanium (Ti), nickel (Ni), silver (Ag), aluminum (Al), or gold (Au), or it can be a stacked structure of multiple metals. The back metal layer 7 is deposited on the lower surface of the substrate 10 by processes such as sputtering, evaporation, or electroplating.

[0089] In some examples, the back metal layer 6 forms an ohmic contact with the substrate 1, ensuring that the collector current can be conducted from the inside of the device to the external circuitry with low impedance. In one specific example, the substrate 10 is a heavily doped N-type silicon substrate, and the back metal layer 6 forms a good ohmic contact with the N-type substrate.

[0090] In some embodiments, the semiconductor device is an NPN phototransistor. The substrate 10 is a heavily doped N-type silicon substrate. The epitaxial layer 11 is a lightly doped N-type epitaxial layer. The trench 12 extends from the upper surface of the epitaxial layer 11 toward the substrate 10. The base region 2 is a P-type doped region formed within the epitaxial layer 2 on the sidewalls and bottom of the trench 12, with a junction depth of less than 10 μm. The emitter region 3 is a heavily doped N-type region formed within the base region 3 on the sidewalls of the trench 12. The passivation layer 4 is a silicon oxide layer covering the sidewalls and bottom of the trench 12 and the upper surface of the epitaxial layer 11, and has an opening at the emitter region 3. The metal layer 5 fills the opening and connects to the emitter region 3, electrically connecting all emitter regions 3 together. A back metal layer 6 is formed on the lower surface of the substrate 10.

[0091] In some examples, the specific dimensional parameters of the trench 12 are as follows: the depth B of the trench 12 is greater than 21 μm, and the width A of the trench 12 is determined according to the relationship A / B > 0.08. The spacing C between adjacent base regions 2 in adjacent trenches 12 along the first direction is 30 μm to 120 μm. The spacing D between adjacent metal layers 5 along the first direction is greater than 30 μm.

[0092] In some examples, when light is incident from above the device, it enters the trench 12 through the gaps between the metal layers 5 and illuminates the base region 2 and emitter region 3 on the sidewalls of the trench 12. Photons generate electron-hole pairs in the base region 2 and the epitaxial layer 11. The photogenerated carriers separate under the influence of the reverse bias electric field of the CB junction, forming a photocurrent. This photocurrent is equivalent to the base current of a transistor. After being amplified by the transistor, the amplified electrical signal is output from between the back metal layer 6 (collector) and the metal layer 5 (emitter).

[0093] In this embodiment, the base region 2 and the emitter region 3 are formed within the sidewalls of the trench 12, maximizing the generation of photogenerated carriers near the depletion region of the base region 2, thereby generating an effective photocurrent and significantly improving the current transfer ratio (CTR). Since the sidewalls of the trench 12 serve as the light-receiving surface, light enters the base region 2 and emitter region 3 from the side. This lateral light-receiving structure can better accommodate multiple light wavelengths with different penetration depths, broadening the response wavelength range of the device. Furthermore, the trench structure provides more area for the emitter region 3 and the base region 2, enabling better conductance modulation of the substrate 10, reducing the on-state voltage drop, and thus reducing the device's power consumption. Because the light-receiving surface is a stepped structure, the epitaxial thickness from the bottom of the step to the substrate 10 is not affected by the substrate doping uplift, further reducing the on-state voltage drop and thus further reducing the device's power consumption.

[0094] In some embodiments, please refer to Figure 2 The base region 2 is formed within the epitaxial layer 11 on the sidewalls and bottom of the trench 12, and the emitter region 3 is formed not only within the sidewalls of the trench 12 but also within the bottom of the trench 12. The emitter region 3 at the bottom of the trench 12 and the emitter region 3 on the sidewalls are electrically connected together through the metal layer 5.

[0095] In this embodiment, setting the emitter region 3 at the bottom of the trench 12 can further increase the total area of ​​the emitter region 3, enhance the conductivity modulation effect on the substrate 1, and reduce the on-state voltage drop of the device. Simultaneously, the bottom emitter region 3 can also collect photogenerated carriers generated by some of the light incident from the bottom of the trench 12, improving light utilization efficiency. This bottom-set emitter region 3 design is suitable for applications with high requirements for on-state voltage drop, optimizing the device's conduction characteristics by increasing the emitter region area.

[0096] In some embodiments, please refer to Figure 3 The emission area 3 is formed within the sidewall of the trench 12, but the emission area 3 does not cover the entire area of ​​the sidewall of the trench 12. For example, the emission area 3 only covers a portion of the sidewall of the trench 12 (e.g., the upper half of the sidewall), while the lower half of the sidewall only retains the base area 2 and does not have the emission area 3.

[0097] In this embodiment, on the one hand, the emission region 3 is concentrated in the upper half of the sidewall, which is closer to the opening of the groove 12 where the light is incident, and can more effectively utilize the incident light energy to generate photogenerated carriers; on the other hand, the lower half of the sidewall retains the base region 2 without setting the emission region 3, which increases the effective area of ​​the base region 2, which is beneficial for collecting photogenerated carriers generated by light wavelengths with deeper penetration depth, and further broadens the response light wavelength width of the device.

[0098] The fabrication method of the semiconductor optoelectronic device according to the embodiments of this application will be described in detail below with reference to the specific fabrication process. Please refer to... Figure 1 , Figures 4-9 The preparation method includes the following steps:

[0099] Please see Figure 4 In step S1, a heavily doped N-type silicon substrate is used as substrate 10, and a lightly doped N-type epitaxial layer 11 is formed on the upper surface of substrate 10 by an epitaxial growth process.

[0100] Please see Figure 5 In step S2, a trench 12 pattern is defined on the upper surface of the epitaxial layer 11 using photolithography, and then the trench 12 is etched in the epitaxial layer 11 using a dry etching process (e.g., deep reactive ion etching). The trenches 12 are spaced apart along a first direction and extend along a second direction. The width A and depth B of the trenches 12 satisfy A / B>0.08, and the depth B is greater than 21 μm.

[0101] Please see Figure 6 In step S3, a P-type base region 2 is formed in the epitaxial layer 11 on the sidewalls and bottom of the trench 12 using an ion implantation process. The implanted ion is boron (B), and the implantation energy and dose are optimized according to the junction depth requirements of the base region 2, controlling the junction depth to be less than 10 μm. The implantation angle is adjusted according to the sidewall angle of the trench 12 to ensure that the ions can be effectively implanted into the sidewalls.

[0102] Please see Figure 7 In step S4, an N-type emitter region 3 is formed within the base region 2 on the sidewall of trench 12 using an ion implantation process. The implanted ions are phosphorus (P) or arsenic (As), and the implantation energy and dose are optimized according to the depth and concentration requirements of the emitter region 3. In a specific example, the emitter region 3 is formed only within the sidewall of trench 12, and no emitter region 3 is provided at the bottom of trench 12 to avoid forming unnecessary electrical paths between the bottom emitter region 3 and the bottom base region 2.

[0103] Please see Figure 8 In step S5, a passivation layer 4 is grown on the upper surface of the epitaxial layer 11 and on the sidewalls and bottom of the trench 12. The passivation layer 4 is made of silicon oxide (SiO2) and is formed by thermal oxidation or chemical vapor deposition. The thickness of the passivation layer 4 is set according to the insulation requirements of the device.

[0104] Please see Figure 9 In step S6, a metal pattern is defined using photolithography, and then an opening is formed by etching a passivation layer 4 at the location corresponding to the emitter region 3, allowing the metal layer 5 to fill the opening and directly contact and connect with the emitter region 3. Excess metal layer 5 is removed using an etching process, ensuring that the spacing D between adjacent metal layers 5 is greater than 30 μm.

[0105] Please see Figure 1 In step S7, after thinning and cleaning the lower surface of the substrate 10, a back metal layer 7 is deposited on the lower surface of the substrate 10 as the collector lead-out terminal of the device.

[0106] In some embodiments, multiple trenches 12 are arranged at equal intervals along a first direction within the effective area of ​​the chip. The number of trenches 12 is designed according to the chip area and performance requirements. Increasing the number of trenches 12 can provide more sidewall area within the same chip planar area, thereby increasing the total area of ​​the base region 2 and the emitter region 3. More area of ​​the base region 2 and the emitter region 3 means stronger conductivity modulation effect and higher photogenerated carrier collection efficiency, which is beneficial for improving CTR parameters and reducing on-state voltage drop.

[0107] In some embodiments, the trench 12 may extend through the entire effective area of ​​the chip along the second direction (extension direction), or it may extend only a portion of the effective area of ​​the chip. Each trench 12 is arranged parallel to its adjacent trench 12 on both sides along the second direction, forming a regular trench array structure.

[0108] In some embodiments, the spacing C of the trenches 12 (i.e., the dimension between adjacent base regions 2 in the first direction within two adjacent trenches 12) is optimized based on the diffusion length of photogenerated carriers and the width of the depletion layer. When the spacing C is in the range of 30 μm to 120 μm, the photogenerated carriers generated between adjacent trenches 12 can effectively enter the depletion region of the base region 2 and be collected by the reverse bias electric field to form an effective photocurrent.

[0109] This application also provides an optocoupler device, including a light-emitting device and a receiving device. The light-emitting device is used to emit light signals, and the receiving device is used to receive the light signals emitted by the light-emitting device and convert them into electrical signals, thereby achieving electrical isolation between the input and output terminals.

[0110] In some embodiments, the receiving device employs a semiconductor device (trench-type side base region phototransistor) as described in any of the above embodiments. When the light signal emitted by the light-emitting device illuminates the phototransistor, the light enters the trench 12 through the gap between the metal layers 5, illuminating the base region 2 and the emitting region 3 on the sidewall of the trench 12. The phototransistor converts the light signal into an electrical signal, realizing signal transmission and electrical isolation between the input and output.

[0111] In this embodiment, the phototransistor possesses advantages such as high CTR, wide response wavelength, and low on-state voltage drop. This optocoupler offers the following advantages: good signal transmission stability due to its high CTR and low signal attenuation, enabling reliable signal identification by subsequent circuits; good wavelength compatibility, adaptable to different types of light-emitting devices (such as LEDs of different wavelengths); and low on-state voltage drop and low power consumption, which is beneficial for overall system energy efficiency optimization. This optocoupler can be applied to scenarios such as feedback isolation in power management, signal isolation in industrial control, and photoelectric conversion in communication systems. The semiconductor device of this embodiment can also be applied to fields such as photoelectric switches and counters in industrial automation, biological detection in medical devices, light sensing in smart homes, infrared detection in security monitoring, and environmental sensing systems in new energy vehicles.

[0112] Please note that the above embodiments are for illustrative purposes only and are not intended to limit the scope of this disclosure.

[0113] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. The same or similar parts between the various embodiments can be referred to each other.

[0114] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0115] The embodiments described above are merely illustrative of several implementations of the present invention, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and these all fall within the protection scope of the present invention. Therefore, the protection scope of this invention patent should be determined by the appended claims.

Claims

1. A semiconductor optoelectronic device, characterized in that, include: Substrate; An epitaxial layer is disposed on the upper surface of the substrate; The epitaxial layer has trenches spaced apart along a first direction and extending along a second direction; wherein the first direction and the second direction intersect. The base region is formed within the epitaxial layer of the trench sidewall; The emission region is formed within the epitaxial layer of the trench sidewall and is located within the base region; A passivation layer covers the sidewalls and bottom of the trench; and A metal layer is disposed on the side of the epitaxial layer opposite to the substrate and is connected to the emitter region.

2. The semiconductor optoelectronic device according to claim 1, characterized in that, The junction depth of the base region is less than 10 μm.

3. The semiconductor optoelectronic device according to claim 1, characterized in that, The trench has a first dimension along the first direction and a second dimension along the thickness direction of the substrate, wherein the ratio of the first dimension to the second dimension is greater than 0.

08.

4. The semiconductor optoelectronic device according to claim 3, characterized in that, The second dimension is greater than 21 μm.

5. The semiconductor optoelectronic device according to claim 1, characterized in that, The dimension along the first direction between two adjacent trenches and between two adjacent base regions is greater than 30 μm and less than 120 μm.

6. The semiconductor optoelectronic device according to claim 1, characterized in that, The dimension between two adjacent metal layers along the first direction is greater than 30 μm.

7. The semiconductor optoelectronic device according to claim 1, characterized in that, The base region is also formed within the epitaxial layer at the bottom of the trench.

8. The semiconductor optoelectronic device according to claim 1, characterized in that, The passivation layer also covers the upper surface of the epitaxial layer; the passivation layer located on the upper surface of the epitaxial layer has an opening that exposes the emission region.

9. The semiconductor optoelectronic device according to claim 8, characterized in that, The metal layer fills the opening and is in contact with the emission region.

10. The semiconductor optoelectronic device according to claim 1, characterized in that, Also includes: A back metal layer is disposed on the lower surface of the substrate.

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