A method of manufacturing an image sensor

Abstract

The application discloses a preparation method of an image sensor, and aims to solve the problem of excessive wafer bending in the existing image sensor process, and to overcome the defects of poor process compatibility, high production cost and sacrificed device performance in the existing scheme. In the application, a high-temperature silicon oxide protective layer is deposited on the front surface and / or back surface of the wafer before the pad silicon nitride layer removal step; when the pad silicon nitride layer on the front surface of the wafer is etched and removed, the high-temperature silicon oxide protective layer can block the etching liquid from contacting the pad silicon nitride layer on the back surface of the wafer, so that the pad silicon nitride layer on the back surface of the wafer remains complete. The inherent tensile stress of the pad silicon nitride layer balances the stress of the wafer, greatly reduces the wafer bending, and at the same time, reduces the damage of the plasma to the silicon substrate and reduces the risk of metal ion pollution. The application is completely compatible with the existing process, does not need to add a photoetch process, and can significantly improve the product yield and device reliability.

Description

Technical Field

[0001] This invention relates to the field of image sensors, and more particularly to a method for manufacturing an image sensor. Background Technology

[0002] As image sensors continue to evolve towards higher resolution and smaller pixel sizes, the integration density of pixel units and peripheral circuits is constantly increasing. Correspondingly, the number of layers in the back-end metal interconnect structure is also showing a significant increasing trend. To meet performance requirements such as storage, charge regulation, and signal stabilization, novel structures such as MIM capacitors (MIM CAP) and trench capacitors (Trench CAP) have been gradually introduced into the manufacturing process, and are stacked and integrated between multiple metal layers. However, these structures typically involve the deposition and etching of multiple layers of metal and dielectric materials, and their material properties, film thickness distribution, and internal stress characteristics vary significantly, which can easily introduce large residual stress accumulation at the wafer scale.

[0003] Against this backdrop, with increasing process complexity, the degree of bending (i.e., wafer BOW value) of image sensor wafers during manufacturing is gradually increasing. An excessively high wafer BOW value not only affects the stability of wafer transport and clamping in the equipment but also adversely impacts subsequent critical process steps. For example, in photolithography, excessive wafer bending reduces focusing accuracy and exposure consistency; in wafer bonding, a high BOW value can easily lead to poor bonding at the bonding interface; and in chemical mechanical polishing (CMP) processes, it may cause uneven polishing or localized over-polishing, thus affecting device yield and performance consistency.

[0004] Therefore, effectively reducing or suppressing the wafer BOW value under the existing high-integration image sensor process architecture has become one of the important technical problems restricting the manufacturing of advanced image sensors. Based on this, this patent proposes a new technical solution to improve wafer stress distribution, thereby achieving an effective reduction in the wafer BOW value. Summary of the Invention

[0005] To address the problems existing in the prior art, the present invention provides a method for fabricating an image sensor, the method comprising the following steps: forming a pad oxide layer and a pad silicon nitride layer on a wafer, and performing shallow trench isolation etching and substrate liner oxide deposition; depositing a high-temperature silicon oxide protective layer on the front and / or back of the wafer; performing trench filling and trench isolation planarization polishing steps, and performing a pad silicon nitride removal step after planarization; the high-temperature silicon oxide protective layer protects the pad silicon nitride on the back of the wafer from wet etching during the pad silicon nitride removal process, thereby optimizing wafer stress distribution and reducing wafer bending.

[0006] Furthermore, the high-temperature silicon oxide protective layer is formed by furnace tube oxidation.

[0007] Furthermore, the preferred thickness of the high-temperature silicon oxide protective layer is 100-1000 angstroms.

[0008] Furthermore, the high-temperature silicon oxide protective layer is deposited simultaneously on both the front and back sides of the wafer.

[0009] Furthermore, the high-temperature silicon oxide protective layer is deposited only on the back side of the wafer.

[0010] Furthermore, the trench filling is a high-density plasma filling step to form a trench capacitor or isolation structure.

[0011] Furthermore, the high-temperature silicon oxide protective layer is deposited first to reduce plasma damage to the silicon substrate caused by subsequent high-density plasma deposition and to reduce the risk of metal ion contamination.

[0012] Furthermore, the high-temperature silicon oxide protective layer is deposited after the high-density plasma trench filling step is completed.

[0013] Furthermore, the removal of silicon nitride pads is carried out using wet etching, and during the removal process, the silicon nitride pads on the back side of the wafer are protected from direct exposure to the etching solution of the wet etching process because they are covered by a high-temperature silicon oxide protective layer. The etching solution is hot phosphoric acid.

[0014] Furthermore, after removing the silicon nitride from the pads, subsequent process steps such as gate oxidation, polysilicon deposition, spacing structure formation, contact hole etching, and metal interconnection are carried out.

[0015] Furthermore, after the pad silicon nitride removal step is completed, a continuous pad silicon nitride layer is still retained on the back side of the wafer, and the pad silicon nitride layer is isolated and protected by a high-temperature silicon oxide protective layer covering its surface.

[0016] Compared with existing technologies, this invention has significant technical advantages and beneficial effects. By introducing a reasonable dielectric layer deposition sequence and protection mechanism on the key structures on the back side of the wafer, this invention achieves comprehensive technical effects in multiple aspects without significantly increasing process complexity. On the one hand, by depositing a high-temperature silicon oxide protective layer on the silicon nitride structure corresponding to the back pads of the wafer, the silicon nitride structure is continuously retained in the front-illuminated process flow. Utilizing its inherent tensile stress characteristics, it effectively improves the overall stress distribution of the wafer, thereby significantly reducing wafer bending. On the other hand, the high-temperature silicon oxide layer also exists as a barrier layer, preventing the exposed silicon nitride structure from adversely affecting the subsequent gate oxide layer deposition process, which is beneficial to improving the formation quality and process stability of the gate dielectric layer. In addition, pre-forming the high-temperature silicon oxide layer before high-density plasma deposition can also effectively protect the silicon substrate, reduce the risk of device damage caused by direct plasma action, and reduce the possibility of metal ion contamination. Through the synergistic effect of the above technical means, this invention has achieved significant beneficial effects in reducing wafer bending, improving process compatibility, and improving device reliability. Attached Figure Description

[0017] Figures 1-5 This is a schematic diagram of the process steps in Embodiment 1 of the present invention; Figures 6-10 This is a schematic diagram of the process steps in Embodiment 2 of the present invention. Detailed Implementation

[0018] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below in conjunction with the content of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0019] It should be noted that the terms "comprising" and "having," and any variations thereof, in the specification and claims of this invention are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or apparatus that includes a series of steps is not necessarily limited to those steps explicitly listed, but may include other steps not explicitly listed or inherent to such process, method, product, or apparatus. Furthermore, the terms "first," "second," etc., are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence; they are interchangeable where appropriate so that embodiments of the invention can be implemented in orders other than those described herein.

[0020] This invention relates to the field of semiconductor integrated circuit manufacturing technology, and in particular to a method for fabricating a complementary metal-oxide-semiconductor (CMOS) image sensor. As CMOS image sensor technology rapidly advances towards higher pixel counts, smaller sizes, and higher integration, pixel unit sizes continue to shrink. To meet the demands for device performance and integration, the number of back-end metal interconnect layers is constantly increasing, and novel integration processes such as trench capacitors and metal-insulator-metal capacitors are widely introduced. This results in the continuous accumulation of thin-film stress on the wafer during the fabrication process, leading to a continuous increase in wafer bending.

[0021] Wafer curvature is a core parameter characterizing the degree of wafer bending, referring to the height difference between the wafer's center and edge. When the curvature exceeds the allowable range of the process, it can cause a series of process problems: In photolithography, excessive wafer curvature can lead to deviation of the exposure focal plane, resulting in problems such as inaccurate focusing, pattern distortion, and excessive linewidth deviation, severely affecting the imaging accuracy of pixel units; in chemical mechanical planarization (CMP) processes, wafer curvature can cause uneven distribution of polishing pressure, resulting in insufficient or over-polishing, reducing the uniformity of wafer surface planarization; in wafer bonding processes, excessive curvature can cause gaps and misalignments at the bonding interface, leading to bonding failure and even wafer breakage. Furthermore, wafer curvature can also cause problems such as wafer clipping and dropping during machine transport, significantly reducing production efficiency and product yield.

[0022] Existing technologies for addressing wafer bending issues primarily include adjusting thin film deposition process parameters to optimize thin film stress, depositing a stress compensation layer on the back side of the wafer, and optimizing device structure design to reduce stress superposition. However, all of these solutions have significant drawbacks: adjusting thin film stress has a limited range of adjustment, and excessive adjustment can lead to a decrease in the density, uniformity, and reliability of the thin film itself, affecting the core performance of the device; depositing a stress compensation layer on the back side requires additional deposition, photolithography, and etching processes, significantly increasing process complexity and production costs, and the additionally deposited thin film is prone to introducing particulate contamination and metal ion contamination, reducing device yield; optimizing the device structure sacrifices the pixel integration and photosensitivity of the image sensor, failing to meet the development needs of high-pixel products.

[0023] To address the aforementioned shortcomings of existing technologies, the core inventive concept of this invention lies in depositing a high-temperature silicon oxide protective layer on the back side (or both sides) of the wafer before the removal step of the silicon nitride layer on the pads. Utilizing the high selectivity of the high-temperature silicon oxide material for the silicon nitride etchant, a complete protection layer for the silicon nitride layer on the back side of the wafer is formed during the wet etching process to remove the silicon nitride layer on the front side of the wafer. This prevents the back side silicon nitride layer from being simultaneously etched away, thus preserving a complete silicon nitride layer on the back side of the wafer. By leveraging the inherent tensile stress of the silicon nitride film on the pads, the compressive stress introduced by the front-side process film during the manufacturing process is offset, optimizing the overall stress distribution of the wafer and reducing wafer curvature at its source. Furthermore, the process of this invention is fully compatible with existing complementary metal-oxide-semiconductor (CMOS) image sensor processes, requiring no modification to existing production line equipment or additional photolithography and etching steps. While achieving wafer curvature control, it does not increase process complexity or production costs. It also simultaneously achieves additional technical effects such as plasma damage protection, metal ion contamination blocking, and gate oxide quality optimization, possessing extremely high industrial application value.

[0024] To facilitate a precise understanding of the technical solutions of this invention by those skilled in the art, the core terms involved in this invention are defined as follows: Wafer: refers to silicon substrate wafers used in semiconductor device manufacturing, including but not limited to 8-inch and 12-inch single-crystal silicon wafers, with crystal orientations that can be... <100> , <110> or <111> The doping type includes P-type or N-type, and the resistivity range can be adjusted from 0.1 to 100 Ω·cm according to device requirements.

[0025] Pad oxide layer: refers to the silicon dioxide buffer layer deposited between the silicon substrate and the silicon nitride layer of the pad. Its main function is to alleviate the stress mismatch between the silicon nitride layer and the silicon substrate, and at the same time, it acts as an etching stop layer during the etching process.

[0026] Silicon nitride pad layer: refers to a silicon nitride thin film prepared by chemical vapor deposition, which serves as a hard mask layer for shallow trench isolation etching, and also has the functions of stress regulation and substrate protection. The silicon nitride pad layer described in this invention is a silicon nitride thin film with tensile stress, and the film stress range is 1×10⁻⁶. 9 -1.5×10 9 dyn / cm².

[0027] Shallow trench isolation: refers to a trench-type isolation structure formed in a wafer substrate through etching, filling, and planarization processes. It is used to achieve electrical isolation between devices and is the core isolation structure of complementary metal-oxide-semiconductor image sensors.

[0028] Pad oxide layer: refers to the silicon dioxide film deposited after shallow trench isolation etching is completed. It is used to repair the lattice damage to the silicon substrate caused during the etching process, reduce the interface states between silicon and the filling medium, and improve the isolation performance of the device.

[0029] High-temperature silicon dioxide: refers to silicon dioxide thin films prepared by high-temperature furnace tube low-pressure chemical vapor deposition process. It has the characteristics of high density, low pinhole density, good chemical stability and high etching selectivity, and is the core protective layer material in this invention.

[0030] High-density plasma filling: refers to the use of high-density plasma chemical vapor deposition (PDCVD) to achieve void-free filling of trenches. It has the characteristic of simultaneous deposition and sputtering and is the mainstream process for filling shallow trench isolation trenches.

[0031] Chemical mechanical planarization (CMP) refers to the process of achieving global planarization of the wafer surface through the synergistic effect of chemical etching and mechanical polishing. It is a core planarization technology in semiconductor manufacturing.

[0032] Wafer curvature: refers to the height difference between the center and the edge of a wafer when no external force is applied. It is a core parameter characterizing the stress distribution and curvature of a wafer. The smaller the absolute value of the curvature, the better the wafer flatness.

[0033] The core principle of this invention for wafer bending control lies in the stress balance regulation of both sides of the wafer, specifically as follows: In the active region fabrication process of a conventional complementary metal-oxide-semiconductor (CMOS) image sensor, pad oxide layers and pad silicon nitride layers are first deposited simultaneously on both sides of the wafer. This is followed by shallow trench isolation etching, pad oxide layer deposition, high-density plasma trench filling, and shallow trench isolation chemical-mechanical planarization. Then, a hot phosphoric acid wet etching process is used to remove the pad silicon nitride layer on the front side of the wafer, preparing it for subsequent gate processes. During this wet etching process, because the pad silicon nitride layer on the back side of the wafer has no protection, it is removed simultaneously by hot phosphoric acid etching along with the front pad silicon nitride layer, resulting in the complete disappearance of the pad silicon nitride layer on the back side of the wafer.

[0034] The silicon nitride pad layer is a silicon nitride thin film with strong tensile stress. When there are complete silicon nitride pad layers on both sides of the wafer, the tensile stress on both sides is balanced, and the wafer will not bend significantly. However, when the silicon nitride pad layer on the back side is completely removed, the stress balance on both sides of the wafer is completely broken. With the implementation of subsequent processes such as gate dielectric layer, polysilicon layer, sidewall dielectric layer, multilayer metal interconnect layer, interlayer dielectric layer, metal-insulator-metal capacitor structure, a large number of films with compressive stress are continuously deposited on the front side of the wafer. The stress is constantly superimposed, eventually leading to severe forward bending of the wafer, with the bending value greatly exceeding the allowable range of the process.

[0035] This invention achieves complete protection of the back-side silicon nitride layer by depositing a high-temperature silicon oxide protective layer on the back side of the wafer before the wet etching step of the silicon nitride pads. This is achieved by utilizing the ultra-high etching selectivity between the high-temperature silicon oxide and silicon nitride in a hot phosphoric acid etching solution. In a hot phosphoric acid etching solution at 140-200°C and a mass fraction of 70-90%, the etching rate of silicon nitride can reach 100-200 Å / min, while the etching rate of high-temperature silicon dioxide is only 0.1-1 Å / min, resulting in an etching selectivity ratio of over 50:1. Therefore, during the wet etching process to remove the front-side silicon nitride pad layer, the high-temperature silicon oxide protective layer on the surface of the back-side silicon nitride pad layer is almost completely unetched, effectively preventing contact between the hot phosphoric acid and the back-side silicon nitride pad layer, thus preserving a complete and continuous silicon nitride pad layer on the back side of the wafer.

[0036] The silicon nitride (SiN) layer on the back side of the wafer retains inherent tensile stress that continuously acts on the wafer, effectively offsetting the compressive stress caused by various thin film depositions in subsequent front-side processes. This keeps the stress on both sides of the wafer in balance, fundamentally suppressing wafer bending and significantly reducing wafer curvature. Simultaneously, the high-temperature silicon oxide protective layer also acts as a barrier layer, preventing the back-side SiN layer from being exposed in subsequent high-temperature processes. This prevents impurities in the SiN layer from contaminating the cavity and affecting the gate oxide layer quality. Furthermore, it blocks high-energy plasma bombardment of the silicon substrate during high-density plasma deposition, reducing plasma damage and metal ion contamination, thus comprehensively improving device performance and yield. Example 1

[0037] Please see Figures 1-5 This embodiment provides a method for fabricating an image sensor. The method involves depositing a high-temperature silicon oxide protective layer before filling high-density plasma trenches, simultaneously achieving wafer bending control, plasma damage protection, and metal ion contamination blocking. Specifically, the method includes the following steps: Step 1: Wafer Substrate Preparation and Conventional Active Region Fabrication Process. This embodiment uses a 12-inch P-type single-crystal silicon wafer with the following crystal orientation: <100> With a resistivity of 10-20 Ω·cm, the wafer is first subjected to standard semiconductor silicon wet cleaning to remove particulate contamination, organic contamination and metal contamination on the surface of the wafer 100. After drying, it enters the subsequent process.

[0038] After cleaning, the following processes are performed in sequence: pad oxide deposition, pad silicon nitride deposition, shallow trench isolation etching, and pad oxide deposition: (1) Pad oxide deposition: A dry oxygen thermal oxidation process is used to form a silicon dioxide buffer layer on the surface of wafer 100. The thermal oxidation temperature is 600-1000℃. The thickness of the prepared pad oxide layer 101 is 100-200 angstroms. A uniform pad oxide layer 101 is formed simultaneously on the front and back sides of wafer 100. (2) Pad silicon nitride deposition: A low-pressure chemical vapor deposition process is used with dichlorosilane and ammonia as the reaction gas source. The deposition temperature is 500-1000℃. A silicon nitride hard mask layer, namely the pad silicon nitride layer 102, is prepared on the surface of the pad oxide layer. The thickness is 1300-1600 angstroms. A uniform pad silicon nitride layer 102 is formed simultaneously on the front and back sides of the wafer. (3) Shallow trench isolation etching: Photoresist is spin-coated on the front side of the wafer, and exposed and developed by a photolithography machine to form a photoresist mask for shallow trench isolation pattern. Then, an inductively coupled plasma dry etching process is used, with the silicon nitride layer of the pad as a hard mask, to sequentially etch the pad oxide layer and the silicon substrate. The etching depth is 1000-4000 angstroms to form a shallow trench structure. After etching, the photoresist is removed by oxygen plasma removal process, and etching residues and particulate contamination are removed by standard semiconductor silicon wafer wet cleaning. (4) Pad oxide deposition: A pad oxide layer 103 is formed on the inner wall of the shallow trench and the wafer surface by a dry oxygen thermal oxidation process. The thermal oxidation temperature is 600-1000℃, and the thickness of the prepared pad oxide layer is 20-200 angstroms. It is used to repair silicon lattice damage caused by shallow trench isolation etching, reduce interface states, and improve isolation performance.

[0039] Step 2: High-Temperature Silicon Oxide Protective Layer Double-Sided Deposition Process After the deposition of the pad oxide layer 103, a low-pressure chemical vapor deposition furnace tube process is used to perform double-sided deposition of the high-temperature silicon oxide protective layer. The specific process parameters are as follows: dichlorosilane and nitrous oxide are used as the reaction gas source, the flow ratio of dichlorosilane to nitrous oxide is between 1:5 and 1:6, the deposition temperature is 600-1000℃, the reaction pressure is 280-300 mTorr, the deposition time is 15-22 minutes, and the deposition rate is 12-17 Å / min. Finally, a high-temperature silicon oxide protective layer 104 with a uniform thickness of 280-330 Å is formed simultaneously on the front and back sides of the wafer.

[0040] In this step, the furnace tube low-pressure chemical vapor deposition process enables simultaneous deposition on both sides of the wafer, eliminating the need for additional single-sided deposition equipment or mask processes. It is fully compatible with existing production lines and requires no equipment modifications. A thickness of 300 angstroms is the preferred option, as this thickness results in a high-temperature silicon oxide protective layer with high density and no pinhole defects, providing complete protection for the silicon nitride layer on the back pads without introducing additional stress or increasing the burden on subsequent chemical mechanical planarization (CMP) processes. If the high-temperature silicon oxide thickness is less than 100 angstroms, pinhole defects are likely to occur, failing to achieve a complete protective barrier effect. If the thickness exceeds 1000 angstroms, additional film stress will be introduced, increasing the polishing time of subsequent CMP processes and affecting planarization uniformity.

[0041] Step S3: High-density plasma trench filling, shallow trench isolation chemical mechanical planarization, and pad silicon nitride layer removal process.

[0042] Step S31, High-density plasma trench filling process: After the high-temperature silicon oxide protective layer is deposited, a high-density plasma chemical vapor deposition process is used to fill the shallow trench isolation trench without gaps. The specific process parameters are as follows: silane and oxygen are used as the reaction gas source, argon is used as the sputtering gas source, the deposition temperature is 300-380℃, the reaction pressure is 4-7mTorr, the high-frequency RF power is 1800-2100W, and the low-frequency RF power is 800-1200W. Through a deposition-sputtering-deposition cycle process, silicon dioxide 106 is filled in the shallow trench, and at the same time, a covering silicon dioxide film is formed on the surface of the high-temperature silicon oxide protective layer on the front side of the wafer, realizing the gapless filling of the shallow trench isolation trench and forming a complete shallow trench isolation structure.

[0043] In this step, the high-temperature silicon oxide protective layer on the front side of the wafer can act as a barrier layer, effectively preventing high-energy plasma in the high-density plasma process from directly bombarding the silicon substrate, reducing silicon lattice damage caused by plasma, reducing dark current in the pixel units of the image sensor, and improving photosensitivity. At the same time, the high-temperature silicon oxide protective layer can prevent metal ions such as iron, copper, and sodium in the high-density plasma cavity from diffusing into the silicon substrate, reducing metal ion contamination and significantly improving the reliability and yield of the device.

[0044] Step S32, Shallow Trench Isolation Chemical Mechanical Planarization Process: After completing the high-density plasma trench filling, a chemical mechanical planarization process is performed using a silicon dioxide polishing slurry. The silicon nitride layer on the pads on the front side of the wafer is used as the polishing stop layer. The specific process parameters are as follows: polishing pressure is 1.8-2.1 psi, polishing disk speed is 50-70 rpm, polishing head speed is 40-55 rpm, and polishing time is 1-3 minutes. Polishing removes excess high-density plasma-filled silicon dioxide and high-temperature silicon oxide protective layers outside the trenches on the front side of the wafer until the silicon nitride layer on the pads on the front side of the wafer is exposed, thus achieving global planarization of the wafer surface.

[0045] In this step, both the high-temperature silicon oxide protective layer on the front side of the wafer and the high-density plasma-filled silicon dioxide are silicon dioxide materials with basically the same polishing rate. They can be removed simultaneously during the chemical mechanical planarization process without the need for additional etching processes to remove the high-temperature silicon oxide layer on the front side. This process is fully compatible with existing chemical mechanical planarization processes and will not increase the complexity of the process.

[0046] Step S33, wet removal process of silicon nitride layer on pads: After completing the shallow trench isolation chemical mechanical planarization, the silicon nitride layer on the pads on the front side of the wafer is removed by hot phosphoric acid wet etching process. The specific process parameters are as follows: a hot phosphoric acid solution with a mass fraction of 80-85% is used, the etching temperature is 150-170℃, and the etching time is 10-12 minutes to ensure that the silicon nitride layer on the pads on the front side of the wafer is completely etched and removed. Then, the wafer is overflow-cleaned with deionized water, dried, and then proceeded to the subsequent process.

[0047] This step is crucial for achieving the core effect of this invention. During the wet etching process, the surface of the silicon nitride layer on the back of the wafer is covered with a complete high-temperature silicon oxide protective layer. The etching rate of high-temperature silicon oxide in hot phosphoric acid is extremely low. After etching, the thickness loss of the high-temperature silicon oxide protective layer is only less than 10 angstroms, maintaining a complete and continuous thin film structure. This completely blocks the contact between hot phosphoric acid and the back pad silicon nitride layer. Therefore, the back pad silicon nitride layer on the back of the wafer will not be etched and will remain intact on the back of the wafer. Its inherent tensile stress can continue to play a stress balancing role.

[0048] Step S4: After the removal of the silicon nitride layer from the pads in the subsequent conventional device fabrication process, the subsequent process steps are completed sequentially according to the conventional complementary metal-oxide-semiconductor image sensor process. Specifically, these include: gate oxide deposition, polysilicon layer deposition and etching, sidewall structure formation, source / drain ion implantation and annealing, contact hole etching and tungsten filling, multilayer metal interconnect layer fabrication, passivation layer deposition, pad windowing, and other processes, ultimately completing the fabrication of the image sensor chip.

[0049] In this step, the silicon nitride layer on the back of the wafer is always covered and isolated by a high-temperature silicon oxide protective layer, and will not be exposed during the high-temperature process of gate oxide deposition. This avoids the problem of impurities in the silicon nitride layer on the pads contaminating the process cavity and affecting the quality of the gate oxide layer, effectively reducing the failure risk of gate oxide breakdown and threshold voltage drift, and improving the long-term reliability of the device.

[0050] The technical solution of this embodiment can significantly reduce the final curvature of the wafer, perfectly solving the problem of excessive wafer curvature; at the same time, the dark current of the pixel unit and the defect rate of metal contamination are significantly reduced, the product yield is significantly improved, and the synergistic optimization of stress control and device performance improvement is achieved. Example 2

[0051] Please see Figures 6-10 This embodiment provides a method for fabricating an image sensor. The method involves depositing a high-temperature silicon oxide protective layer after high-density plasma trench filling and before shallow trench isolation chemical mechanical planarization. This method offers greater process flexibility and is easier to implement in existing production lines. The core wafer bending control effect is consistent with that of Embodiment 1. The specific steps include: Step S1: Wafer Substrate Preparation and Conventional Active Region Process. This step is completely consistent with Step S1 of Example 1. The same 12-inch P-type single-crystal silicon wafer is used. After completing the standard semiconductor silicon wafer wet cleaning, the following processes are performed in sequence: pad oxide layer 101 deposition, pad silicon nitride layer 102 deposition, shallow trench isolation etching, and pad oxide layer 103 deposition. The process parameters are exactly the same as in Example 1, and will not be repeated here. The only variable between this example and Example 1 is the timing of the deposition of the high-temperature silicon oxide protective layer.

[0052] Step S2: High-Density Plasma Trench Filling Process. After the pad oxide layer deposition is completed, the high-density plasma trench filling process is directly performed. The process parameters are completely consistent with the high-density plasma process in Step S3 of Example 1. High-density plasma chemical vapor deposition is used to achieve void-free filling of shallow trench isolation trenches, forming a shallow trench isolation structure. In this step, there is no need to pre-deposit a high-temperature silicon oxide protective layer 104, and there is no need to adjust the process sequence of pad oxide layer deposition and high-density plasma filling in the existing active region process. It has stronger process compatibility with existing production lines and does not require significant adjustments to the existing process flow, greatly reducing the verification cycle and modification cost of process introduction.

[0053] Step S3: High-Temperature Silicon Oxide Protective Layer Double-Sided Deposition Process. After the high-density plasma trench filling is completed, a low-pressure chemical vapor deposition furnace tube process is used to deposit a high-temperature silicon oxide protective layer on both sides. The process parameters are completely consistent with Step S2 of Example 1, using silicon dichlorodihydrogen phosphate and nitrous oxide as the reaction gas source, a deposition temperature of 800-900℃, and a reaction pressure of 280-320 mTorr. Finally, a high-temperature silicon oxide protective layer with a thickness of 280-320 angstroms is simultaneously formed on both the front and back sides of the wafer. At this time, the high-density plasma-filled silicon dioxide 106 surface and the surface of the silicon nitride layer on the pads on the front side of the wafer are both covered with a high-temperature silicon oxide protective layer, and the surface of the silicon nitride layer on the pads on the back side of the wafer is also covered with a complete high-temperature silicon oxide protective layer.

[0054] Step S4: Shallow Trench Isolation Chemical Mechanical Planarization and Pad Silicon Nitride Layer Removal Process. Step S41 Shallow Trench Isolation Chemical Mechanical Planarization Process: After the high-temperature silicon oxide protective layer is deposited, a chemical mechanical planarization process is performed. The process parameters are completely consistent with the chemical mechanical planarization process in Step S3 of Example 1. Using the pad silicon nitride layer as the polishing stop layer, the excess high-density plasma-filled silicon dioxide and high-temperature silicon oxide protective layer outside the trench on the front side of the wafer are polished away until the pad silicon nitride layer on the front side of the wafer is exposed, achieving global planarization of the wafer surface. Similarly, the high-temperature silicon oxide protective layer on the front side is removed simultaneously during the chemical mechanical planarization process, without the need for additional process steps.

[0055] Step S42: Wet Removal Process of Silicon Nitride Pads: After completing the shallow trench isolation chemical mechanical planarization, a hot phosphoric acid wet etching process, identical to that in Example 1, is used to remove the silicon nitride layer on the front side of the wafer. The etching temperature is 150-180°C, and the etching time is 10-13 minutes, ensuring complete removal of the silicon nitride layer on the front side of the wafer. During the etching process, the silicon nitride layer on the back side of the wafer is completely protected by a high-temperature silicon oxide protective layer and will not come into contact with the hot phosphoric acid etching solution. Therefore, it remains intact on the back side of the wafer, continuously playing a stress balancing role and achieving effective control of wafer bending.

[0056] Step S5: Subsequent Conventional Device Fabrication Process. This step is completely consistent with Step S4 in Example 1, sequentially completing conventional process steps such as gate oxide deposition, polysilicon layer deposition, sidewall structure formation, ion implantation, and metal interconnection, ultimately completing the fabrication of the image sensor chip. Throughout the entire subsequent process, the silicon nitride layer on the back pads of the wafer is always covered by a high-temperature silicon oxide protective layer, which will not have any adverse effects on subsequent processes, and can effectively optimize wafer stress distribution and suppress wafer bending.

[0057] The technical solution of this embodiment can reduce the final wafer curvature to far below the threshold allowed by the process, perfectly solving the problem of excessive wafer curvature and significantly improving product yield. The advantage of this embodiment lies in its greater process flexibility; it does not require adjustments to the process sequence of existing active region processes, making it easier to implement in existing mass production lines. It is suitable for production lines where high-density plasma processes have been maturely optimized and plasma damage has been effectively controlled.

[0058] The scope of protection of this invention is not limited to the two embodiments described above. Based on the core inventive concept of this invention, there are many other optional implementation methods, all of which fall within the scope of protection of this invention: Single-sided deposition of high-temperature silicon oxide protective layer: The above embodiments adopt a double-sided deposition of high-temperature silicon oxide scheme. In optional embodiments, a single-sided deposition process can be used to deposit a high-temperature silicon oxide protective layer only on the back side of the wafer. For example, a plasma-enhanced chemical vapor deposition single-sided deposition process can be used, or a protective mask can be used to block the front side of the wafer during furnace tube deposition, forming a high-temperature silicon oxide protective layer only on the back side. This can also achieve the protection effect of the silicon nitride layer on the back pads.

[0059] High-temperature silicon oxide protective layer of different thicknesses: The above embodiment adopts a preferred thickness of 300 angstroms. In optional embodiments, the thickness of the high-temperature silicon oxide protective layer can be adjusted in the range of 100-1000 angstroms according to process requirements, such as 100 angstroms, 500 angstroms, 800 angstroms, 1000 angstroms, etc., all of which can achieve effective protection.

[0060] Dry etching to remove silicon nitride layer from pads: The above embodiment uses hot phosphoric acid wet etching to remove silicon nitride layer from pads. In optional embodiments, dry etching process can be used to remove silicon nitride layer from front pads, for example, using carbon tetrafluoride / oxygen-based dry etching gas. This etching system can achieve an etching selectivity ratio of silicon nitride to silicon dioxide of more than 50:1. The high-temperature silicon oxide protective layer can also effectively protect the silicon nitride layer of back pads.

[0061] Trench capacitor structure fabrication: In the above embodiments, high-density plasma filling is used to form a shallow trench isolation structure. In optional embodiments, the high-density plasma filling process can be used to form a trench capacitor structure, which can also be adapted to the high-temperature silicon oxide protective layer process of the present invention to achieve wafer bending control.

[0062] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

[0063] It should be understood that the term "and / or" in this document is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, or B existing alone. Additionally, the character " / " in this document indicates that the preceding and following related objects are in an "or" relationship. "Multiple" in the embodiments of this application refers to two or more. The descriptions such as "first," "second," etc., appearing in the embodiments of this application are only for illustration and to distinguish the described objects; they have no order and do not represent a special limitation on the number of devices in the embodiments of this application, nor do they constitute any limitation on the embodiments of this application.

[0064] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A method for fabricating an image sensor, characterized in that, Includes the following steps: A pad oxide layer and a pad silicon nitride layer are formed on the wafer, and shallow trench isolation etching and substrate liner oxide deposition are performed. A high-temperature silicon oxide protective layer is deposited on the front and / or back of the wafer; Perform trench filling and trench isolation planarization polishing steps, and then perform pad silicon nitride removal steps after planarization; The high-temperature silicon oxide protective layer protects the silicon nitride on the back of the wafer during the removal of silicon nitride from the pads, thereby optimizing wafer stress distribution and reducing wafer bending.

2. The method according to claim 1, characterized in that, The high-temperature silicon oxide protective layer is formed by furnace tube oxidation.

3. The method according to claim 1, characterized in that, The thickness of the high-temperature silicon oxide protective layer is 100-1000 angstroms.

4. The method according to claim 1, characterized in that, The high-temperature silicon oxide protective layer is deposited simultaneously on both the front and back sides of the wafer.

5. The method according to claim 1, characterized in that, The high-temperature silicon oxide protective layer is deposited only on the back side of the wafer.

6. The method according to claim 1, characterized in that, The trench filling is a high-density plasma (HDP) filling step to form a trench capacitor or isolation structure.

7. The method according to claim 1, characterized in that, The high-temperature silicon oxide protective layer is deposited first to reduce damage to the silicon substrate caused by subsequent high-density plasma deposition and to reduce the risk of metal ion contamination.

8. The method according to claim 1, characterized in that, The high-temperature silicon oxide protective layer is deposited after the high-density plasma trench filling step is completed.

9. The method according to claim 1, characterized in that, The silicon nitride pads are removed by wet etching, and during the removal process, the silicon nitride pads on the back side of the wafer are protected from direct exposure to the etching solution by the wet etching process because they are covered by a high-temperature silicon oxide protective layer.

10. The method according to claim 1, characterized in that, After removing the silicon nitride from the pads, subsequent process steps such as gate oxidation, polysilicon deposition, spacing structure formation, contact hole etching, and metal interconnection are performed.

11. The method according to claim 1, characterized in that, After the pad silicon nitride removal step is completed, a continuous pad silicon nitride layer remains on the back side of the wafer, and the pad silicon nitride layer is isolated and protected by a high-temperature silicon oxide protective layer covering its surface.

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