Process method for improving the dark current of a cis

Abstract

The application discloses a process method for improving the dark current of a CIS, which comprises the following steps: providing a semiconductor substrate, forming a gate structure on the semiconductor substrate and completing source-drain injection, wherein the semiconductor substrate comprises a pixel area and a logic area, and the pixel area comprises a pixel unit of the CIS; sequentially depositing an SMT oxide layer and SMT silicon nitride; performing patterned etching on the SMT silicon nitride so that the SMT silicon nitride is reserved only in a channel stress improvement area; performing first annealing to transfer the stress of the SMT silicon nitride to a channel area of the channel stress improvement area, and the first annealing is used for repairing defects of the SMT oxide layer at the same time; removing the SMT silicon nitride; depositing SAB silicon nitride; and forming an SAB layer by stacking the SMT oxide layer and the SAB silicon nitride, wherein the repaired defects of the SMT oxide layer are used for improving the dark current of the CIS. The application can prevent the dark current caused by the SMT process while performing the SMT process, so that the dark current of the CIS is improved.

Description

Technical Field

[0001] This invention relates to the field of semiconductor integrated circuit manufacturing, and in particular to a process method for improving dark current in CMOS image sensors (CIS). Background Technology

[0002] Stress memory technology (SMT) can improve the speed of MOS devices. SMT technology introduces stress in the channel by mechanically stretching or compressing the lattice, thereby changing the electronic band structure and density, and changing the mobility of charge carriers. Tensile stress can increase the drive current of NMOS devices, while compressive stress can increase the drive current of PMOS devices.

[0003] CIS products include pixel areas and logic areas. Applying surface mount technology (SMT) to the logic area can improve the performance of logic devices. However, directly applying existing logic product SMT processes to CIS products results in a significant increase in dark current. Therefore, finding a way to apply SMT processes to CIS products without affecting the device's dark current is crucial for improving the overall performance of CIS products. Summary of the Invention

[0004] The technical problem to be solved by the present invention is to provide a process method for improving the dark current of CIS, which can prevent the dark current caused by the SMT process while performing the SMT process, thereby improving the dark current of CIS.

[0005] To solve the above-mentioned technical problems, the present invention provides a process method for improving the dark current of CIS, comprising the following steps: A semiconductor substrate is provided on which a gate structure is formed and source / drain implantation is completed. The semiconductor substrate includes a pixel region and a logic region, wherein the pixel region includes pixel units of a CIS.

[0006] SMT oxide layer and SMT silicon nitride layer are deposited sequentially.

[0007] The SMT silicon nitride is patterned and etched so that the SMT silicon nitride is retained only in the channel stress improvement region.

[0008] The first annealing transfers the stress of the SMT silicon nitride to the channel region of the channel stress improvement zone, and the first annealing also repairs defects in the SMT oxide layer.

[0009] Remove the SMT silicon nitride.

[0010] Silicon nitride (SAB) is deposited, and an SAB layer is formed by stacking the SMT oxide layer and the SAB silicon nitride layer. The dark current of the CIS is improved by utilizing the defect repair feature of the SMT oxide layer.

[0011] A further improvement is that the logic region includes an NMOS formation region and a PMOS formation region.

[0012] A further improvement is that the SMT silicon nitride is tensile stress silicon nitride, and the channel stress improvement region is the NMOS formation region in the logic region.

[0013] A further improvement is that each pixel unit includes a photodiode and a pixel unit circuit, wherein the pixel unit circuit includes a plurality of transistors; A further improvement is that each transistor in the pixel unit circuit is an NMOS transistor.

[0014] A further improvement is that the gate structure includes a gate dielectric layer and a gate conductive material layer stacked sequentially.

[0015] A further improvement is that sidewalls are formed on the side of the gate structure.

[0016] A further improvement is that the semiconductor substrate is made of silicon.

[0017] A further improvement is that the source-drain injection includes N+ source-drain injection and P+ source-drain injection.

[0018] A further improvement is that the first annealing is performed using the RTA process.

[0019] A further improvement is that the impurities injected into the source / drain are also activated by the first annealing.

[0020] A further improvement is that the patterned etching includes: The etching region of the SMT silicon nitride is defined using photolithography.

[0021] The SMT silicon nitride is first etched to remove all SMT silicon nitride outside the channel stress improvement region.

[0022] A further improvement is that the first etching is either dry etching or wet etching.

[0023] A further improvement is that, after forming the SAB layer, it also includes: Photolithography defines the region where metal silicides are formed.

[0024] A second etching is performed to remove the SAB silicon nitride from the metal silicide formation region.

[0025] Wet etching is performed to remove the SMT oxide layer in the metal silicide formation region.

[0026] A first metal layer is formed and a silicide reaction is carried out to form a metal silicide in the metal silicide formation region.

[0027] A further improvement is that the second etching is a dry etching process.

[0028] In this invention, when introducing SMT technology into the CIS process flow, after the stress transfer annealing (first annealing) of SMT, the SMT silicon nitride and SMT oxide layers are not completely removed. Instead, only the SMT silicon nitride is removed, while the SMT oxide layer is retained and serves as a component of the subsequent SAB layer. Because the SMT oxide layer has undergone the first annealing, its quality is good and defects are eliminated. Therefore, compared with the existing process of removing the SMT oxide layer and then regrowing the SAB oxide layer, this invention can reduce the number of defects, thus reducing the resulting dark current. Therefore, this invention can perform the SMT process while preventing the dark current caused by the SMT process, thereby improving the dark current of CIS. Attached Figure Description

[0029] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments: Figure 1 This is a flowchart of a process method for improving the dark current of CIS according to an embodiment of the present invention; Figures 2-7 This is a schematic diagram of the device structure in each step of the process method for improving the dark current of CIS according to an embodiment of the present invention. Detailed Implementation

[0030] like Figure 1 The diagram shown is a flowchart of a process method for improving the dark current of a CIS according to an embodiment of the present invention; as shown Figures 2 to 7 The diagram shown is a schematic representation of the device structure in each step of the process method for improving the dark current of CIS according to an embodiment of the present invention. The process method for improving the dark current of CIS according to an embodiment of the present invention includes the following steps: Step S101, as follows Figure 2 As shown, a semiconductor substrate 101 is provided, on which a gate structure is formed and source / drain implantation is completed. The semiconductor substrate 101 includes a pixel region 101a and a logic region 101b, and the pixel region 101a includes pixel units of CIS.

[0031] In this embodiment of the invention, the logic region 101b includes an NMOS formation region 101b1 and a PMOS formation region 101b2.

[0032] Depend on Figure 2As shown, in the NMOS formation region 101b1, a P-well 103b is formed in the semiconductor substrate 101; in the PMOS formation region 101b2, an N-well 103a is formed in the semiconductor substrate 101.

[0033] In the pixel region 101a, a well region 104 is formed, which serves as a doped region of the photodiode and is used to collect photogenerated carriers.

[0034] In this embodiment of the invention, each pixel unit includes a photodiode and a pixel unit circuit, and the pixel unit circuit includes a plurality of transistors. Figure 1 In this process, a shallow trench isolation 102 is also formed on the semiconductor substrate 101, through which the active region is isolated.

[0035] In some embodiments, each transistor in the pixel unit circuit is an NMOS transistor.

[0036] In this embodiment of the invention, the gate structure includes a gate dielectric layer 105 and a gate conductive material layer 106 stacked sequentially. In some embodiments, the gate dielectric layer 105 is a gate oxide layer, and the gate conductive material layer 106 is a polysilicon gate. In other embodiments, the gate dielectric layer 105 may be a high dielectric constant material layer, and the gate conductive material layer 106 may be a metal gate.

[0037] Sidewalls 111 are also formed on the side of the gate structure. Figure 2 In this application, the side wall 111 includes multiple side walls. The arrangement of the multiple side walls is the same as that of the existing structure, and will not be described in detail here. It can be set according to actual needs.

[0038] In some embodiments, the semiconductor substrate 101 is made of silicon.

[0039] The source / drain injection includes N+ source / drain injection and P+ source / drain injection. The N+ source / drain regions 110 of the NMOS transistors in the pixel unit circuit and the NMOS transistors in the NMOS formation region 101b1 are formed through N+ source / drain injection; the P+ source / drain regions 108 of the PMOS transistors in the PMOS formation region 101b2 are formed through P+ source / drain injection. Each NMOS transistor also has an N-type lightly doped drain region 109, and each PMOS transistor also has a P-type lightly doped drain region 107. In some embodiments, a P-type doped pocket injection region (not shown) is also formed on the periphery of the channel region of the NMOS transistors in the NMOS formation region 101b1; an N-type doped pocket injection region (not shown) is also formed on the periphery of the channel region of the PMOS transistors in the PMOS formation region 101b2.

[0040] Step S102, as follows Figure 2 As shown, SMT oxide layer 112 and SMT silicon nitride layer 113 are deposited sequentially.

[0041] In this embodiment of the invention, the SMT silicon nitride 113 is tensile stress silicon nitride, and the channel stress improvement region is the NMOS formation region 101b1 in the logic region 101b. In other embodiments, it can also be configured as needed: the SMT silicon nitride 113 is compressive stress silicon nitride, and the channel stress improvement region is the PMOS formation region 101b2 in the logic region 101b.

[0042] Step S103, as follows Figure 3 As shown, the SMT silicon nitride 113 is patterned and etched so that the SMT silicon nitride 113 is retained only in the channel stress improvement region.

[0043] In this embodiment of the invention, the patterned etching includes: The etching region of the SMT silicon nitride 113 was defined using photolithography. Figure 3 As shown, the etched area of ​​the SMT silicon nitride 113 is the area outside the channel stress improvement area.

[0044] The SMT silicon nitride 113 is first etched to remove all SMT silicon nitride 113 outside the channel stress improvement region.

[0045] In this embodiment of the invention, the first etching is a dry etching process. In other embodiments, the first etching may also be a wet etching process.

[0046] Depend on Figure 3 As can be seen, since the SMT silicon nitride 113 in the pixel region 101a is etched away, the SMT oxide layer 112 in the pixel region 101a is easily affected by the first etching and will produce defects. In particular, when the first etching is dry etching, the plasma of dry etching is likely to have an adverse effect on the SMT oxide layer 112 in the pixel region 101a and form defects.

[0047] Step S104, as follows Figure 4 As shown, the first annealing, indicated by arrow 114, transfers the stress of the SMT silicon nitride 113 to the channel region of the channel stress improvement zone. The first annealing also repairs defects in the SMT oxide layer 112.

[0048] In this embodiment of the invention, the first annealing is performed using the RTA process.

[0049] The impurities injected into the source and drain are also activated by the first annealing.

[0050] Step S105, as follows Figure 5 As shown, the SMT silicon nitride 113 is removed.

[0051] In this embodiment of the invention, the process for removing the SMT silicon nitride 113 is wet etching. In other embodiments, the process for removing the SMT silicon nitride 113 can also be dry etching.

[0052] Step S106, as follows Figure 6 As shown, SAB silicon nitride 115 is deposited, and the SAB layer is formed by stacking the SMT oxide layer 112 and the SAB silicon nitride 115. The dark current of CIS is improved by utilizing the defect repair feature of the SMT oxide layer 112.

[0053] like Figure 7 As shown, after forming the SAB layer, the following is also included: Photolithography defines the region where metal silicides are formed. Figure 7 In the NMOS formation region 101b1, the metal silicide formation region includes the top surface region of the N+ source / drain region 110 of each NMOS transistor in the NMOS formation region 101b1 and the top surface region of the gate conductive material layer 106 of the gate structure, and the top surface region of the P+ source / drain region 107 of each PMOS transistor in the PMOS formation region 101b2 and the top surface region of the gate conductive material layer 106 of the gate structure.

[0054] A second etching process is performed to remove the SAB silicon nitride 115 in the metal silicide formation region. It can be seen that the SAB silicon nitride 115 in the pixel region 101a is retained, and the bottom SMT oxide layer 112 is not affected by the second etching. In this embodiment of the invention, the second etching is a dry etching process.

[0055] Wet etching is performed to remove the SMT oxide layer 112 in the metal silicide formation region. Using wet etching to remove the SMT oxide layer 112 does not affect the quality of the SMT oxide layer 112 retained in the pixel region 101a.

[0056] A first metal layer is formed and a silicide reaction is performed to form a metal silicide (not shown) in the metal silicide formation region.

[0057] In this embodiment of the invention, when introducing SMT technology into the CIS process flow, after completing the stress transfer annealing of SMT (i.e., the first annealing), not all SMT silicon nitride 113 and SMT oxide layer 112 are removed. Instead, only SMT silicon nitride 113 is removed, while SMT oxide layer 112 is retained and serves as a component of the subsequent SAB layer. Since SMT oxide layer 112 has undergone the first annealing, its quality is good and defects are eliminated. Therefore, compared with the existing process of regrowing SAB oxide layer after removing SMT oxide layer 112, this embodiment of the invention can reduce the number of defects, thus reducing the resulting dark current. Therefore, this embodiment of the invention can perform SMT technology while preventing dark current caused by SMT technology, thereby improving the dark current of CIS.

[0058] Compared with existing methods, which require the removal of the SMT oxide layer and subsequent re-growth of the SAB oxide layer in the SMT process, experimental verification shows that the dark current of the CIS formed by the embodiments of the present invention can be greatly improved, while the dark current of the CIS formed by existing methods increases by 90%.

[0059] When existing CIS products fully reference logic processes, such as SMT (Surface Mount Technology) in low-power (LP) logic processes, to enhance device performance, the dark current increases significantly, by approximately 90%, as the product size shrinks. After the improvements made in this invention, the dark current is improved to a level comparable to that of CIS products without SMT. In existing processes, the manufacturing process of CIS products without SMT involves rapid thermal annealing (RTA) after SAB oxide deposition to activate source / drain injection impurities. However, in existing methods, with the introduction of SMT, the stress transfer RTA in the SMT process simultaneously activates source / drain injection impurities, and no further RTA is performed after SAB oxide deposition. In this embodiment of the invention, the SMT oxide layer is not removed during the SMT process. Therefore, the SMT oxide layer undergoes RTA, so defects in the SMT oxide layer, such as dangling bonds, can be repaired. Thus, replacing the SAB oxide layer with the SMT oxide layer in this embodiment of the invention not only saves the SMT oxide layer removal and SAB oxide layer growth processes, but also eliminates the defects caused by regrowing the SAB oxide layer, thereby improving the dark current of the device.

[0060] In this embodiment of the invention, the SMT oxide layer replaces the existing regrown SAB oxide layer, and also optimizes the SAB dry etching process, i.e., the second etching, which can improve the silicon nitride (Si3N4) / Oxide selectivity and reduce plasma damage. The residual SMT oxide layer is subsequently removed by wet etching. In the pixel area of ​​the CIS product, the contact film layer with the silicon substrate is the thermally repaired oxide layer, i.e., the SMT oxide layer. Therefore, the dark current level of the CIS product formed in this embodiment of the invention can be improved to the same level as that of existing CIS products without SMT processes.

[0061] The present invention has been described in detail above through specific embodiments, but these are not intended to limit the invention. Many modifications and improvements can be made by those skilled in the art without departing from the principles of the invention, and these should also be considered within the scope of protection of the present invention.

Claims

1. A process method for improving the dark current of a CIS, characterized in that, Includes the following steps: A semiconductor substrate is provided on which a gate structure is formed and source / drain injection is performed. The semiconductor substrate includes a pixel region and a logic region, and the pixel region includes pixel units of a CIS. SMT oxide layer and SMT silicon nitride layer are deposited sequentially; The SMT silicon nitride is patterned and etched so that the SMT silicon nitride is retained only in the channel stress improvement region; The first annealing transfers the stress of the SMT silicon nitride to the channel region of the channel stress improvement zone, and the first annealing also repairs defects in the SMT oxide layer. Remove the SMT silicon nitride; Silicon nitride (SAB) is deposited, and an SAB layer is formed by stacking the SMT oxide layer and the SAB silicon nitride layer. The dark current of the CIS is improved by utilizing the defect repair feature of the SMT oxide layer.

2. The process method for improving the dark current of CIS as described in claim 1, characterized in that: The logic region includes an NMOS formation region and a PMOS formation region.

3. The process method for improving the dark current of CIS as described in claim 2, characterized in that: The SMT silicon nitride is tensile stress silicon nitride, and the channel stress improvement region is the NMOS formation region in the logic region.

4. The process method for improving the dark current of CIS as described in claim 1, characterized in that: Each pixel unit includes a photodiode and a pixel unit circuit, and the pixel unit circuit includes multiple transistors.

5. The process method for improving the dark current of CIS as described in claim 4, characterized in that: Each transistor in the pixel unit circuit is an NMOS transistor.

6. The process method for improving the dark current of CIS as described in claim 1, characterized in that: The gate structure includes a gate dielectric layer and a gate conductive material layer stacked sequentially.

7. The process method for improving the dark current of CIS as described in claim 6, characterized in that: Sidewalls are also formed on the side of the gate structure.

8. The process method for improving the dark current of CIS as described in claim 1, characterized in that: The semiconductor substrate is made of silicon.

9. The process method for improving the dark current of CIS as described in claim 1, characterized in that: The source-drain injection includes N+ source-drain injection and P+ source-drain injection.

10. The process method for improving the dark current of CIS as described in claim 1, characterized in that: The first annealing process uses the RTA process.

11. The process method for improving the dark current of CIS as described in claim 10, characterized in that: The impurities injected into the source and drain are also activated by the first annealing.

12. The process method for improving the dark current of CIS as described in claim 1, characterized in that: The patterning etching includes: The etching region of the SMT silicon nitride is defined using photolithography. The SMT silicon nitride is first etched to remove all SMT silicon nitride outside the channel stress improvement region.

13. The process method for improving the dark current of CIS as described in claim 12, characterized in that: The first etching is either dry etching or wet etching.

14. The process method for improving the dark current of CIS as described in claim 1, characterized in that: After forming the SAB layer, the method further includes: Photolithography defines the region for metal silicide formation; A second etching is performed to remove the SAB silicon nitride from the metal silicide formation region; Wet etching is performed to remove the SMT oxide layer in the metal silicide formation region; A first metal layer is formed and a silicide reaction is carried out to form a metal silicide in the metal silicide formation region.

15. The process method for improving the dark current of CIS as described in claim 14, characterized in that: The second etching is a dry etching process.

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