Method for manufacturing a passivation layer

Abstract

The application discloses a manufacturing method of a passivation layer applied to a manufacturing process of a CIS, comprising the following steps: forming a high-k dielectric layer on a first oxide layer, the high-k dielectric layer containing a material with a dielectric constant greater than 4, the first oxide layer being formed on a patterned substrate back surface, the patterned substrate back surface being formed with grooves, the substrate between the grooves being formed with photodiodes, and the substrate at the bottom of the groove on one side of the photodiodes being formed with a floating diffusion region; forming an anti-reflection layer on the high-k dielectric layer at the top of the substrate between the grooves, the anti-reflection layer containing an oxide; performing annealing treatment on the anti-reflection layer in an environment containing oxygen, so that oxygen elements diffuse into the anti-reflection layer to fill oxygen vacancies; and forming a second oxide layer, the second oxide layer covering the anti-reflection layer and the high-k dielectric layer, and the second oxide layer filling the grooves. The embodiment of the application can improve the passivation effect of the passivation layer, reduce white noise, and improve the film forming quality of the passivation layer film.

Description

Technical Field

[0001] This application relates to the field of semiconductor devices and integrated circuit technology, and in particular to a method for fabricating a passivation layer. Background Technology

[0002] Image sensors are electronic devices that convert light signals into electrical signals and are widely used in fields such as photography, security systems, smartphones, and medical electronics. Among image sensors, complementary metal-oxide-semiconductor (CMOS) image sensors are fabricated using traditional CMOS circuitry. This allows for the integration of the image sensor and its required peripheral circuitry, thus giving CIS a wide range of application prospects.

[0003] Depending on the location where light is received, CIS can be divided into two structures: front-side illumination (FSI) and back-side illumination (BSI). Compared to FSI CIS, BSI CIS changes the internal structure of the element, reversing the direction of the incident light path of the photosensitive layer element, allowing light to enter directly from the back of the element. This avoids the influence of the structure and thickness between the microlens and photodiode (PD) on light in FSI CIS, thus improving the efficiency of light reception.

[0004] For CIS, especially BSI CIS, white pixels are one of the key defects affecting image quality. The generation of white pixels is closely related to dark current, and the level of dark current largely depends on the quality of the back passivation layer. In BSI CIS structures, light enters from the back of the wafer, exposing the back of the photodiode (PD), which requires a high-quality passivation layer to protect the sensitive area.

[0005] Currently, the back passivation layer of BSI CIS typically employs a multilayer composite structure, including a silicon oxide layer, a high-k dielectric layer (containing materials with a dielectric constant k greater than 4, such as alumina (Al2O3)), an antireflective layer (which can be a tantalum oxide (TaO) layer, primarily tantalum pentoxide (Ta2O5)), and a silicon oxide capping layer. The tantalum oxide layer, acting as an antireflective layer, can reduce light reflection and increase light absorption at specific wavelengths. However, during the deposition process, fluctuations in oxygen concentration within the process chamber can easily lead to oxygen vacancy defects, forming oxygen-deficient films (e.g., Ta2O5). 5-x(x is a natural number, x≥1) In thin films, these positively charged oxygen vacancies introduce electron traps and fixed positive charge sources, becoming centers for dark current generation. Simultaneously, they weaken the negative charge passivation capability of the high-k dielectric layer, leading to increased interface dark current and consequently causing white pixels. Therefore, there is an urgent need to provide an improvement method for current CIS fabrication processes to reduce oxygen vacancy defects in antireflective films and decrease white pixels in CIS. Summary of the Invention

[0006] This application provides a method for fabricating a passivation layer, which can solve the problem that the passivation layer fabrication methods provided in related technologies for CIS easily lead to oxygen vacancy defects in the high-k dielectric layer, resulting in high white pixels. The method includes: A high-k dielectric layer is formed on a first oxide layer, the high-k dielectric layer comprising a material with a dielectric constant greater than 4, the first oxide layer is formed on the back side of a patterned substrate, a groove is formed on the back side of the patterned substrate, a photodiode is formed in the substrate between the grooves, and a floating diffusion region is formed in the substrate at the bottom of the groove on one side of the photodiode. An antireflective layer comprising an oxide is formed on a high-k dielectric layer on top of the substrate between the grooves. The antireflective layer is annealed in an oxygen-containing environment to allow oxygen to diffuse into the interior of the antireflective layer and fill oxygen vacancies. A second oxide layer is formed, which covers the antireflective layer and the high-k dielectric layer, and fills the groove.

[0007] In some embodiments, the antireflective layer comprises a tantalum oxide layer.

[0008] In some embodiments, the annealing temperature is 450 degrees Celsius to 550 degrees Celsius.

[0009] In some embodiments, the annealing process takes 30 to 60 minutes.

[0010] In some embodiments, the conductivity type of the impurities doped in the photodiode is the same as the conductivity type of the impurities doped in the floating diffusion region, and the concentration of the impurities doped in the photodiode is less than the concentration of the impurities doped in the floating diffusion region.

[0011] In some embodiments, the first oxide layer and the second oxide layer comprise silicon dioxide layers.

[0012] In some embodiments, the high-k dielectric layer comprises an alumina layer.

[0013] The technical solution of this application has at least the following advantages: By annealing the antireflective layer in an oxygen-containing environment after forming an antireflective layer on a high-k dielectric layer during the fabrication of the passivation layer in CIS, oxygen diffuses into the interior of the antireflective layer. This oxygen fills defects such as dangling bonds, vacancies, and micropores in the antireflective layer, reducing the density of states at the interface, improving the passivation effect, and thus reducing white noise. At the same time, this oxidation treatment can consume some contaminants or residues on the film surface, further improving the film quality of the passivation layer and enhancing the reliability of CIS products. Attached Figure Description

[0014] To more clearly illustrate the technical solutions in the specific embodiments of this application or the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0015] Figure 1 This is a flowchart of a method for fabricating a passivation layer provided in an exemplary embodiment of this application; Figures 2 to 4 This is a schematic diagram illustrating the fabrication process of a passivation layer fabrication method provided in an exemplary embodiment of this application. Detailed Implementation

[0016] The technical solutions of this application will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this application. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0017] In the description of this application, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0018] In the description of this application, it should be noted that, unless otherwise expressly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal connection of two components; and they can refer to a wireless connection or a wired connection. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.

[0019] Furthermore, the technical features involved in the different embodiments of this application described below can be combined with each other as long as they do not conflict with each other.

[0020] refer to Figure 1 It illustrates a flowchart of a method for fabricating a passivation layer according to an exemplary embodiment of this application, which is applied in the fabrication process of CIS, such as... Figure 1 As shown, the method includes: Step S1: A high-k dielectric layer is formed on the first oxide layer. The high-k dielectric layer contains a material with a dielectric constant greater than 4. The first oxide layer is formed on the back side of a patterned substrate. A groove is formed on the back side of the patterned substrate. A photodiode is formed in the substrate between the grooves. A floating diffusion region is formed in the substrate at the bottom of the groove on one side of the photodiode.

[0021] Step S2, an anti-reflective layer comprising an oxide is formed on a high-k dielectric layer on top of the substrate between the grooves.

[0022] This application illustrates embodiments using an antireflective layer comprising a tantalum oxide layer and a high-k dielectric layer comprising an aluminum oxide layer as examples. (See reference...) Figure 2 It shows a schematic cross-sectional view after an anti-reflective layer has been formed on a high-k dielectric layer on top of the substrate between the grooves, exemplarily, such as Figure 2As shown, the back side of the substrate 210 has a patterned structure with grooves 400 extending downward from the back side of the substrate 210. Photodiodes 211 can be formed in the substrate 210 between the grooves 400 via ion implantation. The grooves 400 are used to form a back-side deep trench isolation (BDTI) structure between the photodiodes (which can be constructed by subsequently filling it with a dielectric layer). A floating diffusion (FD) region 212 is formed in the substrate 210 at the bottom of the groove on one side of the photodiode 211. A first oxide layer 221 is formed on the back side of the substrate 210 and the surface of the grooves 400. A high-k dielectric layer 222 is formed on the first oxide layer 221. A tantalum oxide layer can be deposited on the high-k dielectric layer 222 using chemical vapor deposition (CVD). The top tantalum oxide layer is then etched to retain it, forming an anti-reflection layer 223. Since the oxygen concentration in the process chamber typically fluctuates during deposition, oxygen vacancies are generated, forming an oxygen-deficient thin film (Ta2O). 5-x film).

[0023] The first oxide layer 221 includes a silicon dioxide (SiO2) layer, which can be formed on the back side of the substrate 210 and the surface of the groove 400 by a thermal oxidation process. The high-k dielectric layer 222 includes an aluminum oxide layer, which can be formed by atomic layer deposition (ALD) or CVD process. The conductivity type of the impurities doped in the photodiode 211 is the same as the conductivity type of the impurities doped in the floating diffusion region 212. The concentration of the impurities doped in the photodiode 211 is less than the concentration of the impurities doped in the floating diffusion region 212.

[0024] Step S3: Anneal the antireflective layer in an oxygen-containing environment to allow oxygen to diffuse into the interior of the antireflective layer and fill oxygen vacancies.

[0025] refer to Figure 3 This shows a schematic cross-sectional view of the anti-reflective layer after annealing. For example, such as... Figure 3 As shown, when the CIS is working, the surface of the high-k dielectric layer 222 will accumulate charges of the same conductivity type as the photodiode 211 to achieve passivation. There are flowing charge carriers between the photodiode 211 and the floating diffusion region 212. Due to the decrease in oxygen concentration in the process chamber during tantalum oxide deposition, oxygen-deficient Ta2O is easily formed. 5-xThe thin film generates a high density of positively charged oxygen vacancy defects, leading to electron-hole pairs at the surface / interface and increasing the overall dark current. Simultaneously, the positively charged oxygen vacancies neutralize some of the charge on the surface of the high-k dielectric layer 222, weakening the field-effect passivation and increasing the dark current at the interface, thus increasing white pixels. When the antireflective layer 223 is annealed in an oxygen-containing environment, oxygen diffuses into the interior of the antireflective layer 223 to fill oxygen vacancies. This oxygen fills defects such as dangling bonds, vacancies, and micropores in the antireflective layer, reducing the density of states at the interface, improving the passivation effect, and thus reducing white noise. Furthermore, this oxidation treatment can consume some contaminants or residues on the film surface, further improving the film quality of the passivation layer and enhancing the reliability of the CIS product.

[0026] Optionally, in step S3, the annealing temperature is 450 degrees Celsius (°C) to 550 degrees Celsius; optionally, the annealing time is 30 minutes to 60 minutes.

[0027] Step S4: A second oxide layer is formed, which covers the anti-reflective layer and the high-k dielectric layer, and fills the groove.

[0028] refer to Figure 4 This shows a schematic cross-sectional view after the formation of the second oxide layer. For example, as shown... Figure 4 As shown, a second oxide layer 224 can be formed by sequentially depositing a silicon dioxide layer using ALD and CVD processes, and the second oxide layer 224 fills the groove. During the CVD deposition of silicon dioxide, the silicon source is tetraethoxysilane (TEOS, chemical formula: Si(OC2H5)4).

[0029] In summary, in this embodiment of the application, after forming an antireflective layer on a high-k dielectric layer during the fabrication of the passivation layer of the CIS, the antireflective layer is annealed in an oxygen-containing environment. This allows oxygen to diffuse into the interior of the antireflective layer, filling defects such as dangling bonds, vacancies, and micropores in the antireflective layer. This reduces the density of states at the interface, improves the passivation effect, and thus reduces white noise. At the same time, this oxidation treatment can consume some contaminants or residues on the film surface, further improving the film quality of the passivation layer and enhancing the reliability of the CIS product.

[0030] Obviously, the above embodiments are merely illustrative examples for clear explanation and are not intended to limit the implementation. Those skilled in the art will recognize that other variations or modifications can be made based on the above description. It is neither necessary nor possible to exhaustively list all possible implementations here. However, obvious variations or modifications derived therefrom are still within the scope of protection of this application.

Claims

1. A method for fabricating a passivation layer, characterized in that, The method is applied in the manufacturing process of CIS, and the method includes: A high-k dielectric layer is formed on a first oxide layer, the high-k dielectric layer comprising a material with a dielectric constant greater than 4, the first oxide layer is formed on the back side of a patterned substrate, a groove is formed on the back side of the patterned substrate, a photodiode is formed in the substrate between the grooves, and a floating diffusion region is formed in the substrate at the bottom of the groove on one side of the photodiode. An antireflective layer comprising an oxide is formed on a high-k dielectric layer on top of the substrate between the grooves. The antireflective layer is annealed in an oxygen-containing environment to allow oxygen to diffuse into the interior of the antireflective layer and fill oxygen vacancies. A second oxide layer is formed, which covers the antireflective layer and the high-k dielectric layer, and fills the groove.

2. The method according to claim 1, characterized in that, The antireflective layer includes a tantalum oxide layer.

3. The method according to claim 2, characterized in that, The annealing temperature is between 450 degrees Celsius and 550 degrees Celsius.

4. The method according to claim 3, characterized in that, The annealing process takes 30 to 60 minutes.

5. The method according to any one of claims 2 to 4, characterized in that, The conductivity type of the impurities doped in the photodiode is the same as that of the impurities doped in the floating diffusion region, but the concentration of the impurities doped in the photodiode is lower than that of the impurities doped in the floating diffusion region.

6. The method according to claim 5, characterized in that, The first oxide layer and the second oxide layer include silicon dioxide layers.

7. The method according to claim 6, characterized in that, The high-k dielectric layer includes an alumina layer.

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