Pixel circuit, flat panel detection backboard, data reading method and flat panel detection device

Abstract

The present disclosure provides a pixel circuit, a flat panel detection backboard, a data reading method and a flat panel detection device, and relates to the technical field of digital imaging, and aims to adapt to the application of low dose, high resolution and the like. The pixel circuit comprises: a photoelectric conversion element configured to convert a light signal into an electric signal; an amplification circuit comprising a first thin film transistor and a second thin film transistor connected in series; wherein the gate of the first thin film transistor is electrically connected with the photoelectric conversion element, the gate of the second thin film transistor serves as a gate signal input end, and the second thin film transistor is configured to drive the first thin film transistor to work in a saturation region when the first thin film transistor is turned on.

Description

Technical Field

[0001] This disclosure relates to the field of digital imaging technology, and in particular to a pixel circuit, a flat panel detection backplane, a data reading method, and a flat panel detection device. Background Technology

[0002] A flat panel detector (FPD) is a precision electronic imaging device that directly or indirectly converts X-rays or other radiation signals into digital signals. It is a core component of modern digital imaging systems.

[0003] In related technologies, the operation of a flat panel detector involves converting radiation signals into visible light using a scintillator, then integrating the photon signals into a voltage signal using a photodiode, which is then amplified by a signal amplifier. However, these flat panel detector substrates are suitable for medical applications requiring conventional doses, and their application in low-dose, high-resolution scenarios is limited. Summary of the Invention

[0004] A first aspect of this disclosure provides a pixel circuit suitable for a flat panel detection backplane, the pixel circuit comprising: A photoelectric conversion element is configured to convert optical signals into electrical signals; An amplifier circuit includes a first thin-film transistor and a second thin-film transistor connected in series. The gate of the first thin-film transistor is electrically connected to the photoelectric conversion element, the gate of the second thin-film transistor serves as the gate signal input terminal, and the second thin-film transistor is configured to drive the first thin-film transistor to operate in the saturation region when the first thin-film transistor is turned on.

[0005] In an exemplary embodiment, the first terminal of the first thin-film transistor is electrically connected to the first terminal of the second thin-film transistor, the second terminal of the first thin-film transistor is grounded, and the second terminal of the second thin-film transistor serves as a power signal input terminal. The signal output from the power signal input terminal is used to drive the second thin-film transistor to operate in the saturation region.

[0006] In one exemplary embodiment, the second thin-film transistor is further configured as a data signal output terminal of the pixel circuit.

[0007] In one exemplary embodiment, the pixel circuit further includes a reset circuit, which includes a reset transistor; wherein, the first terminal of the reset transistor is electrically connected to the gate of the first thin-film transistor, and the gate of the reset transistor serves as a reset signal terminal. A second aspect of this disclosure provides a flat panel detection backplane, including a plurality of pixels, each pixel including pixel circuitry; and... Substrate; Multiple gate lines are located on one side of the substrate; A pixel circuit layer, located on one side of the substrate, is provided with a photoelectric conversion element, a first thin-film transistor, and a second thin-film transistor in each pixel circuit; The gate of the first thin-film transistor is electrically connected to the photoelectric conversion element, and the gate of the second thin-film transistor is electrically connected to the gate line. The second thin-film transistor is configured to drive the first thin-film transistor to operate in the saturation region when the first thin-film transistor is turned on.

[0008] In one exemplary embodiment, the flat panel detection backplate further includes: The power signal line and the ground signal line are located on one side of the substrate; Wherein, the first electrode of the first thin-film transistor is electrically connected to the first electrode of the second thin-film transistor, the second electrode of the first thin-film transistor is electrically connected to the ground signal line, and the second electrode of the second thin-film transistor is electrically connected to the power signal line.

[0009] In one exemplary embodiment, a plurality of the pixel arrays are arranged, and each of the gate lines is electrically connected to the pixel circuitry of a row of pixels; The flat panel detection backplane includes multiple power signal lines, each of which is electrically connected to the pixel circuit of a column of pixels. The power signal lines are multiplexed as data lines for the flat panel detection backplane.

[0010] In one exemplary embodiment, the pixel circuit layer includes: A first metal patterned layer includes the gates of the first thin-film transistor and the second thin-film transistor; The second metal patterned layer includes the first thin-film transistor and the first and second electrodes of the second thin-film transistor; The active layer includes the channels of the first thin-film transistor and the second thin-film transistor; The photoelectric conversion element is electrically connected to the gate of the first thin-film transistor via a connecting electrode.

[0011] In one exemplary embodiment, the pixel circuit layer further includes: A first dielectric layer is located on the side of the first thin-film transistor and the second thin-film transistor that is away from the substrate; The photoelectric conversion element is located on the side of the first dielectric layer away from the substrate; The photoelectric conversion element includes a bottom electrode, a photoconductive material layer, and a top electrode stacked in the thickness direction of the substrate. The bottom electrode is electrically connected to the connecting electrode through a first via located in the first dielectric layer.

[0012] In an exemplary embodiment, the orthographic projection of the first via on the substrate does not overlap with the orthographic projection of the photoconductive material layer on the substrate.

[0013] In an exemplary embodiment, the orthographic projection of the photoelectric conversion element on the substrate overlaps with the orthographic projection of the first thin-film transistor on the substrate, and / or, the orthographic projection of the photoelectric conversion element on the substrate overlaps with the orthographic projection of the second thin-film transistor on the substrate.

[0014] In one exemplary embodiment, the pixel circuit layer further includes: The second dielectric layer is located between the active layer and the first metal pattern layer, or between the active layer and the second metal pattern layer; The photoelectric conversion element includes a bottom electrode, a photoconductive material layer, and a top electrode stacked in the thickness direction of the substrate, wherein the bottom electrode is located in the second metal pattern layer; The bottom electrode is electrically connected to the connecting electrode through a second via located in the second dielectric layer, and the orthographic projection of the photoconductive material layer on the substrate does not overlap with the orthographic projections of the first thin-film transistor and the second thin-film transistor on the substrate.

[0015] In one exemplary embodiment, the orthographic projection of the photoconductive material layer on the substrate overlaps with the orthographic projection of the second via on the substrate.

[0016] In one exemplary embodiment, the orthographic projection of the photoconductive material layer on the substrate is located between the orthographic projections of the gate line and the connecting electrode on the substrate.

[0017] In one exemplary embodiment, the orthographic projection of the connection electrode on the substrate is parallel to the orthographic projection of the gate line on the substrate.

[0018] In one exemplary embodiment, the flat panel detection backplane further includes a power signal line located in the second metal pattern layer; The power signal line is electrically connected to the second electrode of the second thin-film transistor, and the power signal line and the orthographic projection of the connecting electrode on the substrate do not overlap.

[0019] In one exemplary embodiment, the flat panel detection backplate further includes: A light-shielding layer is located on the side of the pixel circuit layer opposite to the substrate; Wherein, the orthographic projection of the light-shielding layer on the substrate overlaps with the orthographic projection of the channel of the first thin-film transistor and / or the second thin-film transistor on the substrate.

[0020] In one exemplary embodiment, the photoelectric conversion element includes a bottom electrode, a photoconductive material layer, and a top electrode stacked in the thickness direction of the substrate; The light-shielding layer is reused as the top electrode.

[0021] In one exemplary embodiment, the flat panel probe backplane further includes a reset signal line located on one side of the substrate; The pixel circuit further includes a reset circuit, which includes a reset transistor; wherein the first terminal of the reset transistor is electrically connected to the gate of the first thin-film transistor, and the gate of the reset transistor is electrically connected to the reset signal line. A third aspect of this disclosure provides a flat panel detection device, comprising the flat panel detection backplate described in the first aspect and a scintillator layer located on one side of the flat panel detection backplate.

[0022] A fourth aspect of this disclosure provides a data reading method, which is applied to any pixel circuit of the first aspect or to the flat panel detection device of the second aspect; wherein the data reading method includes: In the first time period, the second thin-film transistor is turned on and controlled to operate in the saturation region; During the second time period, the photoelectric conversion element turns on the first thin-film transistor, and the second thin-film transistor pulls up the voltage of the first electrode of the first thin-film transistor, so that the first thin-film transistor continues to operate in the saturation region; The data signal is read through the second electrode of the second thin-film transistor, and the data signal is used to characterize the intensity of the light signal received by the photoelectric conversion element.

[0023] This disclosure discloses a pixel circuit for a flat panel detection backplane. The pixel circuit includes a photoelectric conversion element and an amplification circuit. The photoelectric conversion element is configured to convert an optical signal into an electrical signal. The amplification circuit includes a first thin-film transistor (TFT) and a second TFT connected in series. The gate of the first TFT is electrically connected to the photoelectric conversion element, and the gate of the second TFT serves as a gate signal input terminal. The second TFT is configured to drive the first TFT to operate in the saturation region when the first TFT is turned on. In this embodiment, the photoelectric conversion element can convert the received optical signal into an electrical signal, such as a voltage signal. This voltage signal is applied to the gate of the first TFT, thereby turning on the first TFT. When the first TFT is turned on, the second TFT can adjust the first TFT to always operate in the saturation region. By ensuring that the first TFT always operates in the saturation region under the on state, the current increase (gate-source current Ids) of the first TFT is more significant under the same voltage, making it easier to detect. In this way, the voltage signal detected by the photoelectric conversion element can be amplified within the first TFT, thereby enabling the identification of low-dose radiation signals, suitable for high-resolution applications such as scientific research.

[0024] The above description is merely an overview of the technical solution disclosed herein. In order to better understand the technical means of this disclosure and to implement it in accordance with the contents of the specification, and to make the above and other objects, features and advantages of this disclosure more apparent and understandable, specific embodiments of this disclosure are described below. Attached Figure Description

[0025] To more clearly illustrate the technical solutions in the embodiments or related technologies of this disclosure, the accompanying drawings used in the description of the embodiments or related technologies will be briefly introduced below. Obviously, the accompanying drawings described below are some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort. It should be noted that the scale in the drawings is for illustration only and does not represent the actual scale.

[0026] Figure 1 A plan view of the flat panel detector backplate is shown; Figure 2A The circuit diagram of the amplifier circuit in the pixel circuit is shown; Figure 2B The circuit diagram of the pixel circuit is shown; Figure 3 The graph showing the relationship between the gate-source current Ids and VGS of a thin-film transistor is shown. Figure 4 A cross-sectional view of one pixel of the first type of plate detection backplane is shown; Figure 5A top-view schematic diagram of one pixel of the first type of plate detection backplane is shown; Figure 6 A cross-sectional view of a pixel on the second type of plate detection backplane is shown. Figure 7 A top-view schematic diagram of one pixel of the second type of plate detection backplane is shown; Figure 8 A cross-sectional view of a pixel on the third type of plate detection backplane is shown. Figure 9 A cross-sectional structural schematic diagram of a flat plate detection device according to an embodiment of the present disclosure is shown; Figure 10 A schematic diagram of the planar structure of a flat plate detection device according to an embodiment of the present disclosure is shown; Figure 11 A flowchart illustrating the steps of the data reading method is shown. Detailed Implementation

[0027] To make the above-mentioned objectives, features, and advantages of this disclosure more apparent and understandable, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. Based on the embodiments of this disclosure, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this disclosure.

[0028] In this specification, "electrical connection" and "coupling" include situations where components are connected together by elements that have some electrical function. There are no particular limitations on what constitutes an "electrical function," as long as it allows for the transmission and reception of electrical signals between the connected components. Examples of "electrical functions" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other components with various functions.

[0029] In this specification, "parallel" refers to the state where the angle formed by two straight lines is greater than or equal to -10° and less than 10°, and therefore also includes the state where the angle is greater than or equal to -5° and less than 5°. Similarly, "perpendicular" refers to the state where the angle formed by two straight lines is greater than or equal to 80° and less than 100°, and therefore also includes the state where the angle is greater than or equal to 85° and less than 95°.

[0030] Unless the context otherwise requires, throughout the specification and claims, the term "comprising" is interpreted as open and encompassing, that is, "including, but not limited to".

[0031] In this application, "same layer" refers to the relationship between multiple film layers formed from the same material after undergoing the same step (e.g., a patterning process). "Same layer" here does not always mean that multiple film layers have the same thickness or the same height in a cross-sectional view. The polygons used in this specification are not strictly defined; they can be approximate triangles, parallelograms, trapezoids, pentagons, or hexagons, and may have minor deformations due to tolerances.

[0032] In the embodiments of this application, since the source and drain of the transistor are symmetrical, their source and drain can be interchanged. In the embodiments of this application, one of the source and drain of the transistor can also be called the first electrode, and the other of the source and drain can be called the second electrode.

[0033] In related technologies, taking X-rays as a radiation signal as an example, the working process of a flat panel detector is that X-rays are converted into visible light by a scintillator, and the photodiode integrates the photon signal into a voltage signal, which is then transmitted to a signal amplifier for amplification via a thin-film transistor. The thin-film transistor has no gain effect inside, that is, the signal is not amplified inside the thin-film transistor, which is suitable for conventional dose medical applications, but has limitations in applications such as low dose and high resolution.

[0034] In view of this, the present disclosure provides a pixel circuit for a flat panel detection backplane, a flat panel detection backplane, and a data reading method. The pixel circuit may include a photoelectric conversion element and an amplification circuit connected to the photoelectric conversion element. The amplification circuit includes a first thin-film transistor and a second thin-film transistor connected in series. The photoelectric conversion element is electrically connected to the gate of the first thin-film transistor, and the gate of the second thin-film transistor serves as the gate signal input terminal. When the first thin-film transistor is turned on, the second thin-film transistor can cause the first thin-film transistor to always operate in the saturation region. Since the current of the first thin-film transistor increases more significantly when operating in the saturation region, for example, the current increase slope is higher, thereby improving the detection sensitivity. This allows the electrical signal output by the photoelectric conversion element to be amplified inside the thin-film transistor, enabling the detection of low-dose X-rays, which is suitable for high-resolution applications such as scientific research.

[0035] The pixel circuit of the flat panel detection backplane according to an embodiment of the present disclosure, comprising a photoelectric conversion element and an amplification circuit, will be described below with reference to the accompanying drawings.

[0036] First, please refer to Figure 1 and Figure 2A As shown, Figure 1 A plan view of the flat panel detector backplate is shown. Figure 2A The circuit diagram of the amplifier circuit in the pixel circuit is shown, such as... Figure 1As shown, the flat panel detector backplate includes a display area AA and a non-display area FA. The display area AA includes multiple pixels, and each pixel includes a pixel circuit PC.

[0037] Multiple pixels can be arranged in an array on the flat panel detector backplane, for example, in multiple rows and columns.

[0038] like Figure 1 As shown, the flat panel detector backplane includes multiple grid lines GL and multiple data lines DL, wherein the grid lines GL are electrically connected to the pixel circuit, and the data lines DL are electrically connected to the pixel circuit.

[0039] In this embodiment, the gate line GL is used to turn on the pixel circuit, and the data line DL can be used to read the data signal output by the pixel circuit. This data signal refers to the signal after the electrical signal output by the photoelectric conversion element PIN is amplified by the amplification circuit.

[0040] like Figure 2A As shown, the pixel circuit of each pixel may include a photoelectric conversion element PIN and an amplification circuit; The photoelectric conversion element PIN is configured to convert optical signals into electrical signals. The amplifier circuit includes a first thin-film transistor TFT1 and a second thin-film transistor TFT2 connected in series. In this configuration, the gate of the first thin-film transistor TFT1 is electrically connected to the PIN of the photoelectric conversion element, and the gate of the second thin-film transistor TFT2 serves as the gate signal input terminal. The second thin-film transistor TFT2 is configured to drive the first thin-film transistor TFT1 to operate in the saturation region when the first thin-film transistor TFT1 is turned on.

[0041] In this embodiment, the photoelectric conversion element PIN may include a photodiode, which can be used to convert optical signals into electrical signals, such as voltage signals.

[0042] In this embodiment, the flat panel detector backplane may further include a scintillator layer, wherein the scintillator layer can convert radiation signals, such as X-rays, into visible light signals, which are then converted into electrical signals by photodiodes.

[0043] The voltage signal output by the photodiode can be related to the intensity of the X-rays. For example, stronger X-rays will promote the photodiode to generate a higher voltage signal, while weaker X-rays will promote the photodiode to generate a lower voltage signal.

[0044] like Figure 2AAs shown, the pixel circuit of this embodiment includes an amplifier circuit, which includes a first thin-film transistor (TFT1) and a second thin-film transistor (TFT2) connected in series. The series connection of the first TFT1 and the second TFT2 means that the source and drain of the first TFT1 are electrically connected to the source and drain of the second TFT2.

[0045] like Figure 2A As shown, the gate of the first thin-film transistor TFT1 is electrically connected to the photoelectric conversion element PIN, and the gate of the second thin-film transistor TFT2 serves as the gate signal input terminal.

[0046] When the gate of the first thin-film transistor TFT1 is electrically connected to the photoelectric conversion element PIN, the electrical signal output by the photoelectric conversion element PIN can be loaded onto the gate and turn on the first thin-film transistor TFT1.

[0047] The gate of the second thin-film transistor TFT2 can be electrically connected to the gate line GL on the backplane of the flat panel detector, and the gate turn-on signal on the gate line GL can turn on the second thin-film transistor TFT2.

[0048] In this embodiment, the voltage at the end of the source and drain of the first thin-film transistor TFT1 that is not connected to the second thin-film transistor TFT2 can be less than the voltage at the end of the source and drain of the first thin-film transistor TFT1 that is connected to the second thin-film transistor TFT2. This allows the voltage at the end connected to the second thin-film transistor TFT2 to be pulled down when the first thin-film transistor TFT1 is turned on, and then pulled up again by the second thin-film transistor TFT2, thereby operating in the saturation region.

[0049] The second thin-film transistor TFT2 can be configured such that when the first thin-film transistor TFT1 is turned on, the first thin-film transistor TFT1 always operates in the saturation region.

[0050] In this context, the thin-film transistor operating in the saturation region means that the source-drain voltage VDS of the thin-film transistor is greater than or equal to VGS. VTH; where VGS refers to the gate-source voltage of the thin-film transistor and VTH refers to the threshold voltage of the thin-film transistor.

[0051] Please combine Figure 3 As shown, Figure 3 The graph showing the relationship between the gate-source current Ids and VGS of a thin-film transistor is shown below. Figure 3As shown, a thin-film transistor (TFT) can operate in segments A, B, C, and D when it is turned on. Among these, when the TFT operates in segment D, the slope of Ids is the largest, and the current increase is more significant under the same voltage increase, making it easier to detect. However, when operating in other regions (such as segments A, B, and C), the current is unstable, the current gain is small, and it is not suitable for amplifying electrical signals.

[0052] In this embodiment, the output terminal of the amplifier circuit can be used as a data signal readout terminal. This output terminal can be the end where the first thin-film transistor TFT1 and the second thin-film transistor TFT2 are connected (e.g., ...). Figure 2A Vd1 in the figure can also be the end of the second thin-film transistor TFT2 that is not connected to the first thin-film transistor TFT1 (e.g., Figure 2A VDD in (the context of VDD).

[0053] The data signal output terminal can be understood as the output signal after the electrical signal detected by the photoelectric conversion element PIN is amplified by the first thin film transistor TFT1 and the second thin film transistor TFT2.

[0054] The pixel circuit of this embodiment enables the first thin-film transistor TFT1 to always operate in the saturation region when it is turned on, thereby maximizing the increase of the Ids current of the first thin-film transistor TFT1. This allows the electrical signal output by the photoelectric conversion element PIN to be amplified within the first thin-film transistor TFT1, thus enabling low-dose detection.

[0055] In some embodiments, such as Figure 2A As shown, the first terminal D1 of the first thin-film transistor TFT1 is electrically connected to the first terminal S2 of the second thin-film transistor TFT2, the second terminal S1 of the first thin-film transistor TFT1 is grounded, and the second terminal D2 of the second thin-film transistor TFT2 serves as the power signal input terminal VDD.

[0056] In this embodiment, the first electrode D1 of the first thin-film transistor TFT1 can be the drain and the second electrode S1 can be the source. The first electrode S2 of the second thin-film transistor TFT2 can be the source and the second electrode D2 can be the drain.

[0057] Of course, in some other examples, the first electrode D1 of the first thin-film transistor TFT1 can be the source and the second electrode can be the drain. The first electrode S2 of the second thin-film transistor TFT2 can be the drain and the second electrode can be the source.

[0058] In this embodiment, the second terminal D2 of the second thin-film transistor TFT2 is used as the power signal input terminal VDD, which means that the second terminal D2 of the second thin-film transistor TFT2 is connected to the power signal VDD.

[0059] In this embodiment, the power signal VDD output from the power signal input terminal is used to drive the second thin-film transistor TFT2 to always operate in the saturation region.

[0060] Then the power supply signal VDD input to the second electrode D2 of the second thin-film transistor TFT2 is greater than or equal to VGS. VTH2; where VGS refers to the gate-source voltage of the second thin-film transistor TFT2 and VTH refers to the threshold voltage of the second thin-film transistor TFT2.

[0061] For example, assuming the threshold voltage VTH2 of the second thin film transistor TFT2 is 2V, and the gate voltage Vg2 of the second thin film transistor TFT2 is set to a fixed voltage to ensure that the second thin film transistor TFT2 is turned on, the gate voltage Vg2 is assumed to be 10V.

[0062] The power supply signal VDD input to the second electrode D2 of the second thin-film transistor TFT2 is high voltage, ensuring that the second thin-film transistor TFT2 operates in the saturation region. For example, VDD is 20V.

[0063] In this configuration, the first electrode D1 of the first thin-film transistor TFT1 is connected to the first electrode S2 of the second thin-film transistor TFT2. For example... Figure 2A As shown, Vs2 is connected to Vd1. Since the second thin-film transistor TFT2 operates in the saturation region, Vd1 = Vs2 = Vg2 - Vth. In this context, the threshold voltage Vth1 of the first thin-film transistor TFT1 is assumed to be 2V, and the gate voltage Vg1 of the first thin-film transistor TFT1 is determined by the voltage signal input to the photoelectric conversion element PIN. Here, it is assumed that the voltage signal induced by X-rays fluctuates between 0-5V.

[0064] In this case, the second electrode S1 of the first thin-film transistor TFT1 is grounded.

[0065] In this embodiment, the first thin-film transistor TFT1 needs to operate in the saturation region, so Vd1≥Vg1-Vth1. Substituting into the saturation region calculation formula of the second thin-film transistor TFT2, Vd1=Vs2=Vg2-Vth, we have (Vg2-Vth2)≥Vg1-Vth1.

[0066] Thus, in order to ensure that the second thin-film transistor TFT2 operates in the saturation region at the same time, Vd2 ≥ Vg2 - Vth2 is required, that is, VDD ≥ Vg2 - Vth2.

[0067] Therefore, in this embodiment, by controlling VDD and Vg2, both the first thin-film transistor TFT1 and the second thin-film transistor TFT2 can be controlled to operate in the saturation region.

[0068] In this embodiment, after the X-rays pass through the scintillator, photocharge is generated at the photoelectric conversion element PIN. The photoelectric conversion element PIN is connected to the gate Vg1 of the first thin-film transistor TFT1. Therefore, Vg1 increases, and the first thin-film transistor TFT1 begins to conduct. Since the second terminal S1 of the first thin-film transistor TFT1 is grounded, the voltage at the first terminal D1Vd1 of the first thin-film transistor TFT1 begins to decrease. Because Vd1=Vs2, the decrease in Vd1 leads to an increase in Vg2-Vth2, increasing the conduction capability of the second thin-film transistor TFT2. VDD is charged, Vd1 increases, and stabilizes at an initial state of around 8V. Assuming that the voltage induced by the X-rays at the photoelectric conversion element PIN is 0-5V, 8V= Vd1>VPINmax-Vth1=5-2=3V. Therefore, it can be ensured that the first thin-film transistor TFT1 always operates in the saturation region, realizing the internal amplification of the optical signal.

[0069] In this embodiment, since the second electrode S1 of the first thin film transistor TFT1 is grounded, only a grounding signal line needs to be set on the flat panel detection backplane, without the need to introduce an additional signal line to control the voltage on the second electrode S1 of the first thin film transistor TFT1, thereby reducing the energy consumption of the entire flat panel detection backplane.

[0070] In some embodiments, the second thin-film transistor TFT2 is also configured as a data signal output terminal of the pixel circuit. For example, as... Figure 2A As shown, the second terminal D2VDD of the second thin-film transistor TFT2 can be used as a data signal output terminal. For example, the second terminal D2VDD of the second thin-film transistor TFT2 can be electrically connected to the data line DL. Thus, the data line DL of the flat panel detection backplane can not only serve as the power signal line of the amplifier circuit to input the power supply voltage to the second thin-film transistor TFT2, but also serve as the data line DL to read the data signal output by the pixel circuit (the signal amplified by the first thin-film transistor TFT1 and the second thin-film transistor TFT2 after the electrical signal detected by the photoelectric conversion element PIN is detected).

[0071] In this way, the data line DL can be reused as the power signal line VDD. In the actual driving process, the photoelectric signal amplified by the first thin-film transistor TFT1 can be read by detecting the change in the output current on the power signal line VDD.

[0072] In some embodiments, such as Figure 2B As shown, the pixel circuit of this embodiment may further include a reset circuit, which includes a reset transistor TFT3; wherein, the first terminal of the reset transistor TFT3 is electrically connected to the gate of the first thin film transistor TFT1, and the gate of the reset transistor TFT3 serves as the reset signal terminal Reset.

[0073] After reading the data signal output by the pixel circuit, the reset transistor TFT3 can be turned on, so that the reset voltage Vrst can be applied to the gate of the first thin film transistor, and the gate voltage of the first thin film transistor TFT1 can be reset to the reference potential, for example, the gate voltage of the first thin film transistor TFT1 can be pulled down to Vrst.

[0074] Reset can be a high-level signal.

[0075] This embodiment also provides a flat panel detection backplate; please refer to... Figures 4-8 As shown, the flat panel detector backplate includes multiple pixels, and each pixel includes pixel circuitry.

[0076] like Figure 1 As shown, the flat panel detector backplate includes multiple pixels. Each pixel is the smallest unit that constitutes a digital image. Each pixel corresponds to a tiny photosensitive area on the flat panel detector backplate, which is responsible for converting the received X-ray signal (or the converted light signal) into an electrical signal, and finally forming a point in the digital image.

[0077] Multiple pixel arrays are arranged in this way.

[0078] like Figure 4 , Figure 6 , Figure 8 As shown, the flat panel detector backplane includes a substrate 10, multiple gate lines GL located on one side of the substrate 10, and a pixel circuit layer.

[0079] The multiple gate lines GL can be set in the pixel circuit layer or in a different layer than the pixel circuit layer. This embodiment will be described with the multiple gate lines GL located in the pixel circuit layer as an example.

[0080] In this embodiment, each of the multiple gate lines GL can be electrically connected to a row of pixels to activate the pixel circuit of that row. For example... Figure 1 As shown, the gate line GL can extend along the row direction.

[0081] In this embodiment, the pixel circuit layer contains the components of the pixel circuit for each pixel.

[0082] As mentioned above, the pixel circuit may include a photoelectric conversion element PIN and a first thin-film transistor TFT1 and a second thin-film transistor TFT2 electrically connected to the photoelectric conversion element PIN. The gate of the first thin-film transistor TFT1 is electrically connected to the photoelectric conversion element PIN, and the gate of the second thin-film transistor TFT2 is electrically connected to the gate line GL. The second thin-film transistor TFT2 is configured to drive the first thin-film transistor TFT1 to operate in the saturation region when the first thin-film transistor TFT1 is turned on.

[0083] like Figures 4-8 As shown, the gate of the second thin-film transistor TFT2 is electrically connected to the gate line GL, so that the second thin-film transistor TFT2 can be turned on by the gate turn-on signal loaded on the gate line GL, thereby turning on the second thin-film transistor TFT2.

[0084] like Figures 4-8 As shown, the gate of the first thin-film transistor TFT1 is electrically connected to the photoelectric conversion element PIN, so that the first thin-film transistor TFT1 can be turned on by the voltage signal input to the photoelectric conversion element PIN, thereby turning on the first thin-film transistor TFT1.

[0085] In this embodiment, the voltage at the end of the source and drain of the first thin-film transistor TFT1 that is not connected to the second thin-film transistor TFT2 can be less than the voltage at the end of the source and drain of the first thin-film transistor TFT1 that is connected to the second thin-film transistor TFT2. This allows the voltage at the end connected to the second thin-film transistor TFT2 to be pulled down when the first thin-film transistor TFT1 is turned on, and then pulled up again by the second thin-film transistor TFT2, thereby operating in the saturation region.

[0086] The second thin-film transistor TFT2 can be configured such that when the first thin-film transistor TFT1 is turned on, the first thin-film transistor TFT1 always operates in the saturation region.

[0087] When the first thin-film transistor TFT1 is turned on and the second thin-film transistor TFT2 is turned on, the second thin-film transistor TFT2 can apply the corresponding source / drain voltage to the first thin-film transistor TFT1, thereby making the first thin-film transistor TFT1 always operate in the saturation region.

[0088] As mentioned earlier, a thin-film transistor operating in the saturation region means that the source-drain voltage VDS of the thin-film transistor is greater than or equal to VGS. VTH; where VGS refers to the gate-source voltage of the thin-film transistor and VTH refers to the threshold voltage of the thin-film transistor.

[0089] In this embodiment, one end where the first thin-film transistor TFT1 and the second thin-film transistor TFT2 are connected (e.g.) Figure 2A Vd1 in the diagram can be used as the data signal output terminal. The end of the second thin-film transistor TFT2 that is not connected to the first thin-film transistor TFT1 (e.g., ...) Figure 2A VDD in the signal can also be used as a data signal output terminal.

[0090] The data signal output terminal can be understood as the output signal after the electrical signal detected by the photoelectric conversion element PIN is amplified by the first thin film transistor TFT1 and the second thin film transistor TFT2.

[0091] The pixel circuit of this embodiment enables the first thin-film transistor TFT1 to always operate in the saturation region when it is turned on, thereby maximizing the increase of the Ids current of the first thin-film transistor TFT1. This allows the electrical signal of the photoelectric conversion element PIN to be amplified within the first thin-film transistor TFT1, thus enabling the identification of low-dose signals.

[0092] In this embodiment, the flat panel detection backplane also includes a power signal line and a ground signal line. The power signal line and the ground signal line can be located on one side of the substrate 10, for example, in the pixel circuit layer or on the side of the pixel circuit layer away from the substrate 10.

[0093] This embodiment takes the power signal line VDD and the ground signal line VS1 located in the pixel circuit layer as an example.

[0094] The power signal line VDD and the ground signal line VS1 can be set on the same layer or on different layers.

[0095] Among them, the gate line GL, the power signal line VDD, and the ground signal line VS1 can be set on the same layer or on different layers.

[0096] In the case of heterogeneous layer configuration, the orthogonal projections of the gate line GL, power signal line VDD, and ground signal line VS1 on the substrate 10 can be mutually non-overlapping.

[0097] In this configuration, the first electrode D1 of the first thin-film transistor TFT1 is electrically connected to the first electrode S2 of the second thin-film transistor TFT2, the second electrode S1 of the first thin-film transistor TFT1 is electrically connected to the ground signal line, and the second electrode D2 of the second thin-film transistor TFT2 is electrically connected to the power signal line.

[0098] In this embodiment, the second electrode S1 of the first thin-film transistor TFT1 is electrically connected to the ground signal line, thereby grounding the second electrode S1 of the first thin-film transistor TFT1.

[0099] In this embodiment, the second electrode D2 of the second thin-film transistor TFT2 is electrically connected to the power signal line, so that the power signal line can provide a power signal to the second electrode D2 of the second thin-film transistor TFT2. Figure 2A As shown, the power signal can be a VDD signal.

[0100] In this embodiment, the signal output from the power signal line is used to drive the second thin-film transistor TFT2 to always operate in the saturation region.

[0101] Among them, the power supply signal VDD input to the second electrode D2 of the second thin-film transistor TFT2 is greater than or equal to VGS. VTH2; where VGS refers to the gate-source voltage of the second thin-film transistor TFT2 and VTH refers to the threshold voltage of the second thin-film transistor TFT2.

[0102] As mentioned earlier, after X-rays pass through the scintillator, photocharge is generated at the photoelectric conversion element PIN. The photoelectric conversion element PIN is connected to the gate Vg1 of the first thin-film transistor TFT1. Therefore, Vg1 increases, and the first thin-film transistor TFT1 begins to conduct. Since the second terminal S1 of the first thin-film transistor TFT1 is grounded, the voltage at the first terminal D1 of the first thin-film transistor TFT1 begins to decrease. Because Vd1 = Vs2, the decrease in Vd1 leads to an increase in Vg2 - Vth2, which increases the conduction capability of the second thin-film transistor TFT2. VDD is charged, Vd1 increases, and stabilizes at an initial value of around 8V.

[0103] Assuming the voltage induced by X-rays in the photoelectric conversion element PIN is 0-5V, and 8V = Vd1 > VPINmax - Vth1 = 5 - 2 = 3V, it can be ensured that the first thin-film transistor TFT1 always operates in the saturation region. When the first thin-film transistor TFT1 operates in the saturation region, Ids can be significantly increased, making it easier to detect, which is equivalent to amplifying the electrical signal of the photoelectric conversion element PIN.

[0104] In some embodiments, such as Figure 1 As shown, the flat panel detector backplane includes multiple power signal lines. Each power signal line is electrically connected to the pixel circuit of a column of pixels. The power signal lines are multiplexed into the data line DL of the flat panel detector backplane.

[0105] In this embodiment, the power signal line is multiplexed as the data line DL, so the power signal line can also read the data signal output by the pixel circuit (the signal amplified by the first thin film transistor TFT1 and the second thin film transistor TFT2 after the electrical signal detected by the photoelectric conversion element PIN is detected).

[0106] In this embodiment, the data line DL can be multiplexed as a power signal line. During the actual driving process, VDD voltage can be input to the data line DL at one time period and the signal output on the data line DL can be read at another time period.

[0107] In this embodiment, the data line DL can be arranged to cross the gate line GL, or to be orthogonal to the gate line GL. A pixel circuit can be arranged at the intersection of the gate line GL and the data line DL.

[0108] In other words, the pixel circuit can be located at the intersection of the data line DL and the gate line GL.

[0109] In some other examples, such as Figure 7 and Figure 5As shown, the pixel circuit can be located within the area defined by the power signal line, the ground signal line, and the gate line GL. In other words, in practice, it is not required that the pixel circuit be located within the area enclosed by the power signal line, the ground signal line, and the gate line GL.

[0110] In some embodiments, the flat panel detector backplane may include a pixel circuit layer, in which photoelectric conversion element PIN, first thin film transistor TFT1, and second thin film transistor TFT2 are disposed.

[0111] Among them, such as Figures 4-8 As shown, the pixel circuit layer includes a first metal pattern layer, a second metal pattern layer, and a third metal pattern layer.

[0112] The first metal pattern layer includes the gate G1 of the first thin-film transistor TFT1 and the gate G2 of the second thin-film transistor TFT2. The second metal pattern layer includes the first electrode D1 and the second electrode S1 of the first thin film transistor TFT1, and the first electrode S2 and the second electrode D2 of the second thin film transistor TFT2. The active layer includes the channel A1 of the first thin-film transistor TFT1 and the channel A2 of the second thin-film transistor TFT2. The photoelectric conversion element PIN is electrically connected to the gate G1 of the first thin-film transistor TFT1 via the connecting electrode LJ.

[0113] In this embodiment, the first metal pattern layer, the second metal pattern layer, and the active layer are all disposed in different layers.

[0114] Each of the first metal pattern layer, the second metal pattern layer, and the active layer is separated by an insulating layer.

[0115] For example, such as Figure 4 and Figure 6 As shown, the active layer can be located on the side of the second metal pattern layer away from the substrate 10, and the first metal pattern layer can be located on the side of the active layer away from the substrate 10.

[0116] A gate insulating layer may be disposed between the active layer and the second metal layer, and the first metal pattern layer overlaps with the channel in the active layer.

[0117] For example, such as Figure 8 As shown, the first metal pattern can be located on the side of the active layer away from the substrate 10, and the second metal pattern layer can be located on the side of the first metal pattern away from the substrate 10.

[0118] A gate insulating layer 20 is disposed between the first metal pattern layer and the active layer, and an interlayer dielectric layer 21 is disposed between the second metal pattern layer and the first metal pattern layer.

[0119] In this embodiment, the gate of the first thin-film transistor TFT1 and the gate of the second thin-film transistor TFT2 can be on the same layer, the first electrode S2 and the second electrode D2 of the first thin-film transistor TFT1 and the second thin-film transistor TFT2 can be on the same layer, and the channel A1 of the first thin-film transistor TFT1 and the channel A2 of the second thin-film transistor TFT2 can be on the same layer.

[0120] In some embodiments, such as Figures 4-7 As shown, the orthogonal projection of the photoelectric conversion element PIN on the substrate 10 can overlap with the orthogonal projections of the first thin-film transistor TFT1 and the second thin-film transistor TFT2 on the substrate 10.

[0121] like Figure 4 and Figure 6 As shown, the photoelectric conversion element PIN can be located on the side of the first thin film transistor TFT1 and the second thin film transistor TFT2 away from the substrate 10.

[0122] In some embodiments, such as Figure 8 As shown, the orthogonal projection of the photoelectric conversion element PIN on the substrate 10 can be non-overlapping with the orthogonal projections of the first thin-film transistor TFT1 and the second thin-film transistor TFT2 on the substrate 10.

[0123] like Figure 8 As shown, the photoelectric conversion element PIN can be disposed on the same layer as the first thin film transistor TFT1 and the second thin film transistor TFT2.

[0124] In this embodiment, the photoelectric conversion element PIN can be connected to the gate G1 of the first thin film transistor TFT1 via the connection electrode LJ located in the first metal pattern layer.

[0125] like Figure 4 and Figure 6 As shown, the first thin-film transistor TFT1 and the second thin-film transistor TFT2 are thin-film transistors with a bottom gate structure, and the connection electrode LJ can be located in the first metal pattern layer.

[0126] like Figure 8 As shown, the first thin-film transistor TFT1 and the second thin-film transistor TFT2 are thin-film transistors with a top gate structure. The connecting electrode LJ can be located on the side of the second metal pattern layer away from the substrate 10, and it can be electrically connected to the photoelectric conversion element PIN through the overlapping electrode DJ.

[0127] The lap electrode DJ is located in the first metal pattern layer.

[0128] In some examples of this embodiment, such as Figure 5 and Figure 7As shown, the orthogonal projection of the connecting electrode LJ on the substrate 10 can be approximately parallel to the orthogonal projection of the gate line GL on the substrate 10.

[0129] Here, "approximately parallel" means that the intersection angle of the orthogonal projections of the connecting electrode LJ and the gate line GL on the substrate 10 is less than or equal to 5°.

[0130] In some examples of this embodiment, the photoelectric conversion element PIN can be located on the side of the first thin-film transistor TFT1 and the second thin-film transistor TFT2 away from the substrate 10. Specifically, as shown in the example... Figure 4 As shown, the pixel circuit layer also includes a first dielectric layer (including 30, 40 and 50), which is located on the side of the first thin film transistor TFT1 and the second thin film transistor TFT2 away from the substrate 10, and the photoelectric conversion element PIN is located on the side of the first dielectric layer away from the substrate 10.

[0131] The photoelectric conversion element PIN may include a bottom electrode P1, a photoconductive material layer P2, and a top electrode P3 stacked in the thickness direction of the substrate 10. The bottom electrode P1 is electrically connected to the connection electrode LJ through a first via K1 located in the first dielectric layer.

[0132] In this embodiment, the photoelectric conversion element PIN is a photodiode, which can convert optical signals into electrical signals through the bottom electrode P1, the photoconductive material layer P2, and the top electrode P3.

[0133] The top electrode P3 is usually located on the side of the photoconductive material away from the substrate 10, facing the light-receiving surface or the light-emitting side, for example, facing the scintillator layer. Its main function is to collect and extract photogenerated carriers.

[0134] Among them, the photoconductive material layer P2 can be made of semiconductor materials (such as silicon, perovskite, etc.). When visible light shines on this layer, photons are absorbed, and their energy excites electrons to jump, generating electron-hole pairs (i.e., photogenerated carriers). Electrons jump from the valence band to the conduction band.

[0135] The bottom electrode P1 is located on the side of the photoconductive material layer P2 close to the substrate 10, and is used to collect the charge carriers generated by the photoconductive material layer P2. In some examples, the bottom electrode P1 can also serve as a reflective layer to enhance light absorption.

[0136] like Figures 4-8 As shown, the bottom electrode P1 can be electrically connected to the gate of the first thin-film transistor TFT1.

[0137] like Figure 4 and Figure 5As shown, in some examples of this embodiment, the orthographic projection of the photoelectric conversion element PIN on the substrate 10 overlaps with the orthographic projection of the first thin-film transistor TFT1 on the substrate 10, and / or, the orthographic projection of the photoelectric conversion element PIN on the substrate 10 overlaps with the orthographic projection of the second thin-film transistor TFT2 on the substrate 10.

[0138] For example, the orthographic projection of the photoelectric conversion element PIN on the substrate 10 overlaps with the orthographic projections of the first thin-film transistor TFT1 and the second thin-film transistor TFT2 on the substrate 10.

[0139] As another example, the orthographic projection of the photoelectric conversion element PIN on the substrate 10 may overlap with the orthographic projection of the first thin-film transistor TFT1 on the substrate 10, but may not overlap with the orthographic projection of the second thin-film transistor TFT2 on the substrate 10.

[0140] As another example, the orthographic projection of the photoelectric conversion element PIN on the substrate 10 may overlap with the orthographic projection of the second thin-film transistor TFT2 on the substrate 10, but may not overlap with the orthographic projection of the first thin-film transistor TFT1 on the substrate 10.

[0141] In this embodiment, the example given is that the orthographic projection of the photoelectric conversion element PIN on the substrate 10 overlaps with the orthographic projections of the first thin-film transistor TFT1 and the second thin-film transistor TFT2 on the substrate 10. Specifically, the orthographic projection of at least one of the bottom electrode P1, the photoconductive material layer P2, and the top electrode P3 of the photoelectric conversion element PIN on the substrate 10 can overlap with the orthographic projections of the first thin-film transistor TFT1 and the second thin-film transistor TFT2 on the substrate 10.

[0142] In other words, the photoelectric conversion element PIN, the first thin-film transistor TFT1, and the second thin-film transistor TFT2 can be stacked in the thickness direction of the substrate 10, thereby reducing the space occupied by each pixel circuit and improving the resolution of the flat panel detection backplane.

[0143] In some examples of this embodiment, the orthographic projection of at least one of the bottom electrode P1, the photoconductive material layer P2, and the top electrode P3 onto the substrate 10 may overlap with the orthographic projection of the first thin-film transistor TFT1 and the second thin-film transistor TFT2 onto the substrate 10, including: The orthographic projections of the bottom electrode P1, the photoconductive material layer P2, and the top electrode P3 onto the substrate 10 all overlap with the orthographic projections of the first thin-film transistor TFT1 and the second thin-film transistor TFT2 onto the substrate 10.

[0144] For example, the orthogonal projections of the bottom electrode P1, photoconductive material layer P2, and top electrode P3 onto the substrate 10 overlap with the orthogonal projections of the channels of the first thin-film transistor TFT1 and the second thin-film transistor TFT2 onto the substrate 10. In this way, the channels of the first thin-film transistor TFT1 and the second thin-film transistor TFT2 can be shielded by the bottom electrode P1, photoconductive material layer P2, and top electrode P3, thereby protecting the characteristics of the first thin-film transistor TFT1 and the second thin-film transistor TFT2.

[0145] In this embodiment, the orthogonal projections of the bottom electrode P1, the top electrode P3, and the connecting electrode LJ on the substrate 10 overlap each other.

[0146] In this embodiment, the first dielectric layer can be formed using inorganic or organic materials.

[0147] like Figure 4 As shown, the first dielectric layer may include a first passivation layer 30, a first organic layer 40, and a second passivation layer 50.

[0148] The first passivation layer is located on the side of the first thin film transistor TFT1 and the second thin film transistor TFT2 away from the substrate 10, the first organic layer is located on the side of the planarization layer close to the substrate 10, and the second passivation layer is located on the side of the first organic layer away from the substrate 10.

[0149] like Figure 4 As shown, the bottom electrode P1 is electrically connected to the connecting electrode LJ through the first via K1 formed in the first dielectric layer.

[0150] In some examples of this embodiment, such as Figure 4 As shown, the orthogonal projection of the first via K1 onto the plane in the normal direction of the substrate 10 can be an inverted trapezoid.

[0151] In some other examples, the edge of the first via K1 on the plane in the normal direction of the substrate 10 can also be stepped. In this way, by designing it as a step, the slope of the first via K1 can be reduced, thereby reducing the step difference in the first via and thus avoiding the problem of the bottom electrode P1 climbing and breaking in the first via K1.

[0152] In some examples of this embodiment, such as Figure 4 and Figure 5 As shown, the orthographic projection of the first via K1 on the substrate 10 does not overlap with the orthographic projection of the photoconductive material layer P2 on the substrate 10. In this way, the first via can be set around the photoconductive material layer P2, thereby avoiding occupying the space below the photoelectric conversion element PIN and improving the flatness of the film layer directly below the photoelectric conversion element PIN.

[0153] like Figure 4 and Figure 5As shown, the orthographic projection of the first via K1 on the substrate 10 does not overlap with the orthographic projections of the first thin-film transistor TFT1 and the second thin-film transistor TFT2 on the substrate 10.

[0154] like Figure 5 As shown, in some examples, the distance between the orthogonal projection of the gate of the first thin-film transistor TFT1 on the substrate 10 and the first via can be greater than the distance between the orthogonal projection of the gate of the second thin-film transistor TFT2 on the substrate 10 and the first via.

[0155] Of course, in some other examples, the distance between the orthogonal projection of the gate of the first thin-film transistor TFT1 on the substrate 10 and the first via can be smaller than the distance between the orthogonal projection of the gate of the second thin-film transistor TFT2 on the substrate 10 and the first via.

[0156] This reduces the connection distance between the connecting electrode LJ and the gate.

[0157] like Figure 4 As shown, the side of the first dielectric layer away from the substrate 10 may also include a second organic layer 60, a third passivation layer 70, and a fourth passivation layer 80.

[0158] Among them, the bottom electrode P1 is located on the side of the first dielectric layer away from the substrate 10, the photoconductive material layer P2 is located on the side of the bottom electrode P1 away from the substrate 10, the second organic layer 60 is located on the side of the photoconductive material layer P2 away from the substrate 10, the third passivation layer 70 is located on the side of the second organic layer 60 away from the substrate 10, the fourth passivation layer 80 is located on the side of the third passivation layer 70 away from the substrate 10, and the top electrode P3 is located on the side of the fourth passivation layer 80 away from the substrate 10.

[0159] The top electrode P3 is in contact with the photoconductive material layer P2 through vias formed in the third passivation layer 70 and the fourth passivation layer 80.

[0160] In this embodiment, the vias formed on the third passivation layer 70 and the fourth passivation layer 80 can be non-overlapping with the first via.

[0161] In some embodiments, such as Figure 6 As shown, the pixel circuit layer also includes a second dielectric layer, which is located between the active layer and the first metal pattern layer, or between the active layer and the second metal pattern layer.

[0162] The photoelectric conversion element PIN includes a bottom electrode P1, a photoconductive material layer P2, and a top electrode P3 stacked in the thickness direction of the substrate 10. The bottom electrode P1 is located in the active layer and is electrically connected to the connection electrode LJ through a second via K2 located in the second dielectric layer.

[0163] like Figure 6 As shown, the first thin-film transistor TFT1 and the second thin-film transistor TFT2 have a bottom gate structure, and the second dielectric layer can be the gate insulating layer 20 located between the active layer and the first metal layer.

[0164] In this embodiment, the second via K2 can be formed on the second dielectric layer.

[0165] In this embodiment, the orthographic projection of the photoconductive material layer P2 on the substrate 10 does not overlap with the orthographic projections of the first thin-film transistor TFT1 and the second thin-film transistor TFT2 on the substrate 10. That is, the photoelectric conversion element PIN, the first thin-film transistor TFT1, and the second thin-film transistor TFT2 are arranged in the planar direction of the substrate 10.

[0166] like Figure 6 As shown, the pixel circuit layer may further include a first dielectric layer located on the side of the second metal pattern layer (including S1, D1, S2, and D2) facing away from the substrate 10. The first dielectric layer may include a first passivation layer 30, a first organic layer 40, and a second passivation layer 50. The first organic layer is located on the side of the first passivation layer facing away from the substrate 10, and the second passivation layer is located on the side of the first organic layer facing away from the substrate 10.

[0167] like Figure 6 As shown, the top electrode P3 can contact the photoconductive material layer P2 through a third via K3 formed on the first organic layer 40 and the second passivation layer 50.

[0168] In some examples, the bottom electrode P1 may be located in the second metal pattern layer.

[0169] In some examples of this embodiment, such as Figure 7 As shown, the orthogonal projection of the second via K2 on the substrate 10 does not overlap with the orthogonal projections of the first thin-film transistor TFT1 and the second thin-film transistor TFT2 on the substrate 10.

[0170] In some examples of this embodiment, such as Figure 6 As shown, the orthographic projection of the photoconductive material layer P2 on the substrate 10 overlaps with the orthographic projection of the second via K2 on the substrate 10.

[0171] The orthogonal projection of the photoconductive material layer P2 on the substrate 10 can be located within the orthogonal projection of the second via K2 on the substrate 10.

[0172] In some other examples, the orthogonal projection of the photoconductive material layer P2 onto the substrate 10 can also cover the orthogonal projection of the second via K2 onto the substrate 10.

[0173] In this embodiment, when the photoconductive material layer P2 is located in the second via K2, the space occupied by the photoelectric conversion element PIN, the first thin film transistor TFT1, and the second thin film transistor TFT2 can be reduced, thereby avoiding each pixel occupying a large space.

[0174] In this embodiment, as Figure 7 As shown, the orthographic projection of the photoconductive material layer P2 on the substrate 10 is located between the orthographic projections of the gate line GL and the connecting electrode LJ on the substrate 10.

[0175] In this case, the orthogonal projection of the photoconductive material layer P2 onto the substrate 10 is located in the region between the orthogonal projections of the gate line GL and the connecting electrode LJ onto the substrate 10, for example, close to the connecting electrode LJ. This allows the photoelectric conversion element PIN to be positioned within the space between the connecting electrode LJ and the gate line GL, thereby reducing the space occupied by each pixel.

[0176] As mentioned above, the photoelectric conversion element PIN is located on the side of the first thin film transistor TFT1 and the second thin film transistor TFT2 away from the substrate 10. The flat panel detection backplane also includes a power signal line, which may be located in the second metal pattern layer.

[0177] Among them, such as Figure 5 As shown, the power signal line is electrically connected to the second electrode D2 of the second thin-film transistor TFT2, and the projections of the power signal line and the connection electrode LJ onto the substrate 10 do not overlap. In this case, the formation of capacitance between the connection electrode LJ and the power signal line can be avoided.

[0178] In this embodiment, as Figures 4-8 As shown, the flat panel detector backplate also includes a light-shielding layer located on the side of the pixel circuit layer away from the substrate 10; wherein the orthographic projection of the light-shielding layer on the substrate 10 overlaps with the orthographic projection of the channel of the first thin film transistor TFT1 and / or the second thin film transistor TFT2 on the substrate 10.

[0179] In this embodiment, the light-shielding layer may be located on the side of the photoelectric conversion element PIN away from the substrate 10, or it may be located in the first dielectric layer described above.

[0180] In this embodiment, the light-shielding layer may cover the channel A1 of the first thin-film transistor TFT1, or the light-shielding layer may cover the channel A2 of the second thin-film transistor TFT2. Alternatively, the light-shielding layer may cover both the channels of the first thin-film transistor TFT1 and the second thin-film transistor TFT2.

[0181] In this embodiment, the light-shielding layer may not overlap with or may partially overlap with the orthogonal projection of the photoelectric conversion element PIN on the substrate 10.

[0182] The light-shielding layer can be formed using opaque materials.

[0183] In the case where the light-shielding layer overlaps with the PIN portion of the photoelectric conversion element, the light-shielding layer may be located within the orthogonal projection of the photoconductive material layer on the substrate 10, or may only partially overlap with the orthogonal projection of the photoconductive material layer on the substrate 10.

[0184] like Figure 4 , Figure 6 and Figure 8 As shown, the light-shielding layer can be reused as the top electrode P3 of the photoelectric conversion element PIN. In this case, the light-shielding layer can be formed using an opaque metallic material.

[0185] In some embodiments, such as Figure 4 and Figure 6 As shown, the first thin-film transistor TFT1 and the second thin-film transistor TFT2 have a bottom gate structure. In this case, the first metal pattern layer is located on the side of the active layer close to the substrate 10, and the second metal pattern layer is located on the side of the active layer away from the substrate 10.

[0186] In this embodiment, since the first thin-film transistor TFT1 and the second thin-film transistor TFT2 are bottom-gate structures, the process complexity can be reduced.

[0187] In some embodiments, such as Figure 8 As shown, the first thin-film transistor TFT1 and the second thin-film transistor TFT2 are top-gate structures. The first metal pattern layer is located on the side of the active layer away from the substrate 10. The pixel circuit layer also includes an interlayer dielectric layer 21 located on the side of the first metal pattern layer away from the substrate 10, a second metal pattern layer located on the side of the interlayer dielectric layer 21 away from the substrate 10, and a first dielectric layer located on the side of the second metal pattern layer away from the substrate 10.

[0188] The first dielectric layer includes a first passivation layer 30, a first organic layer 60, and a second passivation layer 70.

[0189] like Figure 8 As shown, the photoelectric conversion element PIN is located on the side of the first thin film transistor TFT1 and the second thin film transistor TFT2 away from the substrate 10. The bottom electrode P1 of the photoelectric conversion element PIN is electrically connected to the lap electrode DJ located in the first metal pattern layer through a fourth via formed on the first passivation layer and the interlayer dielectric layer.

[0190] The lap electrode DJ is electrically connected to the connecting electrode LJ through the fourth via, and the connecting electrode LJ is lapped to the gate of the first thin film transistor TFT1 through the fifth via formed on the first passivation layer 30 and the interlayer dielectric layer 21.

[0191] In this embodiment, the bottom electrode P1 is located on the side of the first passivation layer 30 away from the substrate 10, and the top electrode P3 is in direct contact with the photoconductive material layer P2 through vias formed on the second passivation layer 70 and the first organic layer 60.

[0192] The top electrode P3 is located on the side of the second passivation layer 70 away from the substrate 10.

[0193] A third passivation layer 80 may also be provided on the side of the second passivation layer 70 that is away from the substrate 10.

[0194] In some embodiments, an electrostatic protection layer 90 is further included on the side of the pixel circuit layer away from the substrate 10. The electrostatic protection layer 90 may be formed of a light-transmitting conductive material and may cover the entire substrate 10. The electrostatic protection layer 90 may serve to prevent static electricity.

[0195] like Figure 6 As shown, the electrostatic protection layer 90 can be located on the side of the second passivation layer 50 away from the substrate 10.

[0196] like Figure 4 As shown, the electrostatic protection layer 90 can be located on the side of the fourth passivation layer 80 away from the substrate 10.

[0197] like Figure 8 As shown, the electrostatic protection layer 90 can be located on the side of the third passivation layer 80 away from the substrate 10.

[0198] In some embodiments, such as Figure 8 As shown, a buffer layer 11 can also be provided between the substrate 10 and the active layer.

[0199] As described in the previous embodiment of the pixel circuit, such as Figure 2B As shown, the pixel circuit may also include a reset circuit, and the flat panel detection substrate may also include a reset signal line.

[0200] The reset circuit includes a reset transistor TFT3, the first electrode of which is electrically connected to the gate of the first thin-film transistor, and the gate of the reset transistor is electrically connected to the reset signal line.

[0201] The reset signal line is used to provide a reset signal to the reset transistor. This reset signal is applied to the gate of the reset transistor, thereby turning on the reset transistor. The second terminal of the reset transistor serves as the reset voltage input terminal, receiving a reset voltage Vrst. When the reset transistor is turned on, the reset voltage Vrst is applied to the gate of the first thin-film transistor, thereby allowing the gate of the first thin-film transistor to return to the reference voltage.

[0202] In this embodiment, the reset transistor TFT3 can be disposed on the same layer as the first thin-film transistor and the second thin-film transistor.

[0203] For example, the gate of the reset transistor TFT3 can be located in the first metal pattern layer, the first electrode and the second electrode can be located in the second metal pattern layer, and the channel of the reset transistor TFT3 can be located in the active layer.

[0204] Based on the same inventive concept, this disclosure also provides a flat plate detection device, including... Figures 2A-8 The aforementioned flat panel detector backplane and the scintillator layer SS located on one side of the flat panel detector backplane PD.

[0205] Please refer to Figure 9 and 10 As shown, Figure 9 A cross-sectional structural schematic diagram of a flat plate detection device according to an embodiment of the present disclosure is shown. Figure 10 A schematic diagram of the planar structure of a flat plate detection device according to an embodiment of the present disclosure is shown. Figure 9 and Figure 10 As shown, the scintillator layer can be located on the side of the pixel circuit layer away from the substrate 10, for example, on the side of the electrostatic shielding layer 90 away from the substrate 10.

[0206] In some embodiments, the flat panel detection device may further include a ROIC chip (Readout Integrated Circuit), wherein the ROIC chip can be electrically connected to multiple data lines DL in the flat panel detection backplane, mainly converting the photocurrent signal output by each pixel (or detection unit) into a voltage signal when each row of pixel circuits is turned on, and then reading it out through the output port.

[0207] In this embodiment, the voltage signals output by each pixel in each row of pixels read by the ROIC chip are stored in the computer, thereby obtaining the voltage signals output by each pixel in the entire flat panel detection backplane. Then, the voltage data of each pixel can be converted into image signals for display. For example, the voltage data can be converted into corresponding grayscale data for image display on the display panel.

[0208] In some embodiments, the flat panel detector backplane may further include a scintillator layer. Based on the same inventive concept, this disclosure also provides a data reading method for a flat panel detection backplane. Please refer to... Figure 11 As shown, Figure 11 A flowchart illustrating the steps of this data reading method is shown, as follows: Figure 11 As shown, the specific steps may include: S1: In the first time period, the second thin-film transistor TFT2 is turned on and controlled to operate in the saturation region; S2: In the second time period, the photoelectric conversion element PIN turns on the first thin film transistor TFT1, and the second thin film transistor TFT2 pulls up the voltage of the first electrode D1 of the first thin film transistor TFT1, so that the first thin film transistor TFT1 continues to work in the saturation region. S3: Read the data signal via the second electrode D2 of the second thin-film transistor TFT1. The data signal is used to characterize the intensity of the light signal received by the photoelectric conversion element PIN.

[0209] In this embodiment, a gate line GL connects to the gate of the second thin-film transistor TFT2 in the pixel circuit of a row of pixels. In actual driving, the pixel circuit can be turned on row by row. For example, if there are N rows of pixel circuits and N gate lines GL, a gate turn-on voltage can be applied to each gate line GL row by row, thereby turning on the pixel circuit row by row.

[0210] In this embodiment, during the first time period, the second thin-film transistor TFT2 of the row pixel circuit can be turned on. At this time, a power supply voltage can be applied to the power signal line electrically connected to the first electrode S2 of the second thin-film transistor TFT2, thereby making the second thin-film transistor TFT2 work in the saturation region.

[0211] As mentioned above, when operating in the saturation region, the VDD of the second thin-film transistor TFT2 is greater than or equal to Vg2 - Vth2.

[0212] In this embodiment, during the second time period, after the second thin-film transistor TFT2 is turned on, the first thin-film transistor TFT1 is turned on by the photoelectric conversion element PIN, thus connecting the first thin-film transistor TFT1 and the second thin-film transistor TFT2 in series. Since the second terminal S1 of the first thin-film transistor TFT1 is grounded, the voltage of the first terminal D1 of the first thin-film transistor TFT1 is pulled down. However, since the first thin-film transistor TFT1 and the second thin-film transistor TFT2 are connected in series, the voltage of the first terminal D1 of the first thin-film transistor TFT1 is pulled up by the voltage of the first terminal S2 of the second thin-film transistor TFT2, so that the voltage of the first terminal D1 of the first thin-film transistor TFT1 and the voltage of the first terminal S2 of the second thin-film transistor TFT2 can be the same, thus making Vd1=Vs2=Vg2-Vth, where Vd1 is greater than the difference between the gate voltage and the threshold voltage of the first thin-film transistor TFT1, thereby allowing the first thin-film transistor TFT1 to always operate in the saturation region.

[0213] As mentioned above, the first thin-film transistor TFT1 can always operate in the saturation region, which allows for a larger increase in the slope of Ids of the first thin-film transistor TFT1, thereby realizing the amplification of the electrical signal detected by the photoelectric conversion element PIN inside the first thin-film transistor TFT1.

[0214] In this embodiment, when the first thin-film transistor TFT1 is operating in the saturation region, the data signal can be read through the first electrode D1 of the first thin-film transistor TFT1. That is, the data line DL of the flat panel detection backplane can be electrically connected to the first electrode D1 of the first thin-film transistor TFT1 to read the data signal.

[0215] In some examples, the power signal line can be multiplexed as the data line DL, so that the output data signal can be read through the power signal line.

[0216] In this example, the power supply voltage can be input to the power signal line in the first time period, and then the data output by the power signal line can be read in the second time period.

[0217] After reading the data signal, the system can enter a reset phase. During the reset phase, the reset transistor can be activated, which can reset the gate voltage of the first thin-film transistor to the reference potential.

[0218] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. The same or similar parts between the various embodiments can be referred to each other.

[0219] Finally, it should be noted that in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0220] The pixel circuit, flat panel detection backplane, data reading method, and flat panel detection device provided in this disclosure have been described in detail above. Specific examples have been used to illustrate the principles and implementation methods of this disclosure. The descriptions of the above embodiments are only for the purpose of helping to understand the method and core ideas of this disclosure. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of this disclosure. Therefore, the content of this specification should not be construed as a limitation of this disclosure.

[0221] Other embodiments of this disclosure will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This disclosure is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this disclosure are indicated by the following claims.

[0222] It should be understood that this disclosure is not limited to the precise structures described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of this disclosure is limited only by the appended claims.

[0223] The terms "an embodiment," "embodiment," or "one or more embodiments" as used herein mean that a particular feature, structure, or characteristic described in connection with an embodiment is included in at least one embodiment of this disclosure. Furthermore, please note that the examples of the phrase "in one embodiment" do not necessarily all refer to the same embodiment.

[0224] Numerous specific details are set forth in the specification provided herein. However, it will be understood that embodiments of this disclosure may be practiced without these specific details. In some instances, well-known methods, structures, and techniques have not been shown in detail so as not to obscure the understanding of this specification.

[0225] In the claims, any reference signs placed between parentheses should not be construed as limiting the claims. The word "comprising" does not exclude the presence of elements or steps not listed in the claims. The word "a" or "an" preceding an element does not exclude the presence of a plurality of such elements. This disclosure can be implemented by means of hardware comprising a plurality of different elements and by means of a suitably programmed computer. In a unit claim enumerating a plurality of means, several of these means may be embodied by the same item of hardware. The use of the words first, second, and third, etc., does not indicate any order. These words may be interpreted as names.

[0226] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this disclosure, and are not intended to limit them. Although this disclosure has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this disclosure.

Claims

1. A pixel circuit suitable for a flat panel detector backplane, characterized in that, The pixel circuit includes: A photoelectric conversion element is configured to convert optical signals into electrical signals; An amplifier circuit includes a first thin-film transistor and a second thin-film transistor connected in series. The gate of the first thin-film transistor is electrically connected to the photoelectric conversion element, the gate of the second thin-film transistor serves as the gate signal input terminal, and the second thin-film transistor is configured to drive the first thin-film transistor to operate in the saturation region when the first thin-film transistor is turned on.

2. The pixel circuit of the flat panel detection backplane according to claim 1, characterized in that, The first terminal of the first thin-film transistor is electrically connected to the first terminal of the second thin-film transistor, the second terminal of the first thin-film transistor is grounded, and the second terminal of the second thin-film transistor serves as a power signal input terminal. The signal output from the power signal input terminal is used to drive the second thin-film transistor to operate in the saturation region.

3. The pixel circuit of the flat panel detection backplane according to claim 1, characterized in that, The second thin-film transistor is also configured as a data signal output terminal of the pixel circuit.

4. The pixel circuit of the flat panel detection backplane according to claim 1, characterized in that, The pixel circuit further includes a reset circuit, which includes a reset transistor; wherein, the first terminal of the reset transistor is electrically connected to the gate of the first thin-film transistor, and the gate of the reset transistor serves as a reset signal terminal.

5. A flat panel detector backplate, characterized in that, It includes multiple pixels, each pixel including pixel circuitry; and, Substrate; Multiple gate lines are located on one side of the substrate; A pixel circuit layer, located on one side of the substrate, is provided with a photoelectric conversion element, a first thin-film transistor, and a second thin-film transistor in each pixel circuit; The gate of the first thin-film transistor is electrically connected to the photoelectric conversion element, and the gate of the second thin-film transistor is electrically connected to the gate line. The second thin-film transistor is configured to drive the first thin-film transistor to operate in the saturation region when the first thin-film transistor is turned on.

6. The flat panel detection backplate according to claim 5, characterized in that, The flat panel detector backplate also includes: The power signal line and the ground signal line are located on one side of the substrate; Wherein, the first electrode of the first thin-film transistor is electrically connected to the first electrode of the second thin-film transistor, the second electrode of the first thin-film transistor is electrically connected to the ground signal line, and the second electrode of the second thin-film transistor is electrically connected to the power signal line.

7. The flat panel detection backplate according to claim 6, characterized in that, The plurality of the pixel arrays are arranged in a row, and each of the gate lines is electrically connected to the pixel circuit of a row of pixels; The flat panel detection backplane includes multiple power signal lines, each of which is electrically connected to the pixel circuit of a column of pixels. The power signal lines are multiplexed as data lines for the flat panel detection backplane.

8. The flat panel detection backplate according to claim 5, characterized in that, The pixel circuit layer includes: A first metal patterned layer includes the gates of the first thin-film transistor and the second thin-film transistor; The second metal patterned layer includes the first thin-film transistor and the first and second electrodes of the second thin-film transistor; The active layer includes the channels of the first thin-film transistor and the second thin-film transistor; The photoelectric conversion element is electrically connected to the gate of the first thin-film transistor via a connecting electrode.

9. The flat panel detection backplate according to claim 8, characterized in that, The pixel circuit layer further includes: A first dielectric layer is located on the side of the first thin-film transistor and the second thin-film transistor that is away from the substrate; The photoelectric conversion element is located on the side of the first dielectric layer away from the substrate; The photoelectric conversion element includes a bottom electrode, a photoconductive material layer, and a top electrode stacked in the thickness direction of the substrate. The bottom electrode is electrically connected to the connecting electrode through a first via located in the first dielectric layer.

10. The flat panel detection backplate according to claim 9, characterized in that, The orthographic projection of the first via on the substrate does not overlap with the orthographic projection of the photoconductive material layer on the substrate.

11. The flat panel detection backplate according to claim 9, characterized in that, The orthographic projection of the photoelectric conversion element on the substrate overlaps with the orthographic projection of the first thin-film transistor on the substrate, and / or the orthographic projection of the photoelectric conversion element on the substrate overlaps with the orthographic projection of the second thin-film transistor on the substrate.

12. The flat panel detection backplate according to claim 9, characterized in that, The pixel circuit layer further includes: The second dielectric layer is located between the active layer and the first metal pattern layer, or between the active layer and the second metal pattern layer; The photoelectric conversion element includes a bottom electrode, a photoconductive material layer, and a top electrode stacked in the thickness direction of the substrate, wherein the bottom electrode is located in the second metal pattern layer; The bottom electrode is electrically connected to the connecting electrode through a second via located in the second dielectric layer, and the orthographic projection of the photoconductive material layer on the substrate does not overlap with the orthographic projections of the first thin-film transistor and the second thin-film transistor on the substrate.

13. The flat panel detection backplate according to claim 12, characterized in that, The orthographic projection of the photoconductive material layer on the substrate overlaps with the orthographic projection of the second via on the substrate.

14. The flat panel detection backplate according to claim 12, characterized in that, The orthographic projection of the photoconductive material layer on the substrate is located between the orthographic projections of the gate line and the connecting electrode on the substrate.

15. The flat panel detection backplate according to claim 9, characterized in that, The flat panel detection backplane also includes a power signal line, which is located in the second metal pattern layer; The power signal line is electrically connected to the second electrode of the second thin-film transistor, and the power signal line and the orthographic projection of the connecting electrode on the substrate do not overlap.

16. The flat panel detection backplate according to claim 4, characterized in that, The flat panel detector backplate also includes: A light-shielding layer is located on the side of the pixel circuit layer opposite to the substrate; Wherein, the orthographic projection of the light-shielding layer on the substrate overlaps with the orthographic projection of the channel of the first thin-film transistor and / or the second thin-film transistor on the substrate.

17. The flat panel detection backplate according to claim 16, characterized in that, The photoelectric conversion element includes a bottom electrode, a photoconductive material layer, and a top electrode stacked in the thickness direction of the substrate; The light-shielding layer is reused as the top electrode.

18. The flat panel detection backplate according to claim 5, characterized in that, The flat panel detection backplate also includes a reset signal line located on one side of the substrate; The pixel circuit further includes a reset circuit, which includes a reset transistor; wherein the first terminal of the reset transistor is electrically connected to the gate of the first thin-film transistor, and the gate of the reset transistor is electrically connected to the reset signal line.

19. A flat panel detection device, characterized in that, It includes the flat panel detector backplate as described in any one of claims 5-18 and a scintillator layer located on one side of the flat panel detector backplate.

20. A data reading method, characterized in that, The data reading method is applied to the pixel circuit of any one of claims 1-4, or to the flat panel detection device of claim 19; wherein the data reading method includes: In the first time period, the second thin-film transistor is turned on and controlled to operate in the saturation region; During the second time period, the photoelectric conversion element turns on the first thin-film transistor, and the second thin-film transistor pulls up the voltage of the first electrode of the first thin-film transistor, so that the first thin-film transistor continues to operate in the saturation region; The data signal is read through the second electrode of the second thin-film transistor, and the data signal is used to characterize the intensity of the light signal received by the photoelectric conversion element.

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