Image sensor and method of forming the same

Abstract

The application discloses a forming method of an image sensor, which forms a gate structure of a complete image sensor circuit including NMOS tubes and PMOS tubes through a one-time gate doping process and one-time gate patterning, so as to simplify a preparation process and optimize circuit power consumption.

Description

Technical Field

[0001] This invention relates to a front image sensor and a method for forming the same. Background Technology

[0002] A CMOS image sensor (CIS) is a semiconductor device that converts optical images into electrical signals. A CIS consists of a photodiode (PD) for sensing light and logic circuitry for processing the sensed light into electrical signals.

[0003] The depletion problem of polysilicon gates is a key challenge in MOS devices. Traditional MOS devices use polysilicon as the gate material. However, due to the difficulty in maintaining uniform doping in polysilicon, when the carrier density in the gate material is low, a partial "depletion" phenomenon can occur in the channel region under the gate when a gate voltage is applied. This phenomenon may lead to excessively high threshold voltage, increased off-state leakage current, and even affect the turn-on current, thereby impacting chip performance and power consumption. Currently, polysilicon doping is usually achieved through source-drain re-doping self-aligned implantation. For FinFET devices, due to the certain height of the gate, self-aligned source-drain implantation may result in the bottom of the polysilicon not being effectively doped. Therefore, additional N+ and P+ doping of the polysilicon in NFETs and PFETs is required, which increases the number of process steps and cost. Summary of the Invention

[0004] Based on the problems existing in the prior art, this invention proposes a design and fabrication process for junctionless transistors, which is applied to the field of image sensors. This avoids the problem of polysilicon depletion, simplifies the polysilicon doping process, reduces manufacturing costs, improves logic circuit performance, and reduces circuit power consumption.

[0005] This invention provides a method for forming an image sensor, which forms a gate structure of a complete image sensor circuit including NMOS and PMOS transistors through a single gate doping process and a single gate patterning process, thereby simplifying the fabrication process and optimizing circuit power consumption.

[0006] In some embodiments, the ion doping of the NMOS and PMOS gate structures in the image sensor is formed by a single N-type ion implantation to simplify the fabrication process.

[0007] In some embodiments, the gate structures of the NMOS and PMOS transistors in the image sensor are formed in one step using N-type gate materials to simplify the fabrication process.

[0008] In some embodiments, the PMOS transistors in the image sensor use a core-shell structure defined by the doping type, and the channel cross-sectional area is appropriately adjusted to reduce the device turn-off current and reduce the static power consumption of the image sensor.

[0009] In some embodiments, the cross-sectional area of ​​the P-type channel of the PMOS transistor is adjusted by surrounding it with N-type doped ions, or the cross-sectional area of ​​the P-type channel of the PMOS transistor is adjusted by surrounding it with N-type doped ions.

[0010] In some embodiments, the NMOS transistor includes an N-type fin transistor or an N-type gate-all-around transistor; the PMOS includes a junctionless P-type fin transistor or a P-type gate-all-around transistor in which the channel region and the source / drain region are doped with the same ions.

[0011] In some embodiments, the process of forming the NMOS transistor and the PMOS transistor includes: providing a substrate; forming the well region of the NMOS transistor and the well region of the PMOS transistor respectively by ion implantation; forming the channel structure of the NMOS transistor and the channel structure of the PMOS transistor by etching the substrate; wherein the channel portion controlled by the gate is a fin structure or a suspended structure that does not contact the underlying substrate; forming a polysilicon layer on the substrate and performing N-type ion doping on it once; and etching the polysilicon layer by gate patterning once to form a gate structure including the NMOS transistor and the PMOS transistor.

[0012] In some embodiments, after forming the channel structure, the method further includes: P-type ion doping of the channel structure of the PMOS transistor; or forming P-type ion doping on the surface of the channel structure of the PMOS transistor by means of BSG covering and heat treatment, so that the P-type channel of the PMOS transistor surrounds N-type doped ions to form a core-shell structure; or after P-type ion doping of the channel structure of the PMOS transistor, forming an N-type doped region on the surface by means of PSG covering and heat treatment, so that the P-type channel of the PMOS transistor is surrounded by N-type doped ions to form a core-shell structure.

[0013] In some embodiments, after etching the polysilicon layer through a single gate patterning to form the gate structure of a complete image sensor circuit including an NMOS transistor and a PMOS transistor, the method further includes: forming a first sidewall on the sidewalls of the polysilicon gate structure of the NMOS transistor and the polysilicon gate structure of the PMOS transistor; performing N-type LDD implantation on the polysilicon gate structure of the NMOS transistor, and then performing P-type LDD implantation on the polysilicon gate of the PMOS transistor; or performing P-type LDD implantation on the polysilicon gate structure of the PMOS transistor, and then performing N-type LDD implantation on the polysilicon gate structure of the NMOS transistor.

[0014] In some embodiments, the image sensor is a non-stacked single-chip image sensor.

[0015] The present invention also provides an image sensor formed by the above method.

[0016] Compared with existing technologies, the present invention simplifies the process steps, improves the performance of logic circuits, and reduces the power consumption of image sensors by injecting the gates of NMOS and PMOS transistors through a single polysilicon doping process. Attached Figure Description

[0017] Figure 1 This is a functional block diagram of an image sensor as an exemplary embodiment of the present invention.

[0018] Figures 2 to 23 This is a cross-sectional schematic diagram of the formation process of an image sensor, which is an exemplary embodiment of the present invention. Detailed Implementation

[0019] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are merely some examples or embodiments of the present invention. For those skilled in the art, these drawings can be applied to other similar scenarios without creative effort. Unless obvious from the context or otherwise specified, the same reference numerals in the drawings represent the same structures or operations.

[0020] Figure 1 This is a functional block diagram of an image sensor 100 as an exemplary embodiment of the present invention.

[0021] The image sensor 100 includes a pixel array 105, a readout circuit 110, a functional logic 115, and a control circuit 120.

[0022] The pixel array 105 includes a two-dimensional (“2D”) array of multiple image sensor pixels 125 (e.g., pixels P1, P2…Pn). As shown, each pixel is arranged in rows (e.g., rows R1 to Ry) and columns (e.g., columns C1 to Cx) to acquire image data of a person, place, or object, which can then be used to render a 2D image of the person, place, or object.

[0023] After each pixel has acquired its image data or image charge, the image data is read out by readout circuit 110 and transmitted to functional logic 115. Readout circuit 110 may include amplifier circuitry, analog-to-digital converter (“ADC”), etc. Functional logic 115 may simply store or process the image data. In one embodiment, readout circuit 110 may read out one row of image data at a time along readout column line 102, or may utilize other techniques (not shown) to read out the image data, such as column / row readout, serial readout, or simultaneous parallel readout of all pixels.

[0024] Control circuitry 120 is connected to pixel array 105 to control pixel array 105. For example, control circuitry 120 may generate a shutter signal for controlling image acquisition. In one embodiment, the shutter signal may be a global shutter signal, enabling all pixels within pixel array 105 to simultaneously capture their respective image data during a single acquisition window. In other embodiments, the shutter signal may be a rolling shutter signal, whereby each row, column, or group of pixels is sequentially enabled during successive acquisition windows.

[0025] This invention proposes a method for forming an image sensor, characterized by forming a gate structure for a complete image sensor circuit, including NMOS and PMOS transistors, through a single gate doping process and a single gate patterning process, thereby simplifying the fabrication process and optimizing circuit power consumption.

[0026] In one embodiment, the ion doping of the gate structures of the NMOS and PMOS transistors in the image sensor is formed by a single N-type ion implantation to simplify the fabrication process.

[0027] In one embodiment, the gate structures of the NMOS and PMOS transistors in the image sensor are formed in one step using N-type gate materials to simplify the fabrication process.

[0028] In one embodiment, the PMOS transistor in the image sensor uses a core-shell structure defined by the doping type, and the channel cross-sectional area is appropriately adjusted to reduce the device turn-off current and reduce the static power consumption of the image sensor.

[0029] In one embodiment, the cross-sectional area of ​​the P-type channel of the PMOS transistor is adjusted by surrounding it with N-type doped ions, or the cross-sectional area of ​​the P-type channel of the PMOS transistor is adjusted by surrounding it with N-type doped ions.

[0030] In one embodiment, the NMOS transistor includes an N-type fin transistor or an N-type gate-all-around transistor; the PMOS includes a junctionless P-type fin transistor or a P-type gate-all-around transistor in which the channel region and the source / drain region are doped with the same ions.

[0031] The embodiments of the present invention will be described below with reference to the accompanying drawings. Figures 2 to 21 This is a cross-sectional schematic diagram along the direction perpendicular to the conductive channel during the formation process of an image sensor according to an embodiment of the present invention. Figure 22 and Figure 23 This is a cross-sectional schematic diagram along the conductive channel direction during the formation process of an image sensor according to an embodiment of the present invention.

[0032] refer to Figure 2 A substrate 20 is provided, and a hard mask 201 is formed on the substrate 20. The substrate 20 can be a P-type substrate.

[0033] Before forming the hard mask 201, the well regions of the NMOS transistor and the PMOS transistor can be formed by ion implantation.

[0034] refer to Figure 3 A patterned hard mask layer 201a is formed on the substrate 20.

[0035] refer to Figure 4 The substrate 20 is etched to form trenches 21, and to form channel structures 20a and 20b for the NMOS transistor and the PMOS transistor, respectively. The channel portion controlled by the gate is either a fin structure or a suspended structure that does not contact the underlying substrate. In this embodiment, a fin structure is used as an example for explanation.

[0036] refer to Figure 5 The trench 21 is filled with medium material 22 to form a trench isolation structure.

[0037] refer to Figure 6 The dielectric material 22 in the trench isolation structure is etched so that the upper surface of the dielectric material 22 is lower than the upper surface of the substrate 20 (or the upper surface corresponding to the active region).

[0038] refer to Figure 7 Remove the hard mask layer 201 above the channel structure 20a of the NMOS transistor and the channel structure 20b of the PMOS transistor.

[0039] refer to Figure 8A dielectric layer 23 is formed on the surface of the channel structure 20a of the NMOS transistor and the channel structure 20b of the PMOS transistor.

[0040] refer to Figure 9 A barrier layer 24a is formed on the channel structure 20b of the PMOS transistor, and the channel structure 20a of the NMOS transistor is doped to form a doped region 20c.

[0041] In one embodiment, reference Figure 10 (a) A barrier layer 24a is formed on the channel structure 20a of the NMOS transistor, and the channel structure 20b of the PMOS transistor is doped to form a doped region 20d.

[0042] In one embodiment, reference Figure 10 (b) After P-type ion doping to form doped region 20d of PMOS transistor channel structure, N-type doped region 20e is formed on the surface by PSG covering and heat treatment, so that the periphery of P-type channel of PMOS transistor is surrounded by N-type doped ions, forming core-shell structure.

[0043] In one embodiment, reference Figure 10 (c) After N-type ion doping is performed inside the channel structure of the PMOS transistor to form a doped region 20f, P-type ion doping 20g is formed on the surface of the channel structure of the PMOS transistor by BSG covering and heat treatment, so that the P-type channel of the PMOS transistor surrounds the N-type doped ions 20f, forming a core-shell structure.

[0044] In this embodiment, the following process is as follows: Figure 10 (a) will be used as an example for explanation.

[0045] refer to Figure 11 Remove the dielectric layer 23 from the surface of the channel structure 20a of the NMOS transistor and the channel structure 20b of the PMOS transistor.

[0046] refer to Figure 12 A gate dielectric layer 24 is formed on the surface of the channel structure 20a of the NMOS transistor and the channel structure 20b of the PMOS transistor.

[0047] refer to Figure 13 A polycrystalline silicon layer 25 is formed on the substrate 20 and then subjected to N-type ion doping.

[0048] refer to Figure 14 A patterned barrier layer 26 is formed on the polysilicon layer 25.

[0049] refer to Figure 15By patterning the gate once, the polysilicon layer 25 is etched to form the gate structure 25a of the NMOS transistor and the gate structure 25b of the PMOS transistor, thereby forming the gate structure of a complete image sensor circuit including the NMOS transistor and the PMOS transistor.

[0050] refer to Figure 16 First sidewalls 27a / 27b are formed on the sidewalls of the polysilicon gate structure 25a of the NMOS transistor and the polysilicon gate structure 25b of the PMOS transistor.

[0051] refer to Figure 17 A barrier layer 28a is formed in the polysilicon gate structure 25b region of the PMOS transistor, and N-type LDD implantation is performed on the polysilicon gate structure 25a of the NMOS transistor to form an LDD region 31a (see reference). Figure 22 In this embodiment, an N-type halo implantation can also be performed on the polysilicon gate structure 25a of the NMOS transistor to form a halo region 32a (see reference). Figure 22 ).

[0052] refer to Figure 18 A barrier layer 28b is formed in the polysilicon gate structure 25a region of the NMOS transistor, and P-type LDD implantation is performed on the polysilicon gate structure 25b of the PMOS transistor to form an LDD region 31b (see reference). Figure 23 ).

[0053] In another embodiment, P-type LDD implantation can be performed on the polysilicon gate structure 25b of the PMOS transistor, and then N-type LDD implantation can be performed on the polysilicon gate structure 25 of the NMOS transistor.

[0054] refer to Figure 19 A second sidewall 29a / 29b is formed on the sidewalls of the polysilicon gate structure 25a of the NMOS transistor and the polysilicon gate structure 25b of the PMOS transistor.

[0055] refer to Figure 20 A barrier layer 30a is formed in the polysilicon gate structure 25b region of the PMOS transistor, and an N-type source / drain 33a is formed on the polysilicon gate structure 25a of the NMOS transistor (see reference). Figure 22 )injection.

[0056] refer to Figure 21 A barrier layer 30b is formed in the polysilicon gate structure 25a region of the NMOS transistor, and a P-type source / drain 33b is formed in the polysilicon gate structure 25b of the PMOS transistor (see reference). Figure 23 )injection.

[0057] It will be apparent to those skilled in the art that the present invention is not limited to the details of the exemplary embodiments described above, and that the invention can be implemented in other specific forms without departing from the spirit or essential characteristics of the invention. Therefore, the embodiments should be considered exemplary and not restrictive in any way. Furthermore, it is clear that the word "comprising" does not exclude other elements and steps, and the word "a" does not exclude a plural. Multiple elements recited in the apparatus claims may also be implemented by a single element. The terms "first," "second," etc., are used to denote names and do not indicate any particular order.

Claims

1. A method for forming an image sensor, characterized in that, By employing a single gate doping process and a single gate patterning process, a complete gate structure for an image sensor circuit, including both NMOS and PMOS transistors, is formed, thereby simplifying the fabrication process and optimizing circuit power consumption.

2. The method as described in claim 1, characterized in that, The ion doping of the NMOS and PMOS gate structures in the image sensor is formed by a single N-type ion implantation to simplify the fabrication process.

3. The method as described in claim 1, characterized in that, The NMOS and PMOS transistors in the image sensor have gate structures formed in one step using N-type gate material to simplify the fabrication process.

4. The method as described in claim 1, characterized in that, The PMOS transistors in the image sensor use a core-shell structure defined by the doping type, and the channel cross-sectional area is appropriately adjusted to reduce the device turn-off current and the static power consumption of the image sensor.

5. The method as described in claim 4, characterized in that, The cross-sectional area of ​​the P-type channel of the PMOS transistor is adjusted by surrounding it with N-type doped ions, or the cross-sectional area of ​​the P-type channel of the PMOS transistor is adjusted by surrounding it with N-type doped ions.

6. The method as described in claim 1, characterized in that, The NMOS transistor includes an N-type fin transistor or an N-type gate-all-around transistor; the PMOS includes a junctionless P-type fin transistor or a P-type gate-all-around transistor in which the channel region and the source / drain region are doped with the same ions.

7. The method as described in claim 6, characterized in that, The process of forming the NMOS transistor and the PMOS transistor includes: Provide substrate; The well regions of the NMOS transistor and the PMOS transistor are formed by ion implantation. The NMOS transistor's channel structure and the PMOS transistor's channel structure are formed by etching the substrate; wherein the channel portion controlled by the gate is a fin structure or a suspended structure that does not contact the underlying substrate. A polycrystalline silicon layer is formed on the substrate and then subjected to N-type ion doping. By patterning the gate once, the polysilicon layer is etched to form the gate structure of a complete image sensor circuit, including NMOS and PMOS transistors.

8. The method as described in claim 7, characterized in that, After forming the channel structure, the following is also included: The channel structure of the PMOS transistor is p-type ion doped; or The channel structure of the PMOS transistor is covered with BSG and then heat-treated to form P-type ion doping on the surface, so that the P-type channel of the PMOS transistor surrounds the N-type dopant ions, forming a core-shell structure; or After P-type ion doping of the channel structure of the PMOS transistor, an N-type doped region is formed on the surface by PSG covering and heat treatment, so that the P-type channel of the PMOS transistor is surrounded by N-type doped ions, forming a core-shell structure.

9. The method as described in claim 7, characterized in that, After etching the polysilicon layer through a single gate patterning process to form the gate structure of a complete image sensor circuit including NMOS and PMOS transistors, the process further includes: A first sidewall is formed on the sidewall of the polysilicon gate structure of the NMOS transistor and the polysilicon gate structure of the PMOS transistor. The polysilicon gate structure of the NMOS transistor is subjected to N-type LDD implantation, and then the polysilicon gate of the PMOS transistor is subjected to P-type LDD implantation; or The polysilicon gate structure of the PMOS transistor is subjected to P-type LDD implantation, and the polysilicon gate structure of the NMOS transistor is subjected to N-type LDD implantation.

10. The method as described in claim 1, characterized in that, The image sensor is a non-stacked single-chip image sensor.

11. An image sensor, characterized in that, Formed by any of the methods described in claims 1 to 10.

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