Semiconductor device and method of forming

Abstract

The application provides a semiconductor device and a forming method, wherein the semiconductor device comprises: a first substrate, the first substrate comprising a plurality of pixel regions and a floating region, the first substrate comprising opposite first and second surfaces; a single photon avalanche diode unit in the first substrate at the pixel region, the single photon avalanche diode unit being arranged in the first substrate from the second surface; a deep trench structure in the first substrate, the deep trench structure being located between adjacent pixel regions and between the pixel region and the floating region; a dielectric layer on the first surface, the dielectric layer being formed with a first via and a second via, a bottom of the first via exposing a top surface of the deep trench structure, and a bottom of the second via extending into the first substrate of the floating region; and a conductive layer in the first via and the second via; the application reduces the influence of the dark count rate of the SPAD and improves the performance of the SPAD.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing technology, and in particular to a semiconductor device and a method for forming it. Background Technology

[0002] Time-of-flight (TOF) technology is a method for distance measurement that utilizes the time difference (d-TOF) or phase difference (i-TOF) between the transmission and reception of optical signals. The core pixel photosensitive unit of d-TOF is the single-photon avalanche diode (SPAD), which is a diode operating in the reverse avalanche breakdown region. It can generate photogenerated carriers in the semiconductor through photons. When the photogenerated carriers drift into the strong electric field in the depletion region of the reverse-biased PN junction of the single-photon avalanche diode, it will trigger avalanche breakdown and generate a large current signal, thereby realizing the detection of single-photon signals.

[0003] In practical applications, single-photon avalanche diodes are typically large-area arrays arranged in close proximity. To avoid crosstalk between different single-photon avalanche diodes in terms of optical and photoelectric signals, full-depth isolation is required between them. Typically, silicon-based single-photon avalanche diodes use deep trench isolation (DTI) structures for isolation. After etching, the deep trenches of the deep trench structure are filled with materials for optical and electrical isolation. The filling material generally consists of an electrical insulating material layer on the surface of the deep trench structure and an internal filling material layer.

[0004] The working principle of a SPAD photodetector array is as follows: A laser emits a laser beam, which shines on an object and is reflected. When the reflected laser beam is detected by the SPAD photodetector array, the light signal enters the device from the back of the device through a lens. Photons trigger an avalanche effect at the junction of P+ and DNW, and the device generates an avalanche current, converting the light signal into an electrical signal. The proportion of SPAD miscounts caused by sources other than those emitted by the laser to the total SPAD count is called the dark count rate.

[0005] Currently, thermal noise caused by changes in external temperature and plasma damage introduced during the process can affect the dark count rate of SPADs. Therefore, how to reduce the impact of plasma etching and growth steps on the dark count rate of SPADs is a technical problem that urgently needs to be solved. Summary of the Invention

[0006] The technical problem solved by this invention is to provide a semiconductor device and a method for forming it, which reduces the impact on the dark count rate of SPAD and improves the performance of SPAD.

[0007] To address the aforementioned problems, the present invention provides a semiconductor device comprising: a first substrate, the first substrate including a plurality of pixel regions and a floating region, the first substrate including a first surface and a second surface opposite to each other; a single-photon avalanche diode unit located within the first substrate in the pixel regions, the single-photon avalanche diode unit being disposed within the first substrate from the second surface; a deep trench structure located within the first substrate, the deep trench structure being located between adjacent pixel regions and between the pixel regions and the floating region; a dielectric layer located on the first surface, the dielectric layer forming a first via and a second via, the bottom of the first via exposing the top surface of the deep trench structure, the bottom of the second via extending into the first substrate of the floating region; and a conductive layer located within the first via and the second via.

[0008] Optionally, the conductive layer may be made of aluminum.

[0009] Optionally, the deep trench structure includes a deep trench and a metal filler filling the deep trench, the metal filler being made of tungsten.

[0010] Optionally, the single-photon avalanche diode unit includes a doped layer disposed within the first substrate, the doped layer having a first conductivity type; a deep well located within the first substrate and surrounding the doped layer, the deep well having a second conductivity type, the first conductivity type being the opposite of the second conductivity type; and a heavily doped layer located within the deep well, wherein the deep well separates the doped layer and the heavily doped layer.

[0011] Optionally, it also includes a scattering structure located on the first surface of the pixel region.

[0012] Optionally, it also includes: a first interconnect structure located on the second surface, the first interconnect structure forming an electrical connection with the single-photon avalanche diode unit.

[0013] Optionally, it also includes a second substrate having a device structure on the second substrate, wherein a second interconnect structure is electrically connected to the device structure, the first substrate is bonded to the second substrate, and the first interconnect structure and the second interconnect structure are electrically connected.

[0014] Accordingly, the present invention also provides a method for forming a semiconductor device, comprising: providing a first substrate, the first substrate including a plurality of pixel regions and floating regions, the first substrate including a first surface and a second surface opposite to each other; forming a single-photon avalanche diode cell in the first substrate of the pixel regions from the second surface; forming a deep trench structure in the first substrate from the first surface to the second surface, the deep trench structure being located between adjacent pixel regions and between the pixel regions and the floating regions; forming an initial dielectric layer on the surface of the first surface and the deep trench structure; etching the initial dielectric layer to form a dielectric layer having a first via and a second via in the dielectric layer, the bottom of the first via exposing the top surface of the deep trench structure, and the bottom of the second via extending into the first substrate of the floating regions; and forming a conductive layer in the first via and the second via.

[0015] Optionally, before forming the deep trench structure, the method further includes: forming a first interconnect structure on the second surface, wherein the first interconnect structure is electrically connected to the single-photon avalanche diode unit.

[0016] Optionally, before forming the deep trench structure, the method further includes: providing a second substrate having a device structure on the second substrate; forming an electrically connected second interconnect structure on the surface of the device structure; bonding the first substrate to the second substrate; and electrically connecting the first interconnect structure to the second interconnect structure.

[0017] Optionally, after bonding the first substrate and the second substrate, the deep trench structure is formed. The method for forming the deep trench structure includes: etching the first substrate between adjacent pixel areas and the first substrate between the pixel area and the floating area from the first surface to the second surface, forming a plurality of deep trenches in the first substrate; filling the deep trenches with a metal filler; and planarizing the metal filler.

[0018] Optionally, it also includes forming a scattering structure on the first surface of the pixel region.

[0019] Optionally, the method for forming the scattering structure includes: etching the first surface of the pixel area to form a plurality of grooves on the first surface; forming a passivation layer on the sidewall of the grooves to form the scattering structure, wherein the passivation layer further extends to the sidewall of the deep trench and the first surface.

[0020] Optionally, the conductive layer material includes aluminum.

[0021] Optionally, the material of the metal filler may include tungsten.

[0022] Compared with the prior art, the technical solution of the present invention has the following advantages:

[0023] In the semiconductor device formation method of the present invention, a first substrate includes a first surface and a second surface opposite to each other. The first substrate includes multiple pixel regions and floating regions. After forming a single-photon avalanche diode unit in the first substrate of the pixel region from the second surface, a deep trench structure is directly formed in the first substrate from the first surface to the second surface. The deep trench structure is located between adjacent pixel regions and between pixel regions and floating regions. Subsequently, an initial dielectric layer is formed on the surface of the first surface and the deep trench structure. The initial dielectric layer is etched to form a dielectric layer having a first via and a second via. The bottom of the first via exposes the deep trench structure. The top surface of the trench structure and the bottom of the second via extend into the first substrate of the floating region; a conductive layer is formed in the first and second vias; on the one hand, after forming the single-photon avalanche diode unit, a deep trench structure is formed in the first substrate, so that the first substrate is protected by the deep trench structure, thereby avoiding damage to the first substrate caused by plasma bombardment growth or etching steps, thus reducing the impact on the dark count rate of the SPAD; on the other hand, the first and second vias are formed in the same photomask, and the conductive layer is filled in the first and second vias to bring out the pixel area and the floating region, reducing the photomask, simplifying the steps, and saving costs. Attached Figure Description

[0024] Figures 1 to 6 This is a schematic diagram illustrating the formation of a semiconductor device in one embodiment;

[0025] Figures 7 to 10 This is a schematic diagram illustrating the formation of a semiconductor device in one embodiment of the present invention. Detailed Implementation

[0026] As described in the background section, existing SPADs introduce plasma damage during their formation process, thus affecting the SPAD's dark count rate. (See details...) Figures 1 to 6 Analysis.

[0027] Please refer to the following first. Figure 1The first substrate 100 includes multiple pixel regions I and floating regions II. The first substrate 100 includes a first surface 100a and a second surface 100b opposite to each other. A single-photon avalanche diode unit (not shown) is formed in the pixel region I from the second surface 100b. A first interconnect structure 101 is formed on the second surface 100b, and the first interconnect structure 101 is electrically connected to the single-photon avalanche diode unit. A second substrate 102 has a second interconnect structure 103 on it. The first substrate 100 and the second substrate 102 are bonded together, and the first interconnect structure 101 and the second interconnect structure 103 are electrically connected. The first substrate 100 is etched from the first surface 100a to the second surface 100b to form multiple deep trenches 104 in the first substrate 100. The deep trenches 104 are formed between adjacent pixel regions I and between the pixel region I and the floating region II.

[0028] Please refer to Figure 2 An oxide layer 105 is formed on the first surface using a plasma etching process, and the oxide layer 105 is planarized.

[0029] Please refer to Figure 3 The oxide layer 105 is etched using a plasma etching process to expose the deep trench 104, while a portion of the first substrate 100 in the floating region II is etched away, forming a first groove 106 in the first substrate 100 in the floating region II.

[0030] Please refer to Figure 4 A tungsten layer 107 is filled in the deep trench 104 and the first groove 106, and after the tungsten layer 107 is planarized, a dielectric layer 108 is formed on the first surface 100a and the surface of the tungsten layer 107.

[0031] Please refer to Figure 5 The dielectric layer 108 is etched to form a plurality of through holes 109 in the dielectric layer 108, and the bottom of the through holes 109 exposes the surface of the tungsten layer 107.

[0032] Please refer to Figure 6 An aluminum layer 110 is filled inside the through hole 109.

[0033] The inventors discovered that after the deep trenches are formed, the surface of the first substrate is exposed. During the process of forming the oxide layer using plasma and etching the oxide layer using plasma, the plasma will damage the surface of the first substrate. This damage affects the dark count rate of the SPAD and limits the use of the SPAD to some extent.

[0034] The inventors discovered that after forming a single-photon avalanche diode unit on the second side within the first substrate of the pixel area, a deep trench structure is directly formed from the first side to the second side within the first substrate. This deep trench structure is located between adjacent pixel areas and between the pixel area and the floating area. Subsequently, a dielectric layer is formed on the surface of the first side and the deep trench structure. The dielectric layer is then etched, forming multiple vias within it. The vias in the pixel area expose the surface of the deep trench structure, while the vias in the floating area expose the first substrate and extend their bottoms into a portion of the first substrate. On one hand, forming the deep trench structure within the first substrate immediately after forming the single-photon avalanche diode unit protects the first substrate, preventing damage caused by plasma bombardment during growth or etching, thus reducing the impact on the SPAD's dark count rate. On the other hand, forming multiple vias within the same photomask and filling them with a conductive layer to bring out the pixel area and floating area is a simple and cost-effective method.

[0035] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0036] First, please refer to Figure 7 A first substrate 200 is provided, the first substrate 200 includes a plurality of pixel regions I and floating regions II, and the first substrate 200 includes opposing first surfaces 207 and second surfaces 206.

[0037] In this embodiment, the material of the first substrate 200 is silicon.

[0038] In other embodiments, the material of the first substrate 200 may also be silicon, germanium, germanium, or other materials that can be used as substrates for semiconductor devices.

[0039] In this embodiment, the floating area II is electrically connected to ground.

[0040] exist Figure 7 Only one pixel area I is shown in the image.

[0041] Please continue to refer to this. Figure 7 A single-photon avalanche diode unit 201 is formed from the second surface 206 within the first substrate 200 of the pixel region I.

[0042] In this embodiment, the single-photon avalanche diode unit 201 includes a doped layer (not marked in the figure) disposed within the first substrate 200, the doped layer (not marked in the figure) having a first conductivity type; a deep well (not marked in the figure) located within the first substrate 200 and surrounding the doped layer, the deep well having a second conductivity type, the first conductivity type being the opposite of the second conductivity type; and a heavily doped layer (not marked in the figure) located within the deep well, wherein the deep well separates the doped layer and the heavily doped layer, and a multiplication junction is formed at the interface between the first substrate 200 and the deep well (not marked in the figure).

[0043] During operation, the single-photon avalanche diode unit 201 is reverse biased above its breakdown voltage, and incident light strikes the SPAD semiconductor device from the first surface 207 to generate charge carriers. The charge carriers generated by the photons move to the multiplication junction region and trigger an avalanche current. The avalanche current amplifies the signals generated by the photons, making them easier to detect.

[0044] In this embodiment, the heavily doped layer serves as another electrode of the single-photon avalanche diode unit 201 and is connected to the first interconnect structure.

[0045] Please continue to refer to this. Figure 7 A first interconnect structure 202 is formed on the second surface 206, and the first interconnect structure 202 is electrically connected to the single-photon avalanche diode unit 201.

[0046] In this embodiment, the heavily doped layer serves as another electrode of the single-photon avalanche diode unit 201 and is connected to the first interconnect structure 202.

[0047] In this embodiment, the first interconnect structure 202 includes multiple stacked first interlayer dielectric layers 203 located on the second surface 206, each of the first interlayer dielectric layers 203 having a first metal layer 204, and the first metal layers 204 in adjacent first interlayer dielectric layers 203 forming a connection.

[0048] Please continue to refer to this. Figure 7 A second substrate 300 is provided, on which a device structure (not shown) is provided; a second interconnect structure 301 electrically connected is formed on the surface of the device structure, and the first substrate 200 and the second substrate 300 are bonded together, and the first interconnect structure 202 and the second interconnect structure 301 are electrically connected.

[0049] In this embodiment, the material of the second substrate 300 is silicon.

[0050] In this embodiment, the device structure includes a CMOS device.

[0051] In some embodiments, the device structure may also be a Fin-FET device.

[0052] In this embodiment, a second interconnect structure 301 electrically connected to the device structure is formed thereon. The second interconnect structure 301 includes multiple stacked second interlayer dielectric layers 302 formed on the surface of the device structure. Each second interlayer dielectric layer 302 has a second metal layer 303, and connections are formed between the second metal layers 303 in adjacent second interlayer dielectric layers 302.

[0053] Please continue to refer to this. Figure 7 The first substrate 200 between adjacent pixel regions I and between pixel region I and floating region II is etched from the first surface 207 to the second surface 206, forming a plurality of deep trenches 205 in the first substrate 200.

[0054] In this embodiment, the deep trench 205 penetrates through the first substrate 200.

[0055] In this embodiment, the process parameters for forming the deep trench 205 include using etching gases including SF6 and / or CF4, and inert gases including Ar, Ne, or Kr.

[0056] In this embodiment, a scattering structure 208 is formed on the first surface 207 of the pixel region I.

[0057] In this embodiment, the method for forming the scattering structure 208 includes: etching the first surface 207 of the pixel region I to form a plurality of grooves (not marked in the figure) on the first surface 207; forming a passivation layer (not marked in the figure) on the sidewall of the groove to form the scattering structure 208, wherein the passivation layer also extends to the sidewall of the deep trench 205 and the first surface 207.

[0058] In this embodiment, the scattering structure 208 scatters the incident light, thereby increasing the path length of the light through the semiconductor substrate and increasing the probability that the incident light is absorbed by the semiconductor. The deep trench 205 structure prevents the scattered light from reaching the adjacent single-photon avalanche diode unit 201 and causing crosstalk.

[0059] In this embodiment, the passivation layer may have a lower refractive index than the first substrate 200.

[0060] In this embodiment, the scattering structure 208 has inclined sidewalls (e.g., sidewalls that are not orthogonal to and parallel to the first surface 207). The scattering structure 208 may be pyramidal or may have a triangular cross-section extending along the longitudinal axis (e.g., Figure 7(As shown).

[0061] Of course, in some embodiments, the scattering structure 208 may have vertical sidewalls (orthogonal to the first surface 207).

[0062] Please refer to Figure 8 The deep trench 205 is filled with metal filler 209, and the metal filler 209 is flattened to form a deep trench structure 210.

[0063] In this embodiment, the material of the metal filler 209 includes tungsten.

[0064] In other embodiments, the material of the metal filler 209 may also include copper, etc.

[0065] In this embodiment, the deep trench structure 210 is used to achieve isolation between adjacent single-photon avalanche diode units 201 and isolation between pixel region I and floating region II.

[0066] In this embodiment, the sidewall of the deep trench 205 has a passivation layer, and the metal filler 209 fills the deep trench 205 completely.

[0067] In this embodiment, the metal filler 209 can be planarized using a chemical mechanical polishing process.

[0068] Please continue to refer to this. Figure 8 An initial dielectric layer 211 is formed on the surface of the first surface 207 and the deep trench structure 210.

[0069] In this embodiment, the material of the initial dielectric layer 211 is silicon oxide.

[0070] In some embodiments, the material of the initial dielectric layer 211 may also be silicon nitride, silicon carbide, etc.

[0071] In this embodiment, the process for forming the initial dielectric layer 211 is chemical vapor deposition.

[0072] In other embodiments, the process for forming the initial dielectric layer 211 may also be atomic layer deposition or physical vapor deposition.

[0073] Please refer to Figure 9 The initial dielectric layer 211 is etched to form a dielectric layer 211'. A first via 212 and a second via 212a are provided in the dielectric layer 211. The first via 212 is located in the pixel region I and exposes the surface of the deep trench structure 210 at its bottom. The second via 212a is located in the floating region II and extends to a portion of the first substrate 200 at its bottom.

[0074] In this embodiment, the first through hole 212 and the second through hole 212a formed in the same photomask reduce the use of photomasks, greatly save costs and reduce process difficulty, and improve the accuracy of pattern transmission.

[0075] Please refer to Figure 10 A conductive layer 213 is formed in the first through hole 212 and the second through hole 212a.

[0076] In this embodiment, the conductive layer 213 is made of aluminum.

[0077] In this embodiment, before forming the first via 212 and the second via 212a, a metal filler 209 is filled in the deep trench 205 to form a deep trench isolation structure 210. In this way, the metal filler 209 fills and protects the first substrate 200 exposed by the deep trench 205, thereby avoiding damage to the first substrate 200 caused by plasma bombardment growth or etching steps, thus reducing the impact on the dark count rate of the SPAD. On the other hand, the first via 212 and the second via 212a are formed in the same photomask, and a conductive layer 213 is filled in the first via 212 and the second via 212a to bring out the pixel area I and the floating area II. The steps are simple and cost-effective.

[0078] Accordingly, the present invention also provides a semiconductor device, including a first substrate 200, the first substrate 200 including a plurality of pixel regions I and floating regions II, the first substrate 200 including a first surface 207 and a second surface 206 opposite to each other; a single-photon avalanche diode unit 201 located in the first substrate 200 of the pixel region I, the single-photon avalanche diode unit 201 being disposed in the first substrate 200 from the second surface 206; and a deep trench structure 210 located in the first substrate 200, the deep trench structure... 210 is located between adjacent pixel regions I and between pixel region I and floating region II; a dielectric layer 211' is located on the first surface 207, wherein a first through-hole 212 and a second through-hole 212a are formed in the dielectric layer 211', the bottom of the first through-hole 212 exposes the top surface of the deep trench structure 210, and the bottom of the second through-hole 212a extends into the first substrate 200 of the floating region II; a conductive layer 213 is located in the first through-hole 212 and the second through-hole 212a.

[0079] In this embodiment, on the one hand, after forming the single-photon avalanche diode unit 201, a deep trench structure 210 is formed in the first substrate 200. In this way, the first substrate 200 is protected by the deep trench structure 210, thereby avoiding damage to the first substrate 200 caused by the plasma bombardment growth or etching steps, thus reducing the impact on the dark count rate of the SPAD. On the other hand, the first via 212 and the second via 212a are formed in the same photomask, and the conductive layer 213 is filled in the first via 212 and the second via 212a to bring out the pixel area I and the floating area II. The steps are simple and cost-effective.

[0080] In this embodiment, the conductive layer 213 is made of aluminum.

[0081] In this embodiment, the deep trench structure 210 includes a deep trench 205 and a metal filler 209 filled in the deep trench 205, wherein the material of the metal filler 209 includes tungsten.

[0082] In this embodiment, the single-photon avalanche diode unit 201 includes a doped layer disposed within the first substrate 200, the doped layer having a first conductivity type; a deep well located within the first substrate 200 and surrounding the doped layer, the deep well having a second conductivity type, the first conductivity type being the opposite of the second conductivity type; and a heavily doped layer located within the deep well, wherein the deep well separates the doped layer and the heavily doped layer.

[0083] In this embodiment, it also includes a scattering structure 208 located on the first surface 207 of the pixel region I.

[0084] In this embodiment, it further includes a first interconnect structure 202 located on the second surface 206, the first interconnect structure 202 being electrically connected to the single-photon avalanche diode unit 201.

[0085] In this embodiment, a second substrate 300 is also included, on which a device structure is provided. A second interconnect structure 301 is electrically connected to the device structure. The first substrate 200 is bonded to the second substrate 300, and the first interconnect structure 202 is electrically connected to the second interconnect structure 301.

[0086] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A semiconductor device, characterized in that, include: A first substrate, the first substrate including a plurality of pixel regions and floating regions, the first substrate including opposing first and second surfaces; A single-photon avalanche diode unit located within the first substrate of the pixel area, wherein the single-photon avalanche diode unit is disposed within the first substrate from the second surface; A deep trench structure located within the first substrate, the deep trench structure being located between adjacent pixel regions and between the pixel region and the floating region; A dielectric layer located on the first surface, wherein a first through-hole and a second through-hole are formed, the bottom of the first through-hole exposing the top surface of the deep trench structure, and the bottom of the second through-hole extending into the first substrate of the floating region; The conductive layer located within the first and second through holes.

2. The semiconductor device as claimed in claim 1, characterized in that, The conductive layer is made of aluminum.

3. The semiconductor device as described in claim 1, characterized in that, The deep trench structure includes a deep trench and a metal filler filling the deep trench, wherein the metal filler is made of tungsten.

4. The semiconductor device as claimed in claim 1, characterized in that, The single-photon avalanche diode unit includes a doped layer disposed in the first substrate, and the doped layer is of a first conductivity type; A deep well located within the first substrate and surrounding the doped layer, the deep well exhibiting a second conductivity type, the first conductivity type being the opposite of the second conductivity type; A heavily doped layer is located within the deep well, wherein the deep well separates the doped layer and the heavily doped layer.

5. The semiconductor device as claimed in claim 1, characterized in that, Also includes: The scattering structure located on the first surface of the pixel region.

6. The semiconductor device as claimed in claim 1, characterized in that, Also includes: The first interconnect structure is located on the second surface and is electrically connected to the single-photon avalanche diode unit.

7. The semiconductor device as claimed in claim 6, characterized in that, It also includes a second substrate having a device structure on the second substrate, on which a second interconnect structure is electrically connected, the first substrate being bonded to the second substrate, and the first interconnect structure being electrically connected to the second interconnect structure.

8. A method for forming a semiconductor device, characterized in that, include: A first substrate is provided, the first substrate including a plurality of pixel regions and floating regions, the first substrate including opposing first and second surfaces; A single-photon avalanche diode unit is formed from the second surface within the first substrate of the pixel area; A deep trench structure is formed in the first substrate from the first surface to the second surface, the deep trench structure being located between adjacent pixel areas and between the pixel area and the floating area; An initial dielectric layer is formed on the first surface and the surface of the deep trench structure; The initial dielectric layer is etched to form a dielectric layer having a first via and a second via. The bottom of the first via exposes the top surface of the deep trench structure, and the bottom of the second via extends into the first substrate of the floating region. A conductive layer is formed in the first through hole and the second through hole.

9. The method for forming a semiconductor device as described in claim 8, characterized in that, Before forming the deep trench structure, the method further includes: forming a first interconnect structure on the second surface, wherein the first interconnect structure is electrically connected to the single-photon avalanche diode unit.

10. The method for forming a semiconductor device as described in claim 9, characterized in that, Before forming the deep trench structure, the method further includes: providing a second substrate having a device structure on the second substrate; forming an electrically connected second interconnect structure on the surface of the device structure; bonding the first substrate to the second substrate; and electrically connecting the first interconnect structure to the second interconnect structure.

11. The method for forming a semiconductor device as claimed in claim 10, characterized in that, After bonding the first substrate to the second substrate, the deep trench structure is formed. The method for forming the deep trench structure includes: The first substrate between adjacent pixel areas and between the pixel area and the floating area are etched from the first surface to the second surface to form a plurality of deep trenches in the first substrate; The deep trench is filled with a metal filler. The metal filler is planarized.

12. The method for forming a semiconductor device as claimed in claim 11, further comprising: A scattering structure is formed on the first surface of the pixel region.

13. The method for forming a semiconductor device as described in claim 12, characterized in that, The method for forming the scattering structure includes: The first surface of the pixel area is etched to form a plurality of grooves on the first surface; A passivation layer is formed on the sidewall of the groove to form the scattering structure, wherein the passivation layer also extends to the sidewall of the deep trench and the first surface.

14. The method for forming a semiconductor device as described in claim 8, characterized in that, The conductive layer material includes aluminum.

15. The method for forming a semiconductor device as claimed in claim 11, characterized in that, The material of the metal filler includes tungsten.

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