Image sensor source-drain structure and preparation method thereof

Abstract

The application discloses a source / drain end structure of a pixel transistor of an image sensor, a preparation method and the image sensor. The source / drain end structure comprises a substrate, a gate structure, a source / drain end conductive connecting part, a source / drain end doped region and a contact plug. The side part of the gate structure is provided with an insulating isolation structure. The source / drain end conductive connecting part is electrically connected with a silicon region of the substrate, and at least part of the source / drain end conductive connecting part extends to the insulating isolation structure. The contact plug is arranged on the source / drain end conductive connecting part and is electrically connected with the silicon region through the source / drain end conductive connecting part. In the preparation process, the source / drain end conductive connecting part is doped and annealed, so that the doped impurities diffuse into the silicon region from the source / drain end conductive connecting part to form the source / drain end doped region. The application can relax the limitation of the contact plug on the landing point of the silicon region, reduce the spacing between the gate structures of the pixel transistors, save the pixel layout area, and is beneficial to forming a shallower source / drain junction and improving the pixel performance of the image sensor.

Description

Technical Field

[0001] This invention relates to the field of image sensors, and more particularly to an image sensor source / drain structure and its fabrication method. Background Technology

[0002] A CMOS image sensor (CIS) typically comprises a pixel array, readout circuitry, and peripheral control circuitry. Each pixel unit in the pixel array usually includes a photodiode and multiple pixel transistors, such as transfer transistors, reset transistors, source follower transistors, and row select transistors. The source / drain structure and contact method of the pixel transistors directly affect the pixel unit's layout area, device parasitic parameters, and the image sensor's imaging performance.

[0003] In the existing image sensor pixel transistor fabrication process, a polysilicon gate structure for the transistor is typically formed on a substrate first, followed by the formation of sidewalls on the sidewalls of the polysilicon gate structure. Then, the source / drain regions are heavily doped to form source / drain doped regions in the silicon substrate. Next, contact holes are formed above the source / drain doped regions, and conductive material is filled into the contact holes to form contact plugs. These contact plugs then directly contact the source / drain doped regions in the silicon substrate, thereby achieving electrical connection between the source / drain and the upper interconnect structure.

[0004] However, in the aforementioned traditional structure, since the contact plug needs to land directly on the silicon region and must be completely or substantially completely located within the source / drain silicon region to avoid short circuits between the contact plug and adjacent polysilicon gate structures, a sufficient process safety distance needs to be reserved between the contact plug and adjacent polysilicon gate structures. This safety distance is typically limited by factors such as contact hole size, contact hole overlay accuracy, sidewall width, and gate structure spacing. For the pixel area of ​​an image sensor, as pixel size continues to shrink, multiple pixel transistors and photodiodes need to be arranged within a limited pixel area. The aforementioned contact plug landing point limitations will occupy a large layout space, making it difficult to further reduce the distance between adjacent polysilicon gate structures, which is detrimental to reducing the pixel unit area and improving the pixel fill factor.

[0005] Furthermore, in existing processes, heavily doped source / drain regions are typically formed by directly implanting heavy doping ions into the silicon substrate followed by annealing. Since heavily doped ions penetrate directly through the surface oxide layer or related insulating layer into the silicon substrate, relatively deep source / drain junctions are easily formed. For image sensors, the junction depth, doping distribution, and junction leakage characteristics in the pixel region affect dark current, noise, charge transfer efficiency, and device reliability. Deeper source / drain junctions may increase the junction area or depth with the well region, thus adversely affecting the pixel performance of the image sensor.

[0006] Therefore, how to ensure reliable electrical connection between the source and drain terminals of pixel transistors, while relaxing the restrictions on the silicon region landing point of the contact plug, reducing the distance between polysilicon gate structures within the pixel region, and further improving the junction depth control of the source / drain doped regions, has become a technical problem that urgently needs to be solved in this field. Summary of the Invention

[0007] The purpose of this invention is to provide a source / drain structure for an image sensor pixel transistor, its fabrication method, and an image sensor, so as to at least solve the problem that in existing image sensor pixel transistors, the contact plugs need to be placed directly on the silicon region, resulting in a large process safety distance between the contact plugs and adjacent gate structures, thereby limiting the reduction of the pixel area layout; at the same time, it improves the junction depth control of the source / drain doped regions, reducing the adverse effects of deeper source / drain junctions on the pixel performance of the image sensor.

[0008] To achieve the above objectives, the present invention provides a source / drain structure for a pixel transistor of an image sensor. The source / drain structure includes a substrate, a gate structure, a source / drain conductive connection portion, a source / drain doped region, and a contact plug. The substrate includes a silicon region. The gate structure is disposed on the substrate, and an insulating isolation structure is disposed on the side of the gate structure. The source / drain conductive connection portion is disposed on one side of the gate structure, electrically connected to the silicon region, and at least a portion of the source / drain conductive connection portion extends onto the insulating isolation structure. The source / drain doped region is formed in the silicon region corresponding to the source / drain conductive connection portion. The contact plug is disposed on the source / drain conductive connection portion and electrically connected to the silicon region through the source / drain conductive connection portion. The source / drain conductive connection portion serves as an intermediate connection structure between the contact plug and the silicon region, and the source / drain doped region is formed at least partially by dopant impurities in the source / drain conductive connection portion diffusing into the silicon region.

[0009] In some embodiments, the source / drain conductive connection includes a polysilicon connection. Therefore, the source / drain conductive connection is process-compatible with polysilicon-related processes in image sensor pixel transistors and can serve as a diffusion source for subsequent doping of impurities into the silicon region.

[0010] In some embodiments, the gate structure includes a transistor polysilicon gate, and the insulating isolation structure includes a sidewall disposed on the sidewall of the transistor polysilicon gate. The source / drain conductive connection includes a first portion and a second portion, the first portion being in direct contact with the silicon region, and the second portion extending from the first portion toward the transistor polysilicon gate and located on the sidewall. Further, the orthographic projection of the second portion onto the substrate surface at least partially coincides with the orthographic projection of the transistor polysilicon gate onto the substrate surface, and the second portion is electrically isolated from the transistor polysilicon gate by the sidewall. Thus, the source / drain conductive connection can extend toward one side of the gate structure without short-circuiting with the transistor polysilicon gate, thereby providing a more flexible landing area for the contact plug.

[0011] In some embodiments, the orthographic projection of the contact plug onto the substrate surface lies at least partially on the insulating isolation structure. Optionally, the contact plug does not directly contact the silicon region, or the contact plug's orthographic projection lies only partially on the silicon region. Thus, the contact plug no longer needs to completely fall within the silicon region, relaxing the restrictions on the contact plug's placement relative to the silicon region, which is beneficial for reducing the design spacing between the contact plug and adjacent gate structures.

[0012] In some embodiments, the source / drain doped region is a shallow junction doped region. The dopant can be an N-type dopant, which includes at least one of phosphorus and arsenic. Since the source / drain doped region is formed at least partially by the diffusion of dopant from the source / drain conductive junction into the silicon region, compared to directly performing heavy doping implantation into the silicon region, it is beneficial to reduce the doped junction depth and improve the junction characteristics between the source / drain and the well region.

[0013] In some embodiments, at least a portion of the surface of the source / drain conductive connection is provided with an oxide layer, and the contact plug penetrates the oxide layer and contacts the source / drain conductive connection. By forming an oxide layer on the surface of the source / drain conductive connection, the process stability of the source / drain structure can be improved in conjunction with subsequent doping, annealing, and contact hole formation processes.

[0014] In some embodiments, the pixel transistor includes at least one of a transfer transistor, a reset transistor, a source follower transistor, and a row select transistor. That is, the source / drain structure of the present invention can be applied to different types of pixel transistors in image sensor pixel units to improve the contact arrangement and area utilization of the transistor source / drain terminals within the pixel region.

[0015] The present invention also provides a method for fabricating a source / drain structure of a pixel transistor for an image sensor. The method includes: forming a gate structure on a substrate, wherein an insulating isolation structure is formed on the side of the gate structure; forming an opening on one side of the gate structure to expose a silicon region of the substrate; forming a source / drain conductive connection portion, such that the source / drain conductive connection portion is electrically connected to the silicon region, and at least a portion of the source / drain conductive connection portion extends onto the insulating isolation structure; doping the source / drain conductive connection portion and annealing it, such that dopant diffuses from the source / drain conductive connection portion into the silicon region to form a source / drain doped region in the silicon region; and forming a contact plug on the source / drain conductive connection portion, such that the contact plug is electrically connected to the silicon region through the source / drain conductive connection portion.

[0016] In some embodiments, forming the source / drain conductive connection includes: depositing a polysilicon layer after forming the opening, such that the polysilicon layer is in direct contact with the silicon region exposed by the opening; and patterning the polysilicon layer to retain a polysilicon connection located on one side of the gate structure, wherein at least a portion of the polysilicon connection extends onto the insulating isolation structure. In this way, a polysilicon connection structure that is both electrically connected to the silicon region and extends towards the side of the gate structure can be formed in the source / drain region.

[0017] In some embodiments, the gate structure includes a transistor polysilicon gate, and the insulating isolation structure includes sidewalls. When forming the source / drain conductive connection, the source / drain conductive connection is at least partially overlapped with the orthographic projection of the transistor polysilicon gate onto the substrate surface, and the source / drain conductive connection is electrically isolated from the transistor polysilicon gate by the sidewalls. Thus, while ensuring reliable electrical isolation, the source / drain conductive connection can be arranged closer to the transistor polysilicon gate, thereby increasing the freedom of layout design.

[0018] In some embodiments, prior to doping the source / drain conductive connection, the process further includes oxidizing the source / drain conductive connection to form an oxide layer on its surface. The doping process may include N-type heavy doping implantation into the source / drain conductive connection, and the annealing process causes the N-type dopant to diffuse from the source / drain conductive connection into the silicon region to form an N-type shallow junction source / drain doped region.

[0019] In some embodiments, forming the contact plug includes: forming a dielectric layer covering the source / drain conductive connection; forming a contact hole in the dielectric layer, the contact hole exposing at least a portion of the surface of the source / drain conductive connection; and filling the contact hole with a conductive material to form the contact plug.

[0020] The present invention also provides an image sensor, the image sensor comprising a pixel array, wherein at least one pixel in the pixel array comprises the source / drain structure of any of the above-described image sensor pixel transistors.

[0021] Compared with the prior art, the present invention has at least the following beneficial effects: First, the present invention provides a source / drain conductive connection between the contact plug and the silicon region, so that the contact plug is electrically connected to the silicon region through the source / drain conductive connection. Therefore, the contact plug no longer needs to land directly on the silicon region, which relaxes the restrictions on the contact plug's placement on the silicon region and improves the flexibility of contact plug arrangement.

[0022] Secondly, at least a portion of the source / drain conductive connection of the present invention extends to the insulating isolation structure on the side of the gate structure, allowing the source / drain conductive connection to extend towards the gate structure without short-circuiting with it. This reduces the reserved distance between the contact plug and the gate structure within the pixel area, thereby reducing the design spacing between adjacent gate structures, which helps save pixel layout area and improve the integration density and fill factor of the pixel array.

[0023] Third, the present invention utilizes the diffusion of doped impurities in the source / drain conductive connection into the silicon region to form the source / drain doped region. Compared with the method of directly performing heavy doping on the silicon region, this is beneficial to forming a shallower source / drain junction, improving the junction depth control of the source / drain doped region, and reducing the adverse effects of a deeper junction on dark current, noise, charge transfer efficiency, or device reliability.

[0024] Fourth, the source / drain conductive connection of the present invention can be a polysilicon connection and is compatible with the existing polysilicon, sidewall, contact hole and other process flows of image sensor pixel transistors. It does not require significant changes to the overall process architecture of the image sensor pixel area and has good process adaptability and mass production feasibility. Attached Figure Description

[0025] Figure 1 A schematic diagram illustrating the fabrication process of the source / drain structure of a pixel transistor in an existing image sensor. Figure 1 (a) is a schematic diagram of the structure after forming a sidewall on the polysilicon gate side of a transistor in the existing process; Figure 1 (b) is a schematic diagram of the structure after heavy doping and implantation of silicon regions to form source / drain doped regions in the existing process; Figure 1 (c) is a schematic diagram of the structure after forming a contact plug above the doped region of the source / drain in the existing process; Figure 2 This is a schematic diagram illustrating the fabrication process of the image sensor pixel transistor source / drain structure provided in an embodiment of the present invention; Figure 2 (a) is a schematic diagram of the structure after an insulating isolation structure is formed on the side of the gate structure in an embodiment of the present invention; Figure 2 (b) is a schematic diagram of the structure after forming an opening in the source / drain region and exposing the silicon region in an embodiment of the present invention; Figure 2 (c) is a schematic diagram of the structure after the conductive material layer is deposited in an embodiment of the present invention; Figure 2 (d) is a schematic diagram of the structure after the patterned conductive material layer is formed and the source / drain conductive connection is formed in an embodiment of the present invention; Figure 2 (e) is a schematic diagram of the structure after oxidation treatment of the source / drain conductive connection portion in an embodiment of the present invention; Figure 2 (f) is a schematic diagram of the structure after the source / drain conductive connection portion is doped and annealed in an embodiment of the present invention, and a source / drain doped region is formed in the silicon region; Figure 2 (g) is a schematic diagram of the structure after forming a contact plug on the source / drain conductive connection portion in an embodiment of the present invention; Figure 3 This is a schematic diagram of the design layout of the source / drain structure of the pixel transistor in an image sensor provided in an embodiment of the present invention. Detailed Implementation

[0026] The embodiments of the present invention will be described below with reference to the accompanying drawings. It should be understood that the following embodiments are only for illustrating the technical solutions of the present invention and should not be construed as limiting the scope of protection of the present invention. Where there is no conflict, the technical features in the following embodiments can be combined with each other.

[0027] In this specification, "source / drain" can refer to the source terminal of a pixel transistor, the drain terminal of a pixel transistor, or both. "Silicon region" can refer to the active silicon region in the substrate used to form the source / drain terminals of the pixel transistor. "Contact plug" can refer to a conductive connection structure formed by filling a contact hole with conductive material, which may include tungsten, cobalt, copper, titanium, titanium nitride, or a combination thereof. "Orthographic projection" refers to the projection obtained by projecting onto the substrate surface in a direction perpendicular to the substrate surface.

[0028] To facilitate understanding of this invention, let's first combine... Figure 1 (a) to Figure 1 (c) A description of the source / drain structure of the pixel transistor in an existing image sensor.

[0029] Please refer to Figure 1 (a) to Figure 1 (c), Figure 1The fabrication process of a conventional image sensor pixel transistor source / drain structure 900 is illustrated. The conventional source / drain structure 900 includes a substrate 910, a silicon region 911, a gate structure 920, a transistor polysilicon gate 922, sidewalls 923, source / drain doped regions 940, and contact plugs 950.

[0030] like Figure 1 As shown in (a), in existing processes, a transistor polysilicon gate 922 is typically formed on a substrate 910, and a sidewall 923 is formed on the side of the transistor polysilicon gate 922. The transistor polysilicon gate 922 can be the gate of an image sensor pixel transistor, such as the gate of a transfer transistor, a reset transistor, a source follower transistor, or a row select transistor. The sidewall 923 is typically formed on the sidewall of the transistor polysilicon gate 922 to define a process window during subsequent source / drain implantation and contact via formation, and to isolate the transistor polysilicon gate 922 from adjacent conductive structures.

[0031] like Figure 1 As shown in (b), after forming the sidewalls 923, the source / drain regions are typically subjected to N-type heavy doping implantation to form source / drain doped regions 940 in the silicon region 911. These source / drain doped regions 940 are typically formed by direct implantation of dopant ions into the silicon region 911 followed by annealing. Due to the direct implantation of dopant ions into the silicon region 911, the source / drain doped regions 940 tend to form relatively deep junctions. For the pixel region of an image sensor, deeper source / drain junctions can increase the junction area or depth between the source / drain and the well region, thus adversely affecting dark current, noise, charge transfer efficiency, or device reliability.

[0032] like Figure 1 As shown in (c), after forming the source / drain doped region 940, a contact plug 950 is further formed above the source / drain doped region 940. The contact plug 950 typically needs to directly contact the source / drain doped region 940 in the silicon region 911 to achieve electrical connection between the source / drain and the upper interconnect structure. Therefore, the contact plug 950 needs to lie completely or substantially completely on the silicon region 911.

[0033] Specifically, since the contact plug 950 rests directly on the silicon region 911, a sufficient process safety distance needs to be reserved between the contact plug 950 and the adjacent transistor polysilicon gate 922 to avoid short circuits. This process safety distance is typically limited by the width of the contact plug 950 itself, the contact hole overlay tolerance, the width of the sidewall 923, and the design rules between adjacent structures. Therefore, in the existing source / drain structure 900, the minimum distance between adjacent transistor polysilicon gates 922 typically needs to at least meet the requirements of the width of the contact plug 950 and the sidewalls 923 or safety clearances on both sides of the transistor polysilicon gate 922.

[0034] As the pixel size of CMOS image sensors continues to shrink, photodiodes, transfer transistors, reset transistors, source follower transistors, row select transistors, and corresponding contact structures need to be arranged within the pixel area. The limitation in the existing source / drain structure 900, where the contact plug 950 must fall completely or substantially completely on the silicon region 911, occupies a large layout area and restricts further reduction in the distance between the polysilicon gates 922 of adjacent transistors, which is detrimental to saving pixel area and improving the pixel fill factor.

[0035] Based on this, this embodiment provides a novel source / drain structure 100 for an image sensor pixel transistor. Please refer to... Figure 2 (a) to Figure 2 (g) The source / drain structure 100 includes a substrate 10, a gate structure 20, a source / drain conductive connection portion 30, a source / drain doped region 40, and a contact plug 50.

[0036] The substrate 10 may be a silicon substrate or a silicon substrate with an epitaxial layer formed thereon. The substrate 10 includes a silicon region 11. The silicon region 11 may be the active region of the image sensor pixel transistor, used to form the source / drain doped region 40. In some embodiments, a well region 12, such as a P-type well region, may also be formed in the substrate 10. For an N-type pixel transistor, the source / drain doped region 40 may be an N-type doped region formed in a P-type well region.

[0037] A gate structure 20 is disposed on the substrate 10. The gate structure 20 may include a gate dielectric layer 21 and a transistor polysilicon gate 22. The gate dielectric layer 21 is disposed between the substrate 10 and the transistor polysilicon gate 22. The transistor polysilicon gate 22 may be a control gate of a pixel transistor, such as the gate of a transfer transistor TX, the gate of a reset transistor RST, the gate of a source follower transistor SF, or the gate of a row select transistor SEL.

[0038] An insulating isolation structure 23 is provided on the side of the gate structure 20. In this embodiment, the insulating isolation structure 23 can be a sidewall disposed on the sidewall of the transistor polysilicon gate 22. The sidewall material can include silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof. The insulating isolation structure 23 is used to form electrical isolation between the source / drain conductive connection portion 30 and the transistor polysilicon gate 22, preventing direct electrical connection between the source / drain conductive connection portion 30 and the transistor polysilicon gate 22, thus preventing a short circuit.

[0039] A source / drain conductive connection portion 30 is disposed on one side of the gate structure 20 and electrically connected to the silicon region 11. The source / drain conductive connection portion 30 may include a polysilicon connection portion. In some embodiments, the source / drain conductive connection portion 30 may be a doped polysilicon connection portion, a polysilicon connection portion formed by annealing amorphous silicon, or a polysilicon / silicide composite connection portion, as long as it can form an electrical connection with the silicon region 11 and can serve as a diffusion source for doped impurities to diffuse into the silicon region 11.

[0040] Specifically, the source / drain conductive connection portion 30 includes a first portion 31 and a second portion 32. The first portion 31 is located in the source / drain region and is in direct contact with the silicon region 11. The second portion 32 extends from the first portion 31 toward the gate structure 20, and at least a portion of the second portion 32 extends onto the insulating isolation structure 23. In other words, the source / drain conductive connection portion 30 is not only disposed directly above the silicon region 11, but can extend from above the silicon region 11 to above the insulating isolation structure 23 on the side of the gate structure 20.

[0041] In some embodiments, the orthographic projection of the second portion 32 onto the surface of the substrate 10 may at least partially coincide with the orthographic projection of the transistor polysilicon gate 22 onto the surface of the substrate 10. This overlapping portion may be referred to as the overlapping region 33. Since an insulating isolation structure 23 is provided between the source / drain conductive connection portion 30 at the overlapping region 33 and the transistor polysilicon gate 22, even if the source / drain conductive connection portion 30 partially overlaps with the transistor polysilicon gate 22 in the top view direction, the two will not be directly electrically connected, thereby avoiding a short circuit between the source / drain and the gate.

[0042] A source / drain doped region 40 is formed in the silicon region 11 corresponding to the source / drain conductive connection portion 30. The source / drain doped region 40 is formed at least partially by the diffusion of dopant impurities from the source / drain conductive connection portion 30 into the silicon region 11. Specifically, after forming the source / drain conductive connection portion 30, N-type heavy doping implantation can be performed on the source / drain conductive connection portion 30, and annealing can be used to allow N-type dopant impurities to diffuse from the source / drain conductive connection portion 30 into the silicon region 11, thereby forming the source / drain doped region 40 in the silicon region 11. The N-type dopant impurities may include at least one of phosphorus and arsenic.

[0043] Compared to Figure 1 The method shown involves directly implanting N-type heavy doping into the silicon region 911. In this embodiment, the doped impurities are first implanted into the source / drain conductive connection portion 30, and then annealing is used to allow the doped impurities to diffuse from the source / drain conductive connection portion 30 into the silicon region 11. This helps to reduce the junction depth of the source / drain doped region 40, making the source / drain doped region 40 a shallow junction doped region, thereby improving the junction characteristics between the source / drain doped region 40 and the well region 12.

[0044] A contact plug 50 is disposed on the source / drain conductive connection portion 30 and electrically connected to the silicon region 11 through the source / drain conductive connection portion 30. Specifically, the contact plug 50 may be formed within a contact hole 52 in the dielectric layer 51. The contact hole 52 exposes at least a portion of the surface of the source / drain conductive connection portion 30, and conductive material is filled into the contact hole 52 to form the contact plug 50. Since the contact plug 50 is electrically connected to the silicon region 11 through the source / drain conductive connection portion 30, the contact plug 50 does not need to be completely placed on the silicon region 11 as in conventional structures.

[0045] In some embodiments, the orthographic projection of the contact plug 50 onto the surface of the substrate 10 may at least partially lie on the insulating isolation structure 23. In other embodiments, the contact plug 50 may not directly contact the silicon region 11, but may be electrically connected to the silicon region 11 entirely through the source / drain conductive connection portion 30. In still other embodiments, the contact plug 50 may have only a partial orthographic projection onto the silicon region 11, with the remaining portion orthographically projected onto the insulating isolation structure 23 or other insulating regions. Thus, the landing area of ​​the contact plug 50 can be offset relative to the silicon region 11 towards the gate structure 20, thereby relaxing the landing requirement of the contact plug 50 on the silicon region 11 and reducing the required layout spacing between the contact plug 50 and the transistor polysilicon gate 22.

[0046] In some embodiments, at least a portion of the surface of the source / drain conductive connection 30 may also be formed with an oxide layer 34. The oxide layer 34 may be a thin oxide layer formed after oxidizing the source / drain conductive connection 30. When the contact plug 50 is subsequently formed, the contact hole 52 may penetrate the oxide layer 34 and expose the source / drain conductive connection 30, allowing the contact plug 50 to contact the source / drain conductive connection 30. The oxide layer 34 may protect or process-modulate the source / drain conductive connection 30 during subsequent doping implantation, annealing, or contact hole formation.

[0047] The following is combined with Figure 2 (a) to Figure 2 (g) describes a method for preparing the source / drain structure 100.

[0048] like Figure 2 As shown in (a), a gate structure 20 is formed on a substrate 10, and an insulating isolation structure 23 is formed on the side of the gate structure 20. Specifically, a gate dielectric layer 21 can be formed on the substrate 10 first, and then a transistor polysilicon gate 22 can be formed on the gate dielectric layer 21. Afterwards, a sidewall material layer is deposited on the substrate 10 and the transistor polysilicon gate 22, and the sidewall material layer is anisotropically etched to retain the sidewall material layer on the sidewall of the transistor polysilicon gate 22, thereby forming the insulating isolation structure 23. The insulating isolation structure 23 can be a single-layer sidewall or a multi-layer sidewall.

[0049] like Figure 2 As shown in (b), an opening 60 is formed on one side of the gate structure 20 to expose the silicon region 11. Specifically, a first photomask, i.e., a source / drain opening photomask or an OX CT photomask, can be used to develop and etch the source / drain region to remove at least a portion of the insulating material above the source / drain region, such as an oxide layer, sidewall material, or other dielectric material, thereby forming the opening 60 in the source / drain region and exposing the silicon region 11 through the opening 60. The position of the opening 60 corresponds to the position where the subsequent source / drain conductive connection 30 directly contacts the silicon region 11.

[0050] It should be noted that, in Figure 2 In step (b), the opening 60 is used to allow the subsequently deposited conductive material layer 30a to directly contact the silicon region 11. The opening 60 can be located on one side of the gate structure 20 and correspond to the source / drain region. The size and position of the opening 60 can be set according to the pixel layout design rules, the pattern of the subsequent source / drain conductive connection portion 30, and the landing position of the contact plug 50.

[0051] like Figure 2 As shown in (c), after forming the opening 60, a conductive material layer 30a is deposited. The conductive material layer 30a can be a polysilicon layer. The conductive material layer 30a covers the gate structure 20, the insulating isolation structure 23, and the opening 60, and fills the opening 60, so that the conductive material layer 30a is in direct contact with the silicon region 11 exposed by the opening 60. Thus, the source / drain conductive connection portion 30 subsequently formed by patterning the conductive material layer 30a can be electrically connected to the silicon region 11.

[0052] like Figure 2 As shown in (d), the conductive material layer 30a is patterned to form the source / drain conductive connection portion 30. Specifically, a second photomask, namely a POLY CT photomask, can be used to develop and etch the conductive material layer 30a to remove the conductive material layer 30a that does not need to be retained, and to retain the source / drain conductive connection portion 30 on one side of the gate structure 20.

[0053] The patterned source / drain conductive connection 30 includes a first portion 31 in direct contact with the silicon region 11 and a second portion 32 extending from the first portion 31 toward the transistor polysilicon gate 22. At least a portion of the second portion 32 is located on the insulating isolation structure 23. In some embodiments, the source / drain conductive connection 30 and the transistor polysilicon gate 22 may have an overlapping region 33. The overlapping region 33 refers to the area where the orthographic projection of the source / drain conductive connection 30 on the surface of the substrate 10 coincides with the orthographic projection of the transistor polysilicon gate 22 on the surface of the substrate 10. Since the source / drain conductive connection 30 and the transistor polysilicon gate 22 are separated at the overlapping region 33 by the insulating isolation structure 23, the source / drain conductive connection 30 can be arranged closer to the transistor polysilicon gate 22 without short-circuiting.

[0054] like Figure 2 As shown in (e), the source / drain conductive connection 30 can be oxidized to form an oxide layer 34 on at least a portion of the surface of the source / drain conductive connection 30. The oxide layer 34 can be a thin oxide layer. In some embodiments, before forming the oxide layer 34, the sidewall material, oxide layer, or other insulating material around the source / drain conductive connection 30 that is not covered by the retained conductive material can be etched back or cleaned to expose the surface of the source / drain conductive connection 30 that needs to be oxidized. It should be understood that this etch-back or cleaning will not destroy the insulating isolation structure 23 used to isolate the source / drain conductive connection 30 from the transistor polysilicon gate 22, thereby still ensuring the electrical isolation between the source / drain conductive connection 30 and the transistor polysilicon gate 22.

[0055] like Figure 2 As shown in (f), the source / drain conductive connection portion 30 is subjected to N-type heavy doping implantation and annealing. N-type heavy doping implantation can use phosphorus ions, arsenic ions, or a combination thereof. After the N-type dopant enters the source / drain conductive connection portion 30, it diffuses from the source / drain conductive connection portion 30 into the silicon region 11 below it during the annealing process, thereby forming a source / drain doped region 40 in the silicon region 11. Since the dopant first enters the source / drain conductive connection portion 30 and then diffuses from the source / drain conductive connection portion 30 to the silicon region 11, the problem of excessive junction depth caused by direct implantation of dopant into the silicon region 11 can be reduced, which is beneficial for forming a shallow junction source / drain doped region 40.

[0056] In some embodiments, the junction depth and doping distribution of the source / drain doped region 40 can be controlled by adjusting the thickness, doping concentration, annealing temperature, and annealing time of the source / drain conductive connection 30. For example, the greater the thickness of the source / drain conductive connection 30, the longer the diffusion path of the doped impurities before entering the silicon region 11; the lower or shorter the annealing temperature and annealing time, the shallower the diffusion depth of the doped impurities into the silicon region 11. Thus, the junction depth of the source / drain doped region 40 can be adjusted according to the performance requirements of the image sensor pixel transistors.

[0057] like Figure 2 As shown in (g), a contact plug 50 is formed on the source / drain conductive connection portion 30. Specifically, a dielectric layer 51 covering the source / drain conductive connection portion 30 and the gate structure 20 can be formed. Then, a contact hole photomask is used to develop and etch the dielectric layer 51 to form a contact hole 52 exposing the source / drain conductive connection portion 30. Afterward, conductive material is filled into the contact hole 52 to form the contact plug 50. The contact plug 50 rests on the source / drain conductive connection portion 30 and is electrically connected to the silicon region 11 through the source / drain conductive connection portion 30.

[0058] Since the source / drain conductive connection 30 can extend onto the insulating isolation structure 23, the landing point of the contact plug 50 can be set on the source / drain conductive connection 30, rather than landing entirely on the silicon region 11. In other words, the contact plug 50 can be moved towards the gate structure 20 relative to a conventional contact plug that directly contacts the silicon region, thereby reducing the layout spacing between the contact plug 50 and the transistor polysilicon gate 22. For the pixel region, this structure can effectively reduce the distance between the polysilicon gates of adjacent pixel transistors, saving pixel area and improving the integration density of the image sensor pixel array.

[0059] Please refer to Figure 3 , Figure 3 A schematic diagram of the design layout of the novel image sensor pixel transistor source / drain structure 100 of this embodiment is shown. Figure 3 It can be Figure 2 The source / drain structure 100 shown is a top view of the substrate surface. Figure 3 It may include a silicon region 11, a transistor polysilicon gate 22, a source / drain conductive connection portion 30, an opening pattern 60, a contact plug 50, and an overlapping region 33.

[0060] exist Figure 3 In the transistor, the polysilicon gate 22 can extend along a first direction, and the silicon region 11 is located on one side of the polysilicon gate 22. The opening pattern 60 corresponds to... Figure 2 The opening 60 in (b) is the location where the insulating material of the source / drain region is etched and the silicon region 11 is exposed through the first photomask, such as an OX CT photomask. The source / drain conductive connection portion 30 corresponds to... Figure 2 (c) and Figure 2 The conductive connection structure retained after deposition and patterning in (d) can be patterned on the conductive material layer 30a by a second photomask, such as a POLY CT photomask.

[0061] The source / drain conductive connection portion 30 includes a first portion 31 and a second portion 32. The first portion 31 corresponds to the opening pattern 60 and directly contacts the silicon region 11 through the opening 60. The second portion 32 extends from the first portion 31 toward the transistor polysilicon gate 22 and is at least partially located above the insulating isolation structure 23 on the side of the transistor polysilicon gate 22. Figure 3 In the top view shown, the second portion 32 can form an overlapping region 33 with the transistor polysilicon gate 22. The overlapping region 33 refers to the area where the orthographic projection of the source / drain conductive connection portion 30 on the substrate surface and the orthographic projection of the transistor polysilicon gate 22 on the substrate surface coincide. The width of the overlapping region 33 in the second direction can be denoted as a.

[0062] It should be noted that, Figure 3 Although the source / drain conductive connection portion 30 and the transistor polysilicon gate 22 overlap in a top-view direction with a region 33, they are separated in the vertical direction by an insulating isolation structure 23. Therefore, the source / drain conductive connection portion 30 is not directly electrically connected to the transistor polysilicon gate 22, and a short circuit between the source / drain and the gate is avoided. With this layout design, the source / drain conductive connection portion 30 can be arranged closer to the transistor polysilicon gate 22, thereby shifting the landing area of ​​the contact plug 50 toward the transistor polysilicon gate 22.

[0063] Contact plugs 50 are disposed on the source / drain conductive connection portion 30. In some embodiments, the orthographic projection of the contact plug 50 may lie entirely within the source / drain conductive connection portion 30, but not necessarily entirely within the silicon region 11. In other embodiments, the orthographic projection of the contact plug 50 may lie partially on the silicon region 11 and partially on the insulating isolation structure 23. In still other embodiments, the contact plug 50 may not directly contact the silicon region 11, but may be electrically connected to the silicon region 11 entirely through the source / drain conductive connection portion 30. Thus, the placement of the contact plug 50 is no longer limited to the boundary of the silicon region 11, which can improve the freedom of layout design.

[0064] Figure 3In the layout shown, the positional relationship between the opening pattern 60, the source / drain conductive connection portion 30, and the contact plug 50 can be adjusted according to process capabilities and design rules. Preferably, the opening pattern 60 is at least partially located on the silicon region 11 to ensure that the source / drain conductive connection portion 30 can form reliable contact with the silicon region 11 through the opening 60; the source / drain conductive connection portion 30 at least covers the opening pattern 60 and extends from the opening pattern 60 toward the transistor polysilicon gate 22; the contact plug 50 is disposed on the source / drain conductive connection portion 30 and can be offset relative to the opening pattern 60 toward the transistor polysilicon gate 22. With this layout relationship, the area required in the silicon region 11 to accommodate the contact plug 50 can be reduced while ensuring the reliability of the source / drain electrical connection.

[0065] and Figure 1 Compared to the existing source / drain structure 900 shown, Figure 3 The layout structure shown has at least the following differences: First, in the existing source / drain structure 900, the contact plug 950 needs to land directly on the silicon region 911, while in this embodiment, the contact plug 50 is connected to the silicon region 11 through the source / drain conductive connection portion 30; Second, in the existing source / drain structure 900, a large gap needs to be reserved between the contact plug 950 and the transistor polysilicon gate 922, while in this embodiment, the source / drain conductive connection portion 30 can extend to the insulating isolation structure 23, so that the contact plug 50 can be offset towards the side of the transistor polysilicon gate 22; Third, in the existing source / drain structure 900, the source / drain doped region 940 is usually formed by directly implanting heavy doping into the silicon region 911, while in this embodiment, the source / drain doped region 40 can be formed by the diffusion of doped impurities in the source / drain conductive connection portion 30 into the silicon region 11, which is beneficial for forming a shallow junction.

[0066] therefore, Figure 3 The map shown is Figure 2 The preparation processes shown correspond to each other: the opening pattern 60 corresponds to... Figure 2 (b) source / drain opening step; source / drain conductive connection portion 30 corresponds to Figure 2 (c) and Figure 2 (d) Polysilicon deposition and patterning steps; Overlapping region 33 corresponds to the region where the source / drain conductive connection portion 30 extends onto the insulating isolation structure 23 and overlaps with the transistor polysilicon gate 22 in top view; Contact plug 50 corresponds to Figure 2 (g) involves etching the contact holes and filling them with conductive material. Through the above structure and process, this embodiment achieves miniaturization of the source / drain contact structure and shallow junction reduction at the source / drain terminals.

[0067] In other embodiments, the insulating isolation structure 23 is not limited to a single-layer sidewall, but can also be a multi-layer sidewall structure. For example, the insulating isolation structure 23 may include a silicon oxide layer near the transistor polysilicon gate 22 and a silicon nitride layer located outside the silicon oxide layer, or may include a silicon oxide / silicon nitride / silicon oxide composite structure. As long as the insulating isolation structure 23 can electrically isolate the source / drain conductive connection portion 30 from the transistor polysilicon gate 22 and allow the source / drain conductive connection portion 30 to at least partially extend above it, it can be applied to this embodiment.

[0068] In other embodiments, the contact plug 50 may be entirely disposed on the first portion 31 of the source / drain conductive connection portion 30, or at least partially disposed on the second portion 32. Preferably, the contact plug 50 is at least partially disposed on the second portion 32, such that the landing area of ​​the contact plug 50 is offset toward the side of the transistor polysilicon gate 22, thereby more effectively reducing the area occupied by the source / drain contact structure in the pixel region.

[0069] In other embodiments, the source / drain structure 100 can be applied to one pixel transistor in the same pixel cell, or to multiple pixel transistors. For example, the source / drain structure 100 can be located at the drain or source of the transmission transistor TX, or at the source / drain of the reset transistor RST, the source follower transistor SF, or the row select transistor SEL. For shared pixel structures, the source / drain structure 100 can also be applied to the floating diffusion region shared by multiple photodiodes or the source / drain region of related transistors to further improve the compactness of the shared pixel layout.

[0070] In other embodiments, the dopant in the source / drain conductive connection portion 30 is not limited to N-type dopant. For pixel transistors of different conductivity types, P-type dopant can also be incorporated into the source / drain conductive connection portion 30, and annealing can diffuse the P-type dopant from the source / drain conductive connection portion 30 into the silicon region 11 to form a P-type source / drain doped region. That is, the source / drain structure 100 of this embodiment can select different conductivity types of dopant according to the transistor type.

[0071] In summary, this embodiment, by providing a source / drain conductive connection portion 30 between the contact plug 50 and the silicon region 11, electrically connects the contact plug 50 to the silicon region 11 via the source / drain conductive connection portion 30, and extends at least a portion of the source / drain conductive connection portion 30 to the insulating isolation structure 23 on the side of the gate structure 20, thereby changing the structural limitation of the traditional contact plug having to directly rest on the silicon region 11. This structure not only reduces the layout spacing between pixel transistors, saving pixel area, but also utilizes the diffusion of doped impurities in the source / drain conductive connection portion 30 to form a shallower source / drain doped region 40, improving the source / drain junction characteristics of the image sensor pixel transistors.

Claims

1. A source / drain structure for a pixel transistor in an image sensor, characterized in that, include: Substrate, the substrate including silicon regions; A gate structure is disposed on the substrate, and an insulating isolation structure is provided on the side of the gate structure; A source / drain conductive connection is disposed on one side of the gate structure, the source / drain conductive connection is electrically connected to the silicon region, and at least a portion of the source / drain conductive connection extends to the insulating isolation structure; Source / drain doped regions are formed in the silicon region corresponding to the source / drain conductive connection portion; as well as A contact plug is disposed on the source / drain conductive connection portion and is electrically connected to the silicon region through the source / drain conductive connection portion; The source / drain conductive connection portion serves as an intermediate connection structure between the contact plug and the silicon region, and the source / drain doped region is formed at least partially by the diffusion of doped impurities from the source / drain conductive connection portion into the silicon region.

2. The source / drain structure of the image sensor pixel transistor according to claim 1, characterized in that, The source / drain conductive connection includes a polysilicon connection.

3. The source / drain structure of the image sensor pixel transistor according to claim 1, characterized in that, The gate structure includes a transistor polysilicon gate, and the insulating isolation structure includes a sidewall disposed on the sidewall of the transistor polysilicon gate.

4. The source / drain structure of the image sensor pixel transistor according to claim 3, characterized in that, The source / drain conductive connection includes a first portion and a second portion. The first portion is in direct contact with the silicon region, and the second portion extends from the first portion toward the transistor polysilicon gate and is located on the sidewall.

5. The source / drain structure of the image sensor pixel transistor according to claim 4, characterized in that, The orthographic projection of the second portion onto the substrate surface at least partially coincides with the orthographic projection of the transistor polysilicon gate onto the substrate surface, and the second portion is electrically isolated from the transistor polysilicon gate through the sidewall.

6. The source / drain structure of the image sensor pixel transistor according to claim 1, characterized in that, The orthographic projection of the contact plug onto the substrate surface is at least partially located on the insulating isolation structure.

7. The source / drain structure of the image sensor pixel transistor according to claim 1, characterized in that, The contact plug is not in direct contact with the silicon region, or the contact plug is only partially projected onto the silicon region.

8. The source / drain structure of the image sensor pixel transistor according to claim 1, characterized in that, The source / drain doped regions are shallow junction doped regions.

9. The source / drain structure of the image sensor pixel transistor according to claim 1, characterized in that, The doping impurity is an N-type doping impurity, which includes at least one of phosphorus and arsenic.

10. The source / drain structure of the image sensor pixel transistor according to claim 1, characterized in that, At least a portion of the surface of the source / drain conductive connection is provided with an oxide layer, and the contact plug penetrates the oxide layer and contacts the source / drain conductive connection.

11. The source / drain structure of the image sensor pixel transistor according to claim 1, characterized in that, The pixel transistor includes at least one of a transfer transistor, a reset transistor, a source follower transistor, and a row select transistor.

12. A method for fabricating a source / drain structure of a pixel transistor in an image sensor, characterized in that, include: A gate structure is formed on a substrate, and an insulating isolation structure is formed on the side of the gate structure; An opening is formed on one side of the gate structure to expose a silicon region of the substrate; A source / drain conductive connection is formed, which is electrically connected to the silicon region, and at least a portion of the source / drain conductive connection extends to the insulating isolation structure. The source / drain conductive connection is doped and annealed to allow the doped impurities to diffuse from the source / drain conductive connection into the silicon region, thereby forming a source / drain doped region in the silicon region. A contact plug is formed on the source / drain conductive connection portion, and the contact plug is electrically connected to the silicon region through the source / drain conductive connection portion.

13. The preparation method according to claim 12, characterized in that, The source / drain conductive connection includes: After the opening is formed, a polysilicon layer is deposited so that the polysilicon layer is in direct contact with the silicon region exposed by the opening; The polysilicon layer is patterned to retain a polysilicon connection located on one side of the gate structure, at least a portion of which extends onto the insulating isolation structure.

14. The preparation method according to claim 12, characterized in that, The gate structure includes a transistor polysilicon gate, and the insulating isolation structure includes sidewalls; When forming the source / drain conductive connection, the source / drain conductive connection is made to at least partially coincide with the orthographic projection of the transistor polysilicon gate on the substrate surface, and the source / drain conductive connection is electrically isolated from the transistor polysilicon gate through the sidewall.

15. The preparation method according to claim 12, characterized in that, Before doping the source / drain conductive connection, the method further includes: The source / drain conductive connection is oxidized to form an oxide layer on the surface of the source / drain conductive connection.

16. The preparation method according to claim 12, characterized in that, Forming the contact plug includes: A dielectric layer is formed covering the source / drain conductive connection portion; A contact hole is formed in the dielectric layer, the contact hole exposing at least a portion of the surface of the source / drain conductive connection; The contact hole is filled with conductive material to form the contact plug.

17. The preparation method according to claim 12, characterized in that, The doping process includes N-type heavy doping implantation into the source / drain conductive connection portion, and the annealing process causes the N-type doped impurities to diffuse from the source / drain conductive connection portion into the silicon region to form an N-type shallow junction source / drain doped region.

18. An image sensor, characterized in that, The array includes a pixel array, wherein at least one pixel in the pixel array includes the source / drain structure of the image sensor pixel transistor according to any one of claims 1 to 11.

Images