Space heterojunction solar cell and method of making same

Abstract

The application discloses a space heterojunction solar cell and a manufacturing method thereof. The space heterojunction solar cell comprises a single crystal silicon wafer, a first intrinsic amorphous silicon layer, an N-type microcrystalline silicon layer, a first transparent conductive film layer and a first electrode are sequentially formed on the front surface of the single crystal silicon wafer, a second intrinsic amorphous silicon layer, a P-type microcrystalline silicon layer, a second transparent conductive film layer and a second electrode are sequentially formed on the back surface of the single crystal silicon wafer, and the surface of the edge area with a width of 0.2mm-0.8mm and the side surface of the single crystal silicon wafer are polished and removed and covered with a silicon oxide passivation layer. The application can reduce the TCO film removal cost, avoid ion damage and fluorine residual pollution caused by dry etching of the TCO film, effectively remove the cutting damage, and improve the bending resistance, electrical performance and conversion efficiency of the cell and the assembly.

Description

Technical Field

[0001] This invention relates to the field of photovoltaic manufacturing, and in particular to space heterojunction solar cells and their manufacturing methods. Background Technology

[0002] Space photovoltaics refers to generating electricity by installing solar panels in space environments such as satellites and space stations. This not only powers the spacecraft themselves but may also provide power to the ground via wireless transmission in the future. P-type heterojunction (HJT) cell technology is a solution for achieving large-scale, low-cost mass production of space solar cells.

[0003] Space photovoltaic modules need to have excellent bending resistance. However, during folding, the V-shaped grooves between the textured pyramids on the edges of silicon wafers or cells resemble microcracks, making the silicon wafers prone to breakage during bending. Therefore, it is essential to smooth the pyramid texture and V-shaped grooves on the edges of silicon wafers or cells. This means that the transparent conductive film (TCO film) on the corresponding area of ​​the edge of the silicon wafer or cell must be removed first. In existing technology, one TCO film etching method involves masking a single silicon wafer or cell and then performing dry or wet etching to remove the TCO film from its edge area. This single-wafer processing method is costly and difficult to adopt for mass production.

[0004] Another existing TCO film etching method involves stacking solar cells with fabricated electrodes and removing the TCO film using dry etching. This method presents several problems: First, the TCO film removal area is too narrow (less than 0.1 mm), failing to meet the requirements of space photovoltaics. Second, dry etching of the TCO film tends to be physical etching, causing significant damage to the interface and reducing the efficiency of the solar cells. Currently, there is no mature and feasible technology on the market for mass-producing smoothing techniques for the pyramidal textured surfaces and V-shaped grooves on the edges of silicon wafers or solar cells after TCO film removal.

[0005] Therefore, how to provide a space heterojunction solar cell and its fabrication method to reduce the cost of TCO film removal, avoid ion damage and fluorine residue pollution caused by dry etching of TCO film, effectively remove cutting damage, and improve the bending resistance, electrical performance and conversion efficiency of cells and modules has become a technical problem that urgently needs to be solved in the industry. Summary of the Invention

[0006] To address the aforementioned problems in the prior art, this invention proposes a method for fabricating a space heterojunction solar cell, comprising the following steps: Step 1: Provide monocrystalline silicon wafers and perform texturing and cleaning; Step 2: A first intrinsic amorphous silicon layer and a second intrinsic amorphous silicon layer are formed on the front and back surfaces of the monocrystalline silicon wafer respectively using an intrinsic PECVD process. Step 3: An N-type microcrystalline silicon layer is formed on the first intrinsic amorphous silicon layer on the front side of the monocrystalline silicon wafer using an N-type PECVD process. Step 4: A P-type microcrystalline silicon layer is formed on the second intrinsic amorphous silicon layer on the reverse side of the monocrystalline silicon wafer using a P-type PECVD process. Step 5: The monocrystalline silicon wafer is supported by a carrier plate with a predetermined mask pattern and its N-type microcrystalline silicon layer is facing down. A first transparent conductive film layer with a predetermined pattern is formed on the N-type microcrystalline silicon layer by PVD process. The predetermined mask pattern includes slicing lines and edge areas of the monocrystalline silicon wafer. Step 6: The single-crystal silicon wafer is supported by a carrier plate with the predetermined mask pattern and its P-type microcrystalline silicon layer is facing down. The second transparent conductive film layer with the predetermined pattern is formed on the P-type microcrystalline silicon layer by PVD process. Step 7: Cut the monocrystalline silicon wafer into multiple monocrystalline silicon sub-wafers along the slicing lines that do not cover the first transparent conductive film and the second transparent conductive film; Step 8: Polish the edge areas and sides of multiple single-crystal silicon wafers with an alkaline solution, and then clean them; Step nine, forming a silicon oxide passivation layer on the edge region and sides of the single-crystal silicon wafer; and Step 10: Form a first electrode and a second electrode on the first transparent conductive film and the second transparent conductive film, respectively.

[0007] In one embodiment, the width of the dicing lines included in the predetermined mask pattern in steps five and six is ​​0.2 mm to 0.8 mm, the width of the edge region of the monocrystalline silicon wafer included in the predetermined mask pattern is 50% to 80% of the width of the dicing lines, the thickness of the first transparent conductive film layer and the second transparent conductive film layer is 20 nm to 110 nm, and the thickness of the first intrinsic amorphous silicon layer and the second intrinsic amorphous silicon layer formed in step two is 5 nm to 20 nm.

[0008] In one embodiment, the method for fabricating the space heterojunction solar cell further includes step eleven, stacking multiple space heterojunction solar cells together and depositing amorphous silicon and / or silicon nitride passivation layers on the edge region and sides of each cell using a PECVD process. The reaction gases introduced into the PECVD reaction chamber during the deposition of the amorphous silicon passivation layer include silane and hydrogen, and the reaction gases introduced into the PECVD reaction chamber during the deposition of the silicon nitride passivation layer include silane, ammonia, hydrogen, and nitrogen.

[0009] In one embodiment, in step nine, a silicon oxide passivation layer is generated on the edge area and side surface of the single-crystal silicon wafers by placing multiple single-crystal silicon wafers in a cleaning tank filled with ozone for 1 min to 5 min, or by placing multiple single-crystal silicon wafers in a hydrogen peroxide solution for 1 min to 5 min.

[0010] In one embodiment, between steps five and six, there is also step five zero, unloading the monocrystalline silicon wafer from the carrier and flipping the monocrystalline silicon wafer so that its P-type microcrystalline silicon layer is placed face down in the carrier.

[0011] In one embodiment, in step one, the monocrystalline silicon wafer is immersed in a solution of potassium hydroxide and isopropanol at 80°C to 90°C for 2 to 3 minutes to form a pyramidal textured surface with a size of 2 μm to 5 μm on the surface of the monocrystalline silicon wafer. The thickness of the monocrystalline silicon wafer after texturing is 30 μm to 120 μm.

[0012] In one embodiment, the process gases in the N-type PECVD process in step three include SiH4, H2, and PH3, and also include CO2 or N2O. The RF power is 2000W to 10000W, the gas volume ratio of PH3 to SiH4 is 1% to 10%, the gas volume ratio of CO2 (N2O) to SiH4 is 0% to 100%, and the thickness of the formed N-type microcrystalline silicon layer is 5nm to 20nm.

[0013] In one embodiment, the process gases of the P-type PECVD process in step four include SiH4, H2 and B2H6, the RF power is 2000W to 10000W, the gas volume ratio of B2H6 to SiH4 is 0.1% to 10%, and the thickness of the P-type microcrystalline silicon layer is 5nm to 30nm.

[0014] In one embodiment, in step ten, silver paste is screen-printed and sintered to form the first electrode and the second electrode, and the PVD process in steps five and six is ​​magnetron sputtering.

[0015] The present invention also discloses a space heterojunction solar cell, which is manufactured by any of the above-described methods for fabricating a space heterojunction solar cell. The space heterojunction solar cell includes a monocrystalline silicon wafer. A first intrinsic amorphous silicon layer, an N-type microcrystalline silicon layer, a first transparent conductive film layer, and a first electrode are sequentially formed on the front side of the monocrystalline silicon wafer. A second intrinsic amorphous silicon layer, a P-type microcrystalline silicon layer, a second transparent conductive film layer, and a second electrode are sequentially formed on the back side of the monocrystalline silicon wafer. The edge region with a width of 0.2 mm to 0.8 mm and the textured surface on the side surface of the monocrystalline silicon wafer are polished off and covered with a silicon oxide passivation layer.

[0016] Compared to existing technologies that use dry etching to remove the TCO film at the edges of silicon wafers or solar cells, resulting in poor etching effects and significant damage, the fabrication method of the space heterojunction solar cell of the present invention first provides a monocrystalline silicon wafer and performs texturing and cleaning; then, an intrinsic amorphous silicon layer and a second intrinsic amorphous silicon layer are formed on the front and back sides of the monocrystalline silicon wafer respectively using an intrinsic PECVD process; next, an N-type microcrystalline silicon layer is formed on the first intrinsic amorphous silicon layer on the front side of the monocrystalline silicon wafer using an N-type PECVD process; then, a P-type microcrystalline silicon layer is formed on the second intrinsic amorphous silicon layer on the back side of the monocrystalline silicon wafer using a P-type PECVD process; finally, the monocrystalline silicon wafer is supported by a carrier plate with a predetermined mask pattern and its N-type microcrystalline silicon layer is facing down, and a PVD process is used to fabricate the N-type microcrystalline silicon layer... A first transparent conductive film layer with a predetermined pattern is formed on the substrate. The predetermined mask pattern includes dicing lines and edge regions of the monocrystalline silicon wafer. The monocrystalline silicon wafer is then supported by a carrier plate with the predetermined mask pattern, with its P-type microcrystalline silicon layer facing down. A second transparent conductive film layer with the predetermined pattern is formed on the P-type microcrystalline silicon layer using a PVD process. Next, the monocrystalline silicon wafer is diced into multiple monocrystalline silicon sub-wafers along the dicing lines that do not cover the first and second transparent conductive films. The edge regions and sides of the multiple monocrystalline silicon sub-wafers are then polished and cleaned using an alkaline solution. A silicon oxide passivation layer is then formed on the edge regions and sides of the monocrystalline silicon sub-wafers. Finally, a first electrode and a second electrode are formed on the first and second transparent conductive films, respectively. This invention reduces the cost of TCO film removal, avoids ion damage and fluorine residue contamination caused by dry etching of TCO films, effectively removes dicing damage, and improves the bending resistance, electrical performance, and conversion efficiency of batteries and modules. Attached Figure Description

[0017] The above-described features and advantages of the present invention will be better understood after reading the following detailed description of embodiments of the present disclosure in conjunction with the accompanying drawings. In the drawings, components are not necessarily drawn to scale, and components having similar related characteristics or features may have the same or similar reference numerals.

[0018] Figure 1 This is a schematic diagram illustrating the specific process of an embodiment of the fabrication method of the space heterojunction solar cell of the present invention.

[0019] Figure 2 To complete Figure 1 A schematic diagram of the battery structure after step S110.

[0020] Figure 3 To complete Figure 1 A schematic diagram of the battery structure after step S120.

[0021] Figure 4 To complete Figure 1 A schematic diagram of the battery structure after step S130.

[0022] Figure 5 To complete Figure 1 A schematic diagram of the battery structure after step S140.

[0023] Figure 6 To complete Figure 1 A schematic diagram of the battery structure after step S160.

[0024] Figure 7 To complete Figure 1 A schematic diagram of the battery structure after step S170.

[0025] Figure 8 To complete Figure 1 A schematic diagram of the battery structure after step S180.

[0026] Figure 9 To complete Figure 1 A schematic diagram of the battery structure after step S190.

[0027] Figure 10 This is a schematic diagram of the structural composition of an embodiment of the heterojunction solar cell of the present invention, and also... Figure 1 A schematic diagram of the battery structure after step S200.

[0028] Figure 11 This is a schematic diagram of the composition and structure of another embodiment of the heterojunction solar cell of the present invention, and also for the purpose of completing... Figure 1 A schematic diagram of the battery structure after step S210. Detailed Implementation

[0029] The following specific embodiments illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. Although the description of the present invention is presented in conjunction with preferred embodiments, this does not mean that the features of the invention are limited to these embodiments. On the contrary, the purpose of describing the invention in conjunction with embodiments is to cover other options or modifications that may be derived based on the claims of the present invention. To provide a thorough understanding of the invention, many specific details will be included in the following description. The invention may also be implemented without using these details. Furthermore, to avoid confusion or obscuring the focus of the invention, some specific details will be omitted in the description.

[0030] In the description of this invention, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in this invention based on the specific circumstances.

[0031] Furthermore, the terms "upper," "lower," "left," "right," "top," "bottom," "horizontal," and "vertical" used in the following description should be understood as the orientations shown in the relevant paragraphs and accompanying drawings. These relative terms are for illustrative purposes only and do not imply that the described apparatus must be manufactured or operated in a specific orientation, and therefore should not be construed as limiting the invention.

[0032] It is understood that although terms such as "first," "second," and "third" may be used herein to describe various components, regions, layers, and / or parts, these components, regions, layers, and / or parts should not be limited by these terms, and these terms are only used to distinguish different components, regions, layers, and / or parts. Therefore, the first components, regions, layers, and / or parts discussed below may be referred to as second components, regions, layers, and / or parts without departing from some embodiments of the present invention.

[0033] The microcrystalline silicon layer in the P-type microcrystalline silicon layer and N-type microcrystalline silicon layer of the present invention includes an amorphous silicon layer, a microcrystalline silicon layer, and a mixture layer of amorphous silicon and microcrystalline silicon in any proportion.

[0034] See Figure 1 This is a schematic diagram illustrating the specific process of an embodiment of the fabrication method for a space heterojunction solar cell of the present invention. Figure 1 As shown, in step S10 of the present invention, step S100 is first performed, in which a monocrystalline silicon wafer is provided and texturized and cleaned. In this embodiment, in step S100, the monocrystalline silicon wafer is immersed in a solution of potassium hydroxide and isopropanol at 80°C to 90°C for 2 to 3 minutes, thereby forming a pyramidal textured surface with a size of 0.8 μm to 5 μm on the surface of the monocrystalline silicon wafer. The thickness of the monocrystalline silicon wafer after texturing is 30 μm to 120 μm. The dimensions of the monocrystalline silicon wafer include 210 mm × 210 mm, 182 mm × 182 mm, 182 mm × 91 mm, 182 mm × 45.5 mm, 210 mm × 105 mm, 210 mm × 52.5 mm, 30 mm × 60 mm, and 40 mm × 80 mm.

[0035] The fabrication method of the space heterojunction solar cell continues in step S110, where a first intrinsic amorphous silicon layer and a second intrinsic amorphous silicon layer are formed on the front and back surfaces of the monocrystalline silicon wafer using an intrinsic PECVD process. In this embodiment, in step S110, the first intrinsic amorphous silicon layer and the second intrinsic amorphous silicon layer can be formed simultaneously on the front and back surfaces of the monocrystalline silicon wafer using an intrinsic PECVD process performed in the same PECVD reaction chamber, or the first intrinsic amorphous silicon layer and the second intrinsic amorphous silicon layer can be formed sequentially on the front and back surfaces of the monocrystalline silicon wafer using an intrinsic PECVD process in different PECVD reaction chambers. The thickness of both the first intrinsic amorphous silicon layer and the second intrinsic amorphous silicon layer is 5 nm to 20 nm, and the process gas for the intrinsic PECVD process can be silane or a mixture of silane and hydrogen.

[0036] See Figure 2 It is for completion Figure 1 A schematic diagram of the battery structure after step S110. (See diagram below.) Figure 2 As shown, in step S110, a first intrinsic amorphous silicon layer 21 and a second intrinsic amorphous silicon layer 22 are formed on the front and back sides of the monocrystalline silicon wafer 20, respectively.

[0037] The fabrication method of the space heterojunction solar cell continues in step S120, where an N-type microcrystalline silicon layer is formed on the first intrinsic amorphous silicon layer on the front side of the monocrystalline silicon wafer using an N-type PECVD process. In this embodiment, the process gases in the N-type PECVD process in step S120 include SiH4, H2, and PH3, and also include CO2 or N2O. The radio frequency (RF) power is 2000W to 10000W, the gas volume ratio of PH3 to SiH4 is 1% to 10%, the gas volume ratio of CO2 (N2O) to SiH4 is 0% to 100%, and the thickness of the formed N-type microcrystalline silicon layer is 5nm to 20nm.

[0038] See Figure 3 It is for completion Figure 1 A schematic diagram of the battery structure after step S120. (See diagram below.) Figure 3 As shown, in step S120, an N-type microcrystalline silicon layer 23 is formed on the first intrinsic amorphous silicon layer 21 on the front side of the monocrystalline silicon wafer 20.

[0039] The fabrication method of the space heterojunction solar cell, S10, continues to step S130, where a P-type microcrystalline silicon layer is formed on the second intrinsic amorphous silicon layer on the reverse side of the monocrystalline silicon wafer using a P-type PECVD process. In this embodiment, the process gases for the P-type PECVD process in step S130 include SiH4, H2, and B2H6; the radio frequency (RF) power is 2000W to 10000W; the gas volume ratio of B2H6 to SiH4 is 0.1% to 10%; and the thickness of the P-type microcrystalline silicon layer is 5nm to 30nm.

[0040] See Figure 4 It is for completion Figure 1 A schematic diagram of the battery structure after step S130. (See diagram below.) Figure 4 As shown, in step S130, a P-type microcrystalline silicon layer 24 is formed on the second intrinsic amorphous silicon layer 22 on the reverse side of the monocrystalline silicon wafer 20.

[0041] The fabrication method of the space heterojunction solar cell, S10, continues to step S140, where a single-crystal silicon wafer is supported by a carrier plate with a predetermined mask pattern, with its N-type microcrystalline silicon layer facing down. A first transparent conductive film layer with a predetermined pattern is formed on the N-type microcrystalline silicon layer using a PVD process. The predetermined mask pattern includes dicing lines and edge regions of the single-crystal silicon wafer. In this embodiment, the PVD process is a magnetron sputtering process, the thickness of the first transparent conductive film layer is 70 nm to 110 nm, the width of the dicing lines included in the predetermined mask pattern is 0.2 mm to 0.8 mm, and the width of the edge regions of the single-crystal silicon wafer included in the predetermined mask pattern is 50% to 80% of the width of the dicing lines.

[0042] See Figure 5 It is for completion Figure 1 A schematic diagram of the battery structure after step S140. (See diagram below.) Figure 5 As shown, in step S140, a first transparent conductive film layer 25 is formed on the N-type microcrystalline silicon layer on the front side of the monocrystalline silicon wafer 20. The first transparent conductive film layer 25 is not formed on the slitting line CL, the edge region EL of the monocrystalline silicon wafer, or the side surface.

[0043] The fabrication method of the space heterojunction solar cell S10 then proceeds to step S150, in which the monocrystalline silicon wafer is unloaded from the carrier plate and flipped over so that its P-type microcrystalline silicon layer is placed face down in the carrier plate.

[0044] The fabrication method of the space heterojunction solar cell, S10, continues to step S160, where the monocrystalline silicon wafer is supported by a carrier plate with the predetermined mask pattern, with its P-type microcrystalline silicon layer facing down. A second transparent conductive film layer with the predetermined pattern is formed on the P-type microcrystalline silicon layer using a PVD process. In this embodiment, the PVD process is a magnetron sputtering process, the thickness of the second transparent conductive film layer is 70 nm to 110 nm, the width of the dicing lines included in the predetermined mask pattern is 0.2 mm to 0.8 mm, and the width of the edge region of the monocrystalline silicon wafer included in the predetermined mask pattern is 50% to 80% of the width of the dicing lines.

[0045] See Figure 6 It is for completion Figure 1 A schematic diagram of the battery structure after step S160. (See diagram below.) Figure 6 As shown, in step S160, a second transparent conductive film layer 26 is formed on the P-type microcrystalline silicon layer on the reverse side of the monocrystalline silicon wafer 20. The second transparent conductive film layer 26 is not formed on the slitting line CL, the edge region EL of the monocrystalline silicon wafer, or the side surface.

[0046] The fabrication method of the space heterojunction solar cell S10 then proceeds to step S170, whereby the monocrystalline silicon wafer 20 is cut into multiple monocrystalline silicon sub-wafers along the slicing lines that do not cover the first transparent conductive film 25 and the second transparent conductive film 26.

[0047] See Figure 7 It is for completion Figure 1 A schematic diagram of the battery structure after step S170. (See diagram below.) Figure 7 As shown, the monocrystalline silicon wafer 20 is cut into multiple monocrystalline silicon sub-wafers 20, and the edges and sides of the monocrystalline silicon sub-wafers 20 have cutting damage.

[0048] The fabrication method of the space heterojunction solar cell, S10, continues to step S180, where the edges and sides of multiple monocrystalline silicon wafers are polished and cleaned using an alkaline solution. The alkaline solution in step S180 is a sodium hydroxide or potassium hydroxide solution, which has a higher concentration than the potassium hydroxide solution used to texturize the monocrystalline silicon in step S100.

[0049] See Figure 8 It is for completion Figure 1 A schematic diagram of the battery structure after step S180. (See diagram below.) Figure 8 As shown, the first intrinsic amorphous silicon layer 21 and N-type microcrystalline silicon layer 23, which are not covered by the first transparent conductive film 25, and the second intrinsic amorphous silicon layer 22 and P-type microcrystalline silicon layer 24, which are not covered by the second transparent conductive film 26, are all removed by alkaline polishing.

[0050] The fabrication method of the space heterojunction solar cell, S10, continues to step S190, where a silicon oxide passivation layer is formed on the edge region and sides of the monocrystalline silicon wafer. In step S190, the silicon oxide passivation layer is formed on the edge region and sides of the monocrystalline silicon wafer by placing multiple monocrystalline silicon wafers in a cleaning tank purged with ozone for 1 to 5 minutes. Alternatively, step S190 can be performed by placing multiple monocrystalline silicon wafers in a hydrogen peroxide solution for 1 to 5 minutes to form the silicon oxide passivation layer on the edge region and sides of the monocrystalline silicon wafer. The weight percentage of H2O2 in the hydrogen peroxide solution is 0.5% to 5%.

[0051] See Figure 9 It is for completion Figure 1 A schematic diagram of the battery structure after step S190. (See diagram below.) Figure 9 As shown, a silicon oxide passivation layer 27 is formed on the edge region and side surface of the single-crystal silicon wafer 20. The thickness of the silicon oxide passivation layer is 5 nm to 10 nm.

[0052] The fabrication method of the space heterojunction solar cell, S10, then proceeds to step S200, where a first electrode and a second electrode are formed on the first transparent conductive film and the second transparent conductive film, respectively. In this embodiment, in step S200, silver paste is screen-printed and sintered to form the first electrode and the second electrode.

[0053] See Figure 10 It is for completion Figure 1 A schematic diagram of the battery structure after step S200. (See diagram below.) Figure 10 As shown, in step S200, a first electrode 28 and a second electrode 29 are formed on the first transparent conductive film 25 and the second transparent conductive film 26, respectively.

[0054] When the single-crystal silicon wafer 20 is cut along the slitting line in step S170, cutting damage will be caused. The alkaline solution polishing in step S180 can remove the cutting damage layer. The silicon oxide passivation layer 27 formed in step S190 can passivate dangling bonds and reduce surface recombination. Steps S180 and S190 can improve the cell conversion efficiency by 0.4% to 0.5%.

[0055] See Figure 10 This is the structural composition of an embodiment of the space heterojunction solar cell of the present invention, wherein the space heterojunction solar cell is constructed using, as described above... Figure 1 The method shown is used to fabricate a space heterojunction solar cell. For example... Figure 10As shown, the space heterojunction solar cell 2 includes a monocrystalline silicon wafer 20. On the front side of the monocrystalline silicon wafer 20, a first intrinsic amorphous silicon layer 21, an N-type microcrystalline silicon layer 23, a first transparent conductive film layer 25, and a first electrode 28 are formed sequentially. On the back side of the monocrystalline silicon wafer 20, a second intrinsic amorphous silicon layer 22, a P-type microcrystalline silicon layer 24, a second transparent conductive film layer 26, and a second electrode 29 are formed sequentially. The first intrinsic amorphous silicon layer 21, the N-type microcrystalline silicon layer 23, the second intrinsic amorphous silicon layer 22, the P-type microcrystalline silicon layer 24, and the textured surface on the edge region and side surface of the monocrystalline silicon wafer 20 with a width of 0.2 mm to 0.8 mm are polished off and covered with a silicon oxide passivation layer 27.

[0056] The monocrystalline silicon wafer 20 can be an N-type monocrystalline silicon wafer with a resistivity of 0.5–3 Ω·cm or a P-type monocrystalline silicon wafer with a resistivity of 0.4–1.2 Ω·cm. Its thickness can be 30 μm–120 μm (micrometers), and its size can be commonly used or future standard sizes such as 40×80 mm and 30×60 mm. Except for the edge region and sides with a width of 0.2 mm–0.8 mm, the other surface areas of the monocrystalline silicon wafer 20 have a pyramidal textured surface of 0.8 μm–5 μm. The thickness of the first intrinsic amorphous silicon layer 21 and the second intrinsic amorphous silicon layer 22 can both be 5nm to 20nm, the thickness of the N-type microcrystalline silicon layer 23 is 5nm to 20nm, the thickness of the P-type microcrystalline silicon layer 24 is 5nm to 30nm, and the thickness of the first transparent conductive film layer 25 and the second transparent conductive film layer 26 is 20nm to 110nm. The thickness of the silicon oxide passivation layer 27 is 5nm to 10nm. The first electrode 28 and the second electrode 29 can be formed by screen printing silver paste and sintering, or by electroplating, or by other processes developed in the industry in the future.

[0057] See also Figure 1 The fabrication method S10 of the space heterojunction solar cell can continue to step S210 after step S200, where multiple space heterojunction solar cells are stacked together and amorphous silicon and / or silicon nitride passivation layers are deposited on the edge region and sides of each cell using a PECVD process. In this embodiment, the reaction gases introduced into the PECVD reaction chamber during the deposition of the amorphous silicon passivation layer in step S210 include silane and hydrogen, while the reaction gases introduced into the PECVD reaction chamber during the deposition of the silicon nitride passivation layer include silane, ammonia, and hydrogen and nitrogen.

[0058] See Figure 11 It is for completion Figure 1 A schematic diagram of the battery structure after step S210. (See diagram below.) Figure 11As shown, in step S210, an amorphous silicon and / or silicon nitride passivation layer 30 is formed on the silicon oxide passivation layer 27 on the edge region and side of the single crystal silicon wafer 20.

[0059] Figure 11 This is also the structural composition of another embodiment of the space heterojunction solar cell of the present invention, which is similar to... Figure 10 The difference in the illustrated embodiment is that, Figure 11 In the illustrated embodiment, the silicon oxide passivation layer 27 is further covered with an amorphous silicon and / or silicon nitride passivation layer 30.

[0060] In summary, the fabrication method of the space heterojunction solar cell of the present invention first provides a monocrystalline silicon wafer and performs texturing and cleaning; then, an intrinsic amorphous silicon layer and a second intrinsic amorphous silicon layer are formed on the front and back sides of the monocrystalline silicon wafer respectively using an intrinsic PECVD process; next, an N-type microcrystalline silicon layer is formed on the first intrinsic amorphous silicon layer on the front side of the monocrystalline silicon wafer using an N-type PECVD process; then, a P-type microcrystalline silicon layer is formed on the second intrinsic amorphous silicon layer on the back side of the monocrystalline silicon wafer using a P-type PECVD process; next, the monocrystalline silicon wafer is supported by a carrier plate with a predetermined mask pattern and its N-type microcrystalline silicon layer is facing down, and a first transparent conductive film layer with a predetermined pattern is formed on the N-type microcrystalline silicon layer using a PVD process. The predetermined mask pattern includes dicing lines and edge regions of a monocrystalline silicon wafer. The monocrystalline silicon wafer is then supported by a carrier plate with the predetermined mask pattern, with its P-type microcrystalline silicon layer facing down. A second transparent conductive film layer with the predetermined pattern is formed on the P-type microcrystalline silicon layer using a PVD process. Next, the monocrystalline silicon wafer is diced into multiple monocrystalline silicon sub-wafers along the dicing lines that do not cover the first and second transparent conductive films. The edge regions and sides of the multiple monocrystalline silicon sub-wafers are then polished and cleaned using an alkaline solution. A silicon oxide passivation layer is then formed on the edge regions and sides of the monocrystalline silicon sub-wafers. Finally, a first electrode and a second electrode are formed on the first and second transparent conductive films, respectively. This invention reduces the cost of TCO film removal, avoids ion damage and fluorine residue contamination caused by dry etching of TCO films, effectively removes dicing damage, and improves the bending resistance, electrical performance, and conversion efficiency of batteries and modules.

[0061] The prior description of this disclosure is provided to enable any person skilled in the art to make or use it. Various modifications to this disclosure will be apparent to those skilled in the art, and the general principles defined herein can be applied to other variations without departing from the spirit or scope of this disclosure. Therefore, this disclosure is not intended to be limited to the examples and designs described herein, but should be granted the widest scope consistent with the principles and novel features disclosed herein. The above embodiments are provided to those skilled in the art for implementing or using the invention. Those skilled in the art can make various modifications or changes to the above embodiments without departing from the inventive concept of the invention. Therefore, the scope of protection of the invention is not limited to the above embodiments, but should be the maximum scope conforming to the innovative features mentioned in the claims.

Claims

1. A method for fabricating a space heterojunction solar cell, characterized in that, It includes the following steps: Step 1: Provide monocrystalline silicon wafers and perform texturing and cleaning; Step 2: A first intrinsic amorphous silicon layer and a second intrinsic amorphous silicon layer are formed on the front and back surfaces of the monocrystalline silicon wafer respectively using an intrinsic PECVD process. Step 3: An N-type microcrystalline silicon layer is formed on the first intrinsic amorphous silicon layer on the front side of the monocrystalline silicon wafer using an N-type PECVD process. Step 4: A P-type microcrystalline silicon layer is formed on the second intrinsic amorphous silicon layer on the reverse side of the monocrystalline silicon wafer using a P-type PECVD process. Step 5: The monocrystalline silicon wafer is supported by a carrier plate with a predetermined mask pattern and its N-type microcrystalline silicon layer is facing down. A first transparent conductive film layer with a predetermined pattern is formed on the N-type microcrystalline silicon layer by PVD process. The predetermined mask pattern includes slicing lines and edge areas of the monocrystalline silicon wafer. Step 6: The single-crystal silicon wafer is supported by a carrier plate with the predetermined mask pattern and its P-type microcrystalline silicon layer is facing down. The second transparent conductive film layer with the predetermined pattern is formed on the P-type microcrystalline silicon layer by PVD process. Step 7: Cut the monocrystalline silicon wafer into multiple monocrystalline silicon sub-wafers along the slicing lines that do not cover the first transparent conductive film and the second transparent conductive film; Step 8: Polish the edge areas and sides of multiple single-crystal silicon wafers with an alkaline solution, and then clean them; Step 9: Form a silicon oxide passivation layer on the edge region and side surface of the single-crystal silicon wafer; as well as Step 10: Form a first electrode and a second electrode on the first transparent conductive film and the second transparent conductive film, respectively.

2. The method for fabricating a space heterojunction solar cell according to claim 1, characterized in that, In steps five and six, the width of the dicing lines in the predetermined mask pattern is 0.2 mm to 0.8 mm, the width of the edge region of the monocrystalline silicon wafer in the predetermined mask pattern is 50% to 80% of the width of the dicing lines, the thickness of the first transparent conductive film layer and the second transparent conductive film layer is 20 nm to 110 nm, and the thickness of the first intrinsic amorphous silicon layer and the second intrinsic amorphous silicon layer formed in step two is 5 nm to 20 nm.

3. The method for fabricating a space heterojunction solar cell according to claim 1, characterized in that, The fabrication method of the space heterojunction solar cell further includes step eleven, stacking multiple space heterojunction solar cells together and depositing amorphous silicon and / or silicon nitride passivation layers on the edge region and sides of each cell using a PECVD process. The reaction gases introduced into the PECVD reaction chamber during the deposition of the amorphous silicon passivation layer include silane and hydrogen. The reaction gases introduced into the PECVD reaction chamber during the deposition of the silicon nitride passivation layer include silane, ammonia, hydrogen, and nitrogen.

4. The method for fabricating a space heterojunction solar cell according to claim 1, characterized in that, In step nine, a silicon oxide passivation layer is generated on the edge area and sides of the single-crystal silicon wafers by placing multiple single-crystal silicon wafers in a cleaning tank filled with ozone for 1 to 5 minutes, or by placing multiple single-crystal silicon wafers in a hydrogen peroxide solution for 1 to 5 minutes.

5. The method for fabricating a space heterojunction solar cell according to claim 1, characterized in that, Between steps five and six, there is also step five zero, unloading the monocrystalline silicon wafer from the carrier and flipping the monocrystalline silicon wafer so that its P-type microcrystalline silicon layer is facing down in the carrier.

6. The method for fabricating a space heterojunction solar cell according to claim 1, characterized in that, In step one, the monocrystalline silicon wafer is immersed in a solution of potassium hydroxide and isopropanol at 80℃~90℃ for 2min~3min, thereby forming a pyramidal textured surface with a size of 2μm~5μm on the surface of the monocrystalline silicon wafer. The thickness of the monocrystalline silicon wafer after texturing is 30μm~120μm.

7. The method for fabricating a space heterojunction solar cell according to claim 1, characterized in that, The process gases in the N-type PECVD process in step three include SiH4, H2, and PH3, as well as CO2 or N2O. The RF power is 2000W to 10000W, the gas volume ratio of PH3 to SiH4 is 1% to 10%, the gas volume ratio of CO2 (N2O) to SiH4 is 0% to 100%, and the thickness of the formed N-type microcrystalline silicon layer is 5nm to 20nm.

8. The method for fabricating a space heterojunction solar cell according to claim 1, characterized in that, The process gases for the P-type PECVD process in step four include SiH4, H2, and B2H6. The RF power is 2000W to 10000W, the gas volume ratio of B2H6 to SiH4 is 0.1% to 10%, and the thickness of the P-type microcrystalline silicon layer is 5nm to 30nm.

9. The method for fabricating a space heterojunction solar cell according to claim 1, characterized in that, In step ten, silver paste is screen-printed and sintered to form the first electrode and the second electrode. The PVD processes in steps five and six are both magnetron sputtering processes.

10. A space heterojunction solar cell, characterized in that, The space heterojunction solar cell is manufactured by the method of any one of claims 1 to 9. The space heterojunction solar cell includes a monocrystalline silicon wafer. A first intrinsic amorphous silicon layer, an N-type microcrystalline silicon layer, a first transparent conductive film layer, and a first electrode are sequentially formed on the front side of the monocrystalline silicon wafer. A second intrinsic amorphous silicon layer, a P-type microcrystalline silicon layer, a second transparent conductive film layer, and a second electrode are sequentially formed on the back side of the monocrystalline silicon wafer. The edge region with a width of 0.2 mm to 0.8 mm and the textured surface on the side surface of the monocrystalline silicon wafer are polished off and covered with a silicon oxide passivation layer.

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