Silicon-based germanium photodetector with composite dielectric layer and manufacturing method thereof

Abstract

The application provides a silicon-based germanium photoelectric detector with a composite medium layer and a manufacturing method. A silicon oxide medium layer formed on a silicon substrate comprises a first silicon oxide layer, a second silicon oxide layer and a third silicon oxide layer arranged from bottom to top. The first silicon oxide layer is a thermal silicon oxide layer, the second silicon oxide layer is a high-temperature silicon oxide layer, and the third silicon oxide layer is a high-density plasma chemical vapor deposition silicon oxide layer. The compactness of the second silicon oxide layer is greater than that of the third silicon oxide layer. When HCl etching radicals penetrate downward along micro-pores in the third silicon oxide layer, the second silicon oxide layer can block the downward diffusion of the HCl etching radicals and protect the first silicon oxide layer, so that the interface between the first silicon oxide layer and the silicon substrate is not damaged, thereby avoiding the lateral penetration of the HCl etching radicals along the interface between the first silicon oxide layer and the silicon substrate, i.e., the application can avoid the side etching phenomenon in the process and improve the performance of the device.

Description

Technical Field

[0001] This invention belongs to the field of photoelectric detection technology, and relates to a silicon-based germanium photodetector with a composite dielectric layer and its fabrication method. Background Technology

[0002] At room temperature, silicon has a cutoff wavelength of 1.1 μm, limiting its application in the near-infrared band (1.3–1.5 μm). Ge extends the detector's response wavelength to above 1.55 μm, making it the ideal material for Si-based long-wavelength photodetectors. Among these materials, the crystal quality of germanium directly affects its photoelectric conversion capability, dark current, band gap, carrier mobility, and device stability. To ensure the performance and reliability of silicon-based germanium photodetectors, the quality of pure germanium epitaxial crystals becomes crucial to device performance.

[0003] Currently, the steps involved in forming a silicon-based germanium photodetector include:

[0004] (i) A silicon oxide dielectric layer is formed on a silicon substrate, the silicon oxide dielectric layer including a thermally oxidized silicon oxide layer formed by thermal oxidation of the upper surface of the silicon substrate and a high-density plasma chemical vapor deposition silicon oxide layer (HDP-CVD Oxide) formed on the thermally oxidized silicon oxide layer by a deposition process.

[0005] (ii) The silicon oxide dielectric layer and the silicon substrate are etched by photolithography, etching and other processes to form a dielectric layer trench in the silicon oxide dielectric layer and a silicon trench in the silicon substrate below the dielectric layer trench.

[0006] (iii) The structure after the silicon groove is formed is baked using a baking process, and the surface of the baked structure is treated with hydrogen chloride (HCl);

[0007] (iv) A germanium epitaxial layer is formed in a silicon trench and a dielectric layer trench using a selective epitaxial growth method. During the formation of the germanium epitaxial layer, the introduced gas includes germanane and hydrogen chloride. Hydrogen chloride is used to remove the germanium nucleated on the silicon oxide dielectric layer, so that germanium is formed only on silicon, thereby achieving selective epitaxial growth of germanium.

[0008] The thermally oxidized silicon layer is formed by thermal oxidation of the upper surface of the silicon substrate. The thermally oxidized silicon layer and the silicon substrate have a relatively good interface. The HDP-CVD oxide contains micropores and dangling bonds introduced by plasma bombardment, resulting in a relatively porous film. During surface treatment with HCl and selective epitaxial growth of germane, HCl etching components can reach the thermally oxidized silicon layer along the micropores in the HDP-CVD oxide, damaging the thermally oxidized silicon layer and consequently the interface between the thermally oxidized silicon layer and the silicon substrate. This causes the HCl etching components to easily penetrate laterally along the interface, corroding the single-crystal silicon on the trench sidewalls. Simultaneously, under high temperature and low pressure conditions, silicon atoms can migrate, forming side-holes.Figure 1 The image shown is an electron microscope image of the side-penetration phenomenon. The area within the dashed box represents the region where the side-penetration phenomenon occurs. Side-penetration can adversely affect the electrical performance and reliability of the device.

[0009] Therefore, how to provide a silicon-based germanium photodetector with a composite dielectric layer and its fabrication method to avoid side-hole phenomenon and improve device performance has become a technical problem that urgently needs to be solved by those skilled in the art.

[0010] It should be noted that the above introduction to the technical background is only for the purpose of providing a clear and complete explanation of the technical solutions of this application and facilitating understanding by those skilled in the art. It should not be assumed that these technical solutions are known to those skilled in the art simply because they have been described in the background section of this application. Summary of the Invention

[0011] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide a silicon-based germanium photodetector with a composite dielectric layer and a method for fabricating it, so as to solve the problem of low performance of silicon-based germanium photodetectors caused by the side-penetration phenomenon in the prior art.

[0012] To achieve the above and other related objectives, the present invention provides a method for fabricating a silicon-based germanium photodetector with a composite dielectric layer, comprising the following steps:

[0013] A silicon substrate is provided, and a silicon oxide dielectric layer is formed on the silicon substrate. The silicon oxide dielectric layer includes a first silicon oxide layer, a second silicon oxide layer, and a third silicon oxide layer disposed from bottom to top, wherein the first silicon oxide layer is a thermal silicon oxide layer, the second silicon oxide layer is a high-temperature silicon oxide layer, and the third silicon oxide layer is a high-density plasma chemical vapor deposition silicon oxide layer.

[0014] The silicon oxide dielectric layer is etched to form a dielectric layer trench in the silicon oxide dielectric layer, the dielectric layer trench penetrating the silicon oxide dielectric layer, and the silicon substrate located below the dielectric layer trench is etched to form a silicon trench in the silicon substrate;

[0015] A germanium epitaxial layer is formed in the silicon trench and the dielectric layer trench using a selective epitaxial growth method.

[0016] Optionally, the thickness of the first silicon oxide layer ranges from 110 to 1000 Å, the thickness of the second silicon oxide layer ranges from 500 to 1000 Å, and the thickness of the third silicon oxide layer ranges from 1000 to 3000 Å.

[0017] Optionally, the germanium epitaxial layer includes a first germanium epitaxial layer, a second germanium epitaxial layer, and a third germanium epitaxial layer disposed from bottom to top, and the step of forming the germanium epitaxial layer includes:

[0018] The first germanium epitaxial layer is formed in a temperature range of 350~450℃;

[0019] The second germanium epitaxial layer is formed in a temperature range of 350~650℃, wherein, during the formation of the second germanium epitaxial layer, the deposition temperature is increased from the first temperature to the second temperature at a preset heating rate;

[0020] The third germanium epitaxial layer is formed in a temperature range of 650~750°C, wherein the gas used to form the third germanium epitaxial layer includes germanane and hydrogen chloride.

[0021] Optionally, before forming the germanium epitaxial layer, the following steps are further included:

[0022] The structure after the silicon groove is formed is baked to remove carbon / oxygen from the surface;

[0023] The baked structure was surface-treated with hydrogen chloride to further remove carbon / oxygen from the surface.

[0024] Optionally, before forming the silicon oxide dielectric layer on the silicon substrate, the method further includes the step of forming a first conductivity type doped region and a second conductivity type doped region in the silicon substrate, wherein the first conductivity type doped region and the second conductivity type doped region are separately disposed on both sides of the germanium epitaxial layer; after forming the germanium epitaxial layer in the silicon trench and the dielectric layer trench, the method further includes the following steps:

[0025] An insulating dielectric layer is formed on the silicon oxide dielectric layer, and the insulating dielectric layer covers the germanium epitaxial layer, wherein the insulating dielectric layer is a high-density plasma chemical vapor deposition silicon oxide layer;

[0026] A first contact hole is formed penetrating the insulating dielectric layer and the silicon oxide dielectric layer, the first contact hole exposing the first conductivity type doped region; a second contact hole is formed penetrating the insulating dielectric layer and the silicon oxide dielectric layer, the second contact hole exposing the second conductivity type doped region.

[0027] A first metal layer is formed by filling the first contact hole with metal, and a second metal layer is formed by filling the second contact hole with metal. The first metal layer is electrically connected to the first conductivity type doped region, and the second metal layer is electrically connected to the second conductivity type doped region.

[0028] Optionally, the silicon substrate is the top silicon layer in an SOI wafer.

[0029] The present invention also provides a silicon-based germanium photodetector having a composite dielectric layer, comprising:

[0030] silicon substrate;

[0031] A silicon oxide dielectric layer is located above the silicon substrate. The silicon oxide dielectric layer includes a first silicon oxide layer, a second silicon oxide layer, and a third silicon oxide layer disposed from bottom to top. The first silicon oxide layer is a thermal silicon oxide layer, the second silicon oxide layer is a high-temperature silicon oxide layer, and the third silicon oxide layer is a high-density plasma chemical vapor deposition silicon oxide layer.

[0032] A dielectric layer groove is located in the silicon oxide dielectric layer and penetrates the silicon oxide dielectric layer;

[0033] A silicon trench, located in the silicon substrate below the dielectric layer trench;

[0034] A germanium epitaxial layer is located in the silicon trench and in the dielectric layer trench.

[0035] Optionally, the thickness of the first silicon oxide layer ranges from 110 to 1000 Å, the thickness of the second silicon oxide layer ranges from 500 to 1000 Å, and the thickness of the third silicon oxide layer ranges from 1000 to 3000 Å.

[0036] Optionally, it also includes:

[0037] A first conductivity type doped region is located in the silicon substrate;

[0038] A second conductivity type doped region is located in the silicon substrate, wherein the first conductivity type doped region and the second conductivity type doped region are separately disposed on both sides of the germanium epitaxial layer;

[0039] An insulating dielectric layer is located above the silicon oxide dielectric layer, and the insulating dielectric layer covers the germanium epitaxial layer, wherein the insulating dielectric layer is a high-density plasma chemical vapor deposition silicon oxide layer;

[0040] A first metal layer extends through the insulating dielectric layer and the silicon oxide dielectric layer to be electrically connected to the first conductivity type doped region;

[0041] A second metal layer extends through the insulating dielectric layer and the silicon oxide dielectric layer to be electrically connected to the doped region of the second conductivity type.

[0042] Optionally, the silicon substrate is the top silicon layer in an SOI wafer.

[0043] As described above, in the silicon-based germanium photodetector and fabrication method with a composite dielectric layer of the present invention, the silicon oxide dielectric layer formed on the silicon substrate includes a first silicon oxide layer, a second silicon oxide layer, and a third silicon oxide layer from bottom to top. The first silicon oxide layer is a thermally oxidized silicon oxide layer formed by thermal oxidation of the upper surface of the silicon substrate. Its film is dense, chemically stable, and pore-free, and the defect density at its interface with the substrate is extremely low. The second silicon oxide layer is a high-temperature silicon oxide layer formed by chemical vapor deposition under high-temperature conditions. The third silicon oxide layer is a silicon oxide layer formed by high-density plasma chemical vapor deposition. The density of the silicon layer is greater than that of the third silicon oxide layer. During the surface treatment with HCl and the formation of the germanium epitaxial layer, HCl etching radicals penetrate downwards along the micropores in the third silicon oxide layer. Due to the blocking effect of the second silicon oxide layer, the downward diffusion of HCl etching radicals can be prevented, protecting the first silicon oxide layer and thus preventing damage to the interface between the first silicon oxide layer and the silicon substrate. This avoids the HCl etching radicals laterally penetrating and corroding the single-crystal silicon on the sidewall of the silicon trench along the interface between the first silicon oxide layer and the silicon substrate. In other words, this application can avoid the side-penetration phenomenon during the process and improve the performance of the device. Attached Figure Description

[0044] Figure 1 The image shown is an electron microscope image depicting the formation of a side-cutting phenomenon.

[0045] Figure 2 The diagram shown is a flowchart of the fabrication method of a silicon-based germanium photodetector with a composite dielectric layer in an embodiment of the present invention.

[0046] Figure 3 The diagram shown is a schematic diagram of a silicon oxide dielectric layer formed on a silicon substrate in an embodiment of the present invention.

[0047] Figure 4 The diagram shown illustrates the formation of dielectric layer grooves and silicon grooves in an embodiment of the present invention.

[0048] Figure 5 The diagram shown is a schematic diagram of the formation of a germanium epitaxial layer in an embodiment of the present invention.

[0049] Figure 6 The image shown is an electron microscope image after the formation of the germanium epitaxial layer in an embodiment of the present invention.

[0050] Figure 7 The diagram shown is a schematic diagram of the formation of an insulating dielectric layer in an embodiment of the present invention.

[0051] Figure 8 The diagram shown illustrates the formation of the first and second contact holes in an embodiment of the present invention.

[0052] Figure 9 The diagram shown illustrates the formation of the first metal layer and the second metal layer in an embodiment of the present invention.

[0053] Component labeling: 1-SOI wafer, 100-substrate silicon layer, 101-intermediate buried oxide layer, 102-top silicon layer; 2-first conductivity type doped region; 3-second conductivity type doped region; 4-silicon oxide dielectric layer, 400-first silicon oxide layer, 401-second silicon oxide layer, 402-third silicon oxide layer; 5-dielectric layer trench; 6-silicon trench; 7-germanium epitaxial layer; 8-insulating dielectric layer; 9-first contact hole; 10-second contact hole; 11-first metal layer; 12-second metal layer; S1~S3-steps. Detailed Implementation

[0054] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0055] It should be emphasized that the term "including / comprises" as used herein refers to the presence of a feature, whole, step, or component, but does not exclude the presence or addition of one or more other features, wholes, steps, or components.

[0056] In the detailed description of embodiments of the present invention, for ease of explanation, the cross-sectional views illustrating the device structure may be partially enlarged and not to scale. Furthermore, the schematic diagrams are merely examples and should not limit the scope of protection of the present invention. In actual fabrication, the three-dimensional spatial dimensions of length, width, and depth should be included.

[0057] In the context of this application, the structure described above the first feature may include embodiments in which the first feature and the second feature are in direct contact, or embodiments in which an additional feature is disposed between the first feature and the second feature, such that the first feature and the second feature may not be in direct contact.

[0058] Please see Figures 2 to 9 It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the drawings only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0059] This embodiment provides a method for fabricating a silicon-based germanium photodetector with a composite dielectric layer. Please refer to [link to relevant documentation]. Figure 2 The diagram shows a flowchart of a method for fabricating a silicon-based germanium photodetector with a composite dielectric layer according to an embodiment of the present invention, including the following steps:

[0060] S1: Provide a silicon substrate and form a silicon oxide dielectric layer on the silicon substrate. The silicon oxide dielectric layer includes a first silicon oxide layer, a second silicon oxide layer and a third silicon oxide layer disposed from bottom to top. The first silicon oxide layer is a thermal silicon oxide layer, the second silicon oxide layer is a high-temperature silicon oxide layer, and the third silicon oxide layer is a high-density plasma chemical vapor deposition silicon oxide layer.

[0061] S2: Etch the silicon oxide dielectric layer to form a dielectric layer trench in the silicon oxide dielectric layer, the dielectric layer trench penetrating the silicon oxide dielectric layer, and etch the silicon substrate located below the dielectric layer trench to form a silicon trench in the silicon substrate;

[0062] S3: A germanium epitaxial layer is formed in the silicon trench and the dielectric layer trench using a selective epitaxial growth method.

[0063] The fabrication method of the silicon-based germanium photodetector with a composite dielectric layer in this embodiment will be described in detail below with reference to the specific accompanying drawings.

[0064] First, please refer to Figure 3 Step S1: Provide a silicon substrate and form a silicon oxide dielectric layer 4 on the silicon substrate. The silicon oxide dielectric layer 4 includes a first silicon oxide layer 400, a second silicon oxide layer 401, and a third silicon oxide layer 402 disposed from bottom to top. The first silicon oxide layer 400 is a thermal silicon oxide layer, the second silicon oxide layer 401 is a high-temperature silicon oxide layer, and the third silicon oxide layer 402 is a high-density plasma chemical vapor deposition silicon oxide layer.

[0065] As an example, in this embodiment, the silicon substrate is the top silicon layer 102 of SOI wafer 1 (silicon-on-insulator wafer). SOI wafer 1 includes a base silicon layer 100, an intermediate buried oxide layer 101, and a top silicon layer 102 arranged from bottom to top. Using SOI wafer 1 as the supporting substrate for the detector, the intermediate buried oxide layer 101 provides good electrical isolation, effectively reducing parasitic capacitance and leakage current between the device and the base silicon layer 100, thus improving the detector's response speed and sensitivity. Furthermore, SOI wafers support the integration of various passive devices (such as waveguides, gratings, and couplers) and active devices (such as modulators and detectors) on the same substrate, which is beneficial for realizing complex photonic integrated circuits. In another example, the silicon substrate can also be a silicon wafer, and this embodiment is not a limitation.

[0066] As an example, before forming the silicon oxide dielectric layer 4 on the silicon substrate, the method further includes forming a first conductivity type doped region 2 and a second conductivity type doped region 3 in the top silicon layer 102, wherein the first conductivity type doped region 2 and the second conductivity type doped region 3 have opposite conductivity types. For example, the first conductivity type doped region 2 is a P-type doped region and the second conductivity type doped region 3 is an N-type doped region, or the first conductivity type doped region 2 is an N-type doped region and the second conductivity type doped region 3 is a P-type doped region. Specifically, in this embodiment, the first conductivity type doped region 2 is a P-type doped region and the second conductivity type doped region 3 is an N-type doped region.

[0067] As an example, after forming the first conductivity type doped region 2 and the second conductivity type doped region 3, the silicon oxide dielectric layer 4 is formed on the silicon substrate.

[0068] As an example, the first silicon oxide layer 400 is a thermal oxide layer formed by thermal oxidation of the upper surface of the silicon substrate. Its film is dense, chemically stable, and pore-free. Furthermore, the defect density at the interface between it and the substrate is extremely low. It is the bottom layer of the three-layer stacked structure in the silicon oxide dielectric layer 4.

[0069] As an example, the second silicon oxide layer 401 is a high-temperature silicon oxide layer formed by chemical vapor deposition under high temperature conditions, and its density is better than that of the third silicon oxide layer 402. In this embodiment, the second silicon oxide layer 401 is formed by furnace tube growth method, and the temperature range for forming the second silicon oxide layer 401 is 700~900℃.

[0070] As an example, the third silicon oxide layer 402 is a silicon oxide layer deposited by high-density plasma chemical vapor deposition (HDP-CVD Oxide). Due to the presence of micropores and dangling bonds introduced by plasma bombardment, its density is less than that of the second silicon oxide layer 401.

[0071] As an example, the thickness of the first silicon oxide layer 400 ranges from 110 to 1000 Å, for example, it can be 110 Å, 200 Å, 300 Å, 400 Å, 500 Å, 600 Å, 700 Å, 800 Å, 900 Å, 1000 Å, etc., and can be selected according to the requirements.

[0072] As an example, the thickness of the second silicon oxide layer 401 ranges from 500 to 1000 Å, for example, it can be 500 Å, 600 Å, 700 Å, 800 Å, 900 Å, 1000 Å, etc., and can be selected according to the requirements.

[0073] As an example, the thickness of the third silicon oxide layer 402 ranges from 1000 to 3000 Å, for example, it can be 1000 Å, 1500 Å, 2000 Å, 2500 Å, 3000 Å, etc., and can be selected according to the requirements.

[0074] Next, please refer to 4 and perform step S2: etch the silicon oxide dielectric layer 4 to form a dielectric layer groove 5 in the silicon oxide dielectric layer 4, the dielectric layer groove 5 penetrating the silicon oxide dielectric layer 4, and etch the silicon substrate located below the dielectric layer groove 5 to form a silicon groove 6 in the silicon substrate.

[0075] As an example, the steps of forming the dielectric layer trench 5 and the silicon trench 6 include:

[0076] (i) A photoresist layer is formed and patterned on the structure after the formation of the silicon oxide dielectric layer 4, and the patterned photoresist layer defines the positions of the dielectric layer groove 5 and the silicon groove 6;

[0077] (ii) Using the patterned photoresist layer as a mask, the silicon oxide dielectric layer 4 is etched using a dry etching process to form the dielectric layer groove 5;

[0078] (iii) The silicon substrate is etched using a dry etching process to form the silicon trench 6.

[0079] As an example, in one example, the silicon oxide dielectric layer 4 and the silicon substrate are etched using the same etching process, for example, using CF4, O2, and Ar as etching gases to etch the silicon oxide dielectric layer 4 and the silicon substrate to form the dielectric layer trench 5 and the silicon trench 6; in another example, the silicon oxide dielectric layer 4 and the silicon substrate are etched using different etching processes, for example, using CF4, O2, and Ar as etching gases to etch the silicon oxide dielectric layer 4 to form the dielectric layer trench 5, and then using CF4, SF6, and Ar as etching gases to etch the silicon substrate to form the silicon trench 6. Specifically, the etching process for forming the dielectric layer trench 5 and the silicon trench 6 is selected according to requirements and is not limited to this embodiment.

[0080] As an example, if the patterned photoresist layer is completely consumed during the formation of the dielectric trench 5 and the silicon trench 6, then no additional step of removing the photoresist layer is required after the formation of the dielectric trench 5 and the silicon trench 6; if the patterned photoresist layer is not completely consumed during the formation of the dielectric trench 5 and the silicon trench 6, then an additional step of removing the photoresist layer is required after the formation of the dielectric trench 5 and the silicon trench 6.

[0081] Next, please refer to Figure 5 Step S3: Using selective epitaxial growth, a germanium epitaxial layer 7 is formed in the silicon trench 6 and the dielectric layer trench 5.

[0082] As an example, before forming the germanium epitaxial layer 7, the following steps are also included:

[0083] (i) The structure after forming the silicon groove 6 is baked to remove carbon / oxygen from the surface; specifically, the baking temperature range is 850~880℃;

[0084] (ii) The baked structure is surface treated with hydrogen chloride (HCl) to further remove carbon / oxygen from the surface; specifically, HCl gas is introduced into the process chamber for surface treatment to remove carbon / oxygen from the surface.

[0085] As an example, during the baking process, HCl can be introduced to utilize the etching properties of HCl and adjust the morphology of the silicon groove 6 as needed.

[0086] As an example, the germanium epitaxial layer 7 includes a first germanium epitaxial layer, a second germanium epitaxial layer, and a third germanium epitaxial layer disposed from bottom to top, and the steps for forming the germanium epitaxial layer 7 include:

[0087] (i) The first germanium epitaxial layer is formed in a temperature range of 350~450℃, that is, the first germanium epitaxial layer is a germanium epitaxial layer grown at low temperature;

[0088] (ii) The second germanium epitaxial layer is formed in a temperature range of 350~650℃, wherein, during the formation of the second germanium epitaxial layer, the deposition temperature is increased from the first temperature to the second temperature at a preset heating rate, that is, the second germanium epitaxial layer is a dynamically grown germanium epitaxial layer; in this embodiment, when forming the second germanium epitaxial layer, the deposition temperature is increased from 350℃ to 650℃ at a heating rate of 1.5℃ / s~2.5℃ / s.

[0089] (iii) The third germanium epitaxial layer is formed in a temperature range of 650~750℃, wherein the gas used to form the third germanium epitaxial layer includes germanane and hydrogen chloride, that is, the third germanium epitaxial layer is a germanium epitaxial layer grown at high temperature.

[0090] As an example, during the formation of the germanium epitaxial layer 7, when the germanium epitaxial layer is grown at low temperature, the activation energy of the dielectric layer is low and nucleation is difficult, so there is no need to introduce HCl. When the germanium epitaxial layer is grown dynamically, the flow rate of germane is very low, about 1 / 20 of the flow rate of germane in the low temperature growth stage / high temperature growth stage, so nucleation is difficult on the surface of the dielectric layer, so there is no need to introduce HCl. When the germanium epitaxial layer is grown at high temperature, nucleation will occur on the surface of the dielectric layer without the introduction of HCl. Introducing HCl can inhibit the nucleation of germanium on silicon oxide, so that germanium only nucleates and grows in the silicon trench 6, achieving selective epitaxial growth of germanium. As the thickness of germanium in the silicon trench 6 increases, the formed germanium epitaxial layer 7 extends into the dielectric layer trench 5.

[0091] As an example, in this application, since the silicon oxide dielectric layer 4 includes a first silicon oxide layer 400 (Thermal Oxide), a second silicon oxide layer 401 (High Temperature Oxide), and a third silicon oxide layer 402 (HDP-CVD Oxide) from bottom to top, and the density of the second silicon oxide layer 401 is greater than that of the third silicon oxide layer 402, during the surface treatment with HCl and the formation of the germanium epitaxial layer, HCl etching radicals penetrate downwards along the micropores in the third silicon oxide layer 402. Due to the blocking effect of the second silicon oxide layer 401, the HCl etching radicals can be prevented from diffusing downwards, protecting the first silicon oxide layer 400, and thus preventing damage to the interface between the first silicon oxide layer 400 and the silicon substrate. This avoids HCl etching radicals laterally penetrating and corroding the single-crystal silicon on the sidewall of the silicon trench 6 along the interface between the first silicon oxide layer 400 and the silicon substrate. In other words, this application can avoid the side-penetration phenomenon during the process and improve the performance of the device.

[0092] For example, please refer to Figure 6 The image shown is an electron microscope image of the germanium epitaxial layer formed in an embodiment of the present invention. Figure 6 It is known that no side-cutting phenomenon was formed during the process of this application. Since the first silicon oxide layer 400, the second silicon oxide layer 401 and the third silicon oxide layer 402 in the silicon oxide dielectric layer 4 are all made of silicon oxide, they are difficult to distinguish in electron microscope images.

[0093] As an example, in this application, the upper surface of the germanium epitaxial layer 7 is an arc-shaped surface, which can increase the light absorption area and ensure the responsivity of the device.

[0094] As an example, after forming the germanium epitaxial layer 7, the following steps are also included:

[0095] S4: As Figure 7As shown, an insulating dielectric layer 8 is formed on the silicon oxide dielectric layer 4, and the insulating dielectric layer 8 covers the germanium epitaxial layer 7; in this embodiment, the insulating dielectric layer 8 is a high-density plasma chemical vapor deposition silicon oxide layer (HDP-CVD Oxide).

[0096] S5: As Figure 8 As shown, a first contact hole 9 is formed that penetrates the insulating dielectric layer 8 and the silicon oxide dielectric layer 4, exposing the first conductivity type doped region 2. A second contact hole 10 is formed that penetrates the insulating dielectric layer 8 and the silicon oxide dielectric layer 4, exposing the second conductivity type doped region 3.

[0097] S6: As Figure 9 As shown, a first metal layer 11 is formed by filling the first contact hole 9 with metal, and a second metal layer 12 is formed by filling the second contact hole 10 with metal. The first metal layer 11 is electrically connected to the first conductivity type doped region 2, and the second metal layer 12 is electrically connected to the second conductivity type doped region 3.

[0098] As an example, since the germanium epitaxial layer 7 is not flat, the insulating dielectric layer 8 is a high-density plasma chemical vapor deposition silicon oxide layer, which utilizes its excellent filling ability to fill and cover the germanium epitaxial layer 7; both the insulating dielectric layer 8 and the third silicon oxide layer 402 are high-density plasma chemical vapor deposition silicon oxide layers, which have excellent bonding ability, avoid delamination between the two, and improve the filling and covering effect of the insulating dielectric layer 8.

[0099] Thus, a silicon-based germanium photodetector with a composite dielectric layer has been fabricated. The silicon-based germanium photodetector with a composite dielectric layer includes a silicon substrate, a silicon oxide dielectric layer 4, a dielectric layer groove 5, a silicon groove 6, and a germanium epitaxial layer 7. The silicon oxide dielectric layer 4 is located above the silicon substrate and includes a first silicon oxide layer 400, a second silicon oxide layer 401, and a third silicon oxide layer 402 disposed from bottom to top. The first silicon oxide layer 400 is a thermal silicon oxide layer, the second silicon oxide layer 401 is a high-temperature silicon oxide layer, and the third silicon oxide layer 402 is a high-density plasma chemical vapor deposition silicon oxide layer. The dielectric layer groove 5 is located in the silicon oxide dielectric layer 4 and penetrates the silicon oxide dielectric layer 4. The silicon groove 6 is located in the silicon substrate below the dielectric layer groove 5. The germanium epitaxial layer 7 is located in the silicon groove 6 and is also located in the dielectric layer groove 5.

[0100] As an example, in this embodiment, the silicon substrate is the top silicon layer 102 of SOI wafer 1 (silicon-on-insulator wafer). SOI wafer 1 includes a base silicon layer 100, an intermediate buried oxide layer 101, and a top silicon layer 102 arranged from bottom to top. Using SOI wafer 1 as the supporting substrate for the detector, the intermediate buried oxide layer 101 provides good electrical isolation, effectively reducing parasitic capacitance and leakage current between the device and the base silicon layer 100, thus improving the detector's response speed and sensitivity. Furthermore, SOI wafers support the integration of various passive devices (such as waveguides, gratings, and couplers) and active devices (such as modulators and detectors) on the same substrate, which is beneficial for realizing complex photonic integrated circuits. In another example, the silicon substrate can also be a silicon wafer, and this embodiment is not a limitation.

[0101] As an example, the system also includes a first conductivity type doped region 2 and a second conductivity type doped region 3, which are located in the silicon substrate and are separately disposed on opposite sides of the germanium epitaxial layer 7. The first conductivity type doped region 2 is electrically connected to the germanium epitaxial layer 7, and the second conductivity type doped region 3 is electrically connected to the germanium epitaxial layer 7. The first conductivity type doped region 2 and the second conductivity type doped region 3 have opposite conductivity types. For example, the first conductivity type doped region 2 is a P-type doped region, and the second conductivity type doped region 3 is an N-type doped region, or the first conductivity type doped region 2 is an N-type doped region, and the second conductivity type doped region 3 is a P-type doped region. Specifically, in this embodiment, the first conductivity type doped region 2 is a P-type doped region, and the second conductivity type doped region 3 is an N-type doped region.

[0102] As an example, the first silicon oxide layer 400 is a thermal oxide layer formed by thermal oxidation of the upper surface of the silicon substrate. Its film is dense, chemically stable, and pore-free. Furthermore, the defect density at the interface between it and the substrate is extremely low. It is the bottom layer of the three-layer stacked structure in the silicon oxide dielectric layer 4.

[0103] As an example, the second silicon oxide layer 401 is a high-temperature silicon oxide layer formed by chemical vapor deposition under high temperature conditions, and its density is better than that of the third silicon oxide layer 402.

[0104] As an example, the third silicon oxide layer 402 is a silicon oxide layer deposited by high-density plasma chemical vapor deposition (HDP-CVD Oxide). Due to the presence of micropores and dangling bonds introduced by plasma bombardment, its density is less than that of the second silicon oxide layer 401.

[0105] As an example, the thickness of the first silicon oxide layer 400 ranges from 110 to 1000 Å, for example, it can be 110 Å, 200 Å, 300 Å, 400 Å, 500 Å, 600 Å, 700 Å, 800 Å, 900 Å, 1000 Å, etc., and can be selected according to the requirements.

[0106] As an example, the thickness of the second silicon oxide layer 401 ranges from 500 to 1000 Å, for example, it can be 500 Å, 600 Å, 700 Å, 800 Å, 900 Å, 1000 Å, etc., and can be selected according to the requirements.

[0107] As an example, the thickness of the third silicon oxide layer 402 ranges from 1000 to 3000 Å, for example, it can be 1000 Å, 1500 Å, 2000 Å, 2500 Å, 3000 Å, etc., and can be selected according to the requirements.

[0108] As an example, it also includes:

[0109] An insulating dielectric layer 8 is located above the silicon oxide dielectric layer 4, and the insulating dielectric layer 8 covers the germanium epitaxial layer 7; in this embodiment, the insulating dielectric layer 8 is a high-density plasma chemical vapor deposition silicon oxide layer.

[0110] The first metal layer 11 penetrates the insulating dielectric layer 8 and the silicon oxide dielectric layer 4 to be electrically connected to the first conductivity type doped region 2.

[0111] The second metal layer 12 penetrates the insulating dielectric layer 8 and the silicon oxide dielectric layer 4 to be electrically connected to the second conductivity type doped region 3.

[0112] In summary, in the silicon-based germanium photodetector and fabrication method with a composite dielectric layer of the present invention, the silicon oxide dielectric layer formed on the silicon substrate includes a first silicon oxide layer, a second silicon oxide layer, and a third silicon oxide layer from bottom to top. The first silicon oxide layer is a thermally oxidized silicon oxide layer formed by thermal oxidation of the upper surface of the silicon substrate. Its film is dense, chemically stable, and pore-free, and the defect density at its interface with the substrate is extremely low. The second silicon oxide layer is a high-temperature silicon oxide layer formed by chemical vapor deposition under high-temperature conditions. The third silicon oxide layer is a silicon oxide layer formed by high-density plasma chemical vapor deposition. The silicon layer has a higher density than the third silicon oxide layer. During surface treatment with HCl and the formation of the germanium epitaxial layer, HCl etching radicals penetrate downwards along the micropores in the third silicon oxide layer. Due to the blocking effect of the second silicon oxide layer, the downward diffusion of HCl etching radicals is prevented, protecting the first silicon oxide layer and thus preventing damage to the interface between the first silicon oxide layer and the silicon substrate. This avoids HCl etching radicals laterally penetrating and corroding the single-crystal silicon on the sidewalls of the silicon trench along the interface between the first silicon oxide layer and the silicon substrate. In other words, this application can avoid side-penetration during the process, improving device performance. Therefore, this invention effectively overcomes the various shortcomings of the prior art and has high industrial applicability.

[0113] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A method for fabricating a silicon-based germanium photodetector with a composite dielectric layer, characterized in that, Includes the following steps: A silicon substrate is provided, and a silicon oxide dielectric layer is formed on the silicon substrate. The silicon oxide dielectric layer includes a first silicon oxide layer, a second silicon oxide layer, and a third silicon oxide layer disposed from bottom to top, wherein the first silicon oxide layer is a thermal silicon oxide layer, the second silicon oxide layer is a high-temperature silicon oxide layer, and the third silicon oxide layer is a high-density plasma chemical vapor deposition silicon oxide layer. The silicon oxide dielectric layer is etched to form a dielectric layer trench in the silicon oxide dielectric layer, the dielectric layer trench penetrating the silicon oxide dielectric layer, and the silicon substrate located below the dielectric layer trench is etched to form a silicon trench in the silicon substrate; A germanium epitaxial layer is formed in the silicon trench and the dielectric layer trench using a selective epitaxial growth method.

2. The method for fabricating a silicon-based germanium photodetector with a composite dielectric layer according to claim 1, characterized in that: The thickness of the first silicon oxide layer ranges from 110 to 1000 Å, the thickness of the second silicon oxide layer ranges from 500 to 1000 Å, and the thickness of the third silicon oxide layer ranges from 1000 to 3000 Å.

3. The method for fabricating a silicon-based germanium photodetector with a composite dielectric layer according to claim 1, characterized in that, The germanium epitaxial layer includes a first germanium epitaxial layer, a second germanium epitaxial layer, and a third germanium epitaxial layer disposed from bottom to top. The steps for forming the germanium epitaxial layer include: The first germanium epitaxial layer is formed in a temperature range of 350~450℃; The second germanium epitaxial layer is formed in a temperature range of 350~650℃, wherein, during the formation of the second germanium epitaxial layer, the deposition temperature is increased from the first temperature to the second temperature at a preset heating rate; The third germanium epitaxial layer is formed in a temperature range of 650~750°C, wherein the gas used to form the third germanium epitaxial layer includes germanane and hydrogen chloride.

4. The method for fabricating a silicon-based germanium photodetector with a composite dielectric layer according to claim 1, characterized in that, Before forming the germanium epitaxial layer, the following steps are also included: The structure after the silicon groove is formed is baked to remove carbon / oxygen from the surface; The baked structure was surface-treated with hydrogen chloride to further remove carbon / oxygen from the surface.

5. The method for fabricating a silicon-based germanium photodetector with a composite dielectric layer according to claim 1, characterized in that, Before forming the silicon oxide dielectric layer on the silicon substrate, the method further includes the step of forming a first conductivity type doped region and a second conductivity type doped region in the silicon substrate, wherein the first conductivity type doped region and the second conductivity type doped region are separately disposed on both sides of the germanium epitaxial layer; after forming the germanium epitaxial layer in the silicon trench and the dielectric layer trench, the method further includes the following steps: An insulating dielectric layer is formed on the silicon oxide dielectric layer, and the insulating dielectric layer covers the germanium epitaxial layer, wherein the insulating dielectric layer is a high-density plasma chemical vapor deposition silicon oxide layer; A first contact hole is formed penetrating the insulating dielectric layer and the silicon oxide dielectric layer, the first contact hole exposing the first conductivity type doped region; a second contact hole is formed penetrating the insulating dielectric layer and the silicon oxide dielectric layer, the second contact hole exposing the second conductivity type doped region. A first metal layer is formed by filling the first contact hole with metal, and a second metal layer is formed by filling the second contact hole with metal. The first metal layer is electrically connected to the first conductivity type doped region, and the second metal layer is electrically connected to the second conductivity type doped region.

6. The method for fabricating a silicon-based germanium photodetector with a composite dielectric layer according to claim 1, characterized in that: The silicon substrate is the top silicon layer in an SOI wafer.

7. A silicon-based germanium photodetector with a composite dielectric layer, characterized in that, include: silicon substrate; A silicon oxide dielectric layer is located above the silicon substrate. The silicon oxide dielectric layer includes a first silicon oxide layer, a second silicon oxide layer, and a third silicon oxide layer disposed from bottom to top. The first silicon oxide layer is a thermal silicon oxide layer, the second silicon oxide layer is a high-temperature silicon oxide layer, and the third silicon oxide layer is a high-density plasma chemical vapor deposition silicon oxide layer. A dielectric layer groove is located in the silicon oxide dielectric layer and penetrates the silicon oxide dielectric layer; A silicon trench, located in the silicon substrate below the dielectric layer trench; A germanium epitaxial layer is located in the silicon trench and in the dielectric layer trench.

8. The silicon-based germanium photodetector with a composite dielectric layer according to claim 7, characterized in that: The thickness of the first silicon oxide layer ranges from 110 to 1000 Å, the thickness of the second silicon oxide layer ranges from 500 to 1000 Å, and the thickness of the third silicon oxide layer ranges from 1000 to 3000 Å.

9. The silicon-based germanium photodetector with a composite dielectric layer according to claim 7, characterized in that, Also includes: A first conductivity type doped region is located in the silicon substrate; A second conductivity type doped region is located in the silicon substrate, wherein the first conductivity type doped region and the second conductivity type doped region are separately disposed on both sides of the germanium epitaxial layer; An insulating dielectric layer is located above the silicon oxide dielectric layer, and the insulating dielectric layer covers the germanium epitaxial layer, wherein the insulating dielectric layer is a high-density plasma chemical vapor deposition silicon oxide layer; A first metal layer extends through the insulating dielectric layer and the silicon oxide dielectric layer to be electrically connected to the first conductivity type doped region; A second metal layer extends through the insulating dielectric layer and the silicon oxide dielectric layer to be electrically connected to the doped region of the second conductivity type.

10. The silicon-based germanium photodetector with a composite dielectric layer according to claim 7, characterized in that: The silicon substrate is the top silicon layer in an SOI wafer.

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