Barrier impurity band terahertz detector and fabrication method thereof

Abstract

The application provides a terahertz detector for blocking impurities and a manufacturing method thereof, which comprises the following steps: growing a common negative electrode contact layer on a high-purity gallium arsenide substrate through a molecular beam epitaxy process; growing a gallium arsenide silicon-doped absorption layer on the common negative electrode contact layer through a metal organic chemical vapor deposition process; continuously growing an intrinsic gallium arsenide-doped blocking layer on the gallium arsenide silicon-doped absorption layer through the metal organic chemical vapor deposition process; and growing a gallium arsenide silicon-doped positive electrode contact layer on the intrinsic gallium arsenide-doped blocking layer through the molecular beam epitaxy process. The application can accurately control the impurity concentration and growth depth of the doping, forms a good electrode ohmic contact, avoids the absorption loss of the common negative electrode contact layer to the terahertz radiation, solves the problem that the terahertz radiation cannot penetrate the high-conductivity gallium arsenide substrate, enables the detector to work in an irradiated mode, and is suitable for manufacturing a large-array-scale focal plane detector.

Description

Technical Field

[0001] This invention relates to the field of terahertz detector fabrication technology, specifically to a terahertz detector with a blocking impurity band and its fabrication method. Background Technology

[0002] Gallium arsenide (GaAs)-based blocking impurity band detectors can effectively detect terahertz radiation in the 100μm–300μm wavelength range. They have broad application prospects in fields such as security imaging, biomedicine, aerospace, and astronomical observation. Currently, GaAs-based blocking impurity band detectors are mainly fabricated using two methods: one using a high-conductivity GaAs substrate, and the other using a high-resistivity GaAs substrate. When using a high-conductivity gallium arsenide substrate for fabrication, no additional doping process is required to form the electrode contact layer. The common negative electrode can be directly fabricated on the high-conductivity gallium arsenide substrate. This fabrication process is simple and feasible. However, because terahertz radiation cannot penetrate the high-conductivity gallium arsenide substrate, the detector fabricated by this method can only operate in positive illumination mode (i.e., terahertz radiation irradiates from the blocking layer side, passes through the blocking layer, is absorbed by the absorption layer, and forms a response current), see "Optimization of Fabrication Process of the Mesa-Type GaAs:Te Blocked-Impurity-Band Detector, ICICM, 2017, 168-172". Furthermore, this method is not suitable for fabricating large-scale focal plane detectors. When fabricating on a high-resistivity gallium arsenide substrate, a high-purity GaAs epitaxial layer is first grown on the substrate using liquid phase epitaxy (LPE). Then, a heavily doped absorber layer and positive and negative electrode contact layers are formed by ion implantation (see "Design consideration of GaAs-based blocked-impurityband detector with the absorbing layer formed by ionimplantation, OQE, 2014, DOI 10.1007"). Due to limitations in ion implantation technology, the absorber layer thickness (implantation depth) fabricated by this method is usually less than 1 μm, resulting in a very thin absorber layer with low absorption efficiency for terahertz radiation, leading to low detection sensitivity. Furthermore, this method causes significant lattice damage, resulting in increased dark current in the detector.

[0003] Patent application CN112289872A discloses a barrier impurity band detector with an inverted trapezoidal groove structure and its fabrication method. The detector includes a high-purity gallium arsenide substrate and, sequentially disposed on the substrate, a common negative electrode contact layer, a gallium arsenide sulfur-doped absorber layer, an intrinsic gallium arsenide barrier layer, a silicon nitride passivation layer, a positive electrode contact layer, a positive electrode, and a negative electrode. The intrinsic gallium arsenide barrier layer has a positive electrode groove to accommodate the positive electrode contact layer. Inverted trapezoidal negative electrode grooves are formed on the intrinsic gallium arsenide barrier layer and the gallium arsenide sulfur-doped absorber layer. The silicon nitride passivation layer is distributed on the surface of the intrinsic gallium arsenide barrier layer and the sides of the inverted trapezoidal negative electrode grooves. The positive electrode and negative electrode are respectively disposed on the surfaces of the positive electrode contact layer and the inverted trapezoidal negative electrode grooves, and the negative electrode is connected to the common negative electrode contact layer through the bottom surface of the inverted trapezoidal negative electrode groove. However, this patent cannot completely solve the existing technical problems and cannot meet the needs of this invention. Summary of the Invention

[0004] To address the shortcomings of existing technologies, the purpose of this invention is to provide a terahertz detector with a blocking impurity band and a method for its fabrication.

[0005] The terahertz detector with blocking impurities provided by the present invention includes: a high-purity gallium arsenide substrate, a common negative electrode contact layer, a gallium arsenide silicon-doped absorber layer, an intrinsic gallium arsenide blocking layer, a positive electrode contact layer, a passivation layer and an ion implantation enhancement layer, as well as a positive electrode and a negative electrode. The common negative electrode contact layer is a gallium arsenide-doped silicon layer formed on the front side of the high-purity gallium arsenide substrate by molecular beam epitaxy. The gallium arsenide-doped silicon absorber layer is an epitaxial layer formed on the common negative electrode contact layer by a metal-organic chemical vapor epitaxy process. The intrinsic gallium arsenide barrier layer is an epitaxial layer disposed on the gallium arsenide silicon-doped absorber layer; The positive electrode contact layer is a gallium arsenide-doped silicon layer disposed on the intrinsic gallium arsenide barrier layer; The passivation layer covers the surface of the positive electrode contact layer, the intrinsic gallium arsenide barrier layer, and the inner surface of a V-groove. The passivation layer has through holes in the area corresponding to the bottom of the positive electrode contact layer and the V-groove. The V-shaped groove extends downward from the upper surface of the intrinsic gallium arsenide barrier layer, sequentially penetrating the intrinsic gallium arsenide barrier layer and the gallium arsenide silicon-doped absorber layer, and terminates at the common negative electrode contact layer, thereby exposing part of the surface of the common negative electrode contact layer. The ion implantation enhancement layer is located within the via of the passivation layer and covers the surface of the positive electrode contact layer and the surface of the common negative electrode contact layer exposed at the bottom of the via. The positive electrode and the negative electrode are respectively filled in the through holes of the corresponding positive electrode contact layer and the common negative electrode contact layer, and form an ohmic contact with the ion implantation enhancement layer.

[0006] Preferably, the crystal orientation of the high-purity gallium arsenide substrate is... <100> The resistivity is .

[0007] Preferably, the silicon doping concentration in the common negative electrode contact layer is... Its thickness is .

[0008] Preferably, the silicon doping concentration in the gallium arsenide-doped silicon absorber layer is [value missing]. Its thickness is 150 μm; the thickness of the intrinsic gallium arsenide barrier layer is The silicon doping concentration in the positive electrode contact layer Its thickness is .

[0009] Preferably, the passivation layer is a silicon nitride layer with a thickness of 200 nm; the ion implantation enhancement layer is a heavily doped region formed by silicon ion implantation and annealing.

[0010] The method for fabricating a terahertz detector with a blocking impurity band according to the present invention includes the following steps: Step S1: Provide a high-purity gallium arsenide substrate and grow a silicon-doped common negative electrode contact layer on its front side using molecular beam epitaxy. Step S2: On the common negative electrode contact layer, a gallium arsenide absorber layer doped with silicon is grown using a metal-organic chemical vapor deposition process. Step S3: An intrinsic gallium arsenide barrier layer is grown on the gallium arsenide-doped silicon absorber layer using a metal-organic chemical vapor deposition process. Step S4: A silicon-doped positive electrode contact layer is formed on the intrinsic gallium arsenide barrier layer; Step S5: Define patterns on the positive electrode contact layer and the intrinsic gallium arsenide barrier layer, and use reactive ion etching combined with wet etching process to etch downward to form a V-shaped groove that penetrates the intrinsic gallium arsenide barrier layer and the gallium arsenide silicon-doped absorber layer and terminates at the common negative electrode contact layer. Step S6: Deposit a passivation layer on the surface of the positive electrode contact layer and on the inner surface of the V-groove; Step S7: Etch the area on the passivation layer corresponding to the positive electrode contact layer and the bottom of the V-groove to form an electrode via that exposes the surface of the underlying contact layer; Step S8: Silicon ion implantation is performed on the exposed surfaces of the positive electrode contact layer and the common negative electrode contact layer through the electrode via; Step S9: Perform rapid thermal annealing on the ion-implanted structure to form an ion-implanted enhancement layer; Step S10: Deposit a metal stack in the electrode via to form a positive electrode and a negative electrode; Step S11: Thinning and polishing the back side of the high-purity gallium arsenide substrate.

[0011] Preferably, in step S1, the growth thickness of the common negative electrode contact layer is 50 nm to 100 nm; in step S2, the growth thickness of the gallium arsenide-doped silicon absorber layer is 150 μm; in step S3, the growth thickness of the intrinsic gallium arsenide barrier layer is 10 μm to 15 μm; and in step S4, the growth thickness of the positive electrode contact layer is 30 nm to 50 nm.

[0012] Preferably, in step S5, the wet etching process uses an etching solution containing 85% phosphoric acid, 30% hydrogen peroxide, and deionized water in a volume ratio of 2:1:20, with a etching depth of 165 μm.

[0013] Preferably, in step S8, the silicon ion implantation energy is 50~60 keV, and the implantation dose is... In step S9, rapid thermal annealing is carried out in a nitrogen atmosphere at a temperature of 750°C and a holding time of 30 seconds.

[0014] Preferably, in step S10, the deposited metal stack consists of a gold-germanium alloy layer, a nickel layer, and a gold layer from bottom to top, wherein the thickness of the gold-germanium alloy layer is 100 nm, the thickness of the nickel layer is 20 nm, and the thickness of the gold layer is 120 nm; in step S11, the substrate thickness is reduced to 20 μm using a chemical mechanical polishing process.

[0015] Compared with the prior art, the present invention has the following beneficial effects: (1) This invention uses molecular beam epitaxy to grow a common negative electrode contact layer on the surface of a high-purity gallium arsenide substrate, which can precisely control the impurity concentration of doping (≥1×10). 19 cm -3 The growth depth (≤100nm) not only forms a good electrode ohmic contact but also avoids the absorption loss of terahertz radiation by the common negative electrode contact layer, solving the problem that terahertz radiation cannot penetrate the high-conductivity gallium arsenide substrate. It can enable the detector to work in the irradiated mode and is suitable for fabricating large-scale focal plane detectors. (2) The present invention uses metal-organic chemical vapor phase epitaxy to grow gallium arsenide silicon-doped absorption layer with a thickness of more than 100 μm, which solves the problem that the absorption layer formed by ion implantation is too thin and the absorption efficiency is too low, ensuring the complete absorption of terahertz radiation by the absorption layer and improving the detection sensitivity of the detector. (3) The present invention adopts ion implantation enhanced contact process, which solves the damage to the electrode contact layer caused by etching process and enhances the reliability of electrode contact. Attached Figure Description

[0016] Other features, objects, and advantages of the present invention will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings: Figure 1 This is a flowchart illustrating the fabrication process of a terahertz detector with a blocking impurity band, as proposed in this invention. Figure 2 This is a schematic cross-sectional view of a terahertz detector with a blocking impurity band, which is an application of the present invention. Figure 3 This is a schematic diagram of the structure after a common negative electrode contact layer is grown on a high-purity gallium arsenide substrate using molecular beam epitaxy. Figure 4 This is a schematic diagram of the structure after epitaxial growth of a gallium arsenide-doped silicon absorber layer on the common negative electrode contact layer; Figure 5 This is a schematic diagram of the structure after an intrinsic gallium arsenide barrier layer is epitaxially grown on a gallium arsenide-doped silicon absorber layer. Figure 6 This is a schematic diagram of the structure after epitaxial growth of a positive electrode contact layer on an intrinsic gallium arsenide barrier layer. Figure 7 This is a schematic diagram of the structure after a silicon oxide mask layer is deposited on the surface of the positive electrode contact layer; Figure 8 This is a schematic diagram of the structure after etching openings in the silicon oxide mask layer; Figure 9 This is a schematic diagram of the structure after etching a "V"-shaped common negative electrode trench in the positive electrode contact layer, the intrinsic gallium arsenide barrier layer and the gallium arsenide silicon-doped absorber layer. Figure 10 This is a schematic diagram of the structure after the silicon oxide mask layer has been removed; Figure 11 This is a schematic diagram of the structure after a silicon nitride passivation layer is deposited on the surface of the positive electrode contact layer and the "V"-shaped common negative electrode trench. Figure 12 A schematic diagram of the structure after etching positive and negative electrode holes in the silicon nitride passivation layer; Figure 13 This is a schematic diagram of the structure after ion implantation on the surface of the positive electrode contact layer 5 and the "V"-shaped common negative electrode groove in the positive and negative electrode holes; Figure 14 This is a schematic diagram of the structure after the positive and negative electrodes are vapor-deposited. Figure 15 The response spectrum of the GaAs-based blocking impurity band terahertz detector fabricated for this invention.

[0017] In the figure: 1—High-purity gallium arsenide substrate; 2—Common negative electrode contact layer; 3—Gallium arsenide silicon-doped absorber layer; 4—Intrinsic gallium arsenide barrier layer; 5—Positive electrode contact layer; 6—Silicon oxide mask layer; 7—Silicon nitride passivation layer; 8—Ion implantation layer; 9—Negative electrode; 10—Positive electrode. Detailed Implementation

[0018] The present invention will now be described in detail with reference to specific embodiments. These embodiments will help those skilled in the art to further understand the present invention, but do not limit the invention in any way. It should be noted that those skilled in the art can make several changes and improvements without departing from the concept of the present invention. These all fall within the scope of protection of the present invention.

[0019] Example This invention provides a terahertz detector with a blocking impurity band and its fabrication method. A common negative electrode contact layer is grown on a high-purity gallium arsenide substrate using molecular beam epitaxy (MBE). A gallium arsenide-doped silicon (GaAs:Si) absorber layer is grown on the common negative electrode contact layer using metal-organic chemical vapor deposition (MOCVD). An intrinsic gallium arsenide-doped blocking layer is then grown on the gallium arsenide-doped silicon absorber layer using MOCVD. Finally, a gallium arsenide-doped silicon positive electrode contact layer is grown on the intrinsic gallium arsenide-doped blocking layer using MBE. This method uses MBE to grow the common negative electrode contact layer on the surface of a high-purity gallium arsenide substrate, allowing for precise control of the impurity concentration (≥1×10⁻⁶). 19 cm -3The method utilizes a growth depth (≤100nm) to achieve good ohmic contact while avoiding absorption losses of terahertz radiation by the common negative electrode contact layer. This solves the problem of terahertz radiation not penetrating the high-conductivity gallium arsenide substrate, allowing the detector to operate in irradiated mode and making it suitable for fabricating large-scale focal plane detectors. The gallium arsenide-doped silicon absorber layer is grown using metal-organic chemical vapor deposition (MOCVD) technology, achieving a thickness of over 100μm. This overcomes the problem of low absorption efficiency due to thin absorber layers formed by ion implantation, ensuring complete absorption of terahertz radiation and improving detector sensitivity. Furthermore, the ion implantation-enhanced contact process eliminates damage to the electrode contact layer caused by etching, enhancing electrode contact reliability. Fourier transform spectroscopy analysis shows that the GaAs-based blocking impurity band terahertz detector fabricated using this invention achieves a response spectrum range of 40~350μm, corresponding to a frequency range of 0.86~7.50THz.

[0020] To achieve the above-mentioned objectives, this invention provides a terahertz detector with a blocking impurity band and a method for manufacturing the same, specifically comprising: On the front side (polished surface) of a high-purity gallium arsenide substrate, a gallium arsenide silicon-doped layer is grown using molecular beam epitaxy (MBE) as a common negative electrode contact layer. A gallium arsenide-doped silicon absorber layer is grown on the surface of the common negative electrode contact layer using a metal-organic chemical vapor deposition (MOCVD) process. An intrinsic gallium arsenide-doped barrier layer is further grown on the gallium arsenide-doped silicon absorber layer using a metal-organic chemical vapor phase epitaxy process. On the intrinsic gallium arsenide-doped barrier layer, a gallium arsenide-doped silicon positive electrode contact layer is further grown by molecular beam epitaxy. A silicon oxide (SiO2) mask layer is formed on the surface of the intrinsic gallium arsenide barrier layer and the positive electrode contact layer by a low-pressure chemical vapor deposition (LPCVD) process. Within the intrinsic gallium arsenide barrier layer and the gallium arsenide silicon-doped absorber layer, a "V"-shaped common negative electrode trench structure is formed through photolithography, reactive ion etching (RIE), and wet etching processes. Silicon nitride (SiN) is formed on the surface of the intrinsic gallium arsenide barrier layer, the surface of the positive electrode contact layer, and the sidewall of the "V"-shaped common negative electrode trench structure using plasma-enhanced chemical vapor deposition (PECVD). x Passivation layer; Positive and negative electrode holes are opened on the surface of the positive electrode contact layer and the surface of the "V"-shaped common negative electrode groove structure by photolithography and reactive ion etching processes. Ion implantation is used to enhance contact within the positive and negative electrode holes, thus mitigating the damage to the electrode contact layer caused by the etching process and improving the reliability of the electrode contact.

[0021] Positive and negative electrodes with good ohmic contact are formed in the positive and negative electrode holes through photolithography, electron beam evaporation and electrode annealing processes.

[0022] On the back side of the high-purity gallium arsenide substrate, the substrate is thinned and polished using a chemical mechanical polishing (CMP) process.

[0023] As a preferred embodiment, the high-purity gallium arsenide substrate is a single-sided polished substrate with a crystal orientation of [missing information]. <100> The resistivity is 1×10 8 Ω cm, with a thickness of 350μm.

[0024] As a preferred embodiment, the method for forming the common negative electrode contact layer is molecular beam epitaxy, and the doping element of the common negative electrode contact layer is silicon with a doping concentration ≥ 5 × 10⁻⁶. 18 cm -3 The growth thickness of the common negative electrode contact layer is 50~100nm.

[0025] As a preferred embodiment, the gallium arsenide-doped silicon absorber layer is grown using organometallic chemical vapor deposition (GMCVD), with silicon as the dopant element and a doping concentration of 1×10⁻⁶. 16 ~1×10 17 cm -3 The growth thickness is 150 μm.

[0026] As a preferred embodiment, the intrinsic gallium arsenide-doped barrier layer is grown by metal-organic chemical vapor epitaxy without any doping and with a growth thickness of 10~15μm.

[0027] As a preferred embodiment, the positive electrode contact layer is fabricated using molecular beam epitaxy, with silicon as the doping element and a doping concentration ≥ 5 × 10⁻⁶. 18 cm -3The growth thickness of the common negative electrode contact layer is 30~50nm.

[0028] As a preferred embodiment, the silicon oxide mask layer is fabricated by low-pressure chemical vapor deposition, with a deposition thickness of 300 nm.

[0029] As a preferred embodiment, the fabrication method of the "V"-shaped common negative electrode groove structure is reactive ion etching + wet etching. The etching solution used is a mixed solution of 85% phosphoric acid, 30% hydrogen peroxide and deionized water, with a volume ratio of 2:1:20 for the three components and an etching depth of 165μm.

[0030] As a preferred embodiment, the silicon nitride passivation layer is fabricated by plasma-enhanced chemical vapor deposition, with a deposition thickness of 200 nm.

[0031] As a preferred embodiment, the positive and negative electrode holes are fabricated using reactive ion etching with an etching depth of 200 nm.

[0032] As a preferred embodiment, the ion implantation enhanced contact process uses silicon ions as implanted ions, with an implantation energy of 50-60 keV and an implantation dose of 5-8 × 10⁻⁶. 14 cm -2 The rapid thermal annealing was performed under a nitrogen protective atmosphere at a temperature of 750°C for 30 seconds.

[0033] As a preferred embodiment, the positive and negative electrodes are fabricated by electron beam evaporation. The positive and negative electrodes are deposited by depositing gold-germanium alloy (AuGe), nickel (Ni), and gold (Au) sequentially from bottom to top. The thickness of the gold-germanium alloy is 100 nm, the thickness of the nickel is 20 nm, and the thickness of the gold is 120 nm.

[0034] As a preferred embodiment, the high-purity gallium arsenide substrate is thinned and polished to reduce the substrate thickness by 330nm, that is, the high-purity gallium arsenide substrate is thinned and polished to 20μm.

[0035] This invention also provides a method for fabricating a terahertz detector with a blocking impurity band, such as... Figure 1 It includes the following steps: S1: First Molecular Beam Epitaxy: On a high-purity gallium arsenide substrate 1, a common negative electrode contact layer 2 is grown using molecular beam epitaxy, doped with silicon at a concentration ≥ 5 × 10⁻⁶. 18 cm -3 The growth thickness is 50~100nm, see Figure 3 ; S2: First Metal-Organic Chemical Vapor Phase Epitaxy (MOCVE): A gallium arsenide silicon-doped absorber layer 3 is grown on the common negative electrode layer 2 using MOCVE, with silicon doping at a concentration of 1×10⁻⁶. 16 ~1×10 17 cm -3 The growth thickness is 150 μm, see Figure 4 ; S3: Second Metal-Organic Chemical Vapor Deposition (MOCVD): On the gallium arsenide-doped silicon absorber layer 3, an intrinsic gallium arsenide barrier layer 4 is epitaxially grown using MOCVD, without any element doping, with a growth thickness of 10~15 μm. See [link to MOCVD]. Figure 5 ; S4: Second Molecular Beam Epitaxy: On the intrinsic gallium arsenide barrier layer 4, a positive electrode contact layer 5 is grown using molecular beam epitaxy, doped with silicon at a concentration ≥ 5 × 10⁻⁶. 18 cm -3 The growth thickness is 30~50nm, see Figure 6 ; S5: Low-pressure chemical vapor deposition: A silicon oxide mask layer 6 with a thickness of 300 nm is deposited on the surface of the positive electrode contact layer 5 using a low-pressure chemical vapor deposition process. See [link to relevant documentation] Figure 7 ; S6: First photolithography: Spin-coating positive photoresist AZ5214 with a thickness of 2μm onto the surface of silicon oxide mask layer 6, then exposing and developing to form the etched area window; S7: First reactive ion etching: Reactive ion etching process was used to etch silicon oxide mask layer 6 to a depth of 300nm. See Figure 8 ; S8: Wet etching: A "V"-shaped common negative electrode groove is etched using the wet etching method. See Figure 9 The etching solution used was a mixed solution of 85% phosphoric acid, 30% hydrogen peroxide, and deionized water, with a volume ratio of 2:1:20, and an etching depth of 165 μm. A buffered oxide etchant (BOE) with a volume ratio of hydrofluoric acid (49%) to ammonium fluoride (40%) of 1:6 was used, with an etching time of 120–150 s, removing the silicon oxide mask layer 6. Figure 10 ; S9: Plasma-enhanced chemical vapor deposition: A silicon nitride passivation layer 7 with a thickness of 200 nm was deposited on the surface of the positive electrode contact layer 5 and the "V"-shaped common negative electrode trench using plasma-enhanced chemical vapor deposition. Figure 11 ; S10: Second photolithography: Spin-coating positive photoresist AZ5214 with a thickness of 2μm onto the surface of silicon nitride passivation layer 7, followed by exposure and development to form the etched area window; S11: Second reactive ion etching: Using reactive ion etching, positive and negative electrode holes are etched within the silicon nitride passivation layer 7 to a depth of 200 nm. (See attached image) Figure 12 ; S12: Ion Implantation: Using ion implantation technology, silicon ions are implanted into the surface of the positive electrode contact layer 5 and the "V"-shaped common negative electrode trench within the positive and negative electrode holes. The implanted ions are silicon ions, the implantation energy is 50~60keV, and the implantation dose is 5~8×10⁻⁶. 14 cm -2 The injection angle is 7°, see Figure 13 ; S13: Rapid thermal annealing: In a nitrogen atmosphere, a rapid thermal annealing process is adopted with a heating and cooling rate of 80℃ / s, an annealing temperature of 750℃, and an annealing temperature holding time of 30 seconds to activate implanted ions, repair lattice damage, and enhance electrode contact effect and reliability. S14: Third photolithography: Using a spray photolithography process, 3μm photoresist ROL7133 is sprayed onto the surface of the positive electrode contact layer 5, the silicon nitride passivation layer 7 and the "V"-shaped common negative electrode groove, and then exposed and developed to form positive and negative electrode windows. S15: Plasma Resin Removal: Oxygen plasma resist removal process is used to further remove the residual photoresist film in the positive and negative electrode windows after exposure and development. The resist removal RF power is 400W, the oxygen flow rate is 200sccm, and the resist removal time is 3min. S16: Evaporation of positive and negative electrodes: The positive and negative electrodes are deposited by electron beam evaporation process. From bottom to top, gold-germanium alloy (AuGe), nickel (Ni) and gold (Au) are deposited in sequence. The thickness of the gold-germanium alloy is 100nm, the thickness of the nickel is 20nm, and the thickness of the gold is 120nm. S17: Annealing of positive and negative electrodes: An annealing process is adopted in a nitrogen atmosphere at a temperature of 420°C for 20 minutes to ensure good ohmic contact between the electrodes. See [link to annealing process]. Figure 14 ; S18: Thinning and Polishing: A chemical mechanical polishing process was used to thin and polish the high-purity gallium arsenide substrate 1, reducing its thickness by 330 nm, i.e., reducing the high-purity gallium arsenide substrate 1 to a thickness of 20 μm. (See attached image) Figure 2 .

[0036] Fourier transform spectrometry analysis showed that the GaAs-based blocking impurity band terahertz detector fabricated in this invention has a response spectral range of 40–350 μm, corresponding to a frequency range of 0.86–7.50 THz. Figure 15 .

[0037] Those skilled in the art will understand that, in addition to implementing the system, apparatus, and their modules provided by this invention in purely computer-readable program code, the same program can be implemented in the form of logic gates, switches, application-specific integrated circuits, programmable logic controllers, and embedded microcontrollers by logically programming the method steps. Therefore, the system, apparatus, and their modules provided by this invention can be considered a hardware component, and the modules included therein for implementing various programs can also be considered structures within the hardware component; alternatively, modules for implementing various functions can be considered both software programs implementing the method and structures within the hardware component.

[0038] Specific embodiments of the present invention have been described above. It should be understood that the present invention is not limited to the specific embodiments described above, and those skilled in the art can make various changes or modifications within the scope of the claims, which do not affect the essence of the present invention. Unless otherwise specified, the embodiments and features described in this application can be arbitrarily combined with each other.

Claims

1. A terahertz detector with a blocking impurity band, characterized in that, include: A high-purity gallium arsenide substrate, a common negative electrode contact layer, a gallium arsenide silicon-doped absorber layer, an intrinsic gallium arsenide barrier layer, a positive electrode contact layer, a passivation layer and an ion implantation enhancement layer, as well as a positive electrode and a negative electrode; The common negative electrode contact layer is a gallium arsenide-doped silicon layer formed on the front side of the high-purity gallium arsenide substrate by molecular beam epitaxy. The gallium arsenide-doped silicon absorber layer is an epitaxial layer formed on the common negative electrode contact layer by a metal-organic chemical vapor epitaxy process. The intrinsic gallium arsenide barrier layer is an epitaxial layer disposed on the gallium arsenide silicon-doped absorber layer; The positive electrode contact layer is a gallium arsenide-doped silicon layer disposed on the intrinsic gallium arsenide barrier layer; The passivation layer covers the surface of the positive electrode contact layer, the intrinsic gallium arsenide barrier layer, and the inner surface of a V-groove. The passivation layer has through holes in the area corresponding to the bottom of the positive electrode contact layer and the V-groove. The V-shaped groove extends downward from the upper surface of the intrinsic gallium arsenide barrier layer, sequentially penetrating the intrinsic gallium arsenide barrier layer and the gallium arsenide silicon-doped absorber layer, and terminates at the common negative electrode contact layer, thereby exposing part of the surface of the common negative electrode contact layer. The ion implantation enhancement layer is located within the via of the passivation layer and covers the surface of the positive electrode contact layer and the surface of the common negative electrode contact layer exposed at the bottom of the via. The positive electrode and the negative electrode are respectively filled in the through holes of the corresponding positive electrode contact layer and the common negative electrode contact layer, and form an ohmic contact with the ion implantation enhancement layer.

2. The terahertz detector with blocking impurities according to claim 1, characterized in that, The crystal orientation of the high-purity gallium arsenide substrate is <100> The resistivity is .

3. The terahertz detector with blocking impurities according to claim 1, characterized in that, The silicon doping concentration in the common negative electrode contact layer Its thickness is .

4. The terahertz detector with blocking impurities according to claim 1, characterized in that, The silicon doping concentration in the gallium arsenide-doped silicon absorber layer is: Its thickness is 150μm; The thickness of the intrinsic gallium arsenide barrier layer is: The silicon doping concentration in the positive electrode contact layer Its thickness is .

5. The terahertz detector with blocking impurities according to claim 1, characterized in that, The passivation layer is a silicon nitride layer with a thickness of 200 nm; the ion implantation enhancement layer is a heavily doped region formed by silicon ion implantation and annealing.

6. A method for manufacturing a terahertz detector with a blocking impurity band as described in any one of claims 1 to 5, characterized in that, Includes the following steps: Step S1: Provide a high-purity gallium arsenide substrate and grow a silicon-doped common negative electrode contact layer on its front side using molecular beam epitaxy. Step S2: On the common negative electrode contact layer, a gallium arsenide absorber layer doped with silicon is grown using a metal-organic chemical vapor deposition process. Step S3: An intrinsic gallium arsenide barrier layer is grown on the gallium arsenide-doped silicon absorber layer using a metal-organic chemical vapor deposition process. Step S4: A silicon-doped positive electrode contact layer is formed on the intrinsic gallium arsenide barrier layer; Step S5: Define patterns on the positive electrode contact layer and the intrinsic gallium arsenide barrier layer, and use reactive ion etching combined with wet etching process to etch downward to form a V-shaped groove that penetrates the intrinsic gallium arsenide barrier layer and the gallium arsenide silicon-doped absorber layer and terminates at the common negative electrode contact layer. Step S6: Deposit a passivation layer on the surface of the positive electrode contact layer and on the inner surface of the V-groove; Step S7: Etch the area on the passivation layer corresponding to the positive electrode contact layer and the bottom of the V-groove to form an electrode via that exposes the surface of the underlying contact layer; Step S8: Silicon ion implantation is performed on the exposed surfaces of the positive electrode contact layer and the common negative electrode contact layer through the electrode via; Step S9: Perform rapid thermal annealing on the ion-implanted structure to form an ion-implanted enhancement layer; Step S10: Deposit a metal stack in the electrode via to form a positive electrode and a negative electrode; Step S11: Thinning and polishing the back side of the high-purity gallium arsenide substrate.

7. The method for manufacturing a terahertz detector with a blocking impurity band according to claim 6, characterized in that, In step S1, the growth thickness of the common negative electrode contact layer is 50nm~100nm; in step S2, the growth thickness of the gallium arsenide silicon-doped absorber layer is 150μm; in step S3, the growth thickness of the intrinsic gallium arsenide barrier layer is 10μm~15μm; in step S4, the growth thickness of the positive electrode contact layer is 30nm~50nm.

8. The method for manufacturing a terahertz detector with a blocking impurity band according to claim 6, characterized in that, In step S5, the wet etching process uses an etching solution containing 85% phosphoric acid, 30% hydrogen peroxide, and deionized water in a volume ratio of 2:1:20, with a etching depth of 165 μm.

9. The method for manufacturing a terahertz detector with a blocking impurity band according to claim 6, characterized in that, In step S8, the silicon ion implantation energy is 50-60 keV, and the implantation dose is... In step S9, rapid thermal annealing is carried out in a nitrogen atmosphere at a temperature of 750°C and a holding time of 30 seconds.

10. The method for manufacturing a terahertz detector with a blocking impurity band according to claim 6, characterized in that, In step S10, the deposited metal stack consists of a gold-germanium alloy layer, a nickel layer, and a gold layer from bottom to top, wherein the thickness of the gold-germanium alloy layer is 100 nm, the thickness of the nickel layer is 20 nm, and the thickness of the gold layer is 120 nm; in step S11, the substrate thickness is reduced to 20 μm using a chemical mechanical polishing process.

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