Tunnel oxide passivated contact solar cell, preparation method thereof, battery assembly and electric device

Abstract

The application discloses a tunnel oxide passivated contact solar cell and a preparation method, a battery assembly and an electric device thereof. The tunnel oxide passivated contact solar cell comprises a semiconductor substrate, a back surface of the semiconductor substrate is provided with an electrode area and a non-electrode area; a tunnel oxide layer, a first doped semiconductor layer, a first passivation layer, a second doped semiconductor layer and a back electrode are sequentially arranged in the electrode area in a direction away from the semiconductor substrate; wherein the first passivation layer and the second doped semiconductor layer extend to the non-electrode area. The second doped semiconductor layer contained in the tunnel oxide passivated contact solar cell can play a role in blocking the migration of external positive charge ions to the first passivation layer, improving the stability of the field passivation effect of the first passivation layer, and can improve the potential-induced degradation resistance of the tunnel oxide passivated contact solar cell.

Description

Technical Field

[0001] This application belongs to the field of crystalline silicon solar cell technology, specifically relating to a tunneling oxide passivated contact solar cell and its preparation method, cell module and power device. Background Technology

[0002] To further explore the efficiency potential of tunnel oxide passivated contact (TOPCon) solar cells, several advanced technologies have recently emerged in the industry, such as the back-side partial polysilicon removal technology (poly-finger technology). This approach aims to significantly reduce light loss caused by parasitic absorption of polysilicon in this area, thereby improving the cell's utilization of incident sunlight, effectively increasing the cell's short-circuit current, and ultimately achieving a gain in conversion efficiency.

[0003] However, while this technology demonstrates positive effects in improving efficiency, it also introduces new reliability risks. Specifically, the removal of the polycrystalline silicon layer in the non-electrode regions exposes the direct interface between the underlying passivation layer and the silicon substrate. This structural change leads to a situation where, in module applications, when the cell is subjected to high voltage stress (i.e., potential-induced degradation, PID testing) or long-term operating voltage, external positively charged particles (such as sodium ions) are more likely to migrate and accumulate at the passivation layer-silicon substrate interface in the non-electrode region. These accumulated positive charges neutralize the inherent negative charges in the passivation layer, severely weakening its field passivation effect and causing a sharp increase in back-side recombination. This results in TOPCon cell modules using this technology facing significant PID degradation risks in actual power plant operation, posing a serious challenge to their long-term reliability and power output stability. Summary of the Invention

[0004] In view of the above problems, this application provides a tunneling oxide passivated contact solar cell, a method for preparing the same, a battery module containing the tunneling oxide passivated contact solar cell, and an electrical device, to solve the technical problem that the existing tunneling oxide passivated contact solar cells have unsatisfactory resistance to potential-induced degradation.

[0005] In a first aspect, embodiments of this application provide a tunneling oxide passivated contact solar cell. The tunneling oxide passivated contact solar cell of this application includes a semiconductor substrate, with an electrode region and a non-electrode region disposed on the back surface of the semiconductor substrate; along a direction away from the semiconductor substrate, a tunneling oxide layer, a first doped semiconductor layer, a first passivation layer, a second doped semiconductor layer, and a back electrode are sequentially disposed in the electrode region; wherein the first passivation layer and the second doped semiconductor layer extend into the non-electrode region.

[0006] The TOPCon battery of this application embodiment adds a second doped semiconductor layer to the functional structure layer in both the non-electrode region and the electrode region. This second doped semiconductor layer is disposed on the surface of the first passivation layer away from the semiconductor substrate. This allows the second doped semiconductor layer to block the migration of external positively charged ions to the first passivation layer, particularly to the non-electrode region. It neutralizes these externally migrating positively charged ions, thereby reducing the amount of external positively charged ions migrating to the first passivation layer and improving the stability of the field passivation effect of the first passivation layer. This enhances the resistance to potential-induced degradation (PID) performance of the Topcon battery of this application embodiment. Similarly, the second doped semiconductor layer also neutralizes positively charged ions migrating to the first passivation layer during long-term operation, acting as a protective layer and further improving the stability of the field passivation effect of the first passivation layer. This, in turn, improves the stability of the electrical performance of the Topcon battery of this application embodiment, including photoelectric conversion efficiency.

[0007] Furthermore, the thickness of the second doped semiconductor layer is less than the thickness of the first doped semiconductor layer.

[0008] Furthermore, the thickness of the second doped semiconductor layer is 1 nm to 50 nm.

[0009] Furthermore, the atomic concentration of the doping element in the second doped semiconductor layer is 1×10⁻⁶. 15 ~1×10 21 cm -3 .

[0010] Furthermore, the doping element contained in the second doped semiconductor layer includes at least one of C, N, O, P, and As.

[0011] Furthermore, the first passivation layer, extending into the non-electrode region, is stacked on the backlight surface of the non-electrode region.

[0012] Furthermore, the polarity of the first doped semiconductor layer and the second doped semiconductor layer is the same as the polarity of the semiconductor substrate.

[0013] Furthermore, the polarity of the first doped semiconductor layer and the second doped semiconductor layer is the same as that of the semiconductor substrate, which is an N-type doped semiconductor layer.

[0014] Furthermore, it also includes a second passivation layer, which is disposed between the second doped semiconductor layer and the back electrode in the electrode region, and extends to the non-electrode region and is stacked on the surface of the second doped semiconductor layer in the non-electrode region away from the semiconductor substrate.

[0015] Furthermore, the first doped semiconductor layer includes a doped semiconductor layer a, a barrier layer, and a doped semiconductor layer b, and the doped semiconductor layer a, the barrier layer, and the doped semiconductor layer b are stacked sequentially along a direction away from the semiconductor substrate.

[0016] Furthermore, the total height of the tower base in the electrode region is greater than the total height of the tower base in the non-electrode region.

[0017] Furthermore, the height difference between the total height of the tower base in the electrode region and the total height of the tower base in the non-electrode region is 1 μm to 10 μm.

[0018] Secondly, embodiments of this application also provide a method for fabricating a tunneling oxide layer passivated contact solar cell. The method for fabricating a tunneling oxide layer passivated contact solar cell according to embodiments of this application includes the following steps: A semiconductor substrate is provided, on which an electrode region and a non-electrode region are disposed on the back surface; A tunneling oxide layer and a first doped semiconductor layer are sequentially formed in the electrode region of the backlight surface; A first passivation layer is first formed on the surface of the first doped semiconductor layer away from the semiconductor substrate and in the non-electrode region of the backlight surface, and then a second doped semiconductor layer is formed on the surface of the first passivation layer away from the semiconductor substrate.

[0019] In the TOPCon solar cell fabricated by the tunneling oxide passivation contact solar cell fabrication method of this application, a second doped semiconductor layer is formed in the functional layer structure of the electrode region and non-electrode region. This second doped semiconductor layer acts to block the migration of external positively charged ions to the first passivation layer, improving the stability of the first passivation layer's field passivation effect. Therefore, it can enhance the stability of the Topcon solar cell's electrical performance, such as its resistance to potential-induced degradation (PID) and photoelectric conversion efficiency.

[0020] Furthermore, the thickness of the second doped semiconductor layer is less than the thickness of the first doped semiconductor layer.

[0021] Furthermore, the thickness of the second doped semiconductor layer is 1 nm to 50 nm.

[0022] Furthermore, the atomic concentration of the doped elements in the formed second doped semiconductor layer is 1×10⁻⁶. 15 ~1×10 21 cm -3 .

[0023] Furthermore, the formed second doped semiconductor layer also includes at least one doping element selected from P, C, N, and O.

[0024] Furthermore, after the step of forming the second doped semiconductor layer, the following steps are also included: A second passivation layer is formed on the surface of the second doped semiconductor layer away from the semiconductor substrate.

[0025] Thirdly, this application also provides a battery module. The battery module of this application includes a tunneling oxide passivated contact solar cell according to the embodiment of this application or a tunneling oxide passivated contact solar cell prepared according to the method for preparing a tunneling oxide passivated contact solar cell according to the embodiment of this application. Because the battery module of this application contains a tunneling oxide passivated contact solar cell, compared with existing battery modules with tunneling oxide passivated contact solar cells, the battery module of this application has enhanced anti-degradation performance and improved stability of electrical performance such as photoelectric conversion efficiency.

[0026] Fourthly, this application also provides an electrical device. The electrical device includes a tunneling oxide passivated contact solar cell or a battery module. Because the electrical device contains a tunneling oxide passivated contact solar cell, its energy self-sufficiency is enhanced, and its service life is extended. Attached Figure Description

[0027] To more clearly illustrate the technical solutions in the specific embodiments of this application or the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0028] Figure 1 This is a schematic diagram of a tunnel oxide passivated contact solar cell according to an embodiment of this application; Figure 2 This is a schematic diagram of another structure of a tunnel oxide passivated contact solar cell according to an embodiment of this application.

[0029] The reference numerals in the detailed embodiments are as follows: 1-Semiconductor substrate, 11-Backlight surface, 12-Light-receiving surface; 2-Tunneling oxide layer, 3-First doped semiconductor layer, 31-Doped semiconductor layer a, 32-Barrier layer, 33-Doped semiconductor layer b, 4-First passivation layer, 5-Second doped semiconductor layer, 6-Second passivation layer, 7-Back electrode, 8-Third passivation layer, 9-Antireflection layer, 10-Front electrode. Detailed Implementation

[0030] To make the technical problems, technical solutions, and beneficial effects of this application clearer, the following detailed description is provided in conjunction with embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0031] In this application, the term "and / or" describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, or B existing alone. A and B can be singular or plural. The character " / " generally indicates that the preceding and following related objects have an "or" relationship.

[0032] In this application, "at least one" means one or more, and "more than one" means two or more. "At least one of the following" or similar expressions refer to any combination of these items, including any combination of single or multiple items. For example, "at least one of a, b, or c", or "at least one of a, b, and c", can both mean: a, b, c, ab (i.e., a and b), ac, bc, or abc, where a, b, and c can be single or multiple.

[0033] It should be understood that in the various embodiments of this application, the order of the above processes does not imply the order of execution. Some or all steps may be executed in parallel or sequentially. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application.

[0034] The terminology used in the embodiments of this application is for the purpose of describing particular embodiments only and is not intended to be limiting of this application. The singular forms “a,” “the,” and “the” used in the embodiments of this application and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise.

[0035] The weights of the relevant components mentioned in the embodiments of this application can refer not only to the specific content of each component, but also to the proportional relationship between the weights of the components. Therefore, any scaling up or down of the content of the relevant components according to the embodiments of this application is within the scope disclosed in the embodiments of this application. Specifically, the mass described in the embodiments of this application can be a well-known unit of mass in the chemical industry, such as µg, mg, g, or kg.

[0036] The terms "first" and "second" are used for descriptive purposes only, to distinguish objects, such as substances, from one another, and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. For example, without departing from the scope of the embodiments of this application, "first XX" may also be referred to as "second XX," and similarly, "second XX" may also be referred to as "first XX." Thus, features defined with "first" and "second" may explicitly or implicitly include one or more of that feature.

[0037] To address the challenges of global energy shortages and the increasing depletion of traditional fossil fuels, vigorously developing renewable energy has become a global consensus. Solar energy, due to its cleanliness, safety, and abundant resources, has become one of the fastest-growing renewable energy sources, with photovoltaic (PV) power generation being its most important form of utilization. With decades of technological accumulation, the conversion efficiency of crystalline silicon cells—the core of PV power generation technology—has continuously improved, while costs have steadily decreased, driving the industry's vigorous development. Among various high-efficiency crystalline silicon cell technologies, tunneling oxide passivated contact (TOPCon) cells have gradually become the mainstream technology in the market. TOPCon cells achieve superior field-effect passivation and contact characteristics by fabricating an ultra-thin silicon oxide and doped polycrystalline silicon (poly-Si) stacked structure on the back of the cell, thereby obtaining higher open-circuit voltage and conversion efficiency.

[0038] To further explore the efficiency potential of TOPCon cells, several advanced technologies have recently emerged in the industry, including partial polysilicon removal technology on the back side. This technology, often referred to as poly-finger technology, involves selectively removing the thick doped polysilicon layer from the non-electrode region on the back of the cell, a feature present in the standard TOPCon structure. This aims to significantly reduce light loss caused by parasitic absorption of polysilicon in this region, thereby improving the cell's utilization of incident sunlight, effectively increasing the short-circuit current, and ultimately achieving a gain in conversion efficiency.

[0039] However, while this technology demonstrates positive effects in improving efficiency, it also introduces new reliability risks. The fundamental reason lies in its alteration of the optimized passivation structure on the back of the cell. In the standard TOPCon structure, the complete back polycrystalline silicon layer and tunneling oxide layer together constitute a stable and efficient passivation system. However, when the polycrystalline silicon layer in the non-electrode areas is removed, the direct interface between the underlying passivation layer and the silicon substrate is exposed. This structural change leads to a situation where, under high voltage stress (i.e., potential-induced degradation, PID testing) or long-term operating voltage, external positively charged particles (such as sodium ions) are more likely to converge and accumulate at the passivation layer-silicon substrate interface in the non-electrode areas. These accumulated positive charges neutralize the inherent negative charges in the passivation layer, severely weakening its field passivation effect and causing a sharp increase in back recombination. This results in TOPCon cell modules using this technology facing significant PID degradation risks in actual power plant operation, posing a serious challenge to their long-term reliability and power output stability.

[0040] To address the problem of PID (Problem-Induced Defect) risks introduced by poly-finger technology, existing solutions primarily focus on remedial measures at the system level or in peripheral materials. However, these methods have significant limitations: high-specification packaging materials increase costs; and system-level recovery methods are reactive and cannot fundamentally prevent PID, while also increasing the complexity of operation and maintenance.

[0041] Therefore, in order to enable TOPCon batteries to take into account both the high efficiency advantages brought by poly-finger technology and the high reliability requirements of components under high voltage applications, and to mitigate the risk of PID degradation caused by this technology, the embodiments of this application propose the following technical solutions.

[0042] [Tunneling Oxide Passivated Contact Solar Cells] In one aspect, embodiments of this application provide a tunneling oxide passivated contact solar cell (hereinafter referred to as TOPCon cell). The TOPCon cell of this application includes a semiconductor substrate, which has a backlight surface and a light-receiving surface disposed opposite to the backlight surface, and the backlight surface of the semiconductor substrate is divided into an electrode region and a non-electrode region.

[0043] In the electrode region, a tunneling oxide layer, a first doped semiconductor layer, a first passivation layer, a second doped semiconductor layer, and a back electrode are sequentially disposed in a direction away from the semiconductor substrate; wherein the first passivation layer and the second doped semiconductor layer extend into the non-electrode region.

[0044] In the TOPCon battery of this application embodiment, the non-electrode region contained in the backlight surface of the semiconductor substrate refers to the functional layer region used to form the conventional thick doped polycrystalline silicon layer that has been removed from the standard TOPCon structure.

[0045] Thus, in this embodiment of the TOPCon battery, a second doped semiconductor layer is added to the functional structure layer in the non-electrode region and the functional structure layer in the electrode region. The second doped semiconductor layer is disposed on the surface of the first passivation layer away from the semiconductor substrate, thereby enabling the second doped semiconductor layer to block the migration of external positive charged ions to the first passivation layer, especially to block the migration of external positive charged ions to the first passivation layer in the non-electrode region. For example, it can neutralize the positive charged ions migrating from the outside, thereby reducing the amount of external positive charged ions migrating to the first passivation layer, improving the stability of the first passivation layer in exerting the field passivation effect, and improving the anti-potential-induced degradation (PID) performance of the Topcon battery in this embodiment of the application.

[0046] Meanwhile, due to the provision of the second doped semiconductor layer, it can also neutralize the positively charged ions that migrate from the outside to the first passivation layer during long-term operation of the Topcon battery in this application embodiment, thereby improving the stability of the first passivation layer in exerting the field passivation effect, and thus improving the stability of the electrical performance of the Topcon battery in this application embodiment, including photoelectric conversion efficiency.

[0047] In addition, the second doped semiconductor layer disposed in the electrode region can also prevent the back electrode from being ablated during the process, improve the metal-semiconductor contact interface, reduce the saturation current density (J0metal) in the electrode region, and improve the open circuit voltage and efficiency of Topcon cells.

[0048] Semiconductor substrate: In the tunnel oxide passivated contact solar cell of the embodiments of this application, the semiconductor substrate contained therein has the following characteristics: Figure 1 and Figure 2 The diagram shows a backlight surface 11 and a light-receiving surface 12 opposite to the backlight surface 11. When sunlight (photons) enters the semiconductor substrate 1 from the light-receiving surface 12, if the energy of the photon is greater than or equal to the band gap of the semiconductor material in the semiconductor substrate 1, it will excite the valence band electrons of the semiconductor material to jump to the conduction band, thereby generating electron-hole pairs in the semiconductor.

[0049] In some embodiments, such as Figure 1 and Figure 2 The backlight surface 11 of the semiconductor substrate 1 shown is divided into electrode region A and non-electrode region B, and electrode region A and non-electrode region B are arranged adjacent to each other. In some embodiments, there may be multiple electrode regions A and non-electrode regions B on the backlight surface 11, which are arranged alternately.

[0050] In some embodiments, such as Figure 1 and Figure 2The back surface 11 of the semiconductor substrate 1 shown is a smooth surface, that is, both electrode region A and non-electrode region B are smooth surfaces. In this way, the quality of functional layers in electrode region A, such as the tunneling oxide layer 2 and the first doped semiconductor layer 3, can be improved, thereby improving the carrier tunneling effect and passivation effect.

[0051] In some embodiments, such as Figure 1 and Figure 2 The light-receiving surface 12 of the semiconductor substrate 1 shown can be a textured structure. This can reduce the reflectivity of sunlight on the light-receiving surface 12, increase the absorption rate of sunlight, and thus improve the short-circuit current and conversion efficiency of the Topcon cell.

[0052] In some embodiments, such as Figure 1 and Figure 2 The semiconductor substrate 1 shown can be made of materials such as single-crystal silicon, gallium arsenide, or other III-V compound semiconductors, or materials such as germanium. Of course, the semiconductor substrate 1 can also be made of other semiconductor materials used in the field of tunnel oxide passivated contact solar cells. For example... Figure 1 The semiconductor substrate 1 shown can be N-type doped, or it can be P-type doped.

[0053] Composite functional structure disposed in electrode region A: The tunneling oxide layer, the first doped semiconductor layer, the first passivation layer, the second doped semiconductor layer, and the back electrode disposed in electrode region A on the back surface of the semiconductor substrate together constitute the composite functional structure of the electrode region. For example... Figure 1 and Figure 2 As shown, along the direction away from the semiconductor substrate 1, the electrode region is sequentially disposed with tunneling oxide layer 2, first doped semiconductor layer 3, first passivation layer 4, second doped semiconductor layer 5, and back electrode 7, forming a composite functional structure. Moreover, the first passivation layer 4 and the second doped semiconductor layer 5 extend into the non-electrode region B.

[0054] In some embodiments, such as Figure 1 and Figure 2 The thickness of the tunneling oxide layer 2 shown can be 1~5 nm. In the example, it can be a typical but non-limiting thickness such as 1 nm, 2 nm, 3 nm, 4 nm, 5 nm, or any range between two thickness values. The tunneling oxide layer 2 within this thickness range can improve electron permeability and increase the rate of hole impediment, thereby reducing the carrier recombination probability.

[0055] In some embodiments, such as Figure 1 and Figure 2The material of the tunneling oxide layer 2 shown may include a tunneling oxide. In an exemplary embodiment, the tunneling oxide may be at least one of silicon oxide, silicon oxynitride, aluminum oxide, hafnium oxide, tantalum oxide, and silicon nitride. These materials can improve the electron permeability of the tunneling oxide layer 2 and increase the hole impediment rate.

[0056] In some embodiments, such as Figure 1 The thickness of the first doped semiconductor layer 3 shown can be 30 nm to 200 nm, optionally 30 nm to 80 nm. In the example, it can be a typical but non-limiting thickness such as 30 nm, 40 nm, 50 nm, 60 nm, 70 nm, 80 nm, 90 nm, 100 nm, 130 nm, 150 nm, 180 nm, 200 nm, or any range between two thicknesses. Other thickness ranges are also possible.

[0057] In some embodiments, such as Figure 1 The material of the first doped semiconductor layer 3 shown may include N-type doped polysilicon. In the embodiment, the material of the first doped semiconductor layer 3 is polysilicon doped with phosphorus (P), arsenic (As), etc. In the exemplary example, the material of the first doped semiconductor layer 3 is polysilicon with the same type of doping source as the semiconductor substrate 1 described above.

[0058] In some embodiments, such as Figure 2 The first doped semiconductor layer 3 shown includes a doped semiconductor layer a31, a barrier layer 32, and a doped semiconductor layer b33, which are sequentially stacked along the direction away from the semiconductor substrate 1. At this time, the doped semiconductor layer a31 is stacked with the tunneling oxide layer 2, and the doped semiconductor layer b33 is stacked with the first passivation layer 4. By configuring the first doped semiconductor layer 3 into a composite layer structure comprising the doped semiconductor layer a31, the barrier layer 32, and the doped semiconductor layer b33, the doped semiconductor layers a31 and b33 in this composite layer structure can improve the interface state density and field-effect passivation effect, and optimize the electron transport path. The barrier layer 32 can alleviate the migration of dopants and / or metal particles, and can improve the stability of the interface performance between the tunneling oxide layer 2 and the crystalline silicon. For example, it can reduce the migration of metal particles in the back electrode 7 and / or dopants in the second doped semiconductor layer 5 into the tunneling oxide layer 2, improve the stability of the passivation performance of the tunneling oxide layer 2, and thus enhance the long-term stability and reliability of the TOPCon cell.

[0059] In the embodiments, such as Figure 2The thicknesses of the doped semiconductor layer a31 and the doped semiconductor layer b33 shown can be the same or different, greater than 0 nm and less than or equal to 100 nm. Typical but non-limiting thicknesses such as 1 nm, 5 nm, 10 nm, 20 nm, 30 nm, 40 nm, 50 nm, 60 nm, 70 nm, 80 nm, 90 nm, 100 nm, etc., or any range between two thicknesses, can also be other thickness ranges. In a further embodiment, the total thickness of the doped semiconductor layer a31, the barrier layer 32, and the doped semiconductor layer b33 can be 30 nm to 200 nm.

[0060] In the embodiments, such as Figure 2 The materials of the doped semiconductor layer a31 and the doped semiconductor layer b33 shown may be the same or different, including N-type doped polysilicon. In the embodiment, the materials of the doped semiconductor layer a31 and the doped semiconductor layer b33 may be the same or different, such as phosphorus (P), arsenic (As), or other doped polysilicon. In the exemplary example, the materials of the doped semiconductor layer a31 and the doped semiconductor layer b33 may be polysilicon with the same type of doping source as the semiconductor substrate 1 described above.

[0061] In the embodiments, such as Figure 2 The thickness of the barrier layer 32 shown can be greater than 0 nm to less than or equal to 5 nm, such as typical but non-limiting thicknesses like 1 nm, 2 nm, 3 nm, 4 nm, 5 nm, or any range between two thicknesses, or other thickness ranges. In a further embodiment, the total thickness of the barrier layer 32, the doped semiconductor layer a3, and the doped semiconductor layer b33 can be 30 nm to 200 nm.

[0062] In the embodiments, such as Figure 2 The material of the barrier layer 32 shown may include at least one of silicon oxide, silicon oxynitride, aluminum oxide, hafnium oxide, tantalum oxide, and silicon nitride.

[0063] In some embodiments, such as Figure 1 and Figure 2The thickness of the first passivation layer 4 shown can be 1~10 nm. In the example, it can be a typical but non-limiting thickness such as 1 nm, 2 nm, 3 nm, 4 nm, 5 nm, 6 nm, 7 nm, 8 nm, 9 nm, 10 nm, or any range between two thicknesses, or other thickness ranges. This thickness range of the first passivation layer 4, located in electrode region A, can perform chemical passivation between the first doped semiconductor layer 3 and the second doped semiconductor layer 5, saturating the interface dangling bonds and reducing the interface state density. It works synergistically with the first doped semiconductor layer 3 or doped semiconductor layer b33 and the second doped semiconductor layer 5 on both sides to form a passivated contact structure. This structure as a whole achieves field-effect passivation and allows selective electron passage through the quantum tunneling effect, while effectively blocking holes using the band barrier, thereby significantly reducing the carrier recombination probability. The first passivation layer 4 located in non-electrode region B performs chemical passivation, passivating the back surface 11 of the semiconductor substrate 1 in non-electrode region B.

[0064] In some embodiments, such as Figure 1 and Figure 2 The material of the first passivation layer 4 shown may include aluminum oxide (AlO2). x ), silicon dioxide (SiO) x ), silicon oxynitride (SiO) x N y At least one of silicon nitride (Si3N4). These materials can enhance the chemical passivation effect of the first passivation layer 4 and improve its field-effect passivation effect.

[0065] In some embodiments, such as Figure 1 and Figure 2 The thickness of the second doped semiconductor layer 5 shown is less than the thickness of the first doped semiconductor layer 3. As in some embodiments, such as... Figure 1 and Figure 2The thickness of the second doped semiconductor layer 5 shown can be from 1 nm to 50 nm. In the example, it can be a typical but non-limiting thickness such as 1 nm, 10 nm, 20 nm, 30 nm, 40 nm, or 50 nm, or any range between two thicknesses, such as 1 nm to 40 nm, 1 nm to 30 nm, 1 nm to 20 nm, 1 nm to 10 nm, or 10 nm to 30 nm. Controlling the thickness of the second doped semiconductor layer 5 to be less than the thickness of the first doped semiconductor layer 3, specifically controlling the thickness of the second doped semiconductor layer 5 within the above-mentioned range, can improve the function of the second doped semiconductor layer 5 as described above, such as blocking the migration of external positively charged ions to the first passivation layer 4, especially blocking the migration of external positively charged ions to the first passivation layer 4 located in the non-electrode region B, while improving its ability to prevent the ablation of the back electrode 7 during the manufacturing process. In addition, it can also balance and optimize the "passivation" and "contact" performance of the TOPCon battery.

[0066] In some embodiments, such as Figure 1 and Figure 2 The material of the second doped semiconductor layer 5 shown can be the same as that of the first doped semiconductor layer 3 described above, or it can be different. In the example, the material of the second doped semiconductor layer 5 is polysilicon with the same type of doping source as the semiconductor substrate 1 and the first doped semiconductor layer 3 described above, such as N-type polysilicon.

[0067] In this embodiment, the atomic concentration of the doping element in the material of the second doped semiconductor layer 5 is 1×10⁻⁶. 15 ~1×10 21 cm -3 In the example, the atomic concentration can be 1×10⁻⁶. 15 cm -3 1×10 16 cm -3 1×10 17 cm -3 1×10 18 cm -3 1×10 19 cm -3 1×10 20 cm -3 1×10 21 cm -3 Typical but non-limiting concentrations or any range between two concentrations, such as 1 × 10⁻⁶. 16 ~1×10 21 cm -3 1×10 17 ~1×10 21 cm -3 1×10 18 ~1×1021 cm -3 1×10 19 ~1×10 21 cm -3 1×10 20 ~1×10 21 cm -3 The concentration range is equal. The atomic concentration of the doped elements can improve the ability to prevent external positively charged ions from migrating to the first passivation layer 4, especially to prevent external positively charged ions from migrating to the first passivation layer 4 in the non-electrode region B, thereby improving the balance and optimization of the "passivation" and "contact" performance of the TOPCon battery.

[0068] In this embodiment, when the material of the second doped semiconductor layer 5 is N-type doped polycrystalline silicon, the doping elements it contains include at least one of carbon (C), nitrogen (N), oxygen (O), phosphorus (P), and arsenic (As). These types of doping elements can impart N-type polarity to the second doped semiconductor layer 5, and at the same time improve the ability to prevent external positively charged ions from migrating to the first passivation layer 4, especially playing a role in preventing external positively charged ions from migrating to the first passivation layer 4 located in the non-electrode region B, thereby improving the balance and optimization of the "passivation" and "contact" performance of the TOPCon battery.

[0069] In some embodiments, such as Figure 1 and Figure 2 As shown, the composite functional structure disposed in electrode region A also includes a second passivation layer 6. This second passivation layer 6 is disposed between the second doped semiconductor layer 5 and the back electrode 7 in electrode region A, and extends into non-electrode region B, being stacked on the surface of the second doped semiconductor layer 5 in non-electrode region B that is away from the semiconductor substrate 1. The second passivation layer 6 in electrode region A effectively passivates defects at the film interface, and also prevents metal atoms in the back electrode 7 from penetrating and migrating towards the semiconductor substrate 1 during sintering or operation, thereby improving the stability of the performance of each film layer in the composite functional structure. The second passivation layer 6 in non-electrode region B also passivates defects and impurities on the surface of the second doped semiconductor layer 5, and also acts as an anti-reflection layer, reflecting sunlight incident from the light-receiving surface 12 of the semiconductor substrate 1 back into the semiconductor substrate 1, increasing photoelectric conversion efficiency. It also acts as a protective layer, reducing the erosion of the second doped semiconductor layer 5 and the first passivation layer 4 by moisture and impurities in the environment.

[0070] In the embodiments, such as Figure 1 and Figure 2The thickness of the second passivation layer 6 shown can be 20~200 nm. In the example, it can be a typical but non-limiting thickness such as 20 nm, 50 nm, 80 nm, 100 nm, 130 nm, 150 nm, 180 nm, 200 nm, or any range between two thicknesses.

[0071] In the embodiments, such as Figure 1 and Figure 2 The material of the second passivation layer 6 shown may include silicon nitride (SiN). x ), silicon dioxide (SiO) x ), silicon oxynitride (SiO) x N y At least one of the following.

[0072] The second passivation layer 6, having the aforementioned thickness range and material type, can improve its effectiveness in performing the aforementioned functions in electrode region A and electrode region B.

[0073] In some embodiments, such as Figure 1 and Figure 2 The back electrode 7 shown can be a conventional back electrode and material. In the embodiment, the width of the back electrode 7 in the electrode region is less than the width of any one of the following layers: tunneling oxide layer 2, first doped semiconductor layer 3, first passivation layer 4, second doped semiconductor layer 5, etc. Its material may include at least one of silver, copper, etc.

[0074] Composite functional structure located in non-electrode region B: In some embodiments, such as Figure 1 and Figure 2 In the TOPCon battery of the present application embodiment shown, since the first passivation layer 4, the second doped semiconductor layer 5, or the second passivation layer 6 contained in the composite functional structure in the electrode region A on the backlight surface of the semiconductor substrate all extend from the electrode region A to the non-electrode region B, the non-electrode region B, along the direction away from the semiconductor substrate 1, has a composite functional structure formed by the stacked first passivation layer 4 and the second doped semiconductor layer 5, or has a composite functional structure formed by the stacked first passivation layer 4, the second doped semiconductor layer 5, and the second passivation layer 6.

[0075] In some embodiments, the first passivation layer 4 extending into the non-electrode region B is stacked on the back surface 11 of the non-electrode region B. Thus, the first passivation layer 4 disposed in the non-electrode region B can perform the passivation function as described above, passivating the back surface 11 of the semiconductor substrate 1 in the non-electrode region B, reducing the dangling bond density of the back surface 11 in the non-electrode region B, reducing the recombination rate of charge carriers in the back surface 11 in the non-electrode region B, and improving the short-circuit current and open-circuit voltage of the TOPCon battery in this embodiment. Meanwhile, the second doped semiconductor layer 5, disposed in the non-electrode region B and stacked with the first passivation layer 4, also performs the function as described above, blocking the migration of external positively charged ions to the first passivation layer 4 in the non-electrode region B, improving the anti-PID performance and the stability of electrical performance such as photoelectric conversion efficiency of the TOPCon battery in this embodiment.

[0076] In some embodiments, such as Figure 1 and Figure 2 In the TOPCon battery of the present application embodiment shown, when the composite functional structure disposed in electrode region A and the composite functional structure disposed in non-electrode region B are defined as tower base structures, then as follows: Figure 1 and Figure 2 As shown, the total height h1 of the tower base in electrode region A is greater than the total height h2 of the tower base in non-electrode region B, that is, h1 > h2.

[0077] In this embodiment, the height difference between the total height h1 of the tower base in electrode region A and the total height h2 of the tower base in non-electrode region B is 1 μm to 10 μm, i.e., h1 - h2 = 1 μm to 10 μm. This height difference between electrode region A and non-electrode region B reduces the contact resistance of electrode region A and reduces parasitic light absorption loss in non-electrode region B, thereby improving the current density (Jsc) and fill factor (FF) of the TOPCon cell. Furthermore, this height difference range effectively balances the electrical and optical performance of the TOPCon cell, synergistically improving cell efficiency and reducing performance degradation.

[0078] In some embodiments, such as Figure 1 and Figure 2 In the TOPCon battery of the present application embodiment shown, the width of the composite functional structure disposed in the electrode region A is greater than the width of the composite functional structure disposed in the non-electrode region B along the direction from electrode region A to non-electrode region B.

[0079] In some embodiments, such as Figure 1 and Figure 2In the TOPCon battery of this embodiment shown in this application, the light-receiving surface 12 of the semiconductor substrate 1 is provided with a third passivation layer 8, an antireflection layer 9, and a front electrode 10. The third passivation layer 8 is disposed on the light-receiving surface 12, and the antireflection layer 9 is disposed on the surface of the third passivation layer 8 away from the semiconductor substrate 1. The front electrode 10 is disposed on the surface of the antireflection layer 9 away from the semiconductor substrate 1, and the front electrode 10 is in ohmic contact with the third passivation layer 8. Furthermore, the thicknesses of the third passivation layer 8, the antireflection layer 9, and the front electrode 10 can be set according to conventional dimensions, and the materials of the three can also be conventional materials corresponding to each layer.

[0080] [Preparation method of TOPCon battery] Secondly, embodiments of this application provide a method for fabricating the TOPCon battery described in the above embodiments. In some embodiments, combined with Figure 1 and Figure 2 The method for preparing the TOPCon battery in this application includes the following steps: S10: A semiconductor substrate 1 is provided, on which an electrode region A and a non-electrode region B are disposed on the back surface 11; S20: A tunneling oxide layer 2 and a first doped semiconductor layer 3 are sequentially formed in the electrode region A of the backlight surface 11 in the semiconductor substrate 1. S30: A first passivation layer 4 is first formed on the surface of the first doped semiconductor layer 3 away from the semiconductor substrate 1 and on the backlight surface 11 in the non-electrode region B, and then a second doped semiconductor layer 5 is formed on the surface of the first passivation layer 4 away from the semiconductor substrate 1.

[0081] Because a second doped semiconductor layer 5 is formed on the surface of the first passivation layer 4 located in electrode region A and non-electrode region B on the back surface 11 of the semiconductor substrate 1, away from the semiconductor substrate 1, the functional layer structure of the electrode region A and non-electrode region B of the fabricated TOPCon cell includes the second doped semiconductor layer 5. Thus, the formed second doped semiconductor layer 5 serves to block the migration of external positively charged ions to the first passivation layer 4, particularly to block the migration of external positively charged ions to the first passivation layer 4 located in non-electrode region B. This can neutralize positively charged ions migrating from the outside, improving the stability of the field passivation effect of the first passivation layer 4, thereby enhancing the stability of the electrical performance of the Topcon cell in this embodiment, such as its resistance to potential-induced degradation (PID) and photoelectric conversion efficiency.

[0082] Step S10: The semiconductor substrate 1 provided in step S10 is the semiconductor substrate 1 in the Topcon battery of the above application embodiment. Therefore, the structure and material of the semiconductor substrate 1 are the same as those of the semiconductor substrate 1 in the Topcon battery of the above application.

[0083] In some embodiments, the structure of the semiconductor substrate 1 provided in step S10 may be as follows: Figure 1 and Figure 2 As shown, it has a backlight surface 11 and a light-receiving surface 12. The backlight surface 11 is a polished surface, and the light-receiving surface 12 can be a velvety surface.

[0084] In some embodiments, having as Figure 1 The semiconductor substrate 1 shown, having a polished surface (backlight surface 11) and a textured surface (light-receiving surface 12), can be prepared according to the following pretreatment method: First, the backlight surface 11 and the light-receiving surface 12 of the semiconductor substrate 1 are texturized to form a textured structure; then, a mask for protecting the textured structure is formed on the light-receiving surface 12 of the semiconductor substrate 1; next, the backlight surface 11 of the semiconductor substrate is polished to form a polished surface; finally, the mask is removed.

[0085] The texturing process for the backlight surface 11 and the light-receiving surface 12 of the semiconductor substrate 1 can be performed by etching or other texturing methods; the polishing process for the backlight surface 11 can be performed by polishing liquid such as alkaline polishing liquid; the material of the mask can include at least one of silicon oxide, silicon nitride, and silicon oxynitride, which can be removed in subsequent steps.

[0086] Step S20: In such Figure 1 and Figure 2 The method of sequentially forming a tunneling oxide layer 2 and a first doped semiconductor layer 3 in the electrode region A of the backlight surface 11 of the semiconductor substrate 1 can be based on conventional film preparation methods for each layer material. For example, plasma-enhanced chemical vapor deposition (PECVD) can be used to prepare the corresponding film layer according to each layer material.

[0087] As in the embodiment, a tunneling oxide layer 2, a first doped semiconductor layer 3, and a mask layer are sequentially deposited by PECVD on the entire surface of the backlight side 11 of the semiconductor substrate 1. Then, a high-temperature annealing process is performed, combined with laser-assisted film-opening treatment of the non-electrode region B to remove the tunneling oxide layer 2, the first doped semiconductor layer 3, and the mask layer in the non-electrode region B. Finally, byproducts such as phosphosilicate glass (PSG) are removed and a deep fine cleaning (RCA) process is performed to ensure that the surface of the semiconductor substrate 1 and the surface of the first doped semiconductor layer 3 away from the semiconductor substrate 1 are in an atomically clean state.

[0088] In addition, the materials used for the tunneling oxide layer 2 and the first doped semiconductor layer 3 in step S20, as well as the thickness of the formed film, can be the same as those used for the tunneling oxide layer 2 and the first doped semiconductor layer 3 in the Topcon battery of the above-described application embodiment.

[0089] Step S30: A first passivation layer 4 is first formed on the surface of the first doped semiconductor layer 3 away from the semiconductor substrate 1 and in the non-electrode region B of the backlight surface 11. Then, a second doped semiconductor layer 5 is formed on the surface of the first passivation layer 4 away from the semiconductor substrate 1. Since the first passivation layer 4 and the second doped semiconductor layer 5 are formed on both the surface of the first doped semiconductor layer 3 and in the non-electrode region B of the backlight surface 11, it can be considered that the second doped semiconductor layer 5 in the non-electrode region B and the second doped semiconductor layer 5 in the electrode region A are connected as one unit. Of course, it can also be considered that the first passivation layer 4 in the non-electrode region B and the first passivation layer 4 in the electrode region A are also connected as one unit.

[0090] In this embodiment, after forming the first passivation layer 4 on both the surface of the first doped semiconductor layer 3 and in the non-electrode region B of the backlight surface 11, a third passivation layer 8 can be formed on the light-receiving surface 12 of the semiconductor substrate 1, and then a second doped semiconductor layer 5 can be formed on the surface of the first passivation layer 4 away from the semiconductor substrate 1.

[0091] Furthermore, the materials used for preparing the first passivation layer 4 and the second doped semiconductor layer 5 in step S30, as well as the thickness of the formed film, can be the same as those used for the first passivation layer 4 and the second doped semiconductor layer 5 in the Topcon battery of the above-described embodiments. The formation of the first passivation layer 4 or further the formation of the third passivation layer 8 can be achieved using methods including, but not limited to, atomic layer deposition (ALD), and the formation of the second doped semiconductor layer 5 can be achieved using methods including, but not limited to, plasma-enhanced chemical vapor deposition (PECVD).

[0092] In the embodiments, the film characteristics of the second doped semiconductor layer 5 formed in step S30 include film thickness, dopant element atomic concentration, and dopant element type, which are as described above in the Topcon battery embodiment of the application.

[0093] In some embodiments, after step S30, a surface on the second doped semiconductor layer 5 away from the semiconductor substrate 1 may be formed as shown in the figure. Figure 1 and Figure 2 The second passivation layer 6 in the process.

[0094] In some embodiments, after step S30, the following may also be included: Figure 1 and 2 The third passivation layer 8 is moved away from the surface antireflection layer 9 of the semiconductor substrate 1.

[0095] Of course, the Topcon battery in this application embodiment also includes the fabrication of a functional layer on the surface of the electrode region A on the backlight side of the semiconductor substrate 1, such as... Figure 1 and Figure 2The steps of forming a back electrode 7 and a front electrode 10 on the surface of a functional layer on one side of the light-receiving surface 12 of the semiconductor substrate 1.

[0096] [Battery Components] Thirdly, embodiments of this application also provide a battery module. The battery module includes the Topcon battery of the above-described embodiments, or includes a Topcon battery prepared by the Topcon battery preparation method of the above-described embodiments. Therefore, the battery module of this application has enhanced anti-degradation performance and improved stability of electrical properties such as photoelectric conversion efficiency.

[0097] [Electrical appliances] Fourthly, this application also provides an electrical device. The electrical device of this application includes a power supply unit, and may also include other auxiliary or necessary components. The power supply unit contains the Topcon battery or battery assembly of the above application embodiment, which is used to provide electrical energy. Therefore, the energy self-sufficiency capability of the electrical device of this application embodiment is enhanced, and its service life is extended.

[0098] In some embodiments, the power supply may include at least one of a rechargeable power source, a solar-powered electronic device, a solar-powered drone, etc.

[0099] [Example] The following describes embodiments of this application. The embodiments described below are exemplary and are only used to explain this application, and should not be construed as limiting this application. Where specific techniques or conditions are not specified in the embodiments, they are performed according to the techniques or conditions described in the literature in this field or according to the product instructions. Reagents or instruments used, unless otherwise specified, are all conventional products that can be obtained commercially.

[0100] Example 1: This embodiment provides a Topcon battery, the structure of which is as follows: Figure 1 As shown, the substrate includes an N-type crystalline silicon semiconductor substrate 1, which has a backlight surface 11 and a light-receiving surface 12 with a textured surface. The backlight surface 11 is divided into an electrode region A and a non-electrode region B. Along the direction away from the semiconductor substrate 1, a tunneling oxide layer 2, a first doped semiconductor layer 3, a first passivation layer 4, a second doped semiconductor layer 5, a second passivation layer 6, and a back electrode 7 are sequentially disposed in the electrode region A. The first passivation layer 4, the second doped semiconductor layer 5, and the second passivation layer 6 extend into the entire non-electrode region B; that is, in the non-electrode region B and along the direction away from the semiconductor substrate 1, the first passivation layer 4, the second doped semiconductor layer 5, and the second passivation layer 6 are sequentially disposed. Along the direction away from the semiconductor substrate 1, a third passivation layer 8, an antireflection layer 9, and a front electrode 10 are sequentially disposed on the light-receiving surface 12 of the semiconductor substrate 1.

[0101] In this embodiment of the Topcon battery, the first doped semiconductor layer 3 has the same type of doping source as the semiconductor substrate 1; the first passivation layer 4 is an AlOx layer; the second doped semiconductor layer 5 is an N-type polycrystalline silicon layer with a thickness of 10 nm, and the doping source is phosphorus (P) with a P atom concentration of 1 × 10⁻⁶. 20 cm -3 The second passivation layer 6 is a silicon nitride layer; the third passivation layer 8 is an AlOx layer; and the antireflection layer 9 is a silicon nitride layer.

[0102] The Topcon battery fabrication method includes the following steps: S1: The 210-sized (quasi-square with a side length of 210mm) N-type silicon wafer is subjected to pre-cleaning, texturing, boron diffusion, BSG removal and alkaline polishing in sequence to obtain a backlight surface 11 with a smooth surface and a light-receiving surface 12 with a texturized structure. S2: A tunneling layer 2, a first doped semiconductor layer 3 with the same doping type as the substrate and a mask layer are deposited on the back surface 11 of an N-type crystalline silicon semiconductor substrate 1 using the PECVD method. Then, high-temperature annealing, laser-assisted opening of the non-electrode region B, and PSG and RCA removal cleaning are performed in sequence. S3: In step S2, the backlight surface 11 in the first doped semiconductor layer 3 and non-electrode region B uses ALD to deposit an aluminum oxide thin film as the first passivation layer 4, while a deposited aluminum oxide thin film is formed on the light-receiving surface 12 as the third passivation layer 8. S4: In step S3, a second doped semiconductor layer 5 and a SiNx passivation layer 6 with an ultrathin N+poly layer of 10 nm are sequentially deposited on the surface of the first passivation layer 4; an antireflection layer 9 is formed on the surface of the third passivation layer 8; electrode patterns are printed on the surfaces of the SiNx passivation layer 6 and the antireflection layer 9 by screen printing, and sintering is performed to form the back electrode 7 and the front electrode 10, followed by light injection and Leco laser-assisted sintering.

[0103] Example 2, Example 3: Examples 2 and 3 provide a Topcon battery, which differs from the Topcon battery in Example 1 in that the thickness of the second doped semiconductor layer 5 in Example 2 is 50 nm, while the thickness of the second doped semiconductor layer 5 in Example 3 is 1 nm. The other aspects are the same, as shown in Table 1 below.

[0104] In Examples 2 and 3, the Topcon batteries were prepared using the same method as in Example 1.

[0105] Example 4 and Example 5: Examples 4 and 5 each provide a Topcon battery. Compared with the Topcon battery in Example 1, the difference is that the dopant of the second doped semiconductor layer 5 in Example 4 is carbon (N), and the N atom concentration is 2 × 10⁻⁶. 18 cm -3 The difference lies in that the dopant of the second doped semiconductor layer 5 in Example 5 is carbon (C), and the C atom concentration is 2 × 10⁻⁶. 18 cm -3 The rest are the same, as shown in Table 1 below.

[0106] In Examples 4 and 5, the Topcon batteries were prepared using the same method as in Example 1.

[0107] Comparative Example 1: Comparative Example 1 provides a Topcon battery. The difference between this Topcon battery and the Topcon battery in Example 1 is that the Topcon battery in Comparative Example 1 does not contain the second doped semiconductor layer 5, but is otherwise the same.

[0108] The thickness, type of doped element, and concentration of doped atoms of the second doped semiconductor layer 5 in the above embodiments and comparative examples are shown in Table 1 below.

[0109] Table 1

[0110] Topcon battery performance tests: 1. The Topcon batteries in the above embodiments and comparative examples were subjected to anti-PID performance tests. The Gap% value is the percentage difference between the relevant performance value of the Topcon battery after 192H treatment and the pre-treatment relevant performance value. The test results are shown in Table 2 below. The anti-PID performance test method was the direct pressure application method to the frame.

[0111] Table 2

[0112] As shown in Table 2, the Gap% values ​​of the Topcon batteries in Examples 1 to 5 are significantly lower than the Gap% value of the Topcon battery in Comparative Example 1. Therefore, it can be concluded that the Topcon batteries in this application, with the addition of... Figure 1 and Figure 2 The second doped semiconductor layer 5 can effectively block the migration of external positively charged ions to the first passivation layer 4, thereby improving the anti-PID performance of the Topcon battery.

[0113] 2. The Topcon batteries in the above embodiments and comparative examples were subjected to the relevant performance tests shown in Table 3 below. The test results for Embodiment 1 and Comparative Example 1 are shown in Table 3 below. The relevant performance testing methods employed an industry-standard solar cell IV testing machine. Table 3

[0114] Based on the data in Table 3, comparing the relevant performance of the Topcon batteries in Examples 1 and 2, it can be seen that, compared to the Topcon battery in Comparative Example 1 which does not have a doped semiconductor layer, the addition of such... Figure 1 and Figure 2 The electrical properties of the Topcon cell with the second doped semiconductor layer 5, including Eta, Uoc, Isc, FF, Rs, Rsh, and Irev2, were all improved. Among these, the improvements in open-circuit voltage and fill factor of the Topcon cell were relatively significant. Furthermore, tests of the relevant performance data from Examples 2 to 5, as shown in Table 3, revealed that the electrical properties of the Topcon cell in this application embodiment, including Eta, Uoc, Isc, FF, Rs, Rsh, and Irev2, were all improved.

[0115] The above embodiments merely illustrate several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of this patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. A tunneling oxide passivated contact solar cell, characterized in that, The device includes a semiconductor substrate, wherein an electrode region and a non-electrode region are disposed on the back surface of the semiconductor substrate; along a direction away from the semiconductor substrate, a tunneling oxide layer, a first doped semiconductor layer, a first passivation layer, a second doped semiconductor layer and a back electrode are sequentially disposed in the electrode region; wherein the first passivation layer and the second doped semiconductor layer extend into the non-electrode region.

2. The tunneling oxide passivated contact solar cell as described in claim 1, characterized in that, The second doped semiconductor layer satisfies at least one of the following (1) to (4): (1) The thickness of the second doped semiconductor layer is less than the thickness of the first doped semiconductor layer; (2) The thickness of the second doped semiconductor layer is 1 nm to 50 nm; (3) The atomic concentration of the doped element in the second doped semiconductor layer is 1×10⁻⁶. 15 ~1×10 21 cm -3 ; (4) The doping element contained in the second doped semiconductor layer includes at least one of C, N, O, P and As.

3. The tunneling oxide passivated contact solar cell as described in claim 1 or 2, characterized in that: The first passivation layer, extending into the non-electrode region, is stacked on the back surface of the non-electrode region.

4. The tunneling oxide passivated contact solar cell as described in claim 1 or 2, characterized in that: The polarity of the first doped semiconductor layer and the second doped semiconductor layer is the same as the polarity of the semiconductor substrate; And / or, the polarity of the first doped semiconductor layer and the second doped semiconductor layer is the same as that of the semiconductor substrate, which is an N-type doped semiconductor layer.

5. The tunneling oxide passivated contact solar cell as described in claim 1 or 2, characterized in that: It also includes a second passivation layer, which is disposed between the second doped semiconductor layer and the back electrode in the electrode region, and extends to the non-electrode region and is stacked on the surface of the second doped semiconductor layer in the non-electrode region away from the semiconductor substrate.

6. The tunneling oxide passivated contact solar cell as described in claim 1 or 2, characterized in that: The first doped semiconductor layer includes a doped semiconductor layer a, a barrier layer, and a doped semiconductor layer b, and the doped semiconductor layer a, the barrier layer, and the doped semiconductor layer b are stacked sequentially along a direction away from the semiconductor substrate.

7. The tunneling oxide passivated contact solar cell as described in claim 1 or 2, characterized in that: The total height of the tower base located in the electrode region is greater than the total height of the tower base located in the non-electrode region.

8. The tunneling oxide passivated contact solar cell as described in claim 7, characterized in that: The height difference between the total height of the tower base in the electrode area and the total height of the tower base in the non-electrode area is 1 μm to 10 μm.

9. A method for fabricating a tunneling oxide passivated contact solar cell, characterized in that, Includes the following steps: A semiconductor substrate is provided, on which an electrode region and a non-electrode region are disposed on the back surface; A tunneling oxide layer and a first doped semiconductor layer are sequentially formed in the electrode region of the backlight surface; A first passivation layer is first formed on the surface of the first doped semiconductor layer away from the semiconductor substrate and in the non-electrode region of the backlight surface, and then a second doped semiconductor layer is formed on the surface of the first passivation layer away from the semiconductor substrate.

10. The preparation method as described in claim 9, characterized in that: The formed second doped semiconductor layer satisfies at least one of the following (1) to (4): (1) The thickness of the second doped semiconductor layer is less than the thickness of the first doped semiconductor layer; (2) The thickness of the second doped semiconductor layer is 1 nm to 50 nm; (3) The atomic concentration of the doped element in the second doped semiconductor layer is 1×10⁻⁶. 15 ~1×10 21 cm -3 ; (4) The second doped semiconductor layer further includes at least one doping element selected from P, C, N, and O; and / or Following the step of forming the second doped semiconductor layer, the following steps are also included: A second passivation layer is formed on the surface of the second doped semiconductor layer that is away from the semiconductor substrate.

11. A battery assembly, characterized in that, The invention includes tunneling oxide passivated contact solar cells according to any one of claims 1 to 8, or tunneling oxide passivated contact solar cells prepared by the preparation method according to any one of claims 9 to 10.

12. An electrical appliance, characterized in that, Includes the tunneling oxide passivated contact solar cell according to any one of claims 1 to 8 or the battery module according to claim 11.

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