A method for manufacturing an LED chip and an LED chip

Abstract

The application provides a preparation method of an LED chip and the LED chip, and relates to the technical field of LED chips. In the preparation method, when a positive LED is prepared, a passivation treatment is performed on an area exposed by a first part of a patterned area of a P-type layer before ion source pretreatment, a high-resistance passivation area is formed on a side of the exposed area away from a substrate, the passivation area is used for being connected with a metal electrode, and leakage channels are prevented from being generated in a part of an epitaxial structure corresponding to the exposed area of the P-type layer in the ion source pretreatment process. Therefore, when the positive LED is prepared by using the preparation method, the ion source pretreatment can be used to treat a wafer source composed of the epitaxial structure and a current control layer, the adhesion between the wafer source and a metal adhesive layer of the metal electrode is enhanced, the adhesive metal layer in the metal electrode can be thinned or even removed, the reflectivity of the metal electrode is improved, and better ohmic contact can be formed between the metal electrode and the surface of the wafer source.

Description

Technical Field

[0001] This application relates to the field of LED chip technology, and in particular to a method for preparing an LED chip and an LED chip. Background Technology

[0002] LED chips have experienced rapid development and have widely replaced traditional lighting sources due to their advantages such as high efficiency, energy saving, long lifespan, environmental friendliness, and rich colors. However, conventional LED chips suffer from reduced luminous efficiency due to the light-blocking and light-absorbing effects of their electrodes. Increasing the light reflectivity of the electrodes can effectively improve the chip's luminous efficiency.

[0003] In traditional LED chips, the bottommost layer (the layer closest to the epitaxial structure) of the electrode structure is typically a low-reflectivity adhered metal layer (such as Cr, Ni, or Ti). Generally, the thinner the metal adhered layer in the electrode, the higher the reflectivity of the electrode, and the higher the brightness of the LED chip. However, this metal adhered layer cannot be too thin, otherwise wire bonding and electrode detachment will occur. Therefore, the electrode reflectivity is limited, and it cannot reach the ideal reflectivity value close to that of a high-reflectivity metal layer (such as Al). Summary of the Invention

[0004] In view of this, this application provides a method for fabricating an LED chip and an LED chip, as follows:

[0005] This application provides a method for fabricating an LED chip, comprising:

[0006] Provide a substrate;

[0007] An epitaxial structure is formed on one side of the substrate. The formation of the epitaxial structure includes an N-type layer, a quantum well layer, and a P-type layer arranged in sequence along a direction away from the substrate, wherein the quantum well layer and the P-type layer expose portions of the N-type layer.

[0008] A current control layer is formed on the side of the epitaxial structure away from the substrate. Forming the current control layer includes forming a first portion located on the side of the P-type layer away from the substrate. The first portion includes a patterned region that exposes the P-type layer and its corresponding portion.

[0009] The portion of the P-type layer exposed by the patterned region is passivated to form a high-resistivity passivation region;

[0010] After passivating the portion of the P-type layer exposed by the patterned region, the current control layer and the epitaxial structure are pre-treated, and the metal electrode is placed on the side of the pre-treated current control layer away from the epitaxial structure to enhance the adhesion between the current control layer, the epitaxial structure and the metal electrode.

[0011] The metal electrode located on the side of the first portion away from the epitaxial structure is connected to the high-resistivity passivation region in the P-type layer through the patterned region.

[0012] Optionally, forming the current control layer further includes forming a second portion located on the side of the exposed portion of the N-type layer away from the substrate.

[0013] Optionally, forming the current control layer includes:

[0014] A current blocking layer is formed on the side of the epitaxial structure away from the substrate. The current blocking layer includes a first current blocking layer portion located on the side of the P-type layer away from the substrate, and a second current blocking layer portion located on the exposed portion of the N-type layer away from the substrate.

[0015] A transparent conductive layer is formed on the side of the first current blocking layer away from the epitaxial structure;

[0016] The first current blocking layer includes a first patterned region that exposes the P-type layer and its opposite portion; the transparent conductive layer includes a second patterned region that exposes the first patterned region.

[0017] Optionally, the passivation process on the portion of the P-type layer exposed by the patterned region includes:

[0018] After the transparent conductive layer is formed, the portion of the P-type layer exposed by the first patterned region is passivated using a preset plasma to form the high-resistivity passivation region.

[0019] The preset plasma includes at least one plasma used to passivate the portion of the P-type layer exposed by the first patterned region.

[0020] Optionally, the passivation region extends into the P-type layer along the side of the P-type layer away from the substrate, and the passivation region is located inside the P-type layer, or the passivation region penetrates the P-type layer.

[0021] Optionally, the metal electrode includes a P-metal electrode and an N-metal electrode, and the step of disposing the metal electrode on the side of the pretreated current control layer away from the epitaxial structure includes:

[0022] The P-metal electrode is formed on the side of the first portion away from the epitaxial structure, and the P-metal electrode is connected to the high-resistivity passivation region in the P-type layer through the patterned region;

[0023] The N-metal electrode is formed on the side of the second portion away from the epitaxial structure;

[0024] Wherein, along the direction away from the epitaxial structure, the P metal electrode and the N metal electrode sequentially include an adhesive layer, a reflective layer, a barrier layer and a bonding layer, and the thickness of the adhesive layer is not greater than a preset value; or, along the direction away from the epitaxial structure, the P metal electrode and the N metal electrode sequentially include a reflective layer, a barrier layer and a bonding layer.

[0025] This application also provides an LED chip, which is an LED chip prepared using any of the above-described LED chip preparation methods, comprising:

[0026] Substrate;

[0027] An epitaxial structure located on one side of the substrate, the epitaxial structure comprising an N-type layer, a quantum well layer and a P-type layer sequentially stacked along a direction away from the substrate, wherein the quantum well layer and the P-type layer expose portions of the N-type layer;

[0028] A current control layer located on the side of the epitaxial structure away from the substrate, the current control layer including a first portion located on the side of the P-type layer away from the substrate;

[0029] The first part includes a patterned region that exposes the P-type layer and its corresponding portion, and the portion of the P-type layer exposed by the patterned region includes a high-resistivity passivation region.

[0030] A metal electrode located on the side of the current control layer away from the epitaxial structure, wherein the metal electrode located on the first portion away from the epitaxial structure is connected to the high-resistivity passivation region in the P-type layer through the patterned region.

[0031] Optionally, the current control layer further includes a second portion located on the side of the exposed portion of the N-type layer away from the substrate.

[0032] Optionally, the current control layer includes a current blocking layer and a transparent conductive layer;

[0033] The current blocking layer is located on the side of the epitaxial structure away from the substrate. The current blocking layer includes a first current blocking layer portion located on the side of the P-type layer away from the substrate, and a second current blocking layer portion located on the exposed portion of the N-type layer away from the substrate.

[0034] The transparent conductive layer is located on the side of the first current blocking layer that is away from the epitaxial structure.

[0035] The first current blocking layer includes a first patterned region that exposes the P-type layer and its opposite portion; the transparent conductive layer includes a second patterned region that exposes the first patterned region.

[0036] Optionally, the passivation region extends into the P-type layer along the side of the P-type layer away from the substrate, and the passivation region is located inside the P-type layer, or the passivation region penetrates the P-type layer.

[0037] Optionally, the metal electrode includes a P-metal electrode and an N-metal electrode; the P-metal electrode is located on the side of the first portion away from the substrate, and the P-metal electrode is connected to the high-resistivity passivation region in the P-type layer through the patterned region; the N-metal electrode is located on the side of the second portion away from the substrate.

[0038] Wherein, along the direction away from the epitaxial structure, the P metal electrode and the N metal electrode sequentially include an adhesive layer, a reflective layer, a barrier layer and a bonding layer, and the thickness of the adhesive layer is not greater than a preset value; or, along the direction away from the epitaxial structure, the P metal electrode and the N metal electrode sequentially include a reflective layer, a barrier layer and a bonding layer.

[0039] Optionally, the preset value is 15 angstroms.

[0040] Compared with existing technologies, the beneficial effects of the technical solution of this application are as follows:

[0041] Before the ion source pretreatment, the exposed area of ​​the P-type layer, which is exposed by the patterned region of the first part, is passivated. This forms a high-resistivity passivation region on the side of the exposed P-type layer away from the substrate, which is then used to connect to a metal electrode located on the side of the first part away from the epitaxial structure. This effectively eliminates the leakage current path in the epitaxial structure corresponding to the exposed P-type layer during ion source pretreatment, thus fundamentally preventing leakage current paths from forming in the epitaxial structure due to damage during ion source pretreatment. Therefore, this fabrication method employs ion source pretreatment to pretreat the wafer source composed of the current control layer and epitaxial structure. This enhances the adhesion between the current control layer and the epitaxial structure and the metal bonding layer in the metal electrode. Furthermore, the portion of the epitaxial structure corresponding to the exposed P-type layer will not generate leakage channels due to ion source pretreatment. This allows for the thinning or even removal of the bonding metal layer in the metal electrode, thereby improving the reflectivity of the metal electrode and enhancing the brightness of the LED chip. Simultaneously, ion source pretreatment also helps form better ohmic contact between the metal electrode and the wafer source surface, achieving the goal of reducing the LED chip voltage. Attached Figure Description

[0042] To more clearly illustrate the technical solutions in the embodiments of this application or related technologies, the drawings used in the description of the embodiments or prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of this application. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.

[0043] The structures, proportions, sizes, etc., shown in the accompanying drawings are only for the purpose of assisting those skilled in the art in understanding and reading the content disclosed in the specification, and are not intended to limit the implementation conditions of this application. Therefore, they have no substantial technical significance. Any modifications to the structure, changes in the proportions, or adjustments to the size should still fall within the scope of the technical content disclosed in this application, provided that they do not affect the effects and purposes that this application can produce.

[0044] Figure 1 A flowchart illustrating a method for fabricating an LED chip provided in this application;

[0045] Figures 2-7 A schematic diagram of the structure formed by different process steps in the fabrication method of an LED chip provided in this application;

[0046] Figure 8 This is a schematic diagram of the structure of a metal electrode in an LED chip provided in this application;

[0047] Figure 9 A schematic diagram of the structure of a metal electrode in another LED chip provided in this application;

[0048] Figure 10 A schematic diagram of the etching mask for the current blocking layer;

[0049] Figure 11 A schematic diagram of the photoresist for a transparent conductive layer;

[0050] Figure 12 and Figure 13 These are schematic diagrams of two types of photoresists treated with hydrogen plasma passivation.

[0051] Figure 14 This is a schematic diagram of the etching mask for the metal electrode. Detailed Implementation

[0052] The embodiments of this application will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0053] To make the above-mentioned objectives, features and advantages of this application more apparent and understandable, the application will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0054] As described in the background section, conventional LED chips suffer from reduced luminous efficiency due to the light-blocking and light-absorbing effects of the electrodes.

[0055] Currently, in order to solve the above problems, ion source pretreatment is usually used to remove organic contaminants from the surface of the epitaxial wafer before electrode evaporation. This helps to enhance the adhesion between the electrode metal and the wafer source surface, so that the thickness of the electrode metal adhesion layer can be thinner, or even the adhesion layer can be eliminated.

[0056] However, ion source pretreatment is currently mostly applied to the electrode process of flip-chip LEDs. This is because the epitaxial layer beneath the P-electrode of a flip-chip is not exposed; it is protected by a CB (Current Blocking Layer) or ITO (Indium Tin Oxide), thus preventing damage to the epitaxial wafer during ion source pretreatment. In contrast, the area corresponding to the P-electrode in the epitaxial wafer of a standard LED chip employs a CB and ITO via design. This aims to improve the adhesion of the P-electrode, ensuring it doesn't fall off during wire bonding. Since the adhesion between the electrode metal layer and the P-type layer in the epitaxial wafer is higher than its adhesion to ITO or CB, a via is used between CB and ITO to expose part of the P-type layer, maintaining contact between the P-type layer and the electrode metal and improving wire bonding capabilities.

[0057] However, the drilling of holes in CB and ITO can cause damage to the exposed epitaxial wafers during ion source pretreatment, leading to LED chip leakage and low electrical yield. Therefore, it is currently impossible to effectively reduce the thickness of the metal adhesion layer of the electrode metal in upright LED chips, resulting in limited reflectivity of the upright LED chip electrodes and an inability to achieve the ideal reflectivity value close to that of high-reflectivity metal layers (such as Al).

[0058] Based on the above, this application provides a method for fabricating an LED chip, such as... Figure 1 As shown, Figure 1 This application provides a flowchart of an LED chip fabrication method, which includes:

[0059] S1: As Figure 2 As shown, a substrate 100 is provided.

[0060] S2: As Figure 3 As shown, an epitaxial structure 200 is formed on one side of the substrate 100. Continuing as... Figure 3 As shown, the epitaxial structure 200 includes: an N-type layer 202, a quantum well layer 204, and a P-type layer 206 sequentially formed along a direction away from the substrate 100. Specifically, the quantum well layer 204 and the P-type layer 206 expose portions of the N-type layer 202; that is, both the quantum well layer 204 and the P-type layer 206 expose portions of the N-type layer 202. In other words, in the epitaxial structure 200, a stepped structure with exposed portions of the N-type layer 202 is formed along a direction away from the substrate 100. It should be noted that the N-type layer 202 can be an N-type GaN layer, and the P-type layer 206 can be a P-type GaN layer.

[0061] S3: As Figure 4As shown, a current control layer 208 is formed on the side of the epitaxial structure 200 away from the substrate 100. The current control layer 208 includes a first portion 12, which is located on the side of the P-type layer 206 away from the substrate 100. The first portion 12 includes a patterned region that exposes the P-type layer 206 and its corresponding portion, that is, the patterned region of the first portion 12 exposes the P-type layer 206 beneath it.

[0062] S4: As Figure 5 As shown, Figure 5 for Figure 4 The schematic diagram of the structure after passivation treatment in the area within the dashed box shows that the exposed portion of the patterned area of ​​the P-type layer 206 is passivated. A high-resistivity passivation region 16 extending into the interior of the P-type layer is formed on the side of the exposed portion of the patterned area of ​​the P-type layer 206 away from the substrate 100. In other words, the area of ​​the P-type layer 206 that will subsequently contact the metal electrode is passivated.

[0063] S5: After passivating the portion of the P-type layer 206 exposed by the patterned region of the first part 12, the current control layer 208 and the epitaxial structure 200 are pretreated. That is, the wafer source formed by the current control layer 208 and the epitaxial structure 200 undergoes the aforementioned ion source pretreatment to remove organic contaminants and other pollutants from the surface of the wafer source formed by the epitaxial structure 200 and the current control layer 208, which helps to enhance the adhesion between the metal electrode and the wafer source surface. Afterwards, as... Figure 6 As shown, the metal electrode is disposed on the side of the pretreated current control layer 208 away from the epitaxial structure 200 to enhance the adhesion between the current control layer 208 and the metal electrode, as well as the adhesion between the epitaxial structure 200 and the metal electrode.

[0064] In this process, the metal electrode (P-metal electrode 302, described below) located on the side of the first part 12 away from the epitaxial structure 200 is connected to the high-resistivity passivation region 16 in the P-type layer 206 through a patterned region. Since the wafer source composed of the current control layer 208 and the epitaxial structure 200 has undergone ion source pretreatment before the metal electrode is connected to the high-resistivity passivation region 16 in the P-type layer 206, the adhesion between the high-resistivity passivation region 16 in the P-type layer 206 and the metal electrode can be enhanced.

[0065] As described above, before the ion source pretreatment, this fabrication method passivates the exposed area of ​​the P-type layer 206 exposed by the patterned region of the first portion 12, thereby forming a high-resistivity passivation region 16 on the side of the exposed area of ​​the P-type layer 206 away from the substrate 100. This passivation region 16 is used to connect with the metal electrode. In other words, after forming the current control layer 208 and before the ion source pretreatment, this fabrication method passivates the exposed portion of the P-type layer 206, forming a high-resistivity passivation region 16 on the side of the exposed portion of the P-type layer 206 away from the substrate 100. This cuts off the leakage current path in the epitaxial structure 200 corresponding to the exposed area of ​​the P-type layer 206 during the ion source pretreatment process, thus fundamentally preventing the leakage current path from being generated in the portion of the epitaxial structure 200 corresponding to the exposed area of ​​the P-type layer 206 due to damage during the ion source pretreatment process. Therefore, this fabrication method forms a high-resistivity passivation region 16 on the exposed portion of the P-type layer 206 away from the substrate 100 after forming the current control layer 208 and before ion source pretreatment. This allows the wafer source composed of the current control layer 208 and the epitaxial structure 200 to be pretreated by ion source pretreatment during the fabrication of the upright LED chip. This enhances the adhesion between the wafer source and the metal bonding layer 306 of the metal electrode. Furthermore, the portion of the epitaxial structure 200 corresponding to the exposed portion of the P-type layer 206 will not generate a leakage current channel due to ion source pretreatment.

[0066] Based on the above, since this fabrication method can employ ion source pretreatment to pretreat the wafer source composed of the current control layer 208 and the epitaxial structure 200, enhancing the adhesion between the wafer source and the metal bonding layer 306 in the metal electrode, and preventing leakage channels from forming in the portion of the epitaxial structure 200 corresponding to the exposed P-type layer 206 due to ion source pretreatment, the bonding metal layer in the metal electrode can be thinned or even removed, thereby improving the reflectivity of the metal electrode and enhancing the brightness of the LED chip. Simultaneously, ion source pretreatment also helps the metal electrode form a better ohmic contact with the epitaxial structure 200 and the current control layer 208, thus helping to reduce the LED chip voltage.

[0067] In one embodiment of this application, such as Figure 4 As shown, the formation of the current control layer further includes forming a second portion 14, which is located on the side of the exposed portion of the N-type layer 202 away from the substrate 100. Subsequently, the N-electrode 304 is disposed on the side of the second portion 14 away from the epitaxial structure 200. Specifically, as... Figure 6As shown, the aforementioned metal electrodes include a P-metal electrode 302 and an N-metal electrode 304. The P-metal electrode 302 is located on the side of the first portion 12 of the current control layer 208 away from the epitaxial structure 200, and the high-resistivity passivation region 16 of the P-type layer 206 exposed by the patterned region of the first portion 12 is connected to the P-metal electrode 302. The N-metal electrode 304 is located on the side of the second portion 14 of the current control layer 208 away from the epitaxial structure 200, and is connected to the exposed portion of the N-type layer 202. That is, the N-metal electrode 304 is located on the side of the N-type layer 202 exposed by the quantum well layer 204 and the P-type layer 206 away from the substrate 100, and is connected to the exposed portion of the N-type layer 202.

[0068] In one embodiment of this application, for step S3 above, forming the current control layer 208 includes:

[0069] A current blocking layer 210 is formed on the side of the epitaxial structure 200 away from the substrate 100. For example... Figure 7 As shown, the current blocking layer 210 includes a first current blocking layer portion 1 located on the side of the P-type layer 206 away from the substrate 100, and a second current blocking layer portion 2 located on the exposed portion of the N-type layer 202 away from the substrate 100. A transparent conductive layer 212 is formed on the side of the first current blocking layer portion 1 away from the epitaxial structure 200. It should be noted that the first current blocking layer portion 1 located on the side of the P-type layer 206 away from the substrate 100 and the transparent conductive layer 212 formed on the side of the first current blocking layer portion 1 away from the epitaxial structure 200 constitute the first portion 12 of the current control layer 208, and the second current blocking layer portion 2 located on the exposed portion of the N-type layer 202 away from the substrate 100 constitutes the second portion 14 of the current control layer 208.

[0070] The first current blocking layer portion 1 includes a first patterned region, which exposes the P-type layer 206 and its opposite portion. The transparent conductive layer 212 includes a second patterned region, which exposes the first patterned region.

[0071] Specifically, the first patterned region can be a hollow annular structure, with the hollow region exposing the P-type layer 206 and its opposite portion, i.e., the hollow region of the first patterned region exposing the P-type layer 206 below it. Furthermore, the second patterned region in the transparent conductive layer 212 exposes the first patterned region, meaning the first patterned region is exposed within the second patterned region, so that the exposed area of ​​the P-type layer 206 by the first patterning can also be exposed within the second patterned region. Based on this, the patterned region composed of the first and second patterned regions can be used to passivate the exposed area of ​​the P-type layer 206, thereby forming a high-resistance passivated region in the exposed area of ​​the P-type layer 206. This enhances the adhesion between the P-metal electrode 302 and the epitaxial structure 200 without forming a leakage path, improves the wire bonding capability of the P-metal electrode 302, and ensures the reliability of the LED chip.

[0072] In one embodiment of this application, passivation processing of the exposed portion of the P-type layer 206 in the patterned area includes:

[0073] like Figure 5 As shown, after forming the transparent conductive layer 212, the portion of the P-type layer 206 exposed by the first patterned region is passivated using a preset plasma to form a high-resistivity passivation region 16.

[0074] The preset plasma includes at least one plasma that passivates the portion of the P-type layer 206 exposed by the first patterned region.

[0075] Specifically, hydrogen plasma is used to passivate the portion of the P-type layer 206 exposed by the first patterned region, causing the Mg acceptors in the P-type GaN layer to passivate into a neutral Mg-H complex, forming a high-resistivity passivation region 16. This cuts off the leakage current channel of the epitaxial structure 200 corresponding to the exposed region of the P-type layer 206. This prevents damage to the epitaxial structure 200 due to the exposed P-type layer during subsequent ion source pretreatment, thus avoiding the formation of a complete leakage current channel and ensuring that the electrical yield of the LED chip does not significantly decrease after ion source pretreatment. Based on this, when fabricating a standard LED chip using this method, ion source pretreatment can be used to treat the surface of the epitaxial structure 200, improving the adhesion between the metal electrode and the epitaxial structure 200. This allows for a reduction in the thickness of the metal bonding layer 306 in the metal electrode, thereby improving the reflectivity of the metal electrode.

[0076] In one embodiment of this application, the passivation region 16 extends into the interior of the P-type layer 206 along the side of the P-type layer 206 away from the substrate 100. The passivation region 16 is located inside the P-type layer 206, or the passivation region 16 penetrates the P-type layer 206. That is, the passivation region 16 may penetrate the P-type layer 206 or not, meaning that the extension depth of the passivation region 16 in the P-type layer 206 is not limited, thereby reducing the difficulty of the passivation process. It should be noted that the non-exposed portion of the P-type layer 206 is not passivated, that is, the non-exposed portion is a non-high-resistance region. The metal electrode can pass through the transparent conductive layer 212 and the non-high-resistance region in the P-type layer 206, thus not affecting the current transmission of the P-type layer 206, and consequently not affecting the voltage performance of the LED chip.

[0077] In one embodiment of this application, the metal electrode includes a P-metal electrode 302 and an N-metal electrode 304. Disposing the metal electrode on the side of the pre-treated current control layer 208 away from the epitaxial structure 200 includes:

[0078] like Figure 6 As shown, a P-metal electrode 302 is formed on the side of the first part 12 away from the epitaxial structure 200, and the P-metal electrode 302 is connected to the high-resistivity passivation region 16 in the P-type layer 206 through the patterned region; an N-metal electrode 304 is formed on the side of the second part 14 away from the epitaxial structure 200.

[0079] Among them, such as Figure 8 As shown, Figure 8 This is a schematic diagram of the structure of the metal electrodes of an LED chip provided in this application. Along the direction away from the epitaxial structure 200, the P metal electrode 302 and N metal electrode 304 sequentially include an adhesive layer 306, a reflective layer 308, a barrier layer 310, and a bonding layer 312. The thickness of the adhesive layer 306 is not greater than a preset value. Alternatively, as... Figure 9 As shown, Figure 9 This is a schematic diagram of the structure of the metal electrode of another LED chip provided in this application. Along the direction away from the epitaxial structure 200, the P metal electrode 302 and the N metal electrode 304 sequentially include a reflective layer 308, a barrier layer 310, and a bonding layer 312. That is to say, since the wafer source can be treated by an ion source pretreatment process to enhance the adhesion between the metal electrode and the wafer source, the thickness of the adhesive layer 306 (i.e., the aforementioned metal adhesive layer 306) can be reduced, or even eliminated, to improve the reflectivity of the metal electrode.

[0080] In one embodiment of this application, the aforementioned preset value can be 15 Å, meaning that if the thickness of the adhesive layer 306 is reduced, the thickness of the adhesive layer 306 can be equal to or less than 15 Å. However, this application does not limit the thickness of the adhesive layer 306; it depends on the specific circumstances.

[0081] To gain a clearer understanding of the preparation method provided in this application, a detailed description of specific embodiments of the preparation method is provided below.

[0082] Specifically, 1) a substrate 100 is provided, and an epitaxial structure is grown on the substrate 100 to obtain an epitaxial wafer. The growth of the epitaxial structure includes the sequential growth of an N-type GaN layer, a multiple quantum well layer 204 (MQW), and a P-type GaN layer. The MQW layer is the core light-emitting layer, also known as the active layer.

[0083] 2) The epitaxial wafer is cleaned, coated with photoresist, exposed, and developed to prepare the MESA photolithography pattern. Specifically, part of the epitaxial structure is removed by ICP dry etching (inductively coupled plasma dry etching), and the MESA pattern is formed after removing the photoresist. The purpose of this step is to etch away the P-type GaN layer and MQW layer in a local area to expose the N-type GaN step, so that the N metal electrode 304 can be fabricated on the exposed N-type GaN surface later.

[0084] 3) A dielectric thin film is deposited on the surface of the epitaxial wafer using plasma-enhanced chemical vapor deposition (PECVD) to form the current blocking layer 210. Generally, SiO2, Si3N4, or Al2O3 films can be used as the current blocking layer 210, and its thickness can range from 1000 Å to 8000 Å.

[0085] 4) The photoresist pattern for the current blocking layer 210 is prepared using a positive photoresist photolithography process. Then, the first patterned region is formed by etching with a BOE solution (Buffered Oxide Etchant). The photoresist is then removed with a resist remover to form the current blocking layer 210. This current blocking layer 210 primarily functions to block current, allowing current to be injected downwards from the outer edge of the electrodes into the underlying quantum well layer 204. This reduces the amount of light emitted from the epitaxial structure being blocked or absorbed by the metal electrodes, thereby improving the chip's luminous efficiency. The etching mask for the current blocking layer 210 is shown below. Figure 10 As shown, according to Figure 10As can be seen, the etching mask design for the patterned area of ​​the first part 12 corresponding to the current blocking layer 210 has a hollow annular structure. The hollow area of ​​this annular structure lacks the structural layer of the current blocking layer 210, exposing the P-type layer 206 and its corresponding portion. This allows the P-metal electrode 302 to directly contact the exposed area of ​​the P-type layer 206, which helps improve the adhesion between the P-metal electrode 302 and the epitaxial structure 200, thereby achieving the required wire bonding and push-out effects. Figure 10 In the above hollow ring structure, D represents the outer diameter of the hollow region.

[0086] 5) A transparent conductive film, typically an ITO film, is deposited by sputtering. The thickness of the film can range from 300 Å to 3500 Å.

[0087] 6) The above-mentioned transparent conductive film is annealed in a rapid annealing furnace to form ohmic contacts and improve the transmittance of the film. The annealing temperature range can be 400℃~700℃, and the annealing time can be 1min~30min.

[0088] 7) Using positive photoresist as a mask, a photoresist pattern for forming the transparent conductive layer 212 is created through photolithography, as shown in the image. Figure 11 As shown. Based on the above mask, a wet etching process is used to etch the transparent conductive film to form the pattern of the transparent conductive layer 212. Afterwards, the photoresist is removed, and the transparent conductive layer 212 is formed on the side of the current blocking layer 210 away from the epitaxial structure 200. According to... Figure 11 It can be seen that the pattern of the second patterned region in the transparent conductive layer 212 can be a pattern with a hollow circle in the middle, which exposes the first patterned region.

[0089] 8) Using positive photoresist as a mask, a photoresist pattern passivated by hydrogen plasma is formed after photolithography and development, which can be denoted as HPlasma. For example... Figure 12 As shown, the HPlasma mask can have a hollow circular hole corresponding to the exposed area of ​​the P-type layer 206. The diameter of this hollow circular hole is larger than the outer diameter of the hollow ring formed by the first patterned area of ​​the current blocking layer 210. This ensures that the first patterned area in the current blocking layer 210 can be exposed in the HPlasma mask, allowing the exposed area of ​​the P-type layer 206 to be passivated and pretreated by the ion source. Alternatively, the HPlasma mask can also be designed as a hollow ring structure, such as... Figure 13 As shown, it is necessary to ensure that the hollow ring of the HPlasma mask completely covers the hollow ring of the first patterned area of ​​the current blocking layer 210.

[0090] 9) Under the protection of the aforementioned HPlasma photoresist pattern, hydrogen plasma treatment is performed to passivate the exposed areas of the P-type GaN. The passivation depth can be controlled by the hydrogen plasma treatment time or power. After the hydrogen plasma treatment, the photoresist is removed, that is, after forming a high-resistivity passivation region 16 on the side of the exposed area of ​​the P-type layer 206 away from the substrate 100, the photoresist is removed. The RF power range of the hydrogen plasma treatment can be 3W~100W, the ICP power range can be 100W~800W, the cavity pressure range can be 1mTorr~50mTorr, and the treatment time range can be 3min~90min. In this case, the extension depth of the passivation region 16 is usually less than the thickness of the P-type layer 206. Under other process parameters, the passivation region 16 can also penetrate the P-type layer 206. This application does not limit this; it depends on the specific circumstances.

[0091] 10) The photoresist mask pattern for the metal electrodes is formed using a photolithography process with negative photoresist. See [link to photoresist pattern]. Figure 14 However, it should be noted that the above photomask is a negative adhesive photomask. Figure 14 The opaque areas are used for depositing metal electrodes, namely P-metal electrode 302 and N-metal electrode 304. Ion source pretreatment is performed first in a vapor deposition machine equipped with an ion source pretreatment device. Argon is commonly used as the ion source gas, with a flow rate ranging from 3 sccm to 50 sccm. The ion source anode voltage range is 50V to 300V, the anode current is 0.5A to 10A, the cathode current range is 0.3A to 5A, the chamber pressure range is 0.1 mTorr to 10 mTorr, and the pretreatment time range is 3 min to 120 min.

[0092] 11) The epitaxial structure 200, after undergoing ion source pretreatment, can be directly subjected to subsequent electrode metal evaporation processes without opening cavities or breaking the gas. The metal adhesion layer of conventional electrodes can be metals such as Cr, Ti, or Ni, with a thickness typically ranging from 20 Å to 200 Å. However, the metal adhesion layer thickness in this application can be equal to or less than 15 Å, or even completely eliminated, allowing direct evaporation of a metal electrode with Al as the reflective layer 308. The total thickness of the evaporated metal electrode can range from 1 μm to 5 μm, and after metal stripping and photoresist removal processes, the final metal electrode is formed.

[0093] 12) After the metal electrode is fabricated, a SiO2 insulating layer is coated on the surface of the epitaxial structure 200 and the metal electrode using a PECVD (Plasma-Enhanced Chemical Vapor Deposition) device as a passivation layer (PV) for the LED chip. The thickness can range from 500 Å to 8000 Å, including the endpoint values.

[0094] 13) Then, positive photoresist is used as a mask, and BOE solution is used to wet etch the above SiO2 insulating layer to form a PV pattern, with part of the metal electrode surface exposed for connection with external circuits.

[0095] 14) Subsequently, COW (Chip-on-Wafer, or CoW for short) electrical sampling tests were performed on the wafers with the above structure.

[0096] 15) Then, the wafer is thinned to a certain thickness, such as 60μm~300μm, by grinding and polishing, and a DBR (Distributed Bragg Reflector, abbreviated as DBR) film is deposited on the back of the substrate 100 to enhance the reflection intensity of visible light on the back of the chip. The thickness of the DBR film can range from 1μm to 6μm.

[0097] 16) Cut the above wafers to obtain wafers with dispersed cores.

[0098] 17) The above wafers are tested and sorted to obtain LED chips that can be shipped to customers.

[0099] It should be noted that before the electrode metal evaporation, the surface of the epitaxial structure 200 is pretreated with an ion source. This effectively removes organic contaminants and oxide layers from the surface of the epitaxial structure 200, strengthening the adhesion between the subsequent electrode metal layer and the surface of the epitaxial structure 200, as well as the adhesion between the electrode metal layer and the current control layer 208. This ensures that even if the adhesion layer in the metal electrode is very thin or even eliminated, the adhesion between the metal electrode and the epitaxial structure 200 is sufficient, allowing the metal electrode to pass wire bonding verification without falling off. Specifically, in the ion source pretreatment method of this application, a Hall ion source can be used, and the gas generating the ion source can be Ar, Ne, etc. After ion source treatment, the adhesion between the metal electrode adhesion layer and the wafer source is improved, allowing the metal electrode adhesion layer to be thinned or even completely eliminated. This increases the reflectivity of the metal electrode, improving the overall brightness of the LED chip. Simultaneously, it helps the metal electrode form better ohmic contact with the epitaxial structure 200 and the transparent conductive layer 212, thus reducing the LED chip voltage.

[0100] Based on the fabrication method described in any of the above embodiments, this application also provides an LED chip, which is an LED chip fabricated based on the fabrication method described in any of the above embodiments. As shown in the figure, the LED chip includes a substrate 100, an epitaxial structure 200, a current control layer 208, and a metal electrode located on one side of the substrate 100.

[0101] The aforementioned epitaxial structure 200 includes an N-type layer 202, a quantum well layer 204, and a P-type layer 206 sequentially stacked along a direction away from the substrate 100. The quantum well layer 204 and the P-type layer 206 expose portions of the N-type layer 202.

[0102] The current control layer 208 located on the side of the epitaxial structure away from the substrate includes a first portion 12, which is located on the side of the P-type layer 206 away from the substrate 100.

[0103] The first part 12 includes a patterned region that exposes the P-type layer 206 and its corresponding portion. The portion of the P-type layer 206 exposed by the patterned region includes a high-resistivity passivation region 16. Specifically, the passivation region 16 extends from the side of the exposed portion of the P-type layer 206 away from the substrate into the interior of the P-type layer.

[0104] The metal electrode is located on the side of the current control layer 208 away from the epitaxial structure 200. Among them, the metal electrode (P metal electrode) located on the side of the first part 12 away from the epitaxial structure 200 is connected to the high-resistivity passivation region 16 in the P-type layer 206 through the patterned region.

[0105] As described above, in this LED chip, the exposed area of ​​the P-type layer 206 away from the substrate 100 includes a high-resistivity passivation region 16, which is used to connect with the metal electrode. In other words, during the fabrication of this LED chip, after forming the current control layer 208 and before ion source pretreatment, the exposed portion of the P-type layer 206 can be passivated, thereby forming a high-resistivity passivation region 16 on the exposed portion of the P-type layer 206 away from the substrate 100. This cuts off the leakage current path in the epitaxial structure 200 corresponding to the exposed area of ​​the P-type layer 206 during ion source pretreatment, fundamentally preventing leakage current paths from occurring in the epitaxial structure 200 corresponding to the exposed area of ​​the P-type layer 206 due to damage during ion source pretreatment. Therefore, it can be seen that during the fabrication of this LED chip, ion source pretreatment can enhance the adhesion between the epitaxial structure 200 and the current control layer 208 and the metal electrode. However, the ion source pretreatment will not cause leakage channels in the epitaxial structure, thereby thinning or even removing the bonding metal layer in the metal electrode, improving the reflectivity of the metal electrode, and thus increasing the brightness of the LED chip. At the same time, ion source pretreatment also helps the metal electrode to form a better ohmic contact with the epitaxial structure 200, and with the current control layer 208 (specifically, the transparent conductive layer 212 described later), thereby reducing the LED chip voltage.

[0106] In one embodiment of this application, such as Figure 6 As shown, the current control layer 208 further includes a second portion 14, which is located on the side of the exposed portion of the N-type layer 202 away from the substrate 100. The subsequent N-electrode 304 is located on the side of this second portion 14 away from the epitaxial structure 200. Specifically, as... Figure 6 As shown, the aforementioned metal electrodes include a P-metal electrode 302 and an N-metal electrode 304. The P-metal electrode 302 is located on the side of the first portion 12 of the current control layer 208 away from the epitaxial structure 200, and the high-resistivity passivation region 16 of the P-type layer 206 exposed by the patterned region of the first portion 12 is connected to the P-metal electrode 302. The N-metal electrode 304 is located on the side of the second portion 14 of the current control layer 208 away from the epitaxial structure 200, and is connected to the exposed portion of the N-type layer 202. That is, the N-metal electrode 304 is located on the side of the N-type layer 202 exposed by the quantum well layer 204 and the P-type layer 206 away from the substrate 100, and is connected to the exposed portion of the N-type layer 202.

[0107] In one embodiment of this application, the current control layer 208 includes a current blocking layer 210 and a transparent conductive layer 212. The current blocking layer 210 is located on the side of the epitaxial structure 200 away from the substrate 100, and the current blocking layer 210 includes a first current blocking layer portion 1 located on the side of the P-type layer 206 away from the substrate 100, and a second current blocking layer portion 2 located on the side of the exposed portion of the N-type layer 202 away from the substrate 100.

[0108] The transparent conductive layer 212 is located on the side of the first current blocking layer portion 1 away from the epitaxial structure 200. The first current blocking layer portion 1 includes a first patterned region, which exposes the portion of the P-type layer 206 opposite to it. The transparent conductive layer 212 includes a second patterned region, which exposes the first patterned region. It should be noted that the first current blocking layer portion 1 located on the side of the P-type layer 206 away from the substrate 100 and the transparent conductive layer 212 located on the side of the first current blocking layer portion 1 away from the epitaxial structure 200 constitute the first portion 12 of the current control layer 208, and the second current blocking layer portion 2 located on the side of the exposed portion of the N-type layer 202 away from the substrate 100 constitutes the second portion 14 of the current control layer 208.

[0109] Specifically, the first patterned region can be a hollow annular structure, with the hollow area exposing the P-type layer 206 and its opposite portion, meaning the hollow area of ​​the first patterned region exposes the P-type layer 206 below it. Furthermore, the second patterned region in the transparent conductive layer 212 exposes the first patterned region, meaning the first patterned region is exposed within the second patterned region, so that the exposed area of ​​the P-type layer 206 by the first patterning can also be exposed within the second patterned region. Based on this, the metal electrode located above the first patterned region can connect to the P-type layer 206 through both the first and second patterned regions. Specifically, the P-type metal electrode 302 can connect to the P-type layer 206 through both the first and second patterned regions, thereby enhancing the adhesion between the P-type metal electrode 302 and the epitaxial structure 200, improving the wire bonding capability of the P-type metal electrode 302, and ensuring the reliability of the LED chip.

[0110] In one embodiment of this application, the passivation region 16 extends into the interior of the P-type layer 206 along the side of the P-type layer 206 away from the substrate 100. The passivation region 16 is located inside the P-type layer 206, or the passivation region 16 penetrates the P-type layer 206. That is, the passivation region 16 may penetrate the P-type layer 206 or not, meaning that the extension depth of the passivation region 16 in the P-type layer 206 is not limited, thereby reducing the difficulty of the passivation process. It should be noted that the non-exposed portion of the P-type layer 206 is not passivated, that is, the non-exposed portion is a non-high-resistance region. The metal electrode can pass through the transparent conductive layer 212 and the non-high-resistance region in the P-type layer 206, thus not affecting the current transmission of the P-type layer 206, and consequently not affecting the voltage performance of the LED chip.

[0111] In one embodiment of this application, such as Figure 6 As shown, the metal electrodes include a P-metal electrode 302 and an N-metal electrode 304. The P-metal electrode 302 is located on the side of the first portion 12 away from the epitaxial structure 200, and is connected to the high-resistivity passivation region 16 in the P-type layer 206 through a patterned region. The N-metal electrode 304 is located on the side of the second portion 14 away from the epitaxial structure 200. Along the direction away from the epitaxial structure 200, the P-metal electrode 302 and the N-metal electrode 304 sequentially include an adhesive layer 306, a reflective layer 308, a barrier layer 310, and a bonding layer 312. The thickness of the adhesive layer 306 is not greater than a preset value. Alternatively, along the direction away from the epitaxial structure 200, the P-metal electrode 302 and the N-metal electrode 304 sequentially include a reflective layer 308, a barrier layer 310, and a bonding layer 312. In other words, since the wafer source composed of epitaxial structure 200 and current control layer 208 can be processed by ion source pretreatment process, the adhesion between metal electrode and epitaxial structure 200 and the adhesion between current control layer 208 and metal electrode can be enhanced, thereby reducing the thickness of adhesive layer (i.e., the aforementioned metal adhesive layer 306) in metal electrode, or even eliminating the adhesive layer, to improve the reflectivity of metal electrode.

[0112] In one embodiment of this application, the aforementioned preset value can be 15 Å, meaning that if the thickness of the adhesive layer 306 is reduced, the thickness of the adhesive layer 306 can be equal to or less than 15 Å. However, this application does not limit the thickness of the adhesive layer 306; it depends on the specific circumstances.

[0113] In summary, this application provides a method for fabricating an LED chip and an LED chip. Before ion source pretreatment, the exposed area of ​​the P-type layer, which is exposed by the patterned region of the first portion, is passivated. This forms a high-resistivity passivation region on the side of the exposed P-type layer away from the substrate, and this passivation region is used to connect to a metal electrode. Based on this, the leakage path in the epitaxial structure corresponding to the exposed P-type layer during ion source pretreatment is cut off, thus fundamentally eliminating the possibility of leakage paths in the epitaxial structure corresponding to the exposed P-type layer due to damage during ion source pretreatment. Therefore, this fabrication method employs ion source pretreatment to pretreat the wafer source composed of the epitaxial structure and the current control layer. This enhances the adhesion between the wafer source and the metal bonding layer of the metal electrode. Furthermore, the portion of the epitaxial structure corresponding to the exposed P-type layer will not generate leakage channels due to ion source pretreatment. This pretreatment can also thin or even remove the bonding metal layer in the metal electrode, thereby improving the reflectivity of the metal electrode and thus enhancing the brightness of the LED chip. Simultaneously, ion source pretreatment also helps to form better ohmic contact between the metal electrode and the wafer source surface, achieving the goal of reducing the LED chip voltage.

[0114] The various embodiments in this specification are described in a progressive, parallel, or combined manner. Each embodiment focuses on its differences from other embodiments, and similar or identical parts between embodiments can be referred to interchangeably. For the apparatuses disclosed in the embodiments, since they correspond to the methods disclosed in the embodiments, the descriptions are relatively simple, and relevant parts can be referred to the method section.

[0115] It should be noted that, in the description of this application, the terms "upper," "lower," "top," "bottom," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application. When a component is considered to be "connected" to another component, it can be directly connected to the other component or there may be a component centrally located at the same time.

[0116] It should also be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that an article or apparatus comprising a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such an article or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the article or apparatus that includes the aforementioned element.

[0117] The above description of the disclosed embodiments enables those skilled in the art to make or use this application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of this application. Therefore, this application is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A method for fabricating an LED chip, characterized in that, include: Provide a substrate; An epitaxial structure is formed on one side of the substrate. The formation of the epitaxial structure includes an N-type layer, a quantum well layer, and a P-type layer arranged in sequence along a direction away from the substrate, wherein the quantum well layer and the P-type layer expose portions of the N-type layer. A current control layer is formed on the side of the epitaxial structure away from the substrate. Forming the current control layer includes forming a first portion located on the side of the P-type layer away from the substrate. The first portion includes a patterned region that exposes the P-type layer and its corresponding portion. The portion of the P-type layer exposed by the patterned region is passivated to form a high-resistivity passivation region; After passivating the portion of the P-type layer exposed by the patterned region, the current control layer and the epitaxial structure are pre-treated, and the metal electrode is placed on the side of the pre-treated current control layer away from the epitaxial structure to enhance the adhesion between the current control layer, the epitaxial structure and the metal electrode. The metal electrode located on the side of the first portion away from the epitaxial structure is connected to the high-resistivity passivation region in the P-type layer through the patterned region.

2. The method for preparing an LED chip according to claim 1, characterized in that, Forming the current control layer also includes forming a second portion located on the side of the exposed portion of the N-type layer away from the substrate.

3. The method for preparing an LED chip according to claim 2, characterized in that, The current control layer includes: A current blocking layer is formed on the side of the epitaxial structure away from the substrate. The current blocking layer includes a first current blocking layer portion located on the side of the P-type layer away from the substrate, and a second current blocking layer portion located on the exposed portion of the N-type layer away from the substrate. A transparent conductive layer is formed on the side of the first current blocking layer away from the epitaxial structure; The first current blocking layer includes a first patterned region, which exposes the P-type layer and its corresponding portion; the transparent conductive layer includes a second patterned region, which exposes the first patterned region.

4. The method for preparing an LED chip according to claim 3, characterized in that, The passivation process for the portion of the P-type layer exposed by the patterned region includes: After the transparent conductive layer is formed, the portion of the P-type layer exposed by the first patterned region is passivated using a preset plasma to form the high-resistivity passivation region. The preset plasma includes at least one plasma used to passivate the portion of the P-type layer exposed by the first patterned region.

5. The method for preparing an LED chip according to claim 1 or 4, characterized in that, The passivation region extends into the P-type layer along the side of the P-type layer away from the substrate, and the passivation region is located inside the P-type layer, or the passivation region penetrates the P-type layer.

6. The method for preparing an LED chip according to claim 1, characterized in that, The metal electrode includes a P-metal electrode and an N-metal electrode, and the step of placing the metal electrode on the side of the pretreated current control layer away from the epitaxial structure includes: The P-metal electrode is formed on the side of the first portion away from the epitaxial structure, and the P-metal electrode is connected to the high-resistivity passivation region in the P-type layer through the patterned region; The N-metal electrode is formed on the side of the second portion away from the epitaxial structure; Wherein, along the direction away from the epitaxial structure, the P metal electrode and the N metal electrode sequentially include an adhesive layer, a reflective layer, a barrier layer and a bonding layer, and the thickness of the adhesive layer is not greater than a preset value; or, along the direction away from the epitaxial structure, the P metal electrode and the N metal electrode sequentially include a reflective layer, a barrier layer and a bonding layer.

7. An LED chip, characterized in that, The LED chip is an LED chip prepared by the method of any one of claims 1-6, comprising: Substrate; An epitaxial structure located on one side of the substrate, the epitaxial structure comprising an N-type layer, a quantum well layer and a P-type layer sequentially stacked along a direction away from the substrate, wherein the quantum well layer and the P-type layer expose portions of the N-type layer; A current control layer located on the side of the epitaxial structure away from the substrate, the current control layer including a first portion located on the side of the P-type layer away from the substrate; The first part includes a patterned region that exposes the P-type layer and its corresponding portion, and the portion of the P-type layer exposed by the patterned region includes a high-resistivity passivation region. A metal electrode located on the side of the current control layer away from the epitaxial structure, wherein the metal electrode located on the first portion away from the epitaxial structure is connected to the high-resistivity passivation region in the P-type layer through the patterned region.

8. The LED chip according to claim 7, characterized in that, The current control layer further includes a second portion located on the side of the exposed portion of the N-type layer away from the substrate.

9. The LED chip according to claim 8, characterized in that, The current control layer includes a current blocking layer and a transparent conductive layer; The current blocking layer is located on the side of the epitaxial structure away from the substrate. The current blocking layer includes a first current blocking layer portion located on the side of the P-type layer away from the substrate, and a second current blocking layer portion located on the exposed portion of the N-type layer away from the substrate. The transparent conductive layer is located on the side of the first current blocking layer that is away from the epitaxial structure. The first current blocking layer includes a first patterned region, which exposes the P-type layer and its corresponding portion; the transparent conductive layer includes a second patterned region, which exposes the first patterned region.

10. The LED chip according to claim 7, characterized in that, The passivation region extends into the P-type layer along the side of the P-type layer away from the substrate, and the passivation region is located inside the P-type layer, or the passivation region penetrates the P-type layer.

11. The LED chip according to claim 7, characterized in that, The metal electrode includes a P-metal electrode and an N-metal electrode; the P-metal electrode is located on the side of the first portion away from the substrate, and the P-metal electrode is connected to the high-resistivity passivation region in the P-type layer through the patterned region; the N-metal electrode is located on the side of the second portion away from the substrate. Wherein, along the direction away from the epitaxial structure, the P metal electrode and the N metal electrode sequentially include an adhesive layer, a reflective layer, a barrier layer and a bonding layer, and the thickness of the adhesive layer is not greater than a preset value; or, along the direction away from the epitaxial structure, the P metal electrode and the N metal electrode sequentially include a reflective layer, a barrier layer and a bonding layer.

12. The LED chip according to claim 11, characterized in that, The preset value is 15 angstroms.

Images