Visible light communication LED chip, visible light communication method and detection structure

Abstract

A visible light communication LED chip, a visible light communication method and a detection structure. The visible light communication LED chip comprises a substrate and an epitaxial stack located on one side surface of the substrate; the epitaxial stack comprises an N-type semiconductor layer, an active layer and a P-type semiconductor layer which are sequentially stacked; the active layer comprises a high-energy level light-emitting layer and a low-energy level trap layer, and the low-energy level trap layer is located on at least one side of the high-energy level light-emitting layer facing the substrate or away from the substrate; the active layer radiates first light at the high-energy level light-emitting layer under a first current density; under a second current density, carriers are captured by traps of the low-energy level trap layer, and the high-energy level light-emitting layer does not emit light to maintain the carrier concentration of the active layer; the first current density is greater than the second current density. The visible light communication LED chip constructs a composite structure of the high-energy level light-emitting layer and the low-energy level trap layer, can reduce the visible light communication switching delay, and lays a foundation for high-speed modulation of visible light communication.

Description

Technical Field

[0001] This invention relates to the field of light-emitting diode technology, and more specifically, to a visible light communication LED chip, a visible light communication method, and a detection structure. Background Technology

[0002] Visible light communication uses LED chips (light-emitting diodes) as the core radiating device, and its modulation bandwidth directly determines the communication rate. GaN-based LED chips have become the mainstream choice for visible light communication due to their wide bandgap, high luminous efficiency, and high stability. Traditional monochromatic visible light communication LED chips adopt single-quantum-well or multi-quantum-well epitaxial structures, using sapphire or SiC as substrates. The epitaxial layers sequentially include a buffer layer, an N-type GaN layer, an active layer, and a P-type GaN layer. Signal modulation is achieved through on-off keying (OOK), where high current and strong light represent logic 1, and the no-light state (current drops to 0) represents logic 0. This is currently the mainstream device solution in the field of visible light communication.

[0003] However, traditional monochrome visible light communication LED modulation bandwidth is low, with a typical bandwidth of ≤50MHz. It has large switching delays, with rise time ≥10ns and fall time ≥8ns. Because representing logic 0 requires deep shutdown to completely empty the active layer carriers, and when re-conducting, carriers need to be accumulated from 0, resulting in severe rise delay. When turning off, a quenching current of kA / cm² level is required to forcibly remove the carriers, and carrier recombination hysteresis still exists. The fall delay problem cannot be fundamentally solved.

[0004] Existing high-speed LED bandwidth optimization solutions suffer from high power consumption and low device reliability. The reverse quenching current at the kA / cm² level significantly increases drive power consumption and is prone to causing electrical damage to the active layer, reducing device lifespan. Such solutions only optimize external circuits or local structures without changing the carrier dynamics characteristics of the LED active layer, resulting in limited bandwidth improvement. Summary of the Invention

[0005] In view of this, the present invention provides a visible light communication LED chip, a visible light communication method, and a detection structure, which can reduce the switching delay of visible light communication and lay the foundation for high-speed modulation of visible light communication.

[0006] To achieve the above objectives, the technical solution adopted by the present invention is as follows:

[0007] A visible light communication LED chip, comprising:

[0008] Substrate;

[0009] An epitaxial stack located on one side surface of the substrate; the epitaxial stack includes an N-type semiconductor layer, an active layer, and a P-type semiconductor layer stacked sequentially;

[0010] The active layer includes a high-energy light-emitting layer and a low-energy trapping layer stacked together, wherein the low-energy trapping layer is located on at least one side of the high-energy light-emitting layer facing the substrate and the side away from the substrate.

[0011] The active layer emits a first light at a first current density; at a second current density, charge carriers in the active layer are trapped by traps in the low-energy trapping layer, and the high-energy emitting layer does not emit light to maintain the carrier concentration in the active layer; the first current density is greater than the second current density.

[0012] By alternately adjusting the current density of the active layer, the active layer is alternately placed at a first current density and a second current density to achieve visible light communication signal switching.

[0013] Optionally, the high-energy emitting layer comprises a superlattice structure consisting of a first quantum well layer and a first barrier layer; the first quantum well layer comprises In x Ga (1-x) N, 0 < x < 1;

[0014] The low-energy trap layer comprises a superlattice structure consisting of a second quantum well layer and a second barrier layer; the second quantum well layer comprises In y Ga (1-y) N, 0 < y < 1, y > x;

[0015] The number of periods of the first quantum well layer and the first barrier layer of the high-energy luminescent layer is N, where N > 1 and N is an integer;

[0016] The total number of periods of the second quantum well layer and the second barrier layer of the low-level trap layer is M, where M≥1 and M is an integer, and M is less than N.

[0017] Optionally, the value of the In component x in the first quantum well layer is in the range of 0.15≤x≤0.25; at the first current density, the first light emitted by the high-energy-level light-emitting layer is green light or blue light;

[0018] The In component y in the second quantum well layer has a value range of y≥0.3.

[0019] Optionally, the first current density is in the range of 500 A / cm². 2 -1000 A / cm 2 This includes endpoint values.

[0020] The second current density ranges from 0.05 A / cm². 2 -0.2A / cm 2 This includes endpoint values.

[0021] Optionally, the low-energy trap layer is stacked on the side of the high-energy light-emitting layer facing the substrate;

[0022] The active layer also includes In z Ga (1-z) N transition layer, In z Ga (1-z) The N transition layer is located between the low-energy trap layer and the high-energy emitting layer; along the direction away from the low-energy trap layer, In z Ga (1-z) The In component z of the N transition layer gradually changes linearly from y to x.

[0023] Optionally, the low-energy trap layer is stacked on the side of the high-energy light-emitting layer opposite to the substrate;

[0024] The visible light communication LED chip also includes a P-type electron blocking layer located between the P-type semiconductor layer and the low-energy trap layer.

[0025] Optionally, the low-energy trap layer is provided on both the side of the high-energy light-emitting layer facing the substrate and the side facing away from the substrate;

[0026] The In component of the second quantum well layer, which is close to the low-level trap layer of the N-type semiconductor layer, is y1, where y1 > x;

[0027] The In component of the second quantum well layer of the low-level trap layer near the P-type semiconductor layer is y2, y2 > y1, y2 > x.

[0028] Optionally, when the low-energy trap layer is stacked on the side of the high-energy light-emitting layer facing the substrate, the total thickness of the second quantum well layer ranges from 10nm to 15nm, including the endpoint values.

[0029] When the low-level trap layer is stacked on the side of the high-level light-emitting layer away from the substrate, the thickness of the first barrier layer and the second barrier layer is less than or equal to 10 nm.

[0030] When the low-energy trap layer is provided on both the side of the high-energy light-emitting layer facing the substrate and the side away from the substrate, the thickness of the first barrier layer and the second barrier layer is less than or equal to 10 nm, and the thickness of a single second quantum well layer ranges from 1 nm to 2 nm, including the endpoint value.

[0031] The present invention also provides a visible light communication method, comprising:

[0032] Provide a visible light communication LED chip as described in any one of the above; alternately adjust the current density of the active layer so that the active layer alternately operates at a first current density and a second current density;

[0033] A detection structure is provided; the detection structure includes an optical input module, a filtering module, and a PD detection module;

[0034] The light input module receives the light emitted by the visible light communication LED chip and transmits it to the filtering module;

[0035] The filtering module receives the light transmitted from the optical input module and filters it so that only the first light ray can pass through the filtering module and enter the PD detection module;

[0036] When the PD detection module detects the first light ray, the communication signal representation logic is 1; when the PD detection module does not detect the first light ray, the communication signal representation logic is 0.

[0037] The present invention also provides a detection structure, which includes an optical input module, a filtering module and a PD detection module;

[0038] The light input module is used to receive light emitted by any of the visible light communication LED chips described above, and transmit the light to the filtering module;

[0039] The filtering module has an optical channel and a filter located within the optical channel; the light received by the optical input module is transmitted into the optical channel, and the filter only allows the first light rays to pass through the optical channel and enter the PD detection module;

[0040] The PD detection module is used to detect the first light beam.

[0041] Compared with existing technologies, the technical solution provided by this invention has at least the following advantages:

[0042] Based on the above configuration of the visible light communication LED chip, the active layer achieves visible light communication signal switching within a single chip by constructing a composite structure of a high-energy emitting layer and a low-energy trapping layer. At low current density (second current density), charge carriers are preferentially captured by the low-energy trapping layer, and the high-energy emitting layer does not emit light. The carrier trapping effect maintains the carrier concentration in the active layer, preventing complete carrier depletion. At high current density (first current density), the traps in the low-energy trapping layer are completely occupied by carriers, and excess carriers overflow to the high-energy emitting layer, radiating the first light. By alternately adjusting the current density of the active layer, visible light communication is achieved by alternating between the first and second current densities. The switching time of visible light communication LED chips is on the order of nanoseconds, so the time required for complete turn-off is very long for them. This visible light communication LED chip does not need to be completely turned off; it only needs to switch to a lower current density, eliminating the need to wait for the LED to turn off completely from a low current density, thus reducing the fall-off time. Simultaneously, relying on the carrier trapping effect, a certain carrier concentration is maintained in the active layer at low current densities. The carriers effectively retained by the low-energy trapping layer physically reduce the amount of carrier reconstruction. This visible light communication LED chip significantly shortens the switching delay, breaking through the modulation bandwidth bottleneck of traditional LEDs. It eliminates the need for kA / cm² level quenching current, reducing device power consumption and electrical damage risk, and improving reliability. Attached Figure Description

[0043] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.

[0044] Figure 1 This is a cross-sectional structural schematic diagram of an embodiment of the visible light communication LED chip of this application;

[0045] Figure 2 This is a cross-sectional structural schematic diagram of another embodiment of the visible light communication LED chip of this application;

[0046] Figure 3 This is a cross-sectional structural schematic diagram of another embodiment of the visible light communication LED chip of this application;

[0047] Figure 4 This is a cross-sectional structural schematic diagram of another embodiment of the visible light communication LED chip of this application;

[0048] Figure 5 This is a cross-sectional structural schematic diagram of another embodiment of the visible light communication LED chip of this application;

[0049] Figure 6 This is a cross-sectional structural diagram of another embodiment of the visible light communication LED chip of this application.

[0050] Figure 7 The flowcharts are for each module of the visible light communication method in this application.

[0051] Figure label:

[0052] Substrate 1; N-type semiconductor layer 2; active layer 4; high-energy light-emitting layer 4a; first quantum well layer a1; first barrier layer a2; low-energy trap layer 4b; second quantum well layer b1; second barrier layer b2; In z Ga (1-z) N-transition layer 4c; P-type semiconductor layer 3; buffer layer 10; P-type electron blocking layer 90. Detailed Implementation

[0053] To make the content of this invention clearer, the technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments in this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.

[0054] Many specific details are set forth in the following description in order to provide a full understanding of this application. However, this application may also be implemented in other ways different from those described herein. Those skilled in the art can make similar extensions without departing from the spirit of this application. Therefore, this application is not limited to the specific embodiments disclosed below.

[0055] Secondly, this application provides a detailed description in conjunction with schematic diagrams. When detailing the embodiments of this application, for ease of explanation, the cross-sectional views illustrating the device structure may be partially enlarged, not adhering to the usual scale. Furthermore, the schematic diagrams are merely examples and should not limit the scope of protection of this application. In actual fabrication, the three-dimensional spatial dimensions of length, width, and depth should be included. In this application, unless specifically stated otherwise, all numerical ranges include endpoint values.

[0056] To address the switching delay issue in visible light communication mentioned in the background art, this application provides a visible light communication LED chip.

[0057] refer to Figure 1-3 The visible light communication LED chip includes a substrate 1 and an epitaxial stack located on one side of the substrate 1. The epitaxial stack includes an N-type semiconductor layer 2, an active layer 4, and a P-type semiconductor layer 3 stacked sequentially.

[0058] The active layer 4 includes a high-energy emitting layer 4a and a low-energy trapping layer 4b stacked together. The low-energy trapping layer 4b is located on at least one side of the high-energy emitting layer 4a, facing the substrate 1 and away from the substrate 1. At a first current density, the high-energy emitting layer 4a radiates first light; at a second current density, charge carriers in the active layer 4 are trapped by the low-energy trapping layer 4b, and the high-energy emitting layer 4a does not emit light, thus maintaining the carrier concentration in the active layer 4; the first current density is greater than the second current density.

[0059] By alternately adjusting the current density of the active layer 4, the active layer 4 can be switched between the first current density and the second current density to achieve visible light communication signal switching.

[0060] Optionally, substrate 1 may include, but is not limited to, sapphire substrate 1, SiC substrate 1, etc. The thickness of substrate 1 is preferably in the range of 300 micrometers to 500 micrometers; for scenarios requiring high current injection, SiC substrate 1 with better thermal conductivity may be selected.

[0061] Optionally, the N-type semiconductor layer 2 includes, but is not limited to, an N-type GaN layer, and the P-type semiconductor layer 3 includes, but is not limited to, a P-type GaN layer. The specific materials can be adjusted according to actual light extraction requirements. The N-type semiconductor layer 2 uses Si as the doping source, and the doping concentration ranges from 1 × 10⁻⁶. 18 cm -3 ~1×10 20 cm -3 The thickness ranges from 2 micrometers to 5 micrometers. The P-type semiconductor layer 3 uses Mg as the doping source, with a doping concentration ranging from 1 × 10⁻⁶. 19 cm -3 ~1×10 21 cm -3 The thickness ranges from 0.1 micrometers to 0.5 micrometers. As a hole injection channel, it works with the N-type semiconductor layer 2 to provide carriers (electrons and holes) for the active layer 4. Its doping concentration and thickness match the N-type semiconductor layer 2 to ensure the balance and uniformity of carrier injection, and to ensure the stability of communication signal switching and the high speed of current switching.

[0062] Furthermore, the visible light communication LED chip also includes an N-electrode (not shown in the figure) and a P-electrode (not shown in the figure). The N-electrode is electrically connected to the N-type semiconductor layer, and the P-electrode is electrically connected to the P-type semiconductor layer. The specific positions of the N-electrode and P-electrode can be set according to whether the chip has a conventional, flip-chip, vertical, or horizontal structure.

[0063] Based on the above configuration of the visible light communication LED chip, the active layer 4, by constructing a composite structure of a high-energy emitting layer 4a and a low-energy trapping layer 4b, achieves the switching of visible light communication signals within a single chip by adjusting the current density. At a low current density (second current density), charge carriers are preferentially captured by the low-energy trapping layer 4b, and the high-energy emitting layer 4a does not emit light. The carrier trapping effect maintains the carrier concentration in the active layer, preventing complete carrier depletion. At a high current density (first current density), the traps in the low-energy trapping layer 4b are completely occupied by carriers, and excess carriers overflow to the high-energy emitting layer 4a, radiating the first light. By alternately adjusting the current density of the active layer 4, the active layer 4 is alternately positioned at the first and second current densities, thus achieving the switching of visible light communication signals. The switching time of visible light communication LED chips is on the order of nanoseconds, so the time required for complete turn-off is very long for them. This visible light communication LED chip does not need to be completely turned off; it only needs to switch to a lower current density, eliminating the need to wait for the LED to turn off completely from a low current density, thus reducing the fall-off time. Simultaneously, relying on the carrier trapping effect, a certain carrier concentration is maintained in the active layer 4 at low current densities. The carriers effectively retained by the low-energy trapping layer 4b physically reduce the amount of carrier reconstruction. This visible light communication LED chip significantly shortens the switching delay, breaking through the modulation bandwidth bottleneck of traditional LEDs. It eliminates the need for kA / cm² level quenching current, reducing device power consumption and electrical damage risk, and improving reliability.

[0064] In an optional embodiment, the high-energy emitting layer 4a comprises a superlattice structure consisting of a first quantum well layer a1 and a first barrier layer a2; the first quantum well layer a1 comprises In x Ga (1-x) N, 0 < x < 1. One period consists of a first quantum well layer a1 and a first barrier layer a2.

[0065] The low-level trap layer 4b comprises a superlattice structure consisting of a second quantum well layer b1 and a second barrier layer b2; the second quantum well layer b1 comprises In y Ga (1-y) N, 0 < y < 1, y > x. One period consists of a second quantum well layer b1 and a second barrier layer b2.

[0066] The number of periods of the first quantum well layer a1 and the first barrier layer a2 of the high-energy emitting layer 4a is N, where N > 1 and N is an integer; the total number of periods of the second quantum well layer b1 and the second barrier layer b2 of the low-energy trap layer 4b is M, where M ≥ 1 and M is an integer, and M is less than N. The total number of periods of the low-energy trap layer 4b refers to the sum of the period numbers of all low-energy trap layers 4b in the active layer 4. When low-energy trap layers 4b are disposed on both sides of the high-energy emitting layer 4a facing the substrate 1 and away from the substrate 1, the total number of periods of the low-energy trap layers 4b is the sum of the period numbers of the low-energy trap layers 4b on both sides. When the low-energy trap layer 4b is disposed only on one side of the high-energy emitting layer 4a facing the substrate 1 and away from the substrate 1, the number of periods of the low-energy trap layer 4b is the total number of periods of the low-energy trap layer 4b.

[0067] Optionally, the first barrier layer includes, but is not limited to, a GaN barrier layer. The second barrier layer b2 includes, but is not limited to, a GaN barrier layer.

[0068] Preferably, the In component x in the first quantum well layer a1 has a value range of 0.15≤x≤0.25; at the first current density, the first light emitted by the high-energy-level light-emitting layer 4a is green light or blue light.

[0069] More preferably, the In component y in the second quantum well layer b1 has a value range of y≥0.3.

[0070] Both the high-energy emitting layer 4a and the low-energy trapping layer 4b adopt a superlattice structure composed of a quantum well layer and a barrier layer. The high-energy emitting layer 4a and the low-energy trapping layer 4b are formed by controlling the In composition of the first quantum well layer a1 and the second quantum well layer b1, respectively. The fabrication method is simple.

[0071] In this design, at low current densities, charge carriers in the active layer 4 are trapped by low-energy traps, radiating weak long-wave electromagnetic waves, far exceeding the blue / green communication band. At high current densities, the traps are completely occupied, and excess charge carriers overflow to the high-energy emitting layer 4a, radiating 450-550nm blue / green light. The low-energy trap layer 4b is not designed primarily for luminescence, but rather as a "carrier storage pool"—its weak long-wave electromagnetic wave emission at low current densities serves only as a signal indicating that the low-energy trap layer 4b is filled. At high current densities, the low-energy trap layer 4b actively quenches long-wave emission due to local state saturation and Auger recombination suppression, resulting in pure blue / green light output by the device. That is, under high current density, the local states in the low-level trap layer 4b lose their ability to continue to bind carriers due to the saturation of carrier filling; at the same time, the Auger nonradiative recombination rate in the saturated low-level trap layer 4b increases sharply (its increase is an order of magnitude higher than the radiative recombination rate), so the long-wave emission of the low-level trap layer 4b is effectively quenched, and its intensity is negligible compared to the blue / green light of the high-level emitting layer 4a, and the device spectrum shows pure blue / green light.

[0072] In this invention, the total number of cycles M of the low-level trap layer 4b is less than the number of cycles N of the high-level emitting layer 4a, and the ratio M / N is always less than 1. Due to the strong localization effect of the deep energy level formed by the high In composition, the low-level trap layer 4b requires only a few cycles to provide sufficient low-level trap capacity at low current densities, stably maintaining the carrier concentration of the active layer 4 at 20%~40% of the high current density state, fundamentally preventing complete carrier depletion. If the number of cycles of the low-level trap layer 4b is too large (i.e., M≥N), the low-level traps are difficult to saturate quickly under high current injection due to their excessive capacity, resulting in persistent long-wavelength emission components, causing severe spectral crosstalk. Furthermore, a large number of carriers are bound in the low-level trap layer 4b and cannot participate in blue / green light recombination, degrading the light emission efficiency and modulation bandwidth. Therefore, this invention achieves wavelength switching characteristics of low-current carrier maintenance and high-current, high-efficiency blue / green light emission through a synergistic design of "few-cycle deep traps + multi-cycle shallow emitting traps".

[0073] The green or blue light emitted by the high-energy emitting layer 4a and the long-wave electromagnetic waves emitted by the low-energy trapping layer 4b have a large spectral interval and no crosstalk, which provides a good foundation for subsequent high-speed wavelength demodulation. At the same time, it expands the modulation dimension of optical communication and improves anti-interference capability.

[0074] In an alternative embodiment, reference Figure 1A low-energy trap layer 4b is disposed on the side of the high-energy emitting layer 4a facing the substrate 1, located between the N-type semiconductor layer 2 and the high-energy emitting layer 4a. The low-energy trap layer 4b, being close to the N-type semiconductor layer 2, utilizes its high electron mobility to achieve sub-nanosecond trapping and release, significantly improving the device's modulation bandwidth. Under low current, electrons trapped in the traps separate from holes crossing the potential barrier, effectively maintaining junction capacitance stability. Under high current density, after trap saturation, excess carriers naturally overflow to the upper high-energy emitting layer 4a, generating blue / green light.

[0075] Further optionally, the high-energy emitting layer 4a has 3 cycles and the low-energy trapping layer 4b has 2 cycles, but this application does not limit this and the cycles can be adjusted according to actual needs.

[0076] Optionally, when the low-energy trap layer 4b is stacked on the side of the high-energy emitting layer 4a facing the substrate 1, the total thickness of the second quantum well layer b1 ranges from 10nm to 15nm, including the endpoints. This configuration, by optimizing the total thickness of the second quantum well layer b1, avoids excessive electron confinement leading to overflow difficulties. The total thickness of the second quantum well layer is the sum of the thicknesses of the individual second quantum well layers b1. If the thickness of each individual second quantum well layer is the same, then the total thickness of the second quantum well layer is the product of the thickness of each individual second quantum well layer and the number of periods.

[0077] Further optional, refer to Figure 4 When the low-energy trap layer 4b is stacked on the side of the high-energy light-emitting layer 4a facing the substrate 1, the active layer 4 also includes In z Ga (1-z) N transition layer 4c, In z Ga (1-z) The N-transition layer 4c is located between the low-level trap layer 4b and the high-level luminescent layer 4a. Along the direction away from the low-level trap layer 4b, In... z Ga (1-z) In the N transition layer 4c, the In composition z changes linearly from y to x. This setting can reduce the carrier transport barrier.

[0078] In an alternative embodiment, reference Figure 2 A low-energy trap layer 4b is disposed on the side of the high-energy light-emitting layer 4a away from the substrate 1. At this time, the low-energy trap layer 4b is located between the P-type semiconductor layer 3 and the high-energy light-emitting layer 4a. To address the bottlenecks of low hole mobility and poor injection efficiency, the low-energy trap layer 4b is disposed close to the P-side, so that holes injected from the P-region can directly fill the second quantum well layer without long-distance transport to the N-side, significantly improving the trap filling efficiency and low-current response speed. At the same time, the second quantum well layer can also serve as a hole storage layer, assisting in hole injection into the high-energy light-emitting layer 4a under high current.

[0079] Further optionally, the high-energy emitting layer 4a has 3 cycles and the low-energy trapping layer 4b has 2 cycles, but this application does not limit this and the cycles can be adjusted according to actual needs.

[0080] Further optional, refer to Figure 5 The visible light communication LED chip also includes a P-type electron blocking layer 90 located between the P-type semiconductor layer 3 and the low-energy trap layer 4b. The P-type electron blocking layer 90 is preferably a P-type AlGaN electron blocking layer. The Al composition of the P-type AlGaN electron blocking layer ranges from 0.15 to 0.2, including the endpoints; the thickness ranges from 10 nm to 20 nm, including the endpoints. This configuration prevents electrons from overflowing into the P-region and causing leakage current.

[0081] Alternatively, when the low-energy trap layer 4b is stacked on the side of the high-energy light-emitting layer 4a facing away from the substrate 1, the thickness of the first barrier layer a2 and the second barrier layer b2 is less than or equal to 10 nm. This configuration allows for appropriate thinning of the first barrier layer a2 and the second barrier layer b2, utilizing the hole tunneling effect to assist in implantation.

[0082] In an alternative embodiment, reference Figure 3 Low-energy trap layers 4b are disposed on both the side of the high-energy emitting layer 4a facing the substrate 1 and the side facing away from the substrate 1. At this time, a low-energy trap layer 4b exists between the N-type semiconductor layer 2 and the high-energy emitting layer 4a, and also between the P-type semiconductor layer 3 and the high-energy emitting layer 4a. The high-energy emitting layer 4a has low-energy trap layers 4b on both the N-side and P-side, combining the advantages of the two embodiments to form bidirectional carrier cooperative management. The low-energy trap layer 4b near the N-side mainly traps electrons and acts as a carrier storage pool, while the low-energy trap layer 4b near the P-side assists in hole injection and accelerates the overflow of carriers after trap saturation to the high-energy emitting center, thereby realizing the full-process carrier dynamics control from trap filling to wavelength switching.

[0083] In this design, the number of cycles of the low-level trap layer 4b near the N-type semiconductor layer 2 is M1, and the number of cycles of the low-level trap layer 4b near the P-type semiconductor layer 3 is M2, where M = M1 + M2. Optionally, the number of cycles of the high-level emitting layer 4a is 3, and the number of cycles M1 and M2 of the low-level trap layer 4b are both 1, but this application does not impose any limitations and can be adjusted according to actual needs.

[0084] Further optionally, the In composition of the second quantum well layer b1 of the low-level trap layer 4b adjacent to the N-type semiconductor layer 2 is y1, where y1>x; the In composition of the second quantum well layer b1 of the low-level trap layer 4b adjacent to the P-type semiconductor layer 3 is y2, where y2>y1 and y2>x. The value range of y1 is preferably 0.3-0.4, inclusive; the In composition of the low-level trap layer 4b near the N side can be slightly lower, focusing on high-speed capture and release. The value range of y2 is preferably 0.4-0.6, inclusive; the In composition of the low-level trap layer 4b near the P side can be slightly higher, focusing on strong confinement and hole storage.

[0085] Further optionally, when the low-level trap layers 4b are disposed on both the side of the high-level light-emitting layer 4a facing the substrate 1 and the side facing away from the substrate 1, the thickness of the first barrier layer a2 and the second barrier layer b2 is less than or equal to 10 nm. Such arrangement avoids band distortion caused by excessively strong inter-well coupling. The total period number M of the low-level trap layers 4b must still be less than the light-emitting well period number N, so as to ensure that the traps can be rapidly saturated under high current.

[0086] Further optionally, the thickness of the single-layer second quantum well layer b1 ranges from 1 nm to 2 nm, inclusive.

[0087] In this embodiment, the low-level trap layers 4b are disposed on both the N side and the P side. Since the deep-level trap material is additionally introduced, a small number of non-radiative recombination channels may be increased, which has a slight negative impact on the visible light radiation efficiency. However, the efficiency loss can be controlled within an acceptable range (approximately <10%) through the following designs: (1) Strictly limit the total period number M1+M2=M<N of the low-level trap layers 4b, so as to ensure rapid saturation of traps under high current. (2) The low-level trap layers 4b on both sides adopt an asymmetric In composition design (y1≈0.30~0.40, y2≈0.40~0.60) to avoid functional overlap; (3) The thickness of the single second quantum well layer of the low-level trap layer 4b is controlled within an ultra-thin range of 1~2 nm to minimize material loss. In addition, the carrier transfer process between the low-level trap layers 4b on both sides can indirectly promote the light emission efficiency. In general, this embodiment achieves optimal bidirectional carrier management capability and the highest modulation bandwidth potential at the cost of a tiny efficiency loss, and is suitable for high-end application scenarios with extremely high requirements for communication rate.

[0088] In an optional embodiment, the value range of the first current density is 500 A / cm 2 -1000A / cm 2 , inclusive. The value range of the second current density is 0.05 A / cm 2 -0.2A / cm 2 , inclusive.

[0089] In an alternative embodiment, reference Figure 6 A buffer layer 10 is further included between the substrate 1 and the N-type semiconductor layer 2. Optionally, the buffer layer 10 may include, but is not limited to, AlN, and its thickness is preferably in the range of 50 nm to 200 nm. The buffer layer 10 is used to alleviate the lattice mismatch between the substrate 1 and the subsequent epitaxial layer, reduce the dislocation density, and improve the overall crystal quality of the epitaxial layer.

[0090] In an optional embodiment, a transparent conductive layer (not shown in the figure) is further included on the side of the P-type semiconductor layer 3 facing away from the active layer 4 to achieve uniform current diffusion in the P-type GaN layer, ensuring uniform light emission across the entire active layer and avoiding wavelength shift and carrier lifetime unevenness caused by local current concentration. Optionally, the transparent conductive layer may include, but is not limited to, ITO. The thickness of the transparent conductive layer is preferably in the range of 50 nm to 100 nm.

[0091] Through the precise matching design of the doping and thickness of each film layer, uniform current injection and low-resistance ohmic contact of the electrodes are achieved, ensuring the stability of communication signal switching and the high speed of current switching.

[0092] refer to Figure 7 To match the visible light communication LED chip of this application, this application also provides a visible light communication method, which includes:

[0093] S1: Provide a visible light communication LED chip as described in any one of the above; alternately adjust the current density of the active layer 4 so that the active layer 4 alternately operates at a first current density and a second current density.

[0094] S2: Provides a detection structure; the detection structure includes an optical input module, a filtering module and a PD detection module.

[0095] The light input module receives the light emitted by the visible light communication LED chip and transmits it to the filtering module.

[0096] The filtering module receives the light transmitted from the optical input module and filters it so that only the first light ray can pass through the filtering module and enter the PD detection module.

[0097] If the PD detection module detects the first ray, the communication signal representation logic is 1; if the PD detection module does not detect the first ray, the communication signal representation logic is 0.

[0098] The aforementioned visible light communication method achieves signal switching by alternately adjusting the active layer 4 of the visible light communication LED chip to a first current density and a second current density. After receiving light, the light input module of the detection structure transmits it to the filtering module. The filtering module filters the light, allowing only the first light ray to enter the PD detection module. If the PD detection module detects the first light ray, the communication signal representation logic is 1; if it does not detect the first light ray, the communication signal representation logic is 0, thus achieving visible light communication. Furthermore, because it uses the aforementioned visible light communication LED chip, it possesses all the beneficial effects of such a chip. The specific settings of each module in the detection structure can be referred to the following embodiment of the detection structure.

[0099] To match the visible light communication LED chip of this application, this application also provides a detection structure. The detection structure includes a light input module, a filtering module, and a PD detection module.

[0100] The optical input module receives light emitted by any of the aforementioned visible light communication LED chips and transmits the light to the filtering module. The filtering module has an optical channel and a filter located within the optical channel. The light received by the optical input module is transmitted into the optical channel, and the filter only allows the first light ray to pass through the optical channel and enter the PD detection module. The PD detection module detects the first light ray. Using this detection structure, when the PD detection module detects the first light ray, the communication signal representation logic is 1; when the PD detection module does not detect the first light ray, the communication signal representation logic is 0.

[0101] The aforementioned visible light communication LED chip achieves visible light communication signal switching by alternately adjusting the active layer 4 to a first current density and a second current density. After receiving light, the light input module of the detection structure transmits it to the optical channel of the filtering module. The filter in the optical channel filters the light, allowing only the first light ray to enter the PD detection module. If the PD detection module detects the first light ray, the communication signal representation logic is 1; if it does not detect the first light ray, the communication signal representation logic is 0, thus realizing visible light communication. Furthermore, due to the use of the aforementioned visible light communication LED chip, it possesses all the beneficial effects of such a chip.

[0102] Optionally, the optical input module uses a microlens array (preferably with a focal length of 5 mm to 10 mm) to replace the traditional convex lens, which improves the light-gathering efficiency by 30%, and has a smaller size, reducing the optical signal transmission delay.

[0103] In one alternative embodiment, the sidewall of the optical channel of the filtering module includes a metal shielding layer to block external stray light from entering the detection channel and to isolate high-frequency electromagnetic interference.

[0104] And / or, the sidewalls of the optical channel of the filtering module include a light-absorbing coating that absorbs light other than the first light ray.

[0105] In other words, the sidewalls of the optical path can consist only of a metal shielding layer, or only of a light-absorbing coating, or both a metal shielding layer and a light-absorbing coating. The sidewalls of the optical path in the filtering module, including a metal shielding layer and / or a light-absorbing coating, can prevent interference from external stray light.

[0106] Optionally, the thickness of the metal shielding layer is greater than or equal to 50 micrometers. The filter can be a narrowband filter with a wavelength of 450nm-550nm to accommodate the green or blue light emitted by the high-energy emitting layer 4a, allowing only blue or green light signals to pass through. This narrowband filter design significantly reduces spectral crosstalk. Furthermore, the filter bandwidth is preferably less than or equal to 15nm, and the filter cutoff depth is preferably greater than or equal to OD5.

[0107] The metal shielding layer also isolates high-frequency electromagnetic interference. This metal shielding layer works in conjunction with the 450~550nm narrowband filter built into the channel to ensure high-frequency response bandwidth and low demodulation delay of the detection module in complex environments.

[0108] The materials for the metal shielding layer and the light-absorbing coating can be selected according to the wavelength of the first light, as long as the metal shielding layer and the light-absorbing coating can shield stray light other than the first light.

[0109] In summary, based on the above settings, the response bandwidth of this detection structure is ≥1.5 GHz, the demodulation delay is ≤0.3 ns, and the spectral crosstalk is ≤3%.

[0110] Those skilled in the art should understand that, in the disclosure of this invention, the terms "lateral", "longitudinal", "upper", "lower", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, the above terms should not be construed as limiting this invention.

[0111] It should be noted that the various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. The same or similar parts between the various embodiments can be referred to each other.

[0112] The above description of the disclosed embodiments enables those skilled in the art to make or use the invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the invention. Therefore, the invention is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A visible light communication LED chip, characterized in that, include: Substrate; An epitaxial stack located on one side surface of the substrate; the epitaxial stack includes an N-type semiconductor layer, an active layer, and a P-type semiconductor layer stacked sequentially; The active layer includes a high-energy light-emitting layer and a low-energy trapping layer stacked together, wherein the low-energy trapping layer is located on at least one side of the high-energy light-emitting layer facing the substrate and the side away from the substrate. The active layer emits a first light at a first current density; at a second current density, charge carriers in the active layer are trapped by traps in the low-energy trapping layer, and the high-energy emitting layer does not emit light to maintain the carrier concentration in the active layer; the first current density is greater than the second current density. By alternately adjusting the current density of the active layer, the active layer is alternately placed at a first current density and a second current density to achieve visible light communication signal switching.

2. The visible light communication LED chip as described in claim 1, characterized in that, The high-energy luminescent layer comprises a superlattice structure consisting of a first quantum well layer and a first barrier layer; the first quantum well layer comprises In x Ga (1-x) N, 0 < x < 1; The low-energy trap layer comprises a superlattice structure consisting of a second quantum well layer and a second barrier layer; the second quantum well layer comprises In y Ga (1-y) N, 0 < y < 1, y > x; The number of periods of the first quantum well layer and the first barrier layer of the high-energy luminescent layer is N, where N > 1 and N is an integer; The total number of periods of the second quantum well layer and the second barrier layer of the low-level trap layer is M, where M≥1 and M is an integer, and M is less than N.

3. The visible light communication LED chip as described in claim 2, characterized in that, The In component x in the first quantum well layer has a value range of 0.15≤x≤0.25; at the first current density, the first light emitted by the high-energy-level light-emitting layer is green light or blue light; The In component y in the second quantum well layer has a value range of y≥0.

3.

4. A visible light communication LED chip as described in claim 1 or 2, characterized in that, The first current density ranges from 500 A / cm². 2 -1000 A / cm 2 This includes endpoint values. The second current density ranges from 0.05 A / cm². 2 -0.2A / cm 2 This includes endpoint values.

5. A visible light communication LED chip as described in claim 2, characterized in that, The low-energy trap layer is stacked on the side of the high-energy light-emitting layer facing the substrate; The active layer also includes In z Ga (1-z) N transition layer, In z Ga (1-z) The N transition layer is located between the low-energy trap layer and the high-energy emitting layer; along the direction away from the low-energy trap layer, In z Ga (1-z) The In component z of the N transition layer gradually changes linearly from y to x.

6. A visible light communication LED chip as described in claim 1, characterized in that, The low-energy trap layer is stacked on the side of the high-energy light-emitting layer that is away from the substrate; The visible light communication LED chip also includes a P-type electron blocking layer located between the P-type semiconductor layer and the low-energy trap layer.

7. A visible light communication LED chip as described in claim 2, characterized in that, The low-energy trap layer is provided on both the side of the high-energy light-emitting layer facing the substrate and the side facing away from the substrate. The In component of the second quantum well layer, which is close to the low-level trap layer of the N-type semiconductor layer, is y1, where y1 > x; The In component of the second quantum well layer of the low-level trap layer near the P-type semiconductor layer is y2, y2 > y1, y2 > x.

8. A visible light communication LED chip as described in claim 2, characterized in that, When the low-energy trap layer is stacked on the side of the high-energy light-emitting layer facing the substrate; the total thickness of the second quantum well layer ranges from 10nm to 15nm, including the endpoint values; When the low-level trap layer is stacked on the side of the high-level light-emitting layer away from the substrate, the thickness of the first barrier layer and the second barrier layer is less than or equal to 10 nm. When the low-energy trap layer is provided on both the side of the high-energy light-emitting layer facing the substrate and the side away from the substrate, the thickness of the first barrier layer and the second barrier layer is less than or equal to 10 nm, and the thickness of a single second quantum well layer ranges from 1 nm to 2 nm, including the endpoint value.

9. A visible light communication method, characterized in that, include: Provide a visible light communication LED chip according to any one of claims 1-8; alternately adjust the current density of the active layer so that the active layer is alternately at a first current density and a second current density; A detection structure is provided; the detection structure includes an optical input module, a filtering module, and a PD detection module; The light input module receives the light emitted by the visible light communication LED chip and transmits it to the filtering module; The filtering module receives the light transmitted from the optical input module and filters it so that only the first light ray can pass through the filtering module and enter the PD detection module; When the PD detection module detects the first light ray, the communication signal representation logic is 1; when the PD detection module does not detect the first light ray, the communication signal representation logic is 0.

10. A detection structure, characterized in that, Includes an optical input module, a filtering module, and a PD detection module; The light input module is used to receive light emitted by the visible light communication LED chip according to any one of claims 1-8, and transmit the light to the filtering module; The filtering module has an optical channel and a filter located within the optical channel; the light received by the optical input module is transmitted into the optical channel, and the filter only allows the first light rays to pass through the optical channel and enter the PD detection module; The PD detection module is used to detect the first light beam.

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