Group via element doped amorphous gallium oxide full spectrum natural light chip and preparation method

Abstract

The application provides a full-spectrum natural light chip of group VIA element doped amorphous gallium oxide and a preparation method thereof. The full-spectrum natural light chip comprises a p-type semiconductor layer, an n-type semiconductor layer and an amorphous light-emitting layer arranged between the p-type semiconductor layer and the n-type semiconductor layer. The material of the amorphous light-emitting layer is amorphous gallium oxide doped with group VIA elements, and the group VIA elements include at least one of S, Se and Te; the group VIA elements are used to replace oxygen sites in the amorphous gallium oxide to form anion doping, so as to reduce the band gap of the amorphous gallium oxide. The application can realize the purpose of directly emitting full-spectrum continuous natural light by a single semiconductor chip.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a full-spectrum natural light chip of amorphous gallium oxide anion-doped with group VIA elements and its fabrication method. Background Technology

[0002] Currently, the main methods for preparing white light-emitting diodes (LEDs) include the following three: (1) RGB three-color chip combination method: combining red, green and blue LED chips and mixing them to obtain white light; this method requires complex control circuits and driving systems, which are costly, and the inconsistent aging rates of the three-color chips can easily lead to color deviation. (2) Phosphor conversion method: using ultraviolet LEDs or blue LEDs to excite phosphors, and mixing the downconversion light emission of the phosphors with the residual light emission of the LEDs to form white light; however, the electro-optical conversion efficiency of phosphors is low, and the poor thermal stability leads to severe light decay at high temperatures, the color temperature changes significantly with the angle, and the spectrum is discontinuous (especially the red light component is generally missing), making it difficult to improve the color rendering index. (3) Organic white OLED: using organic light-emitting materials, but its application in the field of high-power lighting is limited due to the poor stability, short lifespan, and high packaging requirements of organic materials.

[0003] In related technologies, a semiconductor heterojunction chip capable of directly emitting white light employs n-type ZnO as the n-type layer and p-type GaN as the p-type layer, with crystalline Ga2O3 and / or ZrO2 inserted between them as a punch-through barrier layer. Its light-emitting principle is as follows: the energy band of the n-ZnO / p-GaN heterojunction is modulated through the punch-through barrier layer, causing the heterojunction to emit yellow, green, and blue light simultaneously; simultaneously, the intensity of violet light from corresponding band edges, blue-green light from oxygen vacancies, and orange light from zinc-oxygen interstitial sites in n-ZnO is modulated to achieve white light. However, because its white light emission mainly relies on the combination of defect emission and band edge emission from ZnO, there are obvious gaps in the spectrum, especially in the red light region above 600nm, where the emission intensity is weak, resulting in a limited color rendering index and making it difficult to meet the high color rendering requirements of applications such as D65 standard daylight.

[0004] Current single-chip white light technology cannot obtain full-spectrum continuous natural light. Therefore, how to achieve the direct emission of full-spectrum continuous natural light from a single semiconductor chip is a technical problem that urgently needs to be solved in this field. Summary of the Invention

[0005] In view of the above problems, the present invention is proposed to provide a full-spectrum natural light chip of VIA group element anion-doped amorphous gallium oxide and its preparation method, which overcomes or at least partially solves the above problems. It can solve the problems of insufficient red light component and low color rendering index in the single-chip white light technology of related technologies, and realize the purpose of directly emitting full-spectrum continuous natural light from a single semiconductor chip.

[0006] Specifically, the present invention provides a full-spectrum natural light chip doped with group VIA elements amorphous gallium oxide, comprising: p-type semiconductor layer; n-type semiconductor layer; and An amorphous light-emitting layer is disposed between the p-type semiconductor layer and the n-type semiconductor layer; The amorphous light-emitting layer is made of amorphous gallium oxide doped with group VIA elements, including at least one of S, Se, and Te. The group VIA elements are used to replace oxygen sites in the amorphous gallium oxide to form anion doping, thereby reducing the band gap of the amorphous gallium oxide.

[0007] Optionally, the thickness of the amorphous light-emitting layer is from 0.5 nm to 50 nm.

[0008] Optionally, the thickness of the amorphous light-emitting layer is 0.5 nm to 1 nm.

[0009] Optionally, the total doping ratio of the VIA group elements in the amorphous light-emitting layer is from 0.01 at% to 30 at%.

[0010] Optionally, the p-type semiconductor layer contains Ga. The n-type semiconductor layer contains the element O; The p-type semiconductor layer, the amorphous light-emitting layer, and the n-type semiconductor layer constitute a crystalline / amorphous / crystalline dual-through heterojunction; wherein, the Ga element in the p-type semiconductor layer and the Ga element in the amorphous light-emitting layer form an atomic-level smooth transition to achieve cation-through growth; the O element in the amorphous light-emitting layer and the O element in the n-type semiconductor layer form an atomic-level smooth transition to achieve anion-through growth.

[0011] Optionally, the material of the p-type semiconductor layer includes one or more of p-GaN, p-AlGaN, p-InGaN, and p-InGaAlN; The material of the n-type semiconductor layer includes n-ZnO, or n-ZnO doped with Si, In, Sn or Al elements.

[0012] Optionally, the full-spectrum natural light chip further includes: p-type electrodes and n-type electrodes, wherein the p-type electrodes and n-type electrodes are located on the same side or on the top and bottom sides of the full-spectrum natural light chip; The p-type electrode is a Cr / Au electrode or a conductive substrate; in the Cr / Au electrode, the thickness of the Cr layer is 2~10nm and the thickness of the Au layer is 20~200nm. The n-type electrode is an AZO or ITO transparent conductive electrode; When the p-type electrode and the n-type electrode are located on the same side of the full-spectrum natural light chip, the full-spectrum natural light chip further includes a substrate, and the p-type semiconductor layer is located on top of the substrate; The substrate is any one of sapphire substrate, SiC substrate, GaN self-supporting substrate, and flexible metal foil.

[0013] On the other hand, embodiments of the present invention also provide a method for fabricating a full-spectrum natural light chip doped with group VIA elements amorphous gallium oxide, the method being used to fabricate a full-spectrum natural light chip doped with group VIA elements amorphous gallium oxide as described in any of the preceding claims; the method includes: The p-type semiconductor layer is fabricated on a substrate; The amorphous light-emitting layer is fabricated on the p-type semiconductor layer; The n-type semiconductor layer is fabricated on the amorphous light-emitting layer; Prepare p-type and n-type electrodes.

[0014] Optionally, the amorphous light-emitting layer can be prepared by any one of atomic layer deposition, metal-organic chemical vapor deposition, reactive magnetron sputtering, and pulsed laser deposition. In the preparation of the amorphous light-emitting layer, the doping source of the group VIA element is a precursor containing S, Se or Te; the preparation temperature of the amorphous light-emitting layer is 200℃ to 500℃; and the growth rate of the amorphous light-emitting layer is 10nm / h to 2000nm / h. When the amorphous light-emitting layer is prepared by atomic layer deposition or metal-organic chemical vapor deposition: the precursor of S includes at least one of tert-butyl mercaptan, di-tert-butyl sulfide, and thiophene compounds; the precursor containing Se includes at least one of dimethylseleno ... When the amorphous light-emitting layer is prepared by reactive magnetron sputtering or pulsed laser deposition: The doping source includes at least one of the following: a target containing S, a target containing Se, and a target containing Te; The S-containing target material includes at least one of ZnS, CdS, MoS2, WS2, and S-doped targets; The Se-containing target material includes at least one of ZnSe, CdSe, WSe2, MoSe2, and Se-doped targets; The Te-containing target includes CdTe, ZnTe, Bi2Te3, Sb2Te3, or Te-doped target.

[0015] Optionally, the p-type semiconductor layer is prepared by metal-organic chemical vapor deposition or molecular beam epitaxy at 1000°C to 1100°C. The n-type semiconductor layer is prepared at 400°C to 800°C using metal-organic chemical vapor deposition, molecular beam epitaxy, or atomic layer deposition.

[0016] In the full-spectrum natural light chip of VIA group element anion-doped amorphous gallium oxide of the present invention, the amorphous light-emitting layer is an amorphous gallium oxide layer doped with VIA group elements. In the amorphous gallium oxide, S / Se / Te replaces the O sites, introducing deep energy level acceptor states, narrowing the effective band gap, and significantly increasing the energy levels corresponding to red light, thereby enhancing the red light emission in the 600nm to 780nm wavelength band, thus enabling the chip to output warm sunlight with a color temperature <5000K.

[0017] The amorphous light-emitting layer, as a two-dimensional amorphous ultrathin layer, has the following light-emitting mechanism: the two-dimensional amorphous material (an amorphous material with a two-dimensional confinement effect) breaks the crystal symmetry, generating a large number of discrete Anderson localized states in the band gap, forming multiple conductive channels. Charge carriers radiatively recombine between localized states, emitting continuous photons covering 380-780nm. The chip of this invention emits a continuous and uniform spectrum with a color rendering index (CRI) ≥ 94, capable of outputting full-spectrum natural light close to the solar spectrum. Therefore, a single chip of this invention can output multiple standard light sources such as D65 standard daylight and equal-energy white light, with the color temperature continuously adjustable within the range of warm white light to cool white light, offering a wider adjustable range to meet the needs of different lighting scenarios.

[0018] Furthermore, compared with the prior art, the full-spectrum emission of the present invention does not rely on the recombination of defect energy levels such as oxygen vacancies and zinc-oxygen interstitial sites in ZnO, but is based on the radiative recombination of Anderson local states in the amorphous layer, thus avoiding the problems of efficiency saturation and poor thermal stability commonly seen in defect luminescence.

[0019] Furthermore, since the chip of this invention directly emits full-spectrum natural light through its own structure, there is no need to add an additional phosphor layer or quantum dot layer, thus avoiding the loss of electro-optical conversion efficiency, thermal stability issues, rare earth resource consumption, and ultraviolet leakage risks associated with phosphor conversion. Therefore, the fabrication process of the chip of this invention is relatively simple, the manufacturing cost is low, and it conforms to the concept of green environmental protection.

[0020] Furthermore, since the p-type semiconductor layer and the amorphous light-emitting layer share Ga, an atomically smooth transition is achieved, enabling cation-through growth. Simultaneously, the amorphous light-emitting layer and the n-type semiconductor layer share O, forming an atomically smooth transition and enabling anion-through growth. This dual-through growth strategy eliminates dangling bonds and non-radiative recombination centers at the heterojunction; the amorphous layer itself has no lattice mismatch stress, and the two-step growth method yields a high-quality single-crystal n-type semiconductor layer. Consequently, the injection efficiency of holes from the p-type semiconductor layer to the n-type semiconductor layer is significantly improved, and electrons can also be injected in the reverse direction, achieving efficient bidirectional carrier transport, increased electron mobility, and a significant improvement in electro-optical conversion efficiency.

[0021] Meanwhile, the amorphous layer and the crystalline semiconductors on both sides achieve atomic-level matching through a dual-through growth strategy, resulting in extremely low interface defect density. Therefore, the chip of this invention has a long service life (low light decay under high temperature and high humidity conditions) and a response time on the order of nanoseconds, which is about 1000 times faster than the microsecond-level response of phosphor-converted LEDs, supporting high-speed modulation applications such as multi-band coding in visible light communication (Li-Fi).

[0022] The above and other objects, advantages and features of the present invention will become more apparent to those skilled in the art from the following detailed description of specific embodiments of the invention in conjunction with the accompanying drawings. Attached Figure Description

[0023] The following sections will describe some specific embodiments of the invention in a detailed manner by way of example and not limitation, with reference to the accompanying drawings. The same reference numerals in the drawings denote the same or similar parts or portions. Those skilled in the art should understand that these drawings are not necessarily drawn to scale. In the drawings: Figure 1 This is a schematic structural diagram of a full-spectrum natural light chip anion-doped amorphous gallium oxide of group VIA elements according to an embodiment of the present invention. Figure 2 This is a schematic structural diagram of a full-spectrum natural light chip anion-doped amorphous gallium oxide of group VIA elements according to an embodiment of the present invention. Figure 3 This is a schematic diagram of the band structure of a crystal / amorphous / crystalline heterojunction in a full-spectrum natural light chip anion-doped amorphous gallium oxide of group VIA elements according to an embodiment of the present invention. Figure 4 (a) is the electroluminescence curve of the white light chip in Comparative Example 1; Figure 4 (b) is the electroluminescence curve of a full-spectrum natural light chip of amorphous gallium oxide anion-doped with group VIA elements according to an embodiment of the present invention; Figure 5 (a) is the CIE coordinate diagram of the white light chip in Comparative Example 1; Figure 5 (b) is a white light CIE coordinate diagram of a full-spectrum natural light chip of amorphous gallium oxide anion-doped with group VIA elements according to an embodiment of the present invention.

[0024] Figure label: 1. Substrate; 2. p-type semiconductor layer; 3. Amorphous light-emitting layer; 4. n-type semiconductor layer; 5. n-type electrode; 6. p-type electrode. Detailed Implementation

[0025] Figure 1 This is a schematic structural diagram of a full-spectrum natural light chip anion-doped amorphous gallium oxide of group VIA elements according to an embodiment of the present invention, as shown below. Figure 1 As shown, and refer to Figures 2 to 3 This invention provides a full-spectrum natural light chip of amorphous gallium oxide (Ga₂O₃) doped with group VIA elements, comprising a p-type semiconductor layer 2, an amorphous light-emitting layer 3, and an n-type semiconductor layer 4. The amorphous light-emitting layer 3 is disposed between the p-type semiconductor layer 2 and the n-type semiconductor layer 4. The amorphous light-emitting layer 3 is made of amorphous gallium oxide (a-Ga₂O₃) doped with group VIA elements, including at least one of S, Se, and Te. The group VIA elements are used to replace oxygen sites in the amorphous gallium oxide, forming anion doping, thereby reducing the band gap of the amorphous gallium oxide.

[0026] like Figure 3 As shown, the p-type semiconductor layer 2, the amorphous light-emitting layer 3, and the n-type semiconductor layer 4 constitute a crystalline / amorphous / crystalline heterojunction. The left side of the figure represents the p-type semiconductor layer 2, the middle side represents the amorphous light-emitting layer 3, and the right side represents the n-type semiconductor layer 4. hν represents the photon energy, and the different colored dashed lines and arrows characterize the carrier transition behavior under photon excitation at different energies. Figure 3 This illustrates the difference between the continuous energy bands of a crystal and the discrete localized energy levels of an amorphous Anderson layer: In a crystal, atoms are arranged periodically and completely, forming a continuous energy band with no discrete localized energy levels. The blue hν dashed line represents high-energy photons incident on the crystal, where charge carriers can only directly cross energy bands in a single transition, resulting in a single transition path. In contrast, the disordered atomic arrangement in an amorphous layer leads to a disordered periodic potential field, causing Anderson localization. The electron wavefunction is confined to local defect sites, and the continuous energy band is split into numerous discrete localized energy levels (the black horizontal dashed lines in the figure represent multi-level transition steps for charge carriers). This effect is called Anderson localized state discretization.

[0027] In this embodiment, the amorphous light-emitting layer is an amorphous gallium oxide layer doped with group VIA elements. In amorphous gallium oxide, S / Se / Te replaces the O sites, introducing deep acceptor states, narrowing the effective bandgap, and significantly increasing the energy levels corresponding to red light, thereby enhancing red light emission in the 600nm to 780nm wavelength band, enabling the chip to output warm sunlight with a color temperature <5000K.

[0028] The amorphous light-emitting layer 3 is an ultrathin amorphous insertion layer with a thickness on the nanometer scale. It is made of an amorphous material with a two-dimensional confinement effect, and its band gap contains discrete Anderson localized states, forming multiple conductive channels. During chip operation, under forward bias, holes are injected into the amorphous light-emitting layer from the p-type semiconductor layer, and electrons are injected from the n-type semiconductor layer. The injected holes and electrons act as charge carriers, undergoing multi-channel radiative recombination between the discrete Anderson localized states, releasing photons of different energies. This forms a continuous spectrum covering the visible light region from 380 nm to 780 nm. After mixing, the photons from each wavelength band output full-spectrum natural light (see [link to relevant documentation]). Figure 4 (b) and Figure 5 (b) The chip of this invention emits a continuous and uniform spectrum with a color rendering index of over 94, enabling it to output full-spectrum natural light close to the solar spectrum. Furthermore, a single chip of this invention can output multiple standard light sources, including D65 standard daylight and equal-energy white light (CIE coordinates 0.33, 0.33), with continuously adjustable color temperature ranging from warm white light to cool white light, offering a wider adjustable range to meet the needs of different lighting scenarios.

[0029] In some alternative embodiments of the present invention, the thickness of the amorphous light-emitting layer is any value from 0.5 nm to 50 nm (e.g., 0.5 nm, 0.6 nm, 0.7 nm, 0.8 nm, 0.9 nm, 0.99 nm, 1 nm, 1.5 nm, 2 nm, 3 nm, 4 nm, 5 nm, 10 nm, 20 nm, or 50 nm). Specifically, the thickness of the amorphous light-emitting layer 3 can be precisely controlled by the number of atomic layer deposition (ALD) cycles.

[0030] Preferably, the thickness of the amorphous light-emitting layer is 0.5 nm to 1 nm, which is close to the limit of atomic thickness. At this ultrathin scale, the charge carriers are subjected to a strong quantum confinement effect in the vertical direction. At the same time, the Anderson local state density caused by the disorder of the amorphous structure increases significantly, and the number of radiative recombination channels increases exponentially, thereby greatly improving the luminous efficiency and helping to further improve the continuity and uniformity of the full-spectrum emission.

[0031] In some embodiments of the present invention, the p-type semiconductor layer 2, the amorphous light-emitting layer 3, and the n-type semiconductor layer 4 constitute a crystalline / amorphous / crystalline dual-through heterojunction. Specifically, the Ga element in the p-type semiconductor layer 2 and the Ga element in the amorphous light-emitting layer 3 form an atomically smooth transition, achieving cation-through growth; the O element in the amorphous light-emitting layer 3 and the O element in the n-type semiconductor layer 4 form an atomically smooth transition, achieving anion-through growth.

[0032] When the p-type semiconductor layer 2 is made of p-GaN and the n-type semiconductor layer 4 is made of n-ZnO, the p-type semiconductor layer 2 and the amorphous light-emitting layer 3 share the Ga element, forming an atomically smooth transition from Ga-N bonds to Ga-O bonds, achieving cation-through growth. Simultaneously, the amorphous light-emitting layer 3 and the n-type semiconductor layer 4 share the O element, forming an atomically smooth transition from O-Ga bonds to O-Zn bonds, achieving anion-through growth. This dual-through growth strategy eliminates dangling bonds and non-radiative recombination centers at the heterojunction. Consequently, the hole injection efficiency from the p-type semiconductor layer 2 to the n-type semiconductor layer 4 is significantly improved, electron mobility is increased, and electro-optical conversion efficiency is significantly enhanced.

[0033] Furthermore, the amorphous layer and the crystalline semiconductors on both sides achieve atomic-level matching through a dual-through growth strategy, resulting in extremely low interface defect density. Therefore, the chip of this invention has a long service life (low light decay under high temperature and humidity conditions) and a response time on the order of nanoseconds, which is about 1000 times faster than the microsecond-level response of phosphor-converted LEDs, supporting high-speed modulation applications such as multi-band coding in visible light communication (Li-Fi).

[0034] In some embodiments of the present invention, the total doping ratio of group VIA elements in the amorphous light-emitting layer is from 0.01 at% to 30 at% (e.g., 0.1 at%, 0.5 at%, 1 at%, 5 at%, 10 at%, 20 at% or 30 at%).

[0035] In some embodiments of the present invention, the material of the p-type semiconductor layer 2 includes one or more of p-GaN, p-AlGaN, p-InGaN, and p-InGaAlN.

[0036] Specifically, when p-AlGaN is used for the p-type semiconductor layer 2, its bandgap width can be adjusted by regulating the Al composition (e.g., Al content of 10%~30%), thereby further optimizing the bandgap matching with the amorphous light-emitting layer 3 and obtaining a lower hole injection barrier. When p-InGaN is used for the p-type semiconductor layer 2, the bandgap can be reduced by adjusting the In composition (e.g., In content of 5%~20%), which is beneficial for hole generation and injection. As a quaternary alloy material, p-InGaAlN allows for simultaneous adjustment of the In, Al, and Ga compositions, enabling independent control of the bandgap and lattice constant, making it suitable for applications with special requirements for band structure.

[0037] In this embodiment, the p-type semiconductor layer 2 is made of Ga, thus enabling a smooth atomic-level transition with the Ga element in the amorphous light-emitting layer 3, achieving cation (Ga) 3+ Through-growth eliminates interface dangling bonds and reduces non-radiative recombination centers.

[0038] In some embodiments of the present invention, the n-type semiconductor layer 4 is made of n-ZnO. Specifically, the thickness of the n-type ZnO layer is not limited, for example, it can be 300nm~600nm. The growth method of n-type ZnO can be molecular beam epitaxy (MBE), metal-organic chemical vapor deposition (MOCVD), magnetron sputtering, thermal evaporation, electron beam evaporation or atomic layer deposition (ALD), preferably MOCVD or ALD.

[0039] In some embodiments of the present invention, the n-type semiconductor layer 4 is made of n-type ZnO doped with Si, In, Sn or Al. The doping ratio of the doping element (such as Si, In, Sn or Al) is preferably 0.1 at% to 5 at% to adjust the carrier concentration, conductivity and emission wavelength of the n-type semiconductor layer 4.

[0040] like Figure 1 As shown, in some embodiments of the present invention, the full-spectrum natural light chip further includes a p-type electrode 6 and an n-type electrode 5. The p-type electrode 6 and the n-type electrode 5 are located on the same side of the full-spectrum natural light chip, which helps to simplify subsequent packaging processes.

[0041] The p-type electrode 6 is a Cr / Au electrode, and the n-type electrode 5 is an AZO (aluminum-doped zinc oxide) or ITO (indium tin oxide) transparent conductive electrode.

[0042] Specifically, in the Cr / Au electrode, the thickness of the Cr layer is 2~10 nm (e.g., 2 nm, 5 nm, 8 nm, or 10 nm), and the thickness of the Au layer is 20~200 nm (e.g., 20 nm, 30 nm, 50 nm, 80 nm, 95 nm, 120 nm, 150 nm, 180 nm, or 200 nm). The Cr layer is used to form an ohmic contact with the p-type semiconductor layer 2, and the Au layer is used to reduce the overall resistance of the electrode. Preferably, the thickness of the Cr layer is 5 nm, and the thickness of the Au layer is 95 nm.

[0043] A stepped surface is formed between the n-type semiconductor layer 4, the amorphous light-emitting layer 3, and the p-type semiconductor layer 2 using photolithography and wet / dry etching, allowing the n-type and p-type electrodes to be fabricated on the same side of the chip. Specifically, the n-type electrode is located on the side of the n-type semiconductor layer 4 away from the amorphous light-emitting layer 3, and the p-type electrode is located on the exposed surface of the p-type semiconductor layer 2. Electrode fabrication methods can include magnetron sputtering, thermal evaporation, electron beam evaporation, or atomic layer deposition, with magnetron sputtering or electron beam evaporation being preferred.

[0044] The full-spectrum natural light chip also includes a substrate 1, on which a p-type semiconductor layer 2 is disposed. The substrate 1 is a sapphire substrate 1, a SiC substrate 1, a GaN self-supporting substrate 1, or a flexible metal foil, preferably a sapphire substrate 1.

[0045] like Figure 2As shown, in some embodiments of the present invention, the p-type electrode 6 and the n-type electrode 5 are located on the lower and upper sides of the full-spectrum natural light chip, respectively. The p-type electrode 6 is a conductive substrate; the n-type electrode 5 is an AZO or ITO transparent conductive electrode. In this embodiment, the current flows in the vertical direction, which is beneficial for uniform current diffusion and reduces current congestion effects, making it particularly suitable for high-power lighting applications.

[0046] Specifically, the p-type semiconductor layer 2 is peeled off from the growth substrate 1 and transferred to a conductive substrate (such as an aluminum substrate, copper substrate or other metal substrate). The conductive substrate serves as the p-type electrode, eliminating the need for additional metal electrode deposition. At the same time, the conductive substrate supports the p-type semiconductor layer 2. The n-type electrode is disposed on the side of the n-type semiconductor layer 4 away from the amorphous light-emitting layer 3.

[0047] In some embodiments of the present invention, a full-spectrum natural light chip doped with VIA group element anions of amorphous gallium oxide can be applied in a display device. The display device includes a full-spectrum natural light chip doped with VIA group element anions of amorphous gallium oxide, and a quantum dot color conversion layer or a fluorescent color conversion layer disposed above the full-spectrum natural light chip.

[0048] Specifically, a full-spectrum natural light chip doped with VIA group element anions emits full-spectrum natural light. A quantum dot color conversion layer or a fluorescent color conversion layer absorbs a portion of the full-spectrum natural light and converts it into narrowband red, green, and blue light, thereby achieving full-color display. Compared to existing solutions that use blue LEDs to excite the color conversion layer, this invention uses a full-spectrum natural light chip doped with VIA group element anions as the excitation source. This chip has a wide and continuous spectrum with sufficient energy in each band. After color conversion, it can obtain three primary colors with higher color purity and better color rendering. Furthermore, it eliminates the need for mass transfer, simplifying the process and allowing for further reduction in pixel size to the micrometer level, making it suitable for Micro-LED display applications. The full-spectrum natural light chip itself does not contain phosphors, eliminating the risk of blue light leakage. The color conversion layer only converts a portion of the spectrum; the combination of these two components results in excellent display performance.

[0049] This invention also provides a method for fabricating a full-spectrum natural light chip doped with VIA group element anions, specifically amorphous gallium oxide. This method is used to fabricate the full-spectrum natural light chip doped with VIA group element anions as described in any of the above embodiments. The fabrication method includes the following steps: S100, the p-type semiconductor layer is prepared on the substrate; S200, the amorphous light-emitting layer is prepared on the p-type semiconductor layer; S300, the n-type semiconductor layer is prepared on the amorphous light-emitting layer; S400 is used to prepare p-type and n-type electrodes to obtain a full-spectrum natural light chip of VIA group element anion-doped amorphous gallium oxide.

[0050] Specifically, the thickness of the p-type semiconductor layer is 100nm~300nm, and the thickness of the n-type semiconductor layer is 100nm~300nm.

[0051] In step S400, if a horizontally structured chip is fabricated (e.g.) Figure 1 A step surface is formed between the n-type semiconductor layer, the amorphous light-emitting layer, and the p-type semiconductor layer using photolithography and etching, and the n-type and p-type electrodes are fabricated on the same side of the chip. The n-type electrode is disposed on the upper surface of the n-type semiconductor layer, and the p-type electrode is disposed on the exposed surface of the p-type semiconductor layer. This is used to fabricate vertical structure chips (such as...). Figure 2 The p-type semiconductor layer is peeled off from the growth substrate and transferred and bonded to a conductive substrate, which directly serves as the p-type electrode; the n-type electrode is disposed on the upper surface of the n-type semiconductor layer. The peeled growth substrate can be recycled and reused.

[0052] In some optional embodiments of the present invention, step S200 specifically includes: growing an amorphous light-emitting layer 3 with a thickness of 0.5 nm to 50 nm on the p-type semiconductor layer 2, so that the amorphous light-emitting layer and the p-type semiconductor layer share gallium element to achieve cation-to-hydrogen growth. Step S300 specifically includes: growing an n-type semiconductor layer 4 on the amorphous light-emitting layer 3, so that the amorphous light-emitting layer 3 and the n-type semiconductor layer 4 share oxygen element to achieve anion-to-hydrogen growth. This preparation method achieves in-situ cation-and-anion-to-hydrogen growth during the growth process, obtaining an atomically matched heterostructure interface without additional interface treatment steps, thus eliminating interface defects at the fabrication process level.

[0053] In some optional embodiments of the present invention, the amorphous light-emitting layer 3 is prepared by any one of atomic layer deposition (ALD), metal-organic chemical vapor deposition (MOCVD), reactive magnetron sputtering, and pulsed laser deposition (PLD). In the preparation of the amorphous light-emitting layer, the doping source of the group VIA elements is a precursor containing S, Se, or Te; the preparation temperature of the amorphous light-emitting layer is 200°C to 500°C (e.g., 200°C, 300°C, 400°C, or 500°C), without the need for high-temperature annealing, thus effectively maintaining the amorphous state of the amorphous light-emitting layer. The growth rate of the amorphous light-emitting layer is 10 nm / h to 2000 nm / h.

[0054] When the amorphous light-emitting layer is prepared by atomic layer deposition or metal-organic chemical vapor deposition: the precursor of S includes at least one of tert-butyl mercaptan, di-tert-butyl sulfide, and thiophene compounds; the precursor containing Se includes at least one of dimethyl selenide, diethyl selenide, and tert-butyl selenol; the precursor of Te includes at least one of dimethyl tellurium, diethyl tellurium, and diisopropyl tellurium; and the precursor flow rate is 20 sccm to 300 sccm.

[0055] When the amorphous light-emitting layer is prepared by reactive magnetron sputtering or pulsed laser deposition: the doping source includes at least one of a S-containing target, a Se-containing target, and a Te-containing target; wherein, the S-containing target includes at least one of ZnS, CdS, MoS2, WS2, and S-doped targets; the Se-containing target includes at least one of ZnSe, CdSe, WSe2, MoSe2, and Se-doped targets; and the Te-containing target includes CdTe, ZnTe, Bi2Te3, Sb2Te3, or Te-doped targets.

[0056] In some optional embodiments of the present invention, the p-type semiconductor layer is prepared by metal-organic chemical vapor deposition or molecular beam epitaxy at 1000°C to 1100°C; the n-type semiconductor layer is prepared by metal-organic chemical vapor deposition, molecular beam epitaxy or atomic layer deposition at 400°C to 800°C.

[0057] The following detailed description of the full-spectrum natural light chip of VIA group element anion doped amorphous gallium oxide of the present invention, with reference to specific embodiments, will be provided in further detail.

[0058] Example 1 like Figure 2 As shown, a full-spectrum natural light chip anion-doped amorphous gallium oxide of group VIA elements has an epitaxial structure comprising, from bottom to top, a p-type electrode, a p-GaN layer, an amorphous light-emitting layer (a-Ga2O3:S / Se / Te), an n-ZnO layer, and an n-type electrode. The thickness of the amorphous light-emitting layer is 0.6 nm, and the total doping ratio of group VIA elements in the amorphous light-emitting layer is 0.5 at%.

[0059] Comparative Example 1 A method for fabricating a chip, comprising, from bottom to top, a p-type electrode, a p-GaN layer, a punch-through barrier layer, an n-ZnO layer, and an n-type electrode. The punch-through barrier layer is a crystalline Ga2O3 layer with a thickness of 30 nm. The electroluminescence curve of this chip is shown below. Figure 4 As shown in (a), the white light CIE coordinate graph is as follows: Figure 5 As shown in (a), its red light is weak and its color rendering is low.

[0060] By taking, for example Figure 4 (b) and Figure 4 (a) It can be seen that the present invention uses an amorphous gallium oxide layer doped with VIA group elements, which can shift the blue-green light peaks in the electroluminescence curve toward the red light direction.

[0061] By taking, for example Figure 5 (b) and Figure 5 (a) It can be seen that the present invention uses an amorphous gallium oxide layer doped with VIA group elements, which can shift the CIE coordinates of white light to the right, thereby realizing full-spectrum natural light including warm white light.

[0062] Therefore, those skilled in the art should recognize that although numerous exemplary embodiments of the present invention have been shown and described in detail herein, many other variations or modifications conforming to the principles of the present invention can be directly determined or derived from the disclosure of the present invention without departing from the spirit and scope of the invention. Thus, the scope of the present invention should be understood and construed as covering all such other variations or modifications.

Claims

1. A full-spectrum natural light chip doped with group VIA elements and composed of amorphous gallium oxide, characterized in that, include: p-type semiconductor layer; n-type semiconductor layer; as well as An amorphous light-emitting layer is disposed between the p-type semiconductor layer and the n-type semiconductor layer; The amorphous light-emitting layer is made of amorphous gallium oxide doped with group VIA elements, including at least one of S, Se, and Te. The group VIA elements are used to replace oxygen sites in the amorphous gallium oxide to form anion doping, thereby reducing the band gap of the amorphous gallium oxide.

2. The full-spectrum natural light chip according to claim 1, characterized in that, The thickness of the amorphous light-emitting layer is from 0.5 nm to 50 nm.

3. The full-spectrum natural light chip according to claim 2, characterized in that, The thickness of the amorphous light-emitting layer is 0.5 nm to 1 nm.

4. The full-spectrum natural light chip according to claim 1, characterized in that, The total doping ratio of the group VIA elements in the amorphous light-emitting layer is from 0.01 at% to 30 at%.

5. The full-spectrum natural light chip according to claim 1, characterized in that, The p-type semiconductor layer contains Ga element; The n-type semiconductor layer contains the element O; The p-type semiconductor layer, the amorphous light-emitting layer, and the n-type semiconductor layer constitute a crystalline / amorphous / crystalline dual-through heterojunction; wherein, the Ga element in the p-type semiconductor layer and the Ga element in the amorphous light-emitting layer form an atomic-level smooth transition to achieve cation-through growth; the O element in the amorphous light-emitting layer and the O element in the n-type semiconductor layer form an atomic-level smooth transition to achieve anion-through growth.

6. The full-spectrum natural light chip according to claim 1, characterized in that, The material of the p-type semiconductor layer includes one or more of p-GaN, p-AlGaN, p-InGaN, and p-InGaAlN; The material of the n-type semiconductor layer includes n-ZnO, or n-ZnO doped with Si, In, Sn or Al elements.

7. The full-spectrum natural light chip according to claim 1, characterized in that, Also includes: p-type electrodes and n-type electrodes, wherein the p-type electrodes and n-type electrodes are located on the same side or on the top and bottom sides of the full-spectrum natural light chip; The p-type electrode is a Cr / Au electrode or a conductive substrate; in the Cr / Au electrode, the thickness of the Cr layer is 2~10nm and the thickness of the Au layer is 20~200nm. The n-type electrode is an AZO or ITO transparent conductive electrode; When the p-type electrode and the n-type electrode are located on the same side of the full-spectrum natural light chip, the full-spectrum natural light chip further includes a substrate, and the p-type semiconductor layer is located on top of the substrate; The substrate is any one of sapphire substrate, SiC substrate, GaN self-supporting substrate, and flexible metal foil.

8. A method for fabricating a full-spectrum natural light chip doped with group VIA elements, characterized in that, The preparation method is used to prepare a full-spectrum natural light chip as described in any one of claims 1 to 7; the preparation method includes: The p-type semiconductor layer is fabricated on a substrate; The amorphous light-emitting layer is fabricated on the p-type semiconductor layer; The n-type semiconductor layer is fabricated on the amorphous light-emitting layer; Prepare p-type and n-type electrodes.

9. The preparation method according to claim 8, characterized in that, The amorphous light-emitting layer is prepared by any one of atomic layer deposition, metal-organic chemical vapor deposition, reactive magnetron sputtering, and pulsed laser deposition. In the preparation of the amorphous light-emitting layer, the doping source of the group VIA element is a precursor containing S, Se or Te; the preparation temperature of the amorphous light-emitting layer is 200℃ to 500℃; and the growth rate of the amorphous light-emitting layer is 10nm / h to 2000nm / h. When the amorphous light-emitting layer is prepared by atomic layer deposition or metal-organic chemical vapor deposition: the precursor of S includes at least one of tert-butyl mercaptan, di-tert-butyl sulfide, and thiophene compounds; the precursor containing Se includes at least one of dimethylseleno ... When the amorphous light-emitting layer is prepared by reactive magnetron sputtering or pulsed laser deposition: The doping source includes at least one of the following: a target containing S, a target containing Se, and a target containing Te; The S-containing target material includes at least one of ZnS, CdS, MoS2, WS2, and S-doped targets; The Se-containing target material includes at least one of ZnSe, CdSe, WSe2, MoSe2, and Se-doped targets; The Te-containing target includes CdTe, ZnTe, Bi2Te3, Sb2Te3, or Te-doped target.

10. The preparation method according to claim 9, characterized in that, The p-type semiconductor layer is prepared by metal-organic chemical vapor deposition or molecular beam epitaxy at 1000°C to 1100°C. The n-type semiconductor layer is prepared at 400°C to 800°C using metal-organic chemical vapor deposition, molecular beam epitaxy, or atomic layer deposition.

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