A multilayer wiring structure and a method for manufacturing the same

Abstract

The application relates to the technical field of semiconductor device packaging and printed circuit board manufacturing, and provides a multilayer circuit structure and a preparation method thereof. The method is characterized in that: a substrate with a preset number of layers is laminated, power supply layers, signal layers and ground heat dissipation layers are arranged in the substrate; laser drilling and hole filling electroplating processes are used to prepare interlayer blind buried hole interconnection units, so that the power supply layers, the signal layers and the ground heat dissipation layers are electrically connected; the surface layer of the substrate is precisely etched to form bonding pads of chips and driving integrated circuits; flip light emitting diode chips and embedded driving integrated circuits are arranged on corresponding electrodes on the top layer of the substrate; a molding and pressing process is used to form an ultrathin packaging glue layer with a thickness suitable for the driving integrated circuits on the surface of the substrate; the substrate after packaging is cut to obtain single device units, and electrical lighting detection and light splitting and sorting are performed to complete the preparation. The signal crosstalk is effectively reduced, and the ground heat dissipation layer improves the overall heat dissipation performance of the device.

Description

Technical Field

[0001] This application relates to the fields of semiconductor device packaging and printed circuit board manufacturing technology, and in particular to a multilayer circuit structure and its preparation method. Background Technology

[0002] Existing multilayer circuit structure fabrication methods cannot simultaneously meet the requirements of ultra-thinness, high integration, low signal crosstalk, and high reliability. Traditional side-emitting devices rely on brackets, light guide plates, and secondary optical bending structures, resulting in a large overall thickness that is unsuitable for ultra-thin applications such as narrow bezels and stealth mounting. Driver integrated circuits often employ discrete external mounting methods, leading to long electrical connection paths, slow response speeds, and susceptibility to connection failures under complex environments such as high and low temperature cycling and vibration. Ineffective isolation of circuit layers results in severe signal crosstalk, limiting the realization of high-density array arrangements. Inadequate heat dissipation path design leads to high device operating temperatures and insufficient long-term reliability. Existing fabrication processes are complex, have low yields, and are difficult to achieve large-scale mass production. Currently, there is no multilayer circuit structure fabrication solution that can simultaneously solve all of the above problems. Summary of the Invention

[0003] This application provides a multilayer circuit structure and its fabrication method, which aims to solve the following problems.

[0004] In a first aspect, embodiments of this application provide a method for fabricating a multilayer circuit structure, the method comprising: A substrate with a preset number of layers is stacked, and a power layer, a signal layer, and a grounding and heat dissipation layer are arranged in layers inside the substrate. Laser drilling and via-filling electroplating processes are used to fabricate interlayer blind and buried via interconnect units to achieve electrical connection between the power layer, signal layer and grounding heat dissipation layer; Precision etching is performed on the surface of the substrate to form bonding pads for the chip and driver integrated circuit; The flip-chip LED and the embedded driver IC are placed on the corresponding electrodes on the top layer of the substrate; An ultra-thin encapsulation adhesive layer adapted to the thickness of the driver integrated circuit is formed on the substrate surface using a molding and pressing process; The packaged substrate is cut to obtain individual device units; The individual device units are sequentially subjected to electrical illumination detection and optical sorting to complete the fabrication of the multi-layer circuit structure.

[0005] In some embodiments, the step of stacking a preset number of substrates and layering a power layer, a signal layer, and a grounding and heat dissipation layer inside the substrate includes: preparing each substrate layer using an ultra-thin resin-based material, providing an ultra-thin low-dielectric dielectric layer for isolation between adjacent substrate layers, and independently arranging the power layer, signal layer, and grounding and heat dissipation layer in different substrate layers, wherein the grounding and heat dissipation layer adopts a large copper foil structure.

[0006] In some embodiments, the process of using laser drilling and via-filling electroplating to prepare interlayer blind and buried via interconnect units to achieve electrical connection between power layer, signal layer and ground heat dissipation layer includes: forming blind and buried vias through corresponding dielectric layers on the laminated substrate by laser processing, and then performing via-filling electroplating on the blind and buried vias to form a continuous conductive layer on the via wall and inside the via, thereby achieving electrical connection between adjacent layers and across layers.

[0007] In some embodiments, the process of performing precision line etching on the substrate surface to form bonding pads for the chip and the driver integrated circuit includes: coating the substrate surface with photoresist, forming a line pattern by exposure and development, and then etching and removing the photoresist from the exposed substrate to form independent bonding pads on the top layer of the substrate corresponding to the flip-chip LED and the embedded driver integrated circuit, respectively.

[0008] In some embodiments, the step of placing the flip-chip and the embedded driver integrated circuit on the corresponding electrode on the top layer of the substrate includes: coating the upper surface and all non-light-emitting sidewalls of the flip-chip with a high-reflectivity light-shielding material, curing it to form a high-reflectivity light-shielding layer, and retaining only the light-emitting surface on the back of the chip's substrate; placing the processed flip-chip and the embedded driver integrated circuit on the corresponding bonding pads on the top layer of the substrate, and completing the electrical and mechanical connection through a flip-chip bonding process.

[0009] In some embodiments, the process of forming an ultra-thin encapsulating adhesive layer adapted to the thickness of the driver integrated circuit on the substrate surface using a molding and pressing process includes: covering the substrate surface and the bonded chip and driver integrated circuit with encapsulating adhesive material, and using a molding and pressing process to completely encapsulate the chip and driver integrated circuit with encapsulating adhesive material to form a planarized ultra-thin encapsulating adhesive layer with a thickness adapted to the thickness of the embedded driver integrated circuit.

[0010] In some embodiments, the step of cutting the packaged substrate to obtain a single device unit includes: cutting the packaged substrate into sections according to a preset device size using a laser cutting process, removing excess portions from the edges of the substrate, and simultaneously cutting to form a half-hole solder pad at the bottom of the device; the half-hole solder pad can improve the soldering firmness of the device mounting and enable the device to support bidirectional lateral mounting in both left and right directions, ultimately obtaining multiple independent cuboid ultrathin single device units.

[0011] In some embodiments, the step of sequentially performing electrical illumination detection and spectral sorting on individual device units to complete the fabrication of a multi-layer circuit structure includes: applying a rated operating voltage to each individual device unit, detecting the illumination status and electrical parameters of the device, and screening out device units with qualified electrical performance; then detecting the luminous parameters of the qualified device units and performing spectral sorting according to the luminous color and brightness level.

[0012] In some embodiments, the individual device unit is a five-sided light-emitting structure. After being flatly attached to the application substrate, the light-emitting surface on the back of the chip substrate faces the side, exhibiting the optical characteristic of the highest lateral light-emitting intensity, while the light-emitting intensity of the other surfaces is relatively low.

[0013] In some embodiments, the method further includes: embedding an embedded driver integrated circuit in the middle layer of the substrate before stacking the substrates with a preset number of layers, and then stacking the substrates and preparing interlayer interconnects.

[0014] In a second aspect, this application provides a multilayer circuit structure, which is prepared based on the method provided in the first aspect, including a multilayer resin-based circuit substrate, a flip-chip light-emitting diode, an embedded driver integrated circuit, a high-reflection light-shielding layer, and an ultra-thin encapsulating adhesive layer. The multilayer resin-based circuit board has a power layer, a signal layer and a grounding and heat dissipation layer. The multilayer resin-based circuit board has interlayer blind and buried via interconnection units to realize the electrical connection between the layers. Flip-chip LEDs and embedded driver integrated circuits are mounted and soldered on the top layer of a multilayer resin-based circuit board; a high-reflectivity light-shielding layer covers the upper surface and all non-light-emitting sidewalls of the flip-chip LEDs, leaving only the light-emitting surface on the back of the chip's substrate. An ultra-thin encapsulating adhesive layer covers the top layer of a multilayer resin-based circuit board, a flip-chip light-emitting diode, and an embedded driver integrated circuit. The bottom of the multilayer circuit structure is provided with a half-hole solder pad. The overall structure is a five-sided light-emitting structure. After being flatly attached to the application substrate, the light-emitting surface on the back of the chip substrate faces to the side, exhibiting the optical characteristics of the highest lateral light-emitting intensity.

[0015] This application achieves physical isolation between power and signals by layering power, signal, and ground heat dissipation layers, effectively reducing signal crosstalk. The ground heat dissipation layer also improves the overall heat dissipation performance of the device. Interlayer electrical connections are achieved using interlayer blind and buried via interconnects, significantly reducing the overall thickness of the multilayer circuit structure and increasing device integration. Flip-chip bonding is used to connect the chip and driver IC to the substrate, eliminating the need for gold wire interconnects, shortening electrical paths, and improving device response speed and reliability. An ultra-thin encapsulation layer adapted to the thickness of the driver IC is formed through molding and pressing, eliminating traditional support structures and achieving extreme device thinning. The overall fabrication process is coherent, with simplified steps, improving product yield and making it suitable for large-scale mass production.

[0016] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and do not limit this application. Attached Figure Description

[0017] To more clearly illustrate the technical solutions of the embodiments of this application, the drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0018] Figure 1 This is a schematic flowchart illustrating the steps of a method for fabricating a multilayer circuit structure according to an embodiment of this application; Figure 2 This is a schematic diagram of a multilayer circuit structure provided in one embodiment of this application; Figure 3 This is a schematic diagram of another multilayer circuit structure provided in one embodiment of this application; Figure 4 This is an exploded view of a multi-layer circuit structure provided in one embodiment of this application; Figure 5 This is a pin diagram of a multilayer circuit structure provided in one embodiment of this application; Figure 6 This is a pin diagram of another multilayer circuit structure provided in one embodiment of this application; Figure 7 This is a schematic block diagram of a multilayer circuit structure fabrication system provided in one embodiment of this application; Figure 8 This is a schematic block diagram of the structure of a computer device provided in an embodiment of this application.

[0019] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and do not limit this application. Detailed Implementation

[0020] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0021] The flowchart shown in the attached diagram is for illustrative purposes only and does not necessarily include all content and operations / steps, nor does it necessarily have to be performed in the order described. For example, some operations / steps can be broken down, combined, or partially merged, so the actual execution order may change depending on the actual situation.

[0022] It should be understood that, in order to clearly describe the technical solutions of the embodiments of the present invention, the terms "first" and "second" are used in the embodiments of the present invention to distinguish identical or similar items with essentially the same function and effect. Those skilled in the art will understand that the terms "first" and "second" do not limit the quantity or execution order, and the terms "first" and "second" are not necessarily different.

[0023] It should be understood that the terminology used in this specification is for the purpose of describing particular embodiments only and is not intended to limit the scope of the application. As used in this specification and the appended claims, the singular forms “a,” “an,” and “the” are intended to include the plural forms unless the context clearly indicates otherwise.

[0024] It should also be understood that the term “and / or” as used in this application specification and the appended claims means any combination of one or more of the associated listed items and all possible combinations, and includes such combinations.

[0025] Existing multilayer circuit structure fabrication methods cannot simultaneously meet the requirements of ultra-thinness, high integration, low signal crosstalk, and high reliability. Traditional side-emitting devices rely on brackets, light guide plates, and secondary optical bending structures, resulting in a large overall thickness that is unsuitable for ultra-thin applications such as narrow bezels and stealth mounting. Driver integrated circuits often employ discrete external mounting methods, leading to long electrical connection paths, slow response speeds, and susceptibility to connection failures under complex environments such as high and low temperature cycling and vibration. Ineffective isolation of circuit layers results in severe signal crosstalk, limiting the realization of high-density array arrangements. Inadequate heat dissipation path design leads to high device operating temperatures and insufficient long-term reliability. Existing fabrication processes are complex, have low yields, and are difficult to achieve large-scale mass production. Currently, there is no multilayer circuit structure fabrication solution that can simultaneously solve all of the above problems.

[0026] Please refer to Figure 1 This application provides a method for fabricating a multilayer circuit structure, applicable to the fabrication of, for example, Figures 2 to 6 The multi-layer circuit structure shown.

[0027] Please refer to Figure 2 , Figure 3 and Figure 4 The multilayer circuit structure prepared in this application embodiment uses a multilayer resin-based circuit substrate 10 as the bottom support substrate. A flip-chip light-emitting diode chip 20 and an embedded driver integrated circuit 30 are disposed on the top surface of the substrate. A high-reflectivity light-shielding layer 40 is disposed corresponding to the flip-chip light-emitting diode chip 20. The outermost layer of the device is integrally molded and encapsulated by an ultra-thin encapsulating adhesive layer 50.

[0028] The multilayer resin-based circuit board 10 serves as the substrate supporting the device and is located at the bottom layer of the structure. It adopts a layered and independently arranged structure, with a power layer, a signal layer, and a grounding and heat dissipation layer respectively. The functional layers are isolated from each other by an insulating dielectric material. The multilayer resin-based circuit board 10 has interlayer blind and buried via interconnection units to realize electrical conduction and signal transmission between the power layer, the signal layer, and the grounding and heat dissipation layer.

[0029] The flip-chip LED 20 and the embedded driver integrated circuit 30 are both disposed on the top surface of the multilayer resin-based circuit substrate 10, at the same horizontal level, and are electrically connected and mechanically fixed by independent bonding pads respectively provided on the top layer of the substrate. The high-reflectivity light-shielding layer 40 is arranged around each flip-chip LED 20, covering the upper surface of the chip and all non-light-emitting sidewalls, leaving only the light-emitting surface on the back of the chip substrate, which is used to constrain the light-emitting direction, improve light utilization, and reduce stray light.

[0030] The ultra-thin encapsulating adhesive layer 50 is integrally molded on the top layer of the multilayer resin-based circuit board 10 through a molding process. It is located on the outermost layer of the structure and completely covers the flip-chip light-emitting diode chip 20, the embedded driver integrated circuit 30, and the high-reflection light-shielding layer 40, forming a planar overall encapsulation structure. The thickness of the ultra-thin encapsulating adhesive layer 50 is adapted to the thickness of the embedded driver integrated circuit 30, so as to achieve the encapsulation protection of internal components while ensuring the overall ultra-thinness of the device.

[0031] like Figure 4 As shown, the top layer of the multilayer resin-based circuit board 10 is a surface circuit pad layer 60. The surface circuit pad layer 60 is a copper-based conductive circuit layer prepared by a patterned etching process. It is sequentially stacked and laminated with the power layer, signal layer, and grounding heat dissipation layer inside the substrate through an insulating dielectric material, together forming the multilayer circuit board body with independent layering.

[0032] The upper surface of the surface circuit pad layer 60 has an independent chip bonding pad for each flip-chip LED chip 20, and an independent drive pad array for the embedded driver integrated circuit 30. Each pad surface is treated with an immersion nickel-gold process to form a low-contact-resistance, oxidation-resistant soldering surface, ensuring the reliability of the soldering between the flip-chip and the drive circuit. The pads are horizontally electrically interconnected through patterned traces on the same layer, forming independent signal paths and power supply routes. Isolation gaps are reserved between different functional lines to effectively reduce crosstalk between signals on the same layer.

[0033] The surface circuit pad layer 60 is provided with a recessed mounting groove corresponding to the placement position of the embedded driver integrated circuit 30. The depth of the mounting groove matches the thickness of the embedded driver integrated circuit 30, so that after the embedded driver integrated circuit 30 is mounted and fixed, its top surface is at the same level as the top surface of the flip-chip light-emitting diode chip 20. This ensures the flatness of the subsequent high-reflectivity light-shielding layer 40 and ultra-thin encapsulation adhesive layer 50, and helps to achieve an overall ultra-thin design of the device.

[0034] The bottom of the surface circuit pad layer 60 has upper conductive terminals of interlayer blind and buried via interconnect units. Each conductive terminal extends vertically downward and is electrically connected to the power layer, signal layer, and ground heat dissipation layer inside the multilayer resin-based circuit board 10, forming a vertical interconnection path. This structure introduces the electrical connection of surface components into the inner layer of the substrate, significantly shortening the electrical transmission path and improving the signal response speed. At the same time, the ground heat dissipation layer enables the rapid downward conduction of heat from the components, optimizing the overall heat dissipation performance and long-term service reliability of the device.

[0035] Please refer to Figure 5 and Figure 6 The multi-layer circuit structure features a half-hole solder pad at the bottom, arranged along both edges of the device's length. The device's pin definitions include a signal input pin (DI), a ground pin (GND), a power supply pin (VDD), and a signal output pin (DO). The power supply pin is configured with a multi-parallel structure to improve power supply stability. This half-hole solder pad structure increases the solder wetting area, improving the solder joint strength after device mounting. Furthermore, it allows for bidirectional side mounting (left-hand and right-hand), adapting to different lamp board wiring directions and light emission directions.

[0036] The multi-layer circuit structure is a five-sided light-emitting structure. When the device is flatly attached to the surface of the application substrate, the light-emitting surface on the back of the chip substrate faces to the side, thus exhibiting the optical characteristics of the highest side light-emitting intensity. The light-emitting intensity of the other surfaces is relatively low, which can directly meet the application requirements of side light emission without the need for additional light guide plates, bending brackets, or other structures. The overall thickness of the device is ultra-thin.

[0037] The provided method for fabricating a multilayer circuit structure includes steps S101 to S107, which are detailed below: Step S101. Stack the substrates with a preset number of layers, and arrange the power layer, signal layer and ground heat dissipation layer in layers inside the substrates.

[0038] Specifically, by stacking substrates with a preset number of layers, power layers, signal layers, and grounding and heat dissipation layers are arranged in layers inside the substrates.

[0039] In practice, the total number of substrate layers is first determined based on the electrical performance indicators and overall thickness requirements of the device, and the function of each layer is defined. Single-layer substrates corresponding to the respective functions are then fabricated, and the multi-layer substrates are laminated into a single structure using a lamination process. During the lamination and layout process, the power layer, signal layer, and grounding / heat dissipation layer are placed in independent layers to avoid electromagnetic crosstalk caused by placing lines with different functions on the same layer. The grounding / heat dissipation layer uses a large-area conductive structure, serving both as a grounding reference plane to improve signal transmission stability and as a continuous heat dissipation path to quickly dissipate the heat generated by the chip and driver circuitry.

[0040] Step S102. Use laser drilling and via-filling electroplating processes to fabricate interlayer blind and buried via interconnect units to achieve electrical connection between the power layer, signal layer and grounding heat dissipation layer.

[0041] Specifically, interlayer blind and buried via interconnect units are fabricated using laser drilling and via-filling electroplating processes to achieve electrical connections between the power layer, signal layer, and grounding and heat dissipation layer.

[0042] In practice, on the stacked substrate, blind vias and buried vias are formed by laser drilling according to the pre-designed interconnection point layout. Blind vias are used to realize electrical connections between the substrate surface layer and adjacent inner layers, while buried vias are used to realize electrical connections between two or more inner layers. The buried vias do not penetrate the upper and lower surfaces of the substrate.

[0043] After drilling, the hole walls are cleaned, descaling is removed, and activation is performed. Then, conductive metal is deposited on the hole walls and inside the hole cavity through a hole-filling electroplating process to form a continuous and dense conductive layer. This enables reliable electrical connection between the power layer, signal layer, and grounding heat dissipation layer in the corresponding layers, thus completing the fabrication of the interlayer interconnection structure.

[0044] Step S103. Perform precision line etching on the surface of the substrate to form bonding pads for the chip and driver integrated circuit.

[0045] Specifically, the bonding pads for the chip and driver integrated circuit are formed by precision etching of the substrate surface.

[0046] In practice, photoresist material is uniformly coated on the top surface of the substrate after the interlayer interconnection is completed; the photoresist is exposed through a mask with a preset line and pad pattern, and then the photoresist in the corresponding area is removed by a development process to expose the copper foil surface below, forming the pattern prototype of the line and pad.

[0047] The exposed copper foil is then etched away using an etching process, leaving the lines and pads covered by photoresist. After etching, the remaining photoresist is removed, and after cleaning and drying, independent bonding pads corresponding to the flip-chip LED and the embedded driver integrated circuit are formed on the top layer of the substrate, as well as surface lines connecting each pad.

[0048] Step S104. Place the flip-chip LED and the embedded driver integrated circuit on the corresponding electrodes on the top layer of the substrate.

[0049] Specifically, this is achieved by placing flip-chip LEDs and embedded driver integrated circuits on corresponding electrodes on the top layer of the substrate.

[0050] In practice, solder material is first applied to the bonding pads on the top layer of the substrate. The flip-chip LED and the embedded driver IC are then placed, aligned with their respective bonding pads, ensuring the electrode bumps of the chip and circuit are aligned with the substrate pads. The solder is then melted and solidified through a soldering process, achieving electrical connection and mechanical fixation between the chip, driver IC, and substrate pads, thus completing the component mounting.

[0051] Step S105. An ultra-thin encapsulation adhesive layer adapted to the thickness of the driver integrated circuit is formed on the substrate surface using a molding and pressing process.

[0052] Specifically, an ultra-thin encapsulation adhesive layer adapted to the thickness of the driver integrated circuit is formed on the substrate surface by using a molding and pressing process.

[0053] In practice, the entire substrate with the components mounted is placed into a molding die, and encapsulating adhesive material is injected into the die cavity. Under preset temperature and pressure conditions, the substrate is pressed and molded to allow the encapsulating adhesive material to flow fully and completely fill all gaps between the chip, the driving circuit and the substrate surface, covering all components and surface circuitry.

[0054] During the molding process, the filling amount of encapsulating adhesive and the height of the mold cavity are precisely controlled to keep the upper surface of the encapsulating adhesive layer flat after molding, and the total thickness of the encapsulating adhesive layer is adapted to the thickness of the embedded driver integrated circuit. Under the premise of completely covering the components, the overall thickness is reduced as much as possible to achieve ultra-thin packaging.

[0055] After lamination, a stepped heating curing process is performed to fully cross-link and cure the encapsulating adhesive, forming a stable solid encapsulation structure. After curing, the material is demolded to obtain an ultra-thin encapsulating adhesive layer with a smooth surface and uniform thickness. This encapsulating adhesive layer can provide physical protection, moisture and corrosion protection for internal components, and at the same time serve as a light-emitting medium layer to ensure normal light emission.

[0056] Step S106. Cut the packaged substrate to obtain individual device units.

[0057] Specifically, individual device units are obtained by cutting the packaged substrate.

[0058] In practice, based on the pre-designed size parameters of individual devices, an array-style cutting path for the entire substrate is planned. Laser cutting is used to slice the entire substrate along the cutting path, removing excess material from the substrate edges. During the cutting process, cutting is performed along the center of the pads at the bottom of the devices, creating a half-hole solder pad structure at the bottom edge of each device. After cutting, the entire substrate is separated into multiple independent cuboid ultra-thin device units.

[0059] During device mounting, the semi-hole solder pad structure allows solder to wet the inner wall and surface of the semi-hole, significantly increasing the solder adhesion area and bonding force compared to ordinary planar pads. This can significantly improve the mechanical strength and electrical connection reliability of the device after mounting, reduce the risk of failures such as cold solder joints and detachment, and improve the service stability of the device under vibration and high / low temperature cycling environments.

[0060] Meanwhile, since the device has half-hole pads on both the left and right sides and the pins are designed with symmetrical adaptation, the device can be mounted on the left side with the light-emitting surface facing left or on the right side with the light-emitting surface facing right. It supports bidirectional side mounting and can adapt to different lamp board wiring directions and light emission direction requirements, improving the application flexibility and versatility of the device.

[0061] Step S107. Perform electrical illumination detection and optical sorting on each individual device unit in sequence to complete the fabrication of the multilayer circuit structure.

[0062] Specifically, the fabrication of a multi-layer circuit structure is achieved by sequentially performing electrical illumination detection and optical sorting on individual device units.

[0063] In practice, the electrical lighting test is first performed: a single device is placed in a test fixture, ensuring that the test probes of the fixture make reliable contact with the half-hole pads of the device; the rated operating voltage and operating signal are applied to the device to test whether the device can light up normally, while testing the device's forward operating current, reverse leakage current, drive circuit function and other electrical parameters; the test results are compared with the preset qualification standards, and qualified devices that meet all electrical parameters are selected, while electrical defects such as open circuit, short circuit, and excessive leakage current are eliminated.

[0064] Next, the electrically qualified devices are sorted by light: the devices are connected to the optical testing station, and after the devices are lit, the light emission parameters such as the brightness, dominant wavelength, color coordinates, and color rendering index of the devices are detected by the optical testing equipment; according to the preset grading standards, the devices are classified and sorted according to the brightness level and color range to ensure the consistency of optical performance of devices used in the same batch and to avoid problems such as brightness difference and color difference.

[0065] After completing electrical testing and optical sorting, the entire fabrication process of the multilayer circuit structure is completed, resulting in finished devices that can be directly shipped for application.

[0066] In some embodiments, the step of stacking a preset number of substrates and layering a power layer, a signal layer, and a grounding and heat dissipation layer inside the substrate includes: preparing each substrate layer using an ultra-thin resin-based material, providing an ultra-thin low-dielectric dielectric layer for isolation between adjacent substrate layers, and independently arranging the power layer, signal layer, and grounding and heat dissipation layer in different substrate layers, wherein the grounding and heat dissipation layer adopts a large copper foil structure.

[0067] In practice, each substrate layer uses an ultra-thin resin-based fiberglass cloth reinforcement material to reduce the overall thickness of the substrate; between adjacent conductive circuit layers, an ultra-thin dielectric material with a low dielectric constant is used for isolation. This dielectric material has a low dielectric constant and dielectric loss, which can reduce loss and crosstalk during signal transmission and improve the transmission quality of high-speed signals.

[0068] The power layer, signal layer, and grounding heat dissipation layer are arranged in independent substrate layers. The circuit layers with different functions are completely isolated from each other by dielectric layers to avoid electromagnetic coupling interference caused by the same layer. The grounding heat dissipation layer adopts a large copper foil structure covering most of the substrate area. It can serve as a complete grounding reference plane to provide a stable reference potential for the signal layer and significantly reduce signal crosstalk. It can also form a continuous large-area heat dissipation path to quickly diffuse and dissipate the heat generated by the chip and driver circuit, thereby improving the heat dissipation capacity and long-term reliability of the device.

[0069] In some embodiments, the process of using laser drilling and via-filling electroplating to prepare interlayer blind and buried via interconnect units to achieve electrical connection between power layer, signal layer and ground heat dissipation layer includes: forming blind and buried vias through corresponding dielectric layers on the laminated substrate by laser processing, and then performing via-filling electroplating on the blind and buried vias to form a continuous conductive layer on the via wall and inside the via, thereby achieving electrical connection between adjacent layers and across layers.

[0070] In practice, the processing steps for blind vias and buried vias are distinguished according to the design requirements of interlayer interconnection: For buried vias, before the corresponding inner layer substrate is stacked, the hole position is first processed on a single or multiple inner layer substrate. After the inner layer is stacked and electroplated, the outer layer substrate is then stacked, so that the buried via is completely located inside the substrate and is not exposed on the substrate surface; For blind vias, after the substrate is stacked as a whole, laser drilling is performed from the surface of the substrate, and the hole depth extends to the target inner layer without penetrating the entire substrate.

[0071] Laser drilling utilizes ultraviolet laser processing technology, allowing for precise control of hole diameter and depth. The resulting holes exhibit excellent wall perpendicularity and minimal thermal damage, making it suitable for high-density, small-diameter blind and buried via machining. After drilling, the holes undergo pretreatment processes such as desmearing, cleaning, and activation. Then, copper metal is deposited on the hole walls through electroplating, gradually filling the entire cavity to form a continuous and dense conductive pillar structure. After the electroplating is completed, the substrate surface is ground smooth to remove excess electroplated copper, ensuring a flat substrate surface.

[0072] By combining blind vias and buried vias, electrical connections between adjacent layers and across multiple layers can be achieved without using through-holes that penetrate the entire substrate. This improves the utilization of wiring space on the substrate surface and reduces signal integrity issues caused by through-holes, thus meeting the wiring requirements of high-density integration.

[0073] In some embodiments, the precise etching of the substrate surface to form bonding pads for the chip and the driver integrated circuit includes: coating the substrate surface with photoresist, forming a circuit pattern by exposure and development, and then etching and removing the photoresist from the exposed substrate to form independent bonding pads on the top layer of the substrate corresponding to the flip-chip LED and the embedded driver integrated circuit, respectively.

[0074] In practice, the copper foil surface on the top layer of the substrate is first cleaned to remove oil, oxides and impurities to ensure the adhesion of the photoresist. A layer of photoresist is uniformly coated on the copper foil surface using spin coating or roll coating processes, and the thickness of the photoresist is controlled to be uniform.

[0075] A photomask with a preset circuit and pad pattern is placed in front of the substrate. The photoresist is exposed using an ultraviolet exposure device, causing the photoresist in the exposed area to cross-link and solidify. After exposure, the substrate is immersed in a developer, and the uncured photoresist is dissolved and removed, exposing the copper foil surface underneath, forming a circuit and pad pattern that is consistent with the photomask pattern.

[0076] The developed substrate is fed into an etching machine, where an etching solution is used to etch the exposed copper foil, completely removing the copper foil without photoresist protection while retaining the lines and pad structures covered by photoresist. During etching, the etching time and etching solution parameters are precisely controlled to avoid over-etching that could cause line width deviations. After etching, the remaining photoresist is removed using a photoresist remover, and the substrate is then cleaned and dried. Finally, high-precision independent bonding pads are formed on the top layer of the substrate, corresponding to the electrodes of the flip-chip LED chip and the pins of the embedded driver integrated circuit. The pad position and dimensional accuracy meet the requirements of flip-chip mounting.

[0077] In some embodiments, the step of placing the flip-chip and the embedded driver integrated circuit on the corresponding electrode on the top layer of the substrate includes: coating the upper surface and all non-light-emitting sidewalls of the flip-chip with a high-reflectivity light-shielding material, curing it to form a high-reflectivity light-shielding layer, and retaining only the light-emitting surface on the back of the chip's substrate; placing the processed flip-chip and the embedded driver integrated circuit on the corresponding bonding pads on the top layer of the substrate, and completing the electrical and mechanical connection through a flip-chip bonding process.

[0078] In practice, the flip-chip LED is first pre-treated: a high-reflectivity light-shielding material is uniformly coated onto the upper surface of the chip and the four non-light-emitting sidewalls using a spraying or dispensing process. This material has high visible light reflectivity and light-shielding performance. During the coating process, the back of the chip's substrate and the light-emitting surface are precisely shielded to ensure that this area is not covered by the light-shielding material. After coating, the material is heated and cured to form a high-reflectivity light-shielding layer covering the upper surface of the chip and the non-light-emitting sidewalls, leaving only the back of the substrate as the sole primary light-emitting surface. This ensures that the light emitted by the chip only exits from the substrate direction, while light from other directions is reflected by the reflective layer and then exits from the light-emitting surface. This improves light utilization and constrains the light emission direction, ensuring the device's lateral light emission characteristics.

[0079] After chip pretreatment, solder paste is printed or applied to the corresponding bonding pads on the top layer of the substrate. Using high-precision mounting equipment, the pretreated flip-chip LEDs and embedded driver integrated circuits are aligned with their corresponding pad positions and mounted, ensuring precise alignment between the chip's electrode bumps and the substrate pads. After mounting, the solder paste is melted using a flip-chip soldering process, and after cooling and solidification, a reliable electrical connection and mechanical fixation between the chip, driver integrated circuit, and substrate is achieved. Various feasible flip-chip soldering processes can be used, such as hot air reflow soldering, laser soldering, and eutectic bonding, selected according to actual production needs and device parameters, all of which can achieve stable flip-chip interconnection.

[0080] In some embodiments, the process of forming an ultra-thin encapsulating adhesive layer adapted to the thickness of the driver integrated circuit on the substrate surface using a molding and pressing process includes: covering the substrate surface and the bonded chip and driver integrated circuit with encapsulating adhesive material, and using a molding and pressing process to completely encapsulate the chip and driver integrated circuit with encapsulating adhesive material to form a planarized ultra-thin encapsulating adhesive layer with a thickness adapted to the thickness of the embedded driver integrated circuit.

[0081] In practice, epoxy encapsulating adhesive with high light transmittance and high weather resistance is selected. The entire substrate with the chip and driver circuit mounted is placed into the lower cavity of the molding mold. After the mold is closed, the molten encapsulating adhesive is injected into the mold cavity through the injection molding process. Under the preset molding temperature and molding pressure, the encapsulating adhesive material is allowed to flow fully, completely filling all gaps between the chip, driver circuit and substrate surface, and covering all components and surface circuits.

[0082] During the molding process, the filling amount of encapsulating adhesive and the height of the mold cavity are precisely controlled to keep the upper surface of the encapsulating adhesive layer flat after molding, and the total thickness of the encapsulating adhesive layer is adapted to the thickness of the embedded driver integrated circuit. Under the premise of completely covering the components, the overall thickness is reduced as much as possible to achieve ultra-thin packaging.

[0083] After lamination, a stepped heating curing process is performed to fully cross-link and cure the encapsulating adhesive, forming a stable solid encapsulation structure. After curing, the material is demolded to obtain an ultra-thin encapsulating adhesive layer with a smooth surface and uniform thickness. This encapsulating adhesive layer can provide physical protection, moisture and corrosion protection for internal components, and at the same time serve as a light-emitting medium layer to ensure normal light emission.

[0084] In some embodiments, the step of cutting the packaged substrate to obtain a single device unit includes: cutting the packaged substrate into sections according to a preset device size using a laser cutting process, removing excess portions from the edges of the substrate, and simultaneously cutting to form a half-hole solder pad at the bottom of the device; the half-hole solder pad can improve the soldering firmness of the device mounting and enable the device to support bidirectional lateral mounting in both left and right directions, ultimately obtaining multiple independent cuboid ultrathin single device units.

[0085] In practice, firstly, based on the length and width of a single device, an array of cutting paths is planned on the entire substrate. The cutting paths are set along the process edges between the devices. For the bottom pad position, the cutting path passes through the center of the pad, so that each device retains a half-hole pad structure after cutting, i.e., a half-hole solder pad.

[0086] The ultraviolet laser cutting equipment is used to cut along a planned cutting path. Laser cutting has high precision and a small heat-affected zone, which can ensure the dimensional accuracy of the cut device, while avoiding damage to the internal chip and circuitry caused by cutting thermal stress. During the cutting process, excess process edges of the substrate are removed and half-hole pads are formed simultaneously. After the entire board is cut, multiple independent cuboid ultrathin device units are obtained.

[0087] During device mounting, the semi-hole solder pad structure allows solder to wet the inner wall and surface of the semi-hole, significantly increasing the solder adhesion area and bonding force compared to ordinary planar pads. This can significantly improve the mechanical strength and electrical connection reliability of the device after mounting, reduce the risk of failures such as cold solder joints and detachment, and improve the service stability of the device under vibration and high / low temperature cycling environments.

[0088] Meanwhile, since the device has half-hole pads on both the left and right sides and the pins are designed with symmetrical adaptation, the device can be mounted on the left side with the light-emitting surface facing left or on the right side with the light-emitting surface facing right. It supports bidirectional side mounting and can adapt to different lamp board wiring directions and light emission direction requirements, improving the application flexibility and versatility of the device.

[0089] Example 7: Refinement of Detection and Sorting Process In some embodiments, the step of sequentially performing electrical illumination detection and spectral sorting on individual device units to complete the fabrication of a multi-layer circuit structure includes: applying a rated operating voltage to each individual device unit, detecting the illumination status and electrical parameters of the device, and screening out device units with qualified electrical performance; then detecting the luminous parameters of the qualified device units and performing spectral sorting according to the luminous color and brightness level.

[0090] In practice, the electrical lighting test is first performed: a single device is placed in a test fixture, ensuring that the test probes of the fixture make reliable contact with the half-hole pads of the device; the rated operating voltage and operating signal are applied to the device to test whether the device can light up normally, while testing the device's forward operating current, reverse leakage current, drive circuit function and other electrical parameters; the test results are compared with the preset qualification standards, and qualified devices that meet all electrical parameters are selected, while electrical defects such as open circuit, short circuit, and excessive leakage current are eliminated.

[0091] Next, the electrically qualified devices are sorted by light: the devices are connected to the optical testing station, and after the devices are lit, the light emission parameters such as the brightness, dominant wavelength, color coordinates, and color rendering index of the devices are detected by the optical testing equipment; according to the preset grading standards, the devices are classified and sorted according to the brightness level and color range, and devices with the same parameters are grouped into the same grade to ensure the consistency of optical performance of devices used in the same batch and avoid problems such as brightness difference and color difference.

[0092] After completing electrical testing and optical sorting, the entire fabrication process of the multilayer circuit structure is completed, resulting in finished devices that can be directly shipped for application.

[0093] In some embodiments, the individual device unit is a five-sided light-emitting structure. After being flatly attached to the application substrate, the light-emitting surface on the back of the chip substrate faces the side, exhibiting the optical characteristic of the highest side light-emitting intensity, while the light-emitting intensity of the other surfaces is relatively low.

[0094] In practice, since the back of the substrate of the flip-chip LED is the main light-emitting surface and the rest of the chip is covered by a high-reflectivity light-shielding layer, most of the light emitted by the chip is emitted from the back of the substrate. After the device is packaged, the light-emitting surface of the back of the substrate corresponds to the side of the device. When the device is mounted flat on the surface of the application substrate, the bottom surface of the device is attached to the substrate and the main light-emitting surface faces the side of the device. Therefore, the device exhibits the optical characteristics with the highest lateral light emission intensity.

[0095] Meanwhile, since the encapsulating adhesive layer is a light-transmitting structure, a small amount of light will also be emitted from the other four surfaces of the device, so the device as a whole is a five-sided light-emitting structure; however, the light intensity of the other surfaces is much lower than that of the main light-emitting side, and the light intensity of the main light-emitting direction accounts for the highest proportion, which can meet the application requirements of side light emission.

[0096] This optical characteristic eliminates the need for additional secondary optical structures such as light guide plates, reflective structures, and bending brackets. The device can achieve side-emitting effect simply by being flat-mounted, significantly reducing the structural thickness of the application and making it suitable for various application scenarios with stringent thickness requirements, such as narrow bezels, ultra-thin designs, and invisible installations.

[0097] Example 9: Embedded Driver IC Solution In some embodiments, the method further includes: embedding an embedded driver integrated circuit in the middle layer of the substrate before stacking the substrates with a preset number of layers, and then stacking the substrates and preparing interlayer interconnects.

[0098] In practice, the driver integrated circuit is integrated using an in-substrate embedding process: First, the lower layer of the substrate is prepared, and a receiving cavity is opened at the corresponding position of the lower substrate. The embedded driver integrated circuit is placed in the receiving cavity. Then, the upper dielectric layer and circuit layer are stacked so that the driver integrated circuit is completely embedded in the middle layer of the substrate and is not exposed on the substrate surface.

[0099] After the substrate is laminated, an interconnect structure is fabricated using an interlayer blind via process, which enables the embedded driver integrated circuit to be electrically connected to the circuits and pads of the upper and lower layers; only flip-chip LEDs are mounted on the surface of the substrate, and the driver circuit is completely hidden inside the substrate.

[0100] This embedded solution can further reduce the overall package thickness of the device and improve integration. At the same time, the driving circuit is protected by the substrate material, which makes it more resistant to vibration and environmental corrosion, and further improves the reliability of the device. In addition, the driving circuit is embedded in the substrate, which can reduce electromagnetic radiation on the surface, reduce signal interference, and improve the electromagnetic compatibility performance of the device.

[0101] Please see Figure 7 As shown, Figure 7This is a schematic diagram of the structure of the multilayer circuit structure fabrication system 200 provided in the embodiments of this application. The multilayer circuit structure fabrication system 200 is used to perform the steps of the multilayer circuit structure fabrication method shown in the above embodiments. The multilayer circuit structure fabrication system 200 can be a single server or a server cluster, or it can be a terminal, such as a handheld terminal, a laptop computer, a wearable device, or a robot.

[0102] like Figure 7 As shown, the fabrication system 200 for multilayer circuit structures includes: The substrate stacking unit 201 is used to stack a substrate with a preset number of layers, and to arrange a power layer, a signal layer and a ground heat dissipation layer in layers inside the substrate. Electrical connection unit 202 is used to prepare interlayer blind and buried via interconnection units using laser drilling and via-filling electroplating processes to realize electrical connection between power layer, signal layer and ground heat dissipation layer; The line etching unit 203 is used to perform precision line etching on the surface of the substrate to form bonding pads for the chip and the driver integrated circuit. The light-emitting embedding unit 204 is used to place the flip-chip light-emitting diode and the embedded driver integrated circuit on the corresponding electrode on the top layer of the substrate; The ultra-thin packaging unit 205 is used to form an ultra-thin packaging adhesive layer adapted to the thickness of the driving integrated circuit on the surface of the substrate using a molding and pressing process. The substrate cutting unit 206 is used to cut the packaged substrate to obtain a single device unit; The detection and sorting unit 207 is used to sequentially perform electrical illumination detection and optical sorting on a single device unit to complete the fabrication of a multi-layer circuit structure.

[0103] In some embodiments, the step of stacking a preset number of substrates and layering a power layer, a signal layer, and a grounding and heat dissipation layer inside the substrate includes: preparing each substrate layer using an ultra-thin resin-based material, providing an ultra-thin low-dielectric dielectric layer for isolation between adjacent substrate layers, and independently arranging the power layer, signal layer, and grounding and heat dissipation layer in different substrate layers, wherein the grounding and heat dissipation layer adopts a large copper foil structure.

[0104] In some embodiments, the process of using laser drilling and via-filling electroplating to prepare interlayer blind and buried via interconnect units to achieve electrical connection between power layer, signal layer and ground heat dissipation layer includes: forming blind and buried vias through corresponding dielectric layers on the laminated substrate by laser processing, and then performing via-filling electroplating on the blind and buried vias to form a continuous conductive layer on the via wall and inside the via, thereby achieving electrical connection between adjacent layers and across layers.

[0105] In some embodiments, the precise etching of the substrate surface to form bonding pads for the chip and the driver integrated circuit includes: coating the substrate surface with photoresist, forming a circuit pattern by exposure and development, and then etching and removing the photoresist from the exposed substrate to form independent bonding pads on the top layer of the substrate corresponding to the flip-chip LED and the embedded driver integrated circuit, respectively.

[0106] In some embodiments, the step of placing the flip-chip and the embedded driver integrated circuit on the corresponding electrode on the top layer of the substrate includes: coating the upper surface and all non-light-emitting sidewalls of the flip-chip with a high-reflectivity light-shielding material, curing it to form a high-reflectivity light-shielding layer, and retaining only the light-emitting surface on the back of the chip's substrate; placing the processed flip-chip and the embedded driver integrated circuit on the corresponding bonding pads on the top layer of the substrate, and completing the electrical and mechanical connection through a flip-chip bonding process.

[0107] In some embodiments, the process of forming an ultra-thin encapsulating adhesive layer adapted to the thickness of the driver integrated circuit on the substrate surface using a molding and pressing process includes: covering the substrate surface and the bonded chip and driver integrated circuit with encapsulating adhesive material, and using a molding and pressing process to completely encapsulate the chip and driver integrated circuit with encapsulating adhesive material to form a planarized ultra-thin encapsulating adhesive layer with a thickness adapted to the thickness of the embedded driver integrated circuit.

[0108] In some embodiments, the step of cutting the packaged substrate to obtain a single device unit includes: cutting the packaged substrate into sections according to a preset device size using a laser cutting process, removing excess portions from the edges of the substrate, and simultaneously cutting to form a half-hole solder pad at the bottom of the device; the half-hole solder pad can improve the soldering firmness of the device mounting and enable the device to support bidirectional lateral mounting in both left and right directions, ultimately obtaining multiple independent cuboid ultrathin single device units.

[0109] In some embodiments, the step of sequentially performing electrical illumination detection and spectral sorting on individual device units to complete the fabrication of a multi-layer circuit structure includes: applying a rated operating voltage to each individual device unit, detecting the illumination status and electrical parameters of the device, and screening out device units with qualified electrical performance; then detecting the luminous parameters of the qualified device units and performing spectral sorting according to the luminous color and brightness level.

[0110] In some embodiments, the individual device unit is a five-sided light-emitting structure. After being flatly attached to the application substrate, the light-emitting surface on the back of the chip substrate faces the side, exhibiting the optical characteristic of the highest side light-emitting intensity, while the light-emitting intensity of the other surfaces is relatively low.

[0111] In some embodiments, the method further includes: embedding an embedded driver integrated circuit in the middle layer of the substrate before stacking the substrates with a preset number of layers, and then stacking the substrates and preparing interlayer interconnects.

[0112] It should be noted that those skilled in the art will understand that, for the sake of convenience and brevity, the specific working process of the multilayer circuit structure fabrication system and each module described above can be referred to the corresponding content in the various embodiments of the multilayer circuit structure fabrication method described above, and will not be repeated here.

[0113] The above-described method for fabricating multilayer circuit structures can be implemented as a computer program, which can be used in, for example... Figure 7 It runs on the system shown.

[0114] Please see Figure 8 , Figure 8 This is a schematic block diagram of the structure of a computer device provided in an embodiment of this application. The computer device includes a processor, a memory, and a network interface connected via a device bus, wherein the memory may include a storage medium and internal memory.

[0115] The storage medium can store operating devices and computer programs. The computer program includes program instructions that, when executed, cause the processor to perform any method for fabricating a multilayer circuit structure.

[0116] The processor provides computing and control capabilities, supporting the operation of the entire computer device.

[0117] Internal memory provides an environment for the execution of computer programs in non-volatile storage media. When the computer program is executed by the processor, it enables the processor to execute any method for fabricating a multilayer circuit structure.

[0118] This network interface is used for network communication, such as sending assigned tasks. Those skilled in the art will understand that... Figure 8 The structure shown is merely a block diagram of a portion of the structure related to the present application and does not constitute a limitation on the terminal to which the present application is applied. Specific computer devices may include more or fewer components than those shown in the figure, or combine certain components, or have different component arrangements.

[0119] It should be understood that the processor can be a Central Processing Unit (CPU), but it can also be other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. Among these, a general-purpose processor can be a microprocessor or any conventional processor.

[0120] In one embodiment, the processor is configured to run a computer program stored in memory to perform the following steps: A substrate with a preset number of layers is stacked, and a power layer, a signal layer, and a grounding and heat dissipation layer are arranged in layers inside the substrate. Laser drilling and via-filling electroplating processes are used to fabricate interlayer blind and buried via interconnect units to achieve electrical connection between the power layer, signal layer and grounding heat dissipation layer; Precision etching is performed on the surface of the substrate to form bonding pads for the chip and driver integrated circuit; The flip-chip LED and the embedded driver IC are placed on the corresponding electrodes on the top layer of the substrate; An ultra-thin encapsulation adhesive layer adapted to the thickness of the driver integrated circuit is formed on the substrate surface using a molding and pressing process; The packaged substrate is cut to obtain individual device units; The individual device units are sequentially subjected to electrical illumination detection and optical sorting to complete the fabrication of the multi-layer circuit structure.

[0121] In some embodiments, the step of stacking a preset number of substrates and layering a power layer, a signal layer, and a grounding and heat dissipation layer inside the substrate includes: preparing each substrate layer using an ultra-thin resin-based material, providing an ultra-thin low-dielectric dielectric layer for isolation between adjacent substrate layers, and independently arranging the power layer, signal layer, and grounding and heat dissipation layer in different substrate layers, wherein the grounding and heat dissipation layer adopts a large copper foil structure.

[0122] In some embodiments, the process of using laser drilling and via-filling electroplating to prepare interlayer blind and buried via interconnect units to achieve electrical connection between power layer, signal layer and ground heat dissipation layer includes: forming blind and buried vias through corresponding dielectric layers on the laminated substrate by laser processing, and then performing via-filling electroplating on the blind and buried vias to form a continuous conductive layer on the via wall and inside the via, thereby achieving electrical connection between adjacent layers and across layers.

[0123] In some embodiments, the precise etching of the substrate surface to form bonding pads for the chip and the driver integrated circuit includes: coating the substrate surface with photoresist, forming a circuit pattern by exposure and development, and then etching and removing the photoresist from the exposed substrate to form independent bonding pads on the top layer of the substrate corresponding to the flip-chip LED and the embedded driver integrated circuit, respectively.

[0124] In some embodiments, the step of placing the flip-chip and the embedded driver integrated circuit on the corresponding electrode on the top layer of the substrate includes: coating the upper surface and all non-light-emitting sidewalls of the flip-chip with a high-reflectivity light-shielding material, curing it to form a high-reflectivity light-shielding layer, and retaining only the light-emitting surface on the back of the chip's substrate; placing the processed flip-chip and the embedded driver integrated circuit on the corresponding bonding pads on the top layer of the substrate, and completing the electrical and mechanical connection through a flip-chip bonding process.

[0125] In some embodiments, the process of forming an ultra-thin encapsulating adhesive layer adapted to the thickness of the driver integrated circuit on the substrate surface using a molding and pressing process includes: covering the substrate surface and the bonded chip and driver integrated circuit with encapsulating adhesive material, and using a molding and pressing process to completely encapsulate the chip and driver integrated circuit with encapsulating adhesive material to form a planarized ultra-thin encapsulating adhesive layer with a thickness adapted to the thickness of the embedded driver integrated circuit.

[0126] In some embodiments, the step of cutting the packaged substrate to obtain a single device unit includes: cutting the packaged substrate into sections according to a preset device size using a laser cutting process, removing excess portions from the edges of the substrate, and simultaneously cutting to form a half-hole solder pad at the bottom of the device; the half-hole solder pad can improve the soldering firmness of the device mounting and enable the device to support bidirectional lateral mounting in both left and right directions, ultimately obtaining multiple independent cuboid ultrathin single device units.

[0127] In some embodiments, the step of sequentially performing electrical illumination detection and spectral sorting on individual device units to complete the fabrication of a multi-layer circuit structure includes: applying a rated operating voltage to each individual device unit, detecting the illumination status and electrical parameters of the device, and screening out device units with qualified electrical performance; then detecting the luminous parameters of the qualified device units and performing spectral sorting according to the luminous color and brightness level.

[0128] In some embodiments, the individual device unit is a five-sided light-emitting structure. After being flatly attached to the application substrate, the light-emitting surface on the back of the chip substrate faces the side, exhibiting the optical characteristic of the highest side light-emitting intensity, while the light-emitting intensity of the other surfaces is relatively low.

[0129] In some embodiments, the method further includes: embedding an embedded driver integrated circuit in the middle layer of the substrate before stacking the substrates with a preset number of layers, and then stacking the substrates and preparing interlayer interconnects.

[0130] This application also provides a computer-readable storage medium storing a computer program that, when executed by a processor, causes the processor to implement the steps of the method for fabricating a multilayer circuit structure as provided in any embodiment of this application.

[0131] The computer-readable storage medium may be an internal storage unit of the computer device described in the foregoing embodiments, such as the hard disk or memory of the computer device. The computer-readable storage medium may also be an external storage device of the computer device, such as a plug-in hard disk, SmartMedia Card (SMC), Secure Digital (SD) card, or Flash Card equipped on the computer device.

[0132] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any person skilled in the art can easily conceive of various equivalent modifications or substitutions within the technical scope disclosed in this application, and these modifications or substitutions should all be covered within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A method for fabricating a multilayer circuit structure, characterized in that, include: A substrate with a preset number of layers is stacked, and a power layer, a signal layer, and a grounding and heat dissipation layer are arranged in layers inside the substrate. Laser drilling and via-filling electroplating processes are used to fabricate interlayer blind and buried via interconnect units to achieve electrical connection between the power layer, signal layer and grounding heat dissipation layer; Precision etching is performed on the surface of the substrate to form bonding pads for the chip and driver integrated circuit; The flip-chip LED and the embedded driver IC are placed on the corresponding electrodes on the top layer of the substrate; An ultra-thin encapsulation adhesive layer adapted to the thickness of the driver integrated circuit is formed on the substrate surface using a molding and pressing process; The packaged substrate is cut to obtain individual device units; The individual device units are sequentially subjected to electrical illumination detection and optical sorting to complete the fabrication of the multi-layer circuit structure.

2. The method according to claim 1, characterized in that, The process of stacking a predetermined number of substrates, and layering a power layer, a signal layer, and a grounding and heat dissipation layer inside the substrate, includes: Each substrate layer is prepared using an ultra-thin resin-based material, and an ultra-thin low-dielectric dielectric layer is set between two adjacent substrate layers for isolation. The power layer, signal layer and grounding heat dissipation layer are independently arranged in different substrate layers, and the grounding heat dissipation layer adopts a large copper foil structure.

3. The method according to claim 1, characterized in that, The process employs laser drilling and via-filling electroplating to fabricate interlayer blind and buried via interconnect units, enabling electrical connections between the power layer, signal layer, and grounding / heat dissipation layer. This includes: Blind and buried vias are formed on the laminated substrate by laser processing, penetrating the corresponding dielectric layers. Then, the blind and buried vias are filled by electroplating to form a continuous conductive layer on the via walls and inside the vias, thus achieving electrical connection between adjacent layers and across layers.

4. The method according to claim 1, characterized in that, The process of precision etching the substrate surface to form bonding pads for the chip and driver integrated circuit includes: Photoresist is coated on the surface of the substrate, and circuit patterns are formed by exposure and development. The exposed substrate is then etched and the photoresist is removed to form independent bonding pads on the top layer of the substrate, corresponding to the flip-chip LED and the embedded driver integrated circuit, respectively.

5. The method according to claim 1, characterized in that, The step of placing the flip-chip LED and the embedded driver integrated circuit on the corresponding electrodes on the top layer of the substrate includes: A high-reflectivity light-shielding material is coated on the upper surface and all non-light-emitting sidewalls of the flip-chip, and after curing, a high-reflectivity light-shielding layer is formed, leaving only the light-emitting surface on the back of the chip's substrate intact. The processed flip-chip LED and embedded driver IC are placed on the corresponding bonding pads on the top layer of the substrate, and the electrical and mechanical connections are completed through flip-chip bonding.

6. The method according to claim 1, characterized in that, The process of forming an ultra-thin encapsulating adhesive layer adapted to the thickness of the driver integrated circuit on the substrate surface using a molding and pressing process includes: Encapsulating adhesive material is applied to the substrate surface and over the bonded chip and driver integrated circuit. Through a molding and pressing process, the encapsulating adhesive material completely covers the chip and driver integrated circuit, forming a planar ultra-thin encapsulating adhesive layer with a thickness that matches the thickness of the embedded driver integrated circuit.

7. The method according to claim 1, characterized in that, The process of cutting the packaged substrate to obtain individual device units includes: According to the preset device size, the packaged substrate is cut using laser cutting technology to remove excess parts from the edges of the substrate and simultaneously cut to form a half-hole solder pad at the bottom of the device. The half-hole solder pad can improve the soldering firmness of the device and enable the device to support bidirectional side mounting from left to right, ultimately resulting in multiple independent cuboid ultra-thin single device units.

8. The method according to claim 1, characterized in that, The process of sequentially performing electrical illumination detection and spectral sorting on individual device units to complete the fabrication of a multilayer circuit structure includes: The rated operating voltage is applied to each individual device unit, and the lighting status and electrical parameters of the device are detected. Device units with qualified electrical performance are selected. Then, the qualified device units are tested for luminous parameters and sorted according to luminous color and brightness level.

9. The method according to claim 1, characterized in that, The individual device unit is a five-sided light-emitting structure. After being flatly attached to the application substrate, the light-emitting surface on the back of the chip substrate faces to the side, exhibiting the optical characteristic of the highest lateral light emission intensity, while the light emission intensity of the other surfaces is relatively low.

10. The method according to claim 1, characterized in that, The method further includes: Before stacking substrates with a predetermined number of layers, embedded driver integrated circuits are pre-embedded inside the middle layer of the substrate, and then the substrates are stacked and interlayer interconnects are fabricated.

11. A multilayer circuit structure, prepared according to the method of any one of claims 1 to 10, characterized in that, It includes a multilayer resin-based circuit board, a flip-chip light-emitting diode, an embedded driver integrated circuit, a high-reflectivity light-shielding layer, and an ultra-thin encapsulating adhesive layer; The multilayer resin-based circuit board has a power layer, a signal layer and a grounding and heat dissipation layer. The multilayer resin-based circuit board has interlayer blind and buried via interconnection units to realize the electrical connection between the layers. Flip-chip LEDs and embedded driver integrated circuits are mounted and soldered on the top layer of a multilayer resin-based circuit board; a high-reflectivity light-shielding layer covers the upper surface and all non-light-emitting sidewalls of the flip-chip LEDs, leaving only the light-emitting surface on the back of the chip's substrate. An ultra-thin encapsulating adhesive layer covers the top layer of a multilayer resin-based circuit board, a flip-chip light-emitting diode, and an embedded driver integrated circuit. The bottom of the multilayer circuit structure is provided with a half-hole solder pad. The overall structure is a five-sided light-emitting structure. After being flatly attached to the application substrate, the light-emitting surface on the back of the chip substrate faces to the side, exhibiting the optical characteristics of the highest lateral light-emitting intensity.

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