Display panel for improving side wall defects and method of manufacturing the same

Abstract

The present disclosure provides a display panel with improved sidewall defects and a preparation method thereof, and belongs to the technical field of optoelectronic manufacturing. The preparation method comprises: providing a semiconductor product comprising a substrate and an epitaxial layer on the substrate; etching the epitaxial layer to form a plurality of spaced light emitting units; forming a sacrificial layer on the sidewall of each light emitting unit, the sacrificial layer being used to generate volatile products to consume defects on the sidewall of the light emitting unit when an oxidation reaction occurs on the sidewall of the light emitting unit; and removing the sacrificial layer. The embodiments of the present disclosure can reduce the sidewall defects of the light emitting units to improve the reliability of the display panel.

Description

Technical Field

[0001] This disclosure relates to the field of optoelectronic manufacturing technology, and in particular to a display panel with improved sidewall defects and a method for its fabrication. Background Technology

[0002] Micro LED (Micro Light Emitting Diode) display panels are an emerging display technology. The core of this technology is to use micron-sized Micro LED chips as light-emitting units and integrate them into a high-density array on a driving substrate to achieve independent light control for each light-emitting unit.

[0003] In related technologies, a display panel includes a driving substrate and multiple light-emitting units, which are arranged at intervals on the driving substrate. In the process of fabricating multiple light-emitting units, an epitaxial layer needs to be formed on the substrate first. Then, inductively coupled plasma dry etching technology is used to pattern the epitaxial layer, dividing the continuous epitaxial layer into multiple independent light-emitting units, thereby achieving pixel-level electrical isolation.

[0004] However, during inductively coupled plasma dry etching, high-energy ions continuously bombard the sidewall region of the light-emitting unit, causing lattice atoms to be forcibly ejected from their original lattice sites, thus forming a large number of dangling bonds and vacancy defects. These defects can cause surface band bending, eventually forming nonradiative recombination centers, which not only reduce the radiative recombination efficiency of the device and lead to a decrease in external quantum efficiency, but also introduce additional leakage current channels, affecting the reliability and lifespan of the device. Summary of the Invention

[0005] This disclosure provides a display panel with improved sidewall defects and a method for manufacturing the same, which can reduce sidewall defects in the light-emitting units and thus improve the reliability of the display panel. The technical solution is as follows: On one hand, this disclosure provides a method for fabricating a display panel, the method comprising: providing a semiconductor article, the semiconductor article comprising a substrate and an epitaxial layer located on the substrate; etching the epitaxial layer to form a plurality of spaced light-emitting units; forming a sacrificial layer on the sidewall of each of the light-emitting units; and removing the sacrificial layer.

[0006] In one implementation of this disclosure, forming a sacrificial layer on the sidewall of each of the light-emitting units includes: forming a Ga2O3 layer on the sidewall of the light-emitting unit; and annealing the Ga2O3 layer.

[0007] In another implementation of this disclosure, annealing the Ga2O3 layer includes: controlling the annealing temperature to be 700°C to 800°C and the annealing time to be 30s to 100s under a nitrogen atmosphere to form a GaON layer.

[0008] In another implementation of this disclosure, forming a Ga2O3 layer on the sidewall of the light-emitting unit includes forming a Ga2O3 layer with a thickness of 5 nm to 50 nm on the sidewall of the light-emitting unit by atomic layer deposition or in-situ high-temperature oxidation process.

[0009] In another implementation of this disclosure, after removing the sacrificial layer, the method further includes depositing a passivation layer on the surface of the GaON layer, the passivation layer comprising an aluminum oxide layer or a silicon oxide layer.

[0010] In another implementation of this disclosure, before forming a sacrificial layer on the sidewall of each of the light-emitting units, the method further includes: pre-treating the etched sidewall of the light-emitting unit with oxygen plasma, wherein the plasma power is 50W to 100W and the treatment time is 10s to 30s.

[0011] In another implementation of this disclosure, removing the sacrificial layer includes immersing the semiconductor product in a dilute hydrochloric acid or sodium hydroxide solution for 30 to 60 seconds.

[0012] In another aspect, embodiments of this disclosure provide a display panel, which is prepared using the display panel preparation method described above.

[0013] In another implementation of this disclosure, the display panel includes: a substrate, a transition layer, and a plurality of light-emitting units, wherein the plurality of light-emitting units are arranged at intervals on the substrate, the transition layer is located on the sidewall of the light-emitting units, and the transition layer includes a GaON layer.

[0014] In another implementation of this disclosure, the thickness of the GaON layer is 5 nm to 50 nm.

[0015] The beneficial effects of the technical solutions provided in this disclosure include at least the following: The display panel fabrication method provided in this disclosure significantly reduces the sidewall defect density of the light-emitting unit by adding a sidewall sacrificial layer growth and oxidation-evaporation process after etching to form the light-emitting unit. The high-energy ion bombardment generated by dry etching would normally lead to a large number of lattice defects such as dangling bonds and vacancies on the sidewalls of the light-emitting unit. The oxidation-evaporation process of the sacrificial layer actively consumes these defects, reducing the sidewall defect density and thus decreasing the formation of non-radiative recombination centers. This helps alleviate surface bandgap bending problems and improves the radiative recombination efficiency and external quantum efficiency of the device.

[0016] Furthermore, the oxidation-evaporation process of the sacrificial layer can repair the sidewall crystal structure damaged by etching. Under the microscopic level, the originally rough and damaged sidewalls become smoother. The disappearance of nanoscale etching pits on the surface can be observed by atomic force microscopy or high-resolution electron microscopy, and the surface smoothness is significantly improved, reducing the negative impact of defects on carrier transport.

[0017] Meanwhile, the reduction of defects directly cuts off the formation path of additional leakage current channels, which can reduce the reverse leakage current of the device and avoid performance degradation and early failure caused by leakage. The improvement of radiative recombination efficiency also helps to reduce heat loss during device operation and improve device reliability. Attached Figure Description

[0018] To more clearly illustrate the technical solutions in the embodiments of this disclosure, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0019] Figure 1 This is a flowchart of a method for manufacturing a display panel according to an embodiment of this disclosure; Figure 2 This is a flowchart of another method for manufacturing a display panel provided in this embodiment; Figure 3 This is a manufacturing state diagram of a display panel provided in an embodiment of this disclosure; Figure 4 This is a manufacturing state diagram of a display panel provided in an embodiment of this disclosure; Figure 5 This is a manufacturing state diagram of a display panel provided in an embodiment of this disclosure; Figure 6 This is a schematic diagram of a display panel provided in an embodiment of this disclosure.

[0020] The markings in the diagram are explained as follows: 11. Substrate; 12. Light-emitting unit; 13. Epitaxial layer; 14. Substrate; 20. Sacrificial layer; 30. Passivation layer; 40. Transparent conductive layer; 50. Transition layer; 60. Connect the electrodes; 70. Bonded metal layer. Detailed Implementation

[0021] To make the objectives, technical solutions, and advantages of this disclosure clearer, the embodiments of this disclosure will be described in further detail below with reference to the accompanying drawings.

[0022] Unless otherwise defined, the technical or scientific terms used herein shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” “third,” and similar terms used in this patent application specification and claims do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Similarly, the terms “an” or “a” and similar terms do not indicate a quantity limitation, but rather indicate the presence of at least one. The terms “comprising” or “including” and similar terms mean that the elements or objects preceding “comprising” or “including” encompass the elements or objects listed following “comprising” or “including” and their equivalents, and do not exclude other elements or objects. The terms “connected” or “linked” and similar terms are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. The terms “upper,” “lower,” “left,” “right,” “top,” and “bottom,” etc., are used only to indicate relative positional relationships, and these relative positional relationships may change accordingly when the absolute position of the described objects changes.

[0023] Figure 1 This is a flowchart illustrating a method for manufacturing a display panel according to an embodiment of this disclosure. Figure 1 As shown, the preparation method includes: Step S11: Provide a semiconductor product.

[0024] Semiconductor products include a substrate and an epitaxial layer located on the substrate.

[0025] Step S12: Etch the epitaxial layer to form multiple spaced light-emitting units.

[0026] Step S13: Form a sacrificial layer on the sidewall of each light-emitting unit.

[0027] The sacrificial layer is used to undergo an oxidation reaction on the sidewall of the light-emitting unit to generate volatile products that consume the defects on the sidewall of the light-emitting unit.

[0028] Step S14: Remove the sacrificial layer.

[0029] The display panel fabrication method provided in this disclosure significantly reduces the sidewall defect density of the light-emitting unit by adding a sidewall sacrificial layer growth and oxidation-evaporation process after etching to form the light-emitting unit. The high-energy ion bombardment generated by dry etching would normally lead to a large number of lattice defects such as dangling bonds and vacancies on the sidewalls of the light-emitting unit. The oxidation-evaporation process of the sacrificial layer actively consumes these defects, reducing the sidewall defect density and thus decreasing the formation of non-radiative recombination centers. This helps alleviate surface bandgap bending problems and improves the radiative recombination efficiency and external quantum efficiency of the device.

[0030] Furthermore, the oxidation-evaporation process of the sacrificial layer can repair the sidewall crystal structure damaged by etching. Under the microscopic level, the originally rough and damaged sidewalls become smoother. The disappearance of nanoscale etching pits on the surface can be observed by atomic force microscopy or high-resolution electron microscopy, and the surface smoothness is significantly improved, reducing the negative impact of defects on carrier transport.

[0031] Meanwhile, the reduction of defects directly cuts off the formation path of additional leakage current channels, which can reduce the reverse leakage current of the device and avoid performance degradation and early failure caused by leakage. The improvement of radiative recombination efficiency also helps to reduce heat loss during device operation and improve device reliability.

[0032] Figure 2 This is a flowchart of another method for manufacturing a display panel provided in this disclosure. Figure 2 As shown, the preparation method includes: Step S21: Provide a semiconductor product.

[0033] Semiconductor products include a substrate and an epitaxial layer located on the substrate.

[0034] The semiconductor product in this embodiment is a semiconductor product that has completed the initial bonding and substrate removal processes.

[0035] The manufacturing process of semiconductor products can be as follows: First, such as Figure 3 As shown, an epitaxial layer 13 is formed on a substrate 14, and then the epitaxial layer 13 is bonded to a substrate 11, and the substrate 14 is removed.

[0036] like Figure 3 As shown, the specific process may include: forming a bonding metal layer 70 on the surface of both the substrate 11 and the epitaxial layer 13, bonding the epitaxial layer 13 and the substrate 11 together, and then removing the substrate 14.

[0037] The bonding metal layer 70 may include at least one of AuBe layer, Au layer, Ti layer, Ni layer and Pt layer.

[0038] For example, the substrate 11 is a silicon-based or metal substrate 11 with excellent electrical and thermal conductivity.

[0039] Optionally, the epitaxial layer 13 includes a first semiconductor layer, a multiple quantum well layer, and a second semiconductor layer sequentially stacked on the substrate 11.

[0040] In this process, one of the first semiconductor layer and the second semiconductor layer is an n-type layer, and the other of the first semiconductor layer and the second semiconductor layer is a p-type layer.

[0041] Optionally, the n-type layer is an n-type GaN layer. The thickness of the n-type GaN layer can be from 0.5 μm to 1 μm.

[0042] Optionally, the multiple quantum well layer includes alternating InGaN quantum well layers and GaN quantum barrier layers. Specifically, the multiple quantum well layer may include 3 to 8 alternating stacked InGaN quantum well layers and GaN quantum barrier layers.

[0043] As an example, in an embodiment of this disclosure, the multi-quantum-well layer includes five alternating stacked InGaN quantum-well layers and GaN quantum-barrier layers.

[0044] Optionally, the thickness of the multi-quantum well layer can be from 150 nm to 200 nm.

[0045] Optionally, the p-type layer is a p-type GaN layer. The thickness of the p-type GaN layer can be from 0.5 μm to 1 μm.

[0046] For example, an n-type GaN layer, an InGaN / GaN multi-quantum-well light-emitting layer and a p-type GaN layer are sequentially stacked on the substrate 11 to form a complete GaN-based epitaxial layer 13. The surface of the epitaxial layer 13 has been preliminarily cleaned and is free of contaminants such as residual photoresist and metal debris.

[0047] Step S22: Etch the epitaxial layer 13 to form a plurality of spaced light-emitting units 12.

[0048] like Figure 3 As shown, specifically, it may include: using an inductively coupled plasma dry etching process, defining the pattern through a pre-prepared photomask, selectively etching the epitaxial layer 13 to a depth of n-type GaN layer, dividing the continuous epitaxial layer 13 into multiple spaced micron-sized light-emitting units 12 to achieve pixel-level electrical isolation; after etching, removing residual photoresist and etching byproducts from the surface through a standard cleaning process.

[0049] Between steps S22 and S23, the process further includes: pre-treating the sidewalls of the etched light-emitting unit 12 with oxygen plasma, the plasma power being 50W to 100W and the treatment time being 10s to 30s, to improve the interfacial bonding force between the GaON layer and GaN.

[0050] Among them, oxygen plasma is used to pre-treat the sidewalls of the etched light-emitting unit 12. The plasma power is controlled at 50W to 100W and the treatment time is 10s to 30s. Oxygen plasma can remove residual organic contaminants on the sidewalls and activate the dangling bonds on the GaN surface, thereby improving the interfacial bonding force between the subsequent GaON layer and GaN.

[0051] Step S23: A Ga2O3 layer is formed on the sidewall of the light-emitting unit 12.

[0052] like Figure 4 As shown, optionally, a Ga2O3 layer with a thickness of 5 nm to 50 nm is formed on the sidewall of the light-emitting unit 12 by atomic layer deposition or in-situ high-temperature oxidation process.

[0053] In one implementation, the ALD (Atomic Layer Deposition) process is used, with ozone as the oxygen source, and layer-by-layer deposition is carried out at a process temperature of 200°C to 300°C. This allows for precise control of the Ga2O3 layer thickness from 5nm to 50nm, resulting in high film uniformity and few impurities.

[0054] Among them, the ALD process can achieve precise control of nanometer-level thickness, has good film density, and can completely cover the nanometer-level etched pits on the sidewalls.

[0055] In another implementation, an in-situ high-temperature oxidation process is used, in which the semiconductor product is placed in an O2 environment and heated for about 20 minutes to allow the GaN surface on the sidewall to naturally oxidize and form a Ga2O3 thin layer.

[0056] Among them, the in-situ high-temperature oxidation process does not require an additional transfer chamber, which can avoid surface exposure to air pollution, reduce impurities such as hydroxyl groups and residual hydrogen, and reduce the number of traps in the oxide layer and at the interface.

[0057] The Ga2O3 layer is designed to be 5nm to 50nm thick, which ensures sufficient defect repair while avoiding incomplete removal and residual impurities that could affect device performance due to excessive thickness.

[0058] like Figure 4 As shown, step S24: Annealing the Ga2O3 layer causes oxidation reaction on the sidewall of the light-emitting unit 12, and atomic rearrangement occurs on the sidewall of the light-emitting unit 12 to form a transition layer 50.

[0059] Optionally, under a nitrogen atmosphere, the annealing temperature is controlled to be 700°C to 800°C and the annealing time is 30s to 100s, so that the Ga2O3 layer and the GaN interface of the sidewall of the light-emitting unit 12 undergo atomic rearrangement to form a GaON layer.

[0060] Specifically, this may include placing the semiconductor product with the Ga2O3 layer in a rapid annealing furnace under a nitrogen atmosphere, controlling the annealing temperature to be 700°C to 800°C, and the annealing time to be 30s to 100s.

[0061] Annealing in a nitrogen atmosphere at 700℃ to 800℃ provides sufficient thermodynamic driving force for the reaction. Oxygen atoms in the Ga2O3 layer diffuse to the GaN sidewall surface and combine with Ga atoms in the GaN lattice to form Ga-O bonds. At the same time, N atoms in the original GaN lattice will escape from the surface in the form of N2. This process will preferentially react with the dangling bonds and vacancy defects exposed on the sidewall after etching.

[0062] The Ga dangling bonds generated by etching directly combine with diffused oxygen atoms to form stable Ga-O bonds, reducing the number of non-radiative recombination centers. The highly active sites at surface vacancy defects accelerate the oxidation reaction, preferentially covering the defect areas and achieving initial passivation. The driving force of this stage is much higher than that of conventional nitriding reactions, enabling the formation of a uniform oxide transition layer 50 in a short time, avoiding defect residue.

[0063] As oxygen atoms continue to diffuse, atomic-level ordered rearrangement occurs at the interface. Oxygen atoms partially replace N atom sites in the GaN lattice, forming a GaON (gallium oxynitride) transition layer 50 containing both Ga-O and Ga-N bonds. The advantage of this structure lies in the excellent lattice matching between GaON and GaN; their lattice constants differ very little from GaN, significantly reducing lattice mismatch stress at the interface and avoiding the problem of increased interface state density. The rearranged GaON layer forms a uniform lattice transition region, microscopically mitigating lattice distortion caused by etching.

[0064] During the oxidation reaction and atomic rearrangement, the deep defects generated by etching are actively consumed by the "oxidation-volatilization" process. Vacancies inside the sidewalls adsorb diffused oxygen atoms, forming unstable oxygen-containing intermediates that escape from the lattice in gaseous form at high temperatures, directly reducing the absolute number of defects. Lattice atoms that were originally displaced by high-energy ion bombardment will gain sufficient migration energy at high temperatures, return to their normal lattice sites, fill vacancy defects, and further reduce the defect density.

[0065] For example, after removing the sacrificial layer 20, the sidewall defect density of the light-emitting unit 12 is reduced by one to two orders of magnitude compared with the sidewall defect density before the formation of the sacrificial layer 20.

[0066] In this embodiment, under high temperature conditions, defects such as dangling bonds and vacancies generated by sidewall etching are oxidized and consumed. At the same time, the atoms at the Ga2O3 and GaN interface rearrange to form a GaON transition layer 50, ultimately achieving a reduction in sidewall defect density by 1-2 orders of magnitude compared to before the formation of the sacrificial layer 20. After crystal structure repair, the surface smoothness of the sidewall is improved, and the disappearance of nanoscale etching pits can be observed under an atomic force microscope. This reduces non-radiative recombination centers, improves radiative recombination efficiency and external quantum efficiency, and cuts off additional leakage current channels, thereby improving device reliability and lifespan.

[0067] Step S25: Immerse the semiconductor product in dilute hydrochloric acid or sodium hydroxide solution for 30 to 60 seconds to remove the sacrificial layer 20.

[0068] like Figure 4 As shown, this can specifically include immersing the annealed semiconductor product in a dilute hydrochloric acid or sodium hydroxide solution at room temperature for 30 to 60 seconds. Ga2O3 is highly soluble in acid / alkali solutions, while GaN materials are almost unaffected by acid / alkali corrosion. Therefore, the Ga2O3 sacrificial layer 20 is completely removed, exposing the sidewalls of the light-emitting unit 12, which have undergone defect repair and are atomically flat.

[0069] After removing the sacrificial layer 20 in step S25, the following steps are also included: First, such as Figure 5 As shown, a passivation layer 30 is deposited on the surface of the GaON layer, so that the passivation layer 30 covers each light-emitting unit 12.

[0070] After removing the sacrificial layer 20, the sidewalls of the GaON layer, which have undergone defect repair and are atomically smooth, are exposed. First, a standard cleaning process (acetone, isopropanol, and deionized water are used sequentially) is employed to remove residual acid / alkali solutions and impurities from the surface. Then, a passivation layer 30 is deposited on the surface of the GaON layer using the following process.

[0071] For example, the passivation layer 30 includes an aluminum oxide layer or a silicon oxide layer.

[0072] In one implementation, an atomic layer deposition (ALD) process is used to transfer the sample into an ALD chamber. Trimethylaluminum (TMA) is used as the aluminum source and ozone (O3) as the oxygen source, or silane is used as the silicon source and nitrous oxide (N2O) as the oxygen source. The layer is deposited layer by layer at a process temperature of 200°C to 400°C. The passivation layer thickness can be controlled from 5 nm to 500 nm. The film has good density and excellent shape retention, and can completely cover the sidewalls and surface of the GaON layer.

[0073] In another implementation, a plasma-enhanced chemical vapor deposition (PECVD) process is used. The sample is placed in a PECVD chamber and silane / laughing gas is introduced (to deposit SiO2) or an aluminum / oxygen source (to deposit Al2O3). The reaction temperature is controlled at 300°C to 500°C, the chamber pressure at 20 torr to 100 torr, and the deposition rate at 0.5 nm / min to 10 nm / min.

[0074] After deposition, low-temperature annealing at 300℃ to 500℃ for 30s to 60s can be performed in a nitrogen atmosphere to further reduce the defect density at the interface between the passivation layer 30 and GaON, thereby improving the passivation effect.

[0075] In this embodiment, the passivation layer 30 can isolate external contaminants such as water, oxygen, and metal ions from eroding the repaired GaON layer, preventing the reintroduction of sidewall defects after repair, maintaining an atomically flat sidewall structure, and extending the device's service life.

[0076] Then, as Figure 5 As shown, the passivation layer 30 is covered by a transparent conductive layer 40.

[0077] The transparent conductive layer 40 is disposed above the passivation layer 30, allowing the transparent conductive layer 40 to be electrically connected to each light-emitting unit 12 through the through-holes in the passivation layer 30.

[0078] For example, the thickness of the transparent conductive layer 40 is greater than or equal to 2000 angstroms.

[0079] Next, as Figure 5 As shown, a connecting electrode 60 is formed on the surface of the transparent conductive layer 40, and the connecting electrode 60 is located in the gap between each light-emitting unit 12.

[0080] Then, a light-collecting structure is formed on the side of the light-emitting unit 12 away from the substrate 11.

[0081] The orthographic projection of the light-emitting unit 12 on the surface of the substrate 11 is located within the orthographic projection of the corresponding light-collecting structure on the surface of the substrate 11.

[0082] Optionally, the top of the light-collecting structure is an arc surface. Specifically, the top of the light-collecting structure is designed as a spherical surface to achieve direct collimation of light at small angles.

[0083] For example, the light-collecting structure can be made of polydimethylsiloxane, polymethyl methacrylate, and silicon dioxide.

[0084] Figure 6 This is a schematic diagram of the structure of a display panel provided in an embodiment of this disclosure. The display panel is manufactured using the display panel fabrication method described above. Figure 6 As shown, the display panel includes: a substrate 11, a transition layer and a plurality of light-emitting units 12. The plurality of light-emitting units 12 are arranged at intervals on the substrate 11. The transition layer is located on the sidewall of the light-emitting unit 12 and includes a GaON layer.

[0085] Optionally, the thickness of the GaON layer is from 5 nm to 50 nm. In this embodiment, the GaON layer may be formed by annealing a Ga2O3 layer attached to the sidewall of the light-emitting unit 12.

[0086] The annealing process includes: under a nitrogen atmosphere, controlling the annealing temperature to 700℃ to 800℃ and the annealing time to 30s to 100s, so that the Ga2O3 layer and the GaN interface of the sidewall of the light-emitting unit 12 undergo atomic rearrangement to form a GaON layer.

[0087] The GaON layer thickness is designed to be between 5nm and 50nm, which ensures sufficient defect repair while avoiding incomplete removal and residual impurities that could affect device performance due to excessive thickness.

[0088] For example, the light-emitting unit 12 includes a first semiconductor layer, a multiple quantum well layer and a second semiconductor layer sequentially stacked on the substrate 11.

[0089] In this process, one of the first semiconductor layer and the second semiconductor layer is an n-type layer, and the other of the first semiconductor layer and the second semiconductor layer is a p-type layer.

[0090] Optionally, the n-type layer is an n-type GaN layer. The thickness of the n-type GaN layer can be from 0.5 μm to 1 μm.

[0091] Optionally, the multiple quantum well layer includes alternating InGaN quantum well layers and GaN quantum barrier layers. Specifically, the multiple quantum well layer may include 3 to 8 alternating stacked InGaN quantum well layers and GaN quantum barrier layers.

[0092] As an example, in an embodiment of this disclosure, the multi-quantum-well layer includes five alternating stacked InGaN quantum-well layers and GaN quantum-barrier layers.

[0093] Optionally, the thickness of the multi-quantum well layer can be from 150 nm to 200 nm.

[0094] Optionally, the p-type layer is a p-type GaN layer. The thickness of the p-type GaN layer can be from 0.5 μm to 1 μm.

[0095] Optionally, the display panel further includes a passivation layer 30 and a transparent conductive layer 40. The passivation layer 30 is located on the substrate 11 and covers the light-emitting units 12. The passivation layer 30 has vias that expose each light-emitting unit 12. The transparent conductive layer 40 is located on the surface of the passivation layer 30 and is connected to each light-emitting unit 12 through the vias.

[0096] In the above implementation, the passivation layer 30 covers the light-emitting unit 12, which can effectively achieve electrical isolation between adjacent light-emitting units 12 and between the light-emitting unit 12 and other film layers, prevent short circuit faults between different circuits, protect the light-emitting unit 12 and the driving circuit from external interference and damage, and improve the stability and reliability of the display panel operation.

[0097] Meanwhile, the via design on the passivation layer 30 is precise, exposing only each light-emitting unit 12. The transparent conductive layer 40 is connected to the light-emitting unit 12 through the via, which can realize the precise electrical connection between the light-emitting unit 12 and the driving circuit, ensuring that each light-emitting unit 12 can receive the driving signal independently and stably, thus guaranteeing the accuracy and consistency of the display effect.

[0098] For example, the transparent conductive layer 40 may be an ITO layer or an IZO layer.

[0099] As an example, the thickness of the transparent conductive layer 40 can be greater than or equal to 2000 angstroms. This thickness range ensures good conductivity for effective transmission of electrical signals while also providing high transparency to reduce obstruction of light emitted from the light-emitting unit 12.

[0100] For example, the passivation layer 30 may include at least one of a silicon oxide layer, a titanium oxide layer, and an epoxy resin layer.

[0101] For example, passivation layer 30 can be a distributed Bragg reflector (DBR) layer.

[0102] The DBR layer may include multiple alternating layers of first material and multiple layers of second material, with different refractive indices for the first and second material layers.

[0103] For example, one of the first material layer and the second material layer is a TiO2 layer, and the other of the first material layer and the second material layer is a SiO2 layer.

[0104] Among them, the reflection band of the DBR has wavelength selectivity, which can accurately reflect light while allowing other stray wavelengths to pass through, thus enhancing the directional output of effective light.

[0105] Optionally, the display panel further includes a connecting electrode 60, which is located on the surface of the transparent conductive layer 40 and in the gap between each light-emitting unit 12.

[0106] The connecting electrode 60 can establish an additional electrical connection channel in the gap between the light-emitting units 12, which facilitates the effective connection of multiple light-emitting units 12 or light-emitting units 12 in different regions, expands the flexibility of circuit connection, helps to realize complex display driving circuit layout, and meets diverse display needs.

[0107] Furthermore, by utilizing the gaps between the light-emitting units 12 to set the connecting electrodes 60, the main display space of the display panel is not occupied additionally, thus avoiding the compression of the display area caused by adding connecting structures. This helps to achieve miniaturization and high pixel density design of the display panel and improves space utilization efficiency.

[0108] Optionally, the display panel also includes a light-collecting structure, which corresponds one-to-one with the light-emitting unit 12. The light-collecting structure is located on the transparent conductive layer 40 and above the corresponding light-emitting unit 12.

[0109] For example, the light-collecting structure can be made of polydimethylsiloxane, polymethyl methacrylate, and silicon dioxide.

[0110] Polydimethylsiloxane (PDMS) is a flexible and bendable material; its light transmittance exceeds 90%, which reduces total reflection and makes it suitable for flexible Micro LED panels.

[0111] Among them, polymethyl methacrylate (PMMA) has a light transmittance of over 92%, good optical uniformity, moderate mechanical strength, good weather resistance, and is easy to mold, making it suitable for preparing the light-collecting structure 8050 for large-area planar displays.

[0112] Among them, silicon dioxide has a light transmittance of over 95% and excellent thermal stability, and can be precisely processed into microstructures through etching, making it suitable for high-temperature processes and high-precision display requirements.

[0113] For example, substrate 11 may be a complementary metal-oxide-semiconductor (CMOS) integrated circuit board.

[0114] The above description is merely an optional embodiment of this disclosure and is not intended to limit this disclosure. The data therein represents only illustrative examples. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this disclosure should be included within the protection scope of this disclosure.

Claims

1. A method for manufacturing a display panel, characterized in that, The preparation method includes: A semiconductor article is provided, the semiconductor article comprising a substrate (11) and an epitaxial layer (13) located on the substrate (11). The epitaxial layer (13) is etched to form a plurality of spaced light-emitting units (12). A sacrificial layer (20) is formed on the sidewall of each of the light-emitting units (12). Remove the sacrificial layer (20).

2. The preparation method according to claim 1, characterized in that, The formation of a sacrificial layer (20) on the sidewall of each of the light-emitting units (12) includes: A Ga2O3 layer is formed on the sidewall of the light-emitting unit (12); The Ga2O3 layer is then annealed.

3. The preparation method according to claim 2, characterized in that, The annealing process for the Ga2O3 layer includes: Under a nitrogen atmosphere, the annealing temperature is controlled at 700℃ to 800℃ and the annealing time is 30s to 100s to form a GaON layer.

4. The preparation method according to claim 2, characterized in that, The formation of a Ga2O3 layer on the sidewall of the light-emitting unit (12) includes: A Ga2O3 layer with a thickness of 5 nm to 50 nm is formed on the sidewall of the light-emitting unit (12) by atomic layer deposition or in-situ high-temperature oxidation process.

5. The preparation method according to claim 3, characterized in that, After removing the sacrificial layer (20), the process further includes: A passivation layer (30) is deposited on the surface of the GaON layer, the passivation layer (30) comprising an aluminum oxide layer or a silicon oxide layer.

6. The preparation method according to claim 2, characterized in that, Before forming the sacrificial layer (20) on the sidewall of each of the light-emitting units (12), the following is also included: The sidewalls of the etched light-emitting unit (12) are pretreated with oxygen plasma. The plasma power is 50W to 100W and the treatment time is 10s to 30s.

7. The preparation method according to any one of claims 1 to 6, characterized in that, Removing the sacrificial layer (20) includes: The semiconductor product is immersed in dilute hydrochloric acid or sodium hydroxide solution for 30 to 60 seconds.

8. A display panel, characterized in that, The display panel is manufactured using the method for manufacturing a display panel as described in any one of claims 1 to 7.

9. The display panel according to claim 8, characterized in that, The display panel includes: a substrate (11), a transition layer and a plurality of light-emitting units (12), wherein the plurality of light-emitting units (12) are arranged at intervals on the substrate (11), the transition layer is located on the sidewall of the light-emitting unit (12), and the transition layer includes a GaON layer.

10. The display panel according to claim 9, characterized in that, The thickness of the GaON layer is 5 nm to 50 nm.

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